linux/drivers/mfd/rtsx_pcr.c
<<
>>
Prefs
   1/* Driver for Realtek PCI-Express card reader
   2 *
   3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of the GNU General Public License as published by the
   7 * Free Software Foundation; either version 2, or (at your option) any
   8 * later version.
   9 *
  10 * This program is distributed in the hope that it will be useful, but
  11 * WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13 * General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License along
  16 * with this program; if not, see <http://www.gnu.org/licenses/>.
  17 *
  18 * Author:
  19 *   Wei WANG <wei_wang@realsil.com.cn>
  20 *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  21 */
  22
  23#include <linux/pci.h>
  24#include <linux/module.h>
  25#include <linux/slab.h>
  26#include <linux/dma-mapping.h>
  27#include <linux/highmem.h>
  28#include <linux/interrupt.h>
  29#include <linux/delay.h>
  30#include <linux/idr.h>
  31#include <linux/platform_device.h>
  32#include <linux/mfd/core.h>
  33#include <linux/mfd/rtsx_pci.h>
  34#include <asm/unaligned.h>
  35
  36#include "rtsx_pcr.h"
  37
  38static bool msi_en = true;
  39module_param(msi_en, bool, S_IRUGO | S_IWUSR);
  40MODULE_PARM_DESC(msi_en, "Enable MSI");
  41
  42static DEFINE_IDR(rtsx_pci_idr);
  43static DEFINE_SPINLOCK(rtsx_pci_lock);
  44
  45static struct mfd_cell rtsx_pcr_cells[] = {
  46        [RTSX_SD_CARD] = {
  47                .name = DRV_NAME_RTSX_PCI_SDMMC,
  48        },
  49        [RTSX_MS_CARD] = {
  50                .name = DRV_NAME_RTSX_PCI_MS,
  51        },
  52};
  53
  54static DEFINE_PCI_DEVICE_TABLE(rtsx_pci_ids) = {
  55        { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  56        { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  57        { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  58        { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  59        { 0, }
  60};
  61
  62MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
  63
  64void rtsx_pci_start_run(struct rtsx_pcr *pcr)
  65{
  66        /* If pci device removed, don't queue idle work any more */
  67        if (pcr->remove_pci)
  68                return;
  69
  70        if (pcr->state != PDEV_STAT_RUN) {
  71                pcr->state = PDEV_STAT_RUN;
  72                if (pcr->ops->enable_auto_blink)
  73                        pcr->ops->enable_auto_blink(pcr);
  74        }
  75
  76        mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200));
  77}
  78EXPORT_SYMBOL_GPL(rtsx_pci_start_run);
  79
  80int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
  81{
  82        int i;
  83        u32 val = HAIMR_WRITE_START;
  84
  85        val |= (u32)(addr & 0x3FFF) << 16;
  86        val |= (u32)mask << 8;
  87        val |= (u32)data;
  88
  89        rtsx_pci_writel(pcr, RTSX_HAIMR, val);
  90
  91        for (i = 0; i < MAX_RW_REG_CNT; i++) {
  92                val = rtsx_pci_readl(pcr, RTSX_HAIMR);
  93                if ((val & HAIMR_TRANS_END) == 0) {
  94                        if (data != (u8)val)
  95                                return -EIO;
  96                        return 0;
  97                }
  98        }
  99
 100        return -ETIMEDOUT;
 101}
 102EXPORT_SYMBOL_GPL(rtsx_pci_write_register);
 103
 104int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
 105{
 106        u32 val = HAIMR_READ_START;
 107        int i;
 108
 109        val |= (u32)(addr & 0x3FFF) << 16;
 110        rtsx_pci_writel(pcr, RTSX_HAIMR, val);
 111
 112        for (i = 0; i < MAX_RW_REG_CNT; i++) {
 113                val = rtsx_pci_readl(pcr, RTSX_HAIMR);
 114                if ((val & HAIMR_TRANS_END) == 0)
 115                        break;
 116        }
 117
 118        if (i >= MAX_RW_REG_CNT)
 119                return -ETIMEDOUT;
 120
 121        if (data)
 122                *data = (u8)(val & 0xFF);
 123
 124        return 0;
 125}
 126EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
 127
 128int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
 129{
 130        int err, i, finished = 0;
 131        u8 tmp;
 132
 133        rtsx_pci_init_cmd(pcr);
 134
 135        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val);
 136        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8));
 137        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
 138        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81);
 139
 140        err = rtsx_pci_send_cmd(pcr, 100);
 141        if (err < 0)
 142                return err;
 143
 144        for (i = 0; i < 100000; i++) {
 145                err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
 146                if (err < 0)
 147                        return err;
 148
 149                if (!(tmp & 0x80)) {
 150                        finished = 1;
 151                        break;
 152                }
 153        }
 154
 155        if (!finished)
 156                return -ETIMEDOUT;
 157
 158        return 0;
 159}
 160EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
 161
 162int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
 163{
 164        int err, i, finished = 0;
 165        u16 data;
 166        u8 *ptr, tmp;
 167
 168        rtsx_pci_init_cmd(pcr);
 169
 170        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
 171        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80);
 172
 173        err = rtsx_pci_send_cmd(pcr, 100);
 174        if (err < 0)
 175                return err;
 176
 177        for (i = 0; i < 100000; i++) {
 178                err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
 179                if (err < 0)
 180                        return err;
 181
 182                if (!(tmp & 0x80)) {
 183                        finished = 1;
 184                        break;
 185                }
 186        }
 187
 188        if (!finished)
 189                return -ETIMEDOUT;
 190
 191        rtsx_pci_init_cmd(pcr);
 192
 193        rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0);
 194        rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0);
 195
 196        err = rtsx_pci_send_cmd(pcr, 100);
 197        if (err < 0)
 198                return err;
 199
 200        ptr = rtsx_pci_get_cmd_data(pcr);
 201        data = ((u16)ptr[1] << 8) | ptr[0];
 202
 203        if (val)
 204                *val = data;
 205
 206        return 0;
 207}
 208EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
 209
 210void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
 211{
 212        rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
 213        rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
 214
 215        rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
 216        rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
 217}
 218EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd);
 219
 220void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
 221                u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
 222{
 223        unsigned long flags;
 224        u32 val = 0;
 225        u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
 226
 227        val |= (u32)(cmd_type & 0x03) << 30;
 228        val |= (u32)(reg_addr & 0x3FFF) << 16;
 229        val |= (u32)mask << 8;
 230        val |= (u32)data;
 231
 232        spin_lock_irqsave(&pcr->lock, flags);
 233        ptr += pcr->ci;
 234        if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
 235                put_unaligned_le32(val, ptr);
 236                ptr++;
 237                pcr->ci++;
 238        }
 239        spin_unlock_irqrestore(&pcr->lock, flags);
 240}
 241EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
 242
 243void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
 244{
 245        u32 val = 1 << 31;
 246
 247        rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
 248
 249        val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
 250        /* Hardware Auto Response */
 251        val |= 0x40000000;
 252        rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
 253}
 254EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait);
 255
 256int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
 257{
 258        struct completion trans_done;
 259        u32 val = 1 << 31;
 260        long timeleft;
 261        unsigned long flags;
 262        int err = 0;
 263
 264        spin_lock_irqsave(&pcr->lock, flags);
 265
 266        /* set up data structures for the wakeup system */
 267        pcr->done = &trans_done;
 268        pcr->trans_result = TRANS_NOT_READY;
 269        init_completion(&trans_done);
 270
 271        rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
 272
 273        val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
 274        /* Hardware Auto Response */
 275        val |= 0x40000000;
 276        rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
 277
 278        spin_unlock_irqrestore(&pcr->lock, flags);
 279
 280        /* Wait for TRANS_OK_INT */
 281        timeleft = wait_for_completion_interruptible_timeout(
 282                        &trans_done, msecs_to_jiffies(timeout));
 283        if (timeleft <= 0) {
 284                dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
 285                                __func__, __LINE__);
 286                err = -ETIMEDOUT;
 287                goto finish_send_cmd;
 288        }
 289
 290        spin_lock_irqsave(&pcr->lock, flags);
 291        if (pcr->trans_result == TRANS_RESULT_FAIL)
 292                err = -EINVAL;
 293        else if (pcr->trans_result == TRANS_RESULT_OK)
 294                err = 0;
 295        else if (pcr->trans_result == TRANS_NO_DEVICE)
 296                err = -ENODEV;
 297        spin_unlock_irqrestore(&pcr->lock, flags);
 298
 299finish_send_cmd:
 300        spin_lock_irqsave(&pcr->lock, flags);
 301        pcr->done = NULL;
 302        spin_unlock_irqrestore(&pcr->lock, flags);
 303
 304        if ((err < 0) && (err != -ENODEV))
 305                rtsx_pci_stop_cmd(pcr);
 306
 307        if (pcr->finish_me)
 308                complete(pcr->finish_me);
 309
 310        return err;
 311}
 312EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd);
 313
 314static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
 315                dma_addr_t addr, unsigned int len, int end)
 316{
 317        u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
 318        u64 val;
 319        u8 option = SG_VALID | SG_TRANS_DATA;
 320
 321        dev_dbg(&(pcr->pci->dev), "DMA addr: 0x%x, Len: 0x%x\n",
 322                        (unsigned int)addr, len);
 323
 324        if (end)
 325                option |= SG_END;
 326        val = ((u64)addr << 32) | ((u64)len << 12) | option;
 327
 328        put_unaligned_le64(val, ptr);
 329        pcr->sgi++;
 330}
 331
 332int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
 333                int num_sg, bool read, int timeout)
 334{
 335        struct completion trans_done;
 336        u8 dir;
 337        int err = 0, i, count;
 338        long timeleft;
 339        unsigned long flags;
 340        struct scatterlist *sg;
 341        enum dma_data_direction dma_dir;
 342        u32 val;
 343        dma_addr_t addr;
 344        unsigned int len;
 345
 346        dev_dbg(&(pcr->pci->dev), "--> %s: num_sg = %d\n", __func__, num_sg);
 347
 348        /* don't transfer data during abort processing */
 349        if (pcr->remove_pci)
 350                return -EINVAL;
 351
 352        if ((sglist == NULL) || (num_sg <= 0))
 353                return -EINVAL;
 354
 355        if (read) {
 356                dir = DEVICE_TO_HOST;
 357                dma_dir = DMA_FROM_DEVICE;
 358        } else {
 359                dir = HOST_TO_DEVICE;
 360                dma_dir = DMA_TO_DEVICE;
 361        }
 362
 363        count = dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dma_dir);
 364        if (count < 1) {
 365                dev_err(&(pcr->pci->dev), "scatterlist map failed\n");
 366                return -EINVAL;
 367        }
 368        dev_dbg(&(pcr->pci->dev), "DMA mapping count: %d\n", count);
 369
 370        val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE;
 371        pcr->sgi = 0;
 372        for_each_sg(sglist, sg, count, i) {
 373                addr = sg_dma_address(sg);
 374                len = sg_dma_len(sg);
 375                rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1);
 376        }
 377
 378        spin_lock_irqsave(&pcr->lock, flags);
 379
 380        pcr->done = &trans_done;
 381        pcr->trans_result = TRANS_NOT_READY;
 382        init_completion(&trans_done);
 383        rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
 384        rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
 385
 386        spin_unlock_irqrestore(&pcr->lock, flags);
 387
 388        timeleft = wait_for_completion_interruptible_timeout(
 389                        &trans_done, msecs_to_jiffies(timeout));
 390        if (timeleft <= 0) {
 391                dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
 392                                __func__, __LINE__);
 393                err = -ETIMEDOUT;
 394                goto out;
 395        }
 396
 397        spin_lock_irqsave(&pcr->lock, flags);
 398
 399        if (pcr->trans_result == TRANS_RESULT_FAIL)
 400                err = -EINVAL;
 401        else if (pcr->trans_result == TRANS_NO_DEVICE)
 402                err = -ENODEV;
 403
 404        spin_unlock_irqrestore(&pcr->lock, flags);
 405
 406out:
 407        spin_lock_irqsave(&pcr->lock, flags);
 408        pcr->done = NULL;
 409        spin_unlock_irqrestore(&pcr->lock, flags);
 410
 411        dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dma_dir);
 412
 413        if ((err < 0) && (err != -ENODEV))
 414                rtsx_pci_stop_cmd(pcr);
 415
 416        if (pcr->finish_me)
 417                complete(pcr->finish_me);
 418
 419        return err;
 420}
 421EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data);
 422
 423int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
 424{
 425        int err;
 426        int i, j;
 427        u16 reg;
 428        u8 *ptr;
 429
 430        if (buf_len > 512)
 431                buf_len = 512;
 432
 433        ptr = buf;
 434        reg = PPBUF_BASE2;
 435        for (i = 0; i < buf_len / 256; i++) {
 436                rtsx_pci_init_cmd(pcr);
 437
 438                for (j = 0; j < 256; j++)
 439                        rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
 440
 441                err = rtsx_pci_send_cmd(pcr, 250);
 442                if (err < 0)
 443                        return err;
 444
 445                memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
 446                ptr += 256;
 447        }
 448
 449        if (buf_len % 256) {
 450                rtsx_pci_init_cmd(pcr);
 451
 452                for (j = 0; j < buf_len % 256; j++)
 453                        rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
 454
 455                err = rtsx_pci_send_cmd(pcr, 250);
 456                if (err < 0)
 457                        return err;
 458        }
 459
 460        memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
 461
 462        return 0;
 463}
 464EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf);
 465
 466int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
 467{
 468        int err;
 469        int i, j;
 470        u16 reg;
 471        u8 *ptr;
 472
 473        if (buf_len > 512)
 474                buf_len = 512;
 475
 476        ptr = buf;
 477        reg = PPBUF_BASE2;
 478        for (i = 0; i < buf_len / 256; i++) {
 479                rtsx_pci_init_cmd(pcr);
 480
 481                for (j = 0; j < 256; j++) {
 482                        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 483                                        reg++, 0xFF, *ptr);
 484                        ptr++;
 485                }
 486
 487                err = rtsx_pci_send_cmd(pcr, 250);
 488                if (err < 0)
 489                        return err;
 490        }
 491
 492        if (buf_len % 256) {
 493                rtsx_pci_init_cmd(pcr);
 494
 495                for (j = 0; j < buf_len % 256; j++) {
 496                        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 497                                        reg++, 0xFF, *ptr);
 498                        ptr++;
 499                }
 500
 501                err = rtsx_pci_send_cmd(pcr, 250);
 502                if (err < 0)
 503                        return err;
 504        }
 505
 506        return 0;
 507}
 508EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf);
 509
 510static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
 511{
 512        int err;
 513
 514        rtsx_pci_init_cmd(pcr);
 515
 516        while (*tbl & 0xFFFF0000) {
 517                rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 518                                (u16)(*tbl >> 16), 0xFF, (u8)(*tbl));
 519                tbl++;
 520        }
 521
 522        err = rtsx_pci_send_cmd(pcr, 100);
 523        if (err < 0)
 524                return err;
 525
 526        return 0;
 527}
 528
 529int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
 530{
 531        const u32 *tbl;
 532
 533        if (card == RTSX_SD_CARD)
 534                tbl = pcr->sd_pull_ctl_enable_tbl;
 535        else if (card == RTSX_MS_CARD)
 536                tbl = pcr->ms_pull_ctl_enable_tbl;
 537        else
 538                return -EINVAL;
 539
 540        return rtsx_pci_set_pull_ctl(pcr, tbl);
 541}
 542EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable);
 543
 544int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
 545{
 546        const u32 *tbl;
 547
 548        if (card == RTSX_SD_CARD)
 549                tbl = pcr->sd_pull_ctl_disable_tbl;
 550        else if (card == RTSX_MS_CARD)
 551                tbl = pcr->ms_pull_ctl_disable_tbl;
 552        else
 553                return -EINVAL;
 554
 555
 556        return rtsx_pci_set_pull_ctl(pcr, tbl);
 557}
 558EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
 559
 560static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
 561{
 562        pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN;
 563
 564        if (pcr->num_slots > 1)
 565                pcr->bier |= MS_INT_EN;
 566
 567        /* Enable Bus Interrupt */
 568        rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
 569
 570        dev_dbg(&(pcr->pci->dev), "RTSX_BIER: 0x%08x\n", pcr->bier);
 571}
 572
 573static inline u8 double_ssc_depth(u8 depth)
 574{
 575        return ((depth > 1) ? (depth - 1) : depth);
 576}
 577
 578static u8 revise_ssc_depth(u8 ssc_depth, u8 div)
 579{
 580        if (div > CLK_DIV_1) {
 581                if (ssc_depth > (div - 1))
 582                        ssc_depth -= (div - 1);
 583                else
 584                        ssc_depth = SSC_DEPTH_4M;
 585        }
 586
 587        return ssc_depth;
 588}
 589
 590int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
 591                u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
 592{
 593        int err, clk;
 594        u8 n, clk_divider, mcu_cnt, div;
 595        u8 depth[] = {
 596                [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M,
 597                [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M,
 598                [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
 599                [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
 600                [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
 601        };
 602
 603        if (initial_mode) {
 604                /* We use 250k(around) here, in initial stage */
 605                clk_divider = SD_CLK_DIVIDE_128;
 606                card_clock = 30000000;
 607        } else {
 608                clk_divider = SD_CLK_DIVIDE_0;
 609        }
 610        err = rtsx_pci_write_register(pcr, SD_CFG1,
 611                        SD_CLK_DIVIDE_MASK, clk_divider);
 612        if (err < 0)
 613                return err;
 614
 615        card_clock /= 1000000;
 616        dev_dbg(&(pcr->pci->dev), "Switch card clock to %dMHz\n", card_clock);
 617
 618        clk = card_clock;
 619        if (!initial_mode && double_clk)
 620                clk = card_clock * 2;
 621        dev_dbg(&(pcr->pci->dev),
 622                        "Internal SSC clock: %dMHz (cur_clock = %d)\n",
 623                        clk, pcr->cur_clock);
 624
 625        if (clk == pcr->cur_clock)
 626                return 0;
 627
 628        if (pcr->ops->conv_clk_and_div_n)
 629                n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
 630        else
 631                n = (u8)(clk - 2);
 632        if ((clk <= 2) || (n > MAX_DIV_N_PCR))
 633                return -EINVAL;
 634
 635        mcu_cnt = (u8)(125/clk + 3);
 636        if (mcu_cnt > 15)
 637                mcu_cnt = 15;
 638
 639        /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */
 640        div = CLK_DIV_1;
 641        while ((n < MIN_DIV_N_PCR) && (div < CLK_DIV_8)) {
 642                if (pcr->ops->conv_clk_and_div_n) {
 643                        int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
 644                                        DIV_N_TO_CLK) * 2;
 645                        n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk,
 646                                        CLK_TO_DIV_N);
 647                } else {
 648                        n = (n + 2) * 2 - 2;
 649                }
 650                div++;
 651        }
 652        dev_dbg(&(pcr->pci->dev), "n = %d, div = %d\n", n, div);
 653
 654        ssc_depth = depth[ssc_depth];
 655        if (double_clk)
 656                ssc_depth = double_ssc_depth(ssc_depth);
 657
 658        ssc_depth = revise_ssc_depth(ssc_depth, div);
 659        dev_dbg(&(pcr->pci->dev), "ssc_depth = %d\n", ssc_depth);
 660
 661        rtsx_pci_init_cmd(pcr);
 662        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
 663                        CLK_LOW_FREQ, CLK_LOW_FREQ);
 664        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
 665                        0xFF, (div << 4) | mcu_cnt);
 666        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
 667        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
 668                        SSC_DEPTH_MASK, ssc_depth);
 669        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
 670        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
 671        if (vpclk) {
 672                rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
 673                                PHASE_NOT_RESET, 0);
 674                rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
 675                                PHASE_NOT_RESET, PHASE_NOT_RESET);
 676        }
 677
 678        err = rtsx_pci_send_cmd(pcr, 2000);
 679        if (err < 0)
 680                return err;
 681
 682        /* Wait SSC clock stable */
 683        udelay(10);
 684        err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
 685        if (err < 0)
 686                return err;
 687
 688        pcr->cur_clock = clk;
 689        return 0;
 690}
 691EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock);
 692
 693int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
 694{
 695        if (pcr->ops->card_power_on)
 696                return pcr->ops->card_power_on(pcr, card);
 697
 698        return 0;
 699}
 700EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on);
 701
 702int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
 703{
 704        if (pcr->ops->card_power_off)
 705                return pcr->ops->card_power_off(pcr, card);
 706
 707        return 0;
 708}
 709EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off);
 710
 711int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card)
 712{
 713        unsigned int cd_mask[] = {
 714                [RTSX_SD_CARD] = SD_EXIST,
 715                [RTSX_MS_CARD] = MS_EXIST
 716        };
 717
 718        if (!pcr->ms_pmos) {
 719                /* When using single PMOS, accessing card is not permitted
 720                 * if the existing card is not the designated one.
 721                 */
 722                if (pcr->card_exist & (~cd_mask[card]))
 723                        return -EIO;
 724        }
 725
 726        return 0;
 727}
 728EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check);
 729
 730int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 731{
 732        if (pcr->ops->switch_output_voltage)
 733                return pcr->ops->switch_output_voltage(pcr, voltage);
 734
 735        return 0;
 736}
 737EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage);
 738
 739unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
 740{
 741        unsigned int val;
 742
 743        val = rtsx_pci_readl(pcr, RTSX_BIPR);
 744        if (pcr->ops->cd_deglitch)
 745                val = pcr->ops->cd_deglitch(pcr);
 746
 747        return val;
 748}
 749EXPORT_SYMBOL_GPL(rtsx_pci_card_exist);
 750
 751void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
 752{
 753        struct completion finish;
 754
 755        pcr->finish_me = &finish;
 756        init_completion(&finish);
 757
 758        if (pcr->done)
 759                complete(pcr->done);
 760
 761        if (!pcr->remove_pci)
 762                rtsx_pci_stop_cmd(pcr);
 763
 764        wait_for_completion_interruptible_timeout(&finish,
 765                        msecs_to_jiffies(2));
 766        pcr->finish_me = NULL;
 767}
 768EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer);
 769
 770static void rtsx_pci_card_detect(struct work_struct *work)
 771{
 772        struct delayed_work *dwork;
 773        struct rtsx_pcr *pcr;
 774        unsigned long flags;
 775        unsigned int card_detect = 0, card_inserted, card_removed;
 776        u32 irq_status;
 777
 778        dwork = to_delayed_work(work);
 779        pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
 780
 781        dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
 782
 783        mutex_lock(&pcr->pcr_mutex);
 784        spin_lock_irqsave(&pcr->lock, flags);
 785
 786        irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
 787        dev_dbg(&(pcr->pci->dev), "irq_status: 0x%08x\n", irq_status);
 788
 789        irq_status &= CARD_EXIST;
 790        card_inserted = pcr->card_inserted & irq_status;
 791        card_removed = pcr->card_removed;
 792        pcr->card_inserted = 0;
 793        pcr->card_removed = 0;
 794
 795        spin_unlock_irqrestore(&pcr->lock, flags);
 796
 797        if (card_inserted || card_removed) {
 798                dev_dbg(&(pcr->pci->dev),
 799                                "card_inserted: 0x%x, card_removed: 0x%x\n",
 800                                card_inserted, card_removed);
 801
 802                if (pcr->ops->cd_deglitch)
 803                        card_inserted = pcr->ops->cd_deglitch(pcr);
 804
 805                card_detect = card_inserted | card_removed;
 806
 807                pcr->card_exist |= card_inserted;
 808                pcr->card_exist &= ~card_removed;
 809        }
 810
 811        mutex_unlock(&pcr->pcr_mutex);
 812
 813        if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event)
 814                pcr->slots[RTSX_SD_CARD].card_event(
 815                                pcr->slots[RTSX_SD_CARD].p_dev);
 816        if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event)
 817                pcr->slots[RTSX_MS_CARD].card_event(
 818                                pcr->slots[RTSX_MS_CARD].p_dev);
 819}
 820
 821static irqreturn_t rtsx_pci_isr(int irq, void *dev_id)
 822{
 823        struct rtsx_pcr *pcr = dev_id;
 824        u32 int_reg;
 825
 826        if (!pcr)
 827                return IRQ_NONE;
 828
 829        spin_lock(&pcr->lock);
 830
 831        int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
 832        /* Clear interrupt flag */
 833        rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
 834        if ((int_reg & pcr->bier) == 0) {
 835                spin_unlock(&pcr->lock);
 836                return IRQ_NONE;
 837        }
 838        if (int_reg == 0xFFFFFFFF) {
 839                spin_unlock(&pcr->lock);
 840                return IRQ_HANDLED;
 841        }
 842
 843        int_reg &= (pcr->bier | 0x7FFFFF);
 844
 845        if (int_reg & SD_INT) {
 846                if (int_reg & SD_EXIST) {
 847                        pcr->card_inserted |= SD_EXIST;
 848                } else {
 849                        pcr->card_removed |= SD_EXIST;
 850                        pcr->card_inserted &= ~SD_EXIST;
 851                }
 852        }
 853
 854        if (int_reg & MS_INT) {
 855                if (int_reg & MS_EXIST) {
 856                        pcr->card_inserted |= MS_EXIST;
 857                } else {
 858                        pcr->card_removed |= MS_EXIST;
 859                        pcr->card_inserted &= ~MS_EXIST;
 860                }
 861        }
 862
 863        if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) {
 864                if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) {
 865                        pcr->trans_result = TRANS_RESULT_FAIL;
 866                        if (pcr->done)
 867                                complete(pcr->done);
 868                } else if (int_reg & TRANS_OK_INT) {
 869                        pcr->trans_result = TRANS_RESULT_OK;
 870                        if (pcr->done)
 871                                complete(pcr->done);
 872                }
 873        }
 874
 875        if (pcr->card_inserted || pcr->card_removed)
 876                schedule_delayed_work(&pcr->carddet_work,
 877                                msecs_to_jiffies(200));
 878
 879        spin_unlock(&pcr->lock);
 880        return IRQ_HANDLED;
 881}
 882
 883static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
 884{
 885        dev_info(&(pcr->pci->dev), "%s: pcr->msi_en = %d, pci->irq = %d\n",
 886                        __func__, pcr->msi_en, pcr->pci->irq);
 887
 888        if (request_irq(pcr->pci->irq, rtsx_pci_isr,
 889                        pcr->msi_en ? 0 : IRQF_SHARED,
 890                        DRV_NAME_RTSX_PCI, pcr)) {
 891                dev_err(&(pcr->pci->dev),
 892                        "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
 893                        pcr->pci->irq);
 894                return -1;
 895        }
 896
 897        pcr->irq = pcr->pci->irq;
 898        pci_intx(pcr->pci, !pcr->msi_en);
 899
 900        return 0;
 901}
 902
 903static void rtsx_pci_idle_work(struct work_struct *work)
 904{
 905        struct delayed_work *dwork = to_delayed_work(work);
 906        struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work);
 907
 908        dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
 909
 910        mutex_lock(&pcr->pcr_mutex);
 911
 912        pcr->state = PDEV_STAT_IDLE;
 913
 914        if (pcr->ops->disable_auto_blink)
 915                pcr->ops->disable_auto_blink(pcr);
 916        if (pcr->ops->turn_off_led)
 917                pcr->ops->turn_off_led(pcr);
 918
 919        mutex_unlock(&pcr->pcr_mutex);
 920}
 921
 922static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
 923{
 924        int err;
 925
 926        rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
 927
 928        rtsx_pci_enable_bus_int(pcr);
 929
 930        /* Power on SSC */
 931        err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
 932        if (err < 0)
 933                return err;
 934
 935        /* Wait SSC power stable */
 936        udelay(200);
 937
 938        if (pcr->ops->optimize_phy) {
 939                err = pcr->ops->optimize_phy(pcr);
 940                if (err < 0)
 941                        return err;
 942        }
 943
 944        rtsx_pci_init_cmd(pcr);
 945
 946        /* Set mcu_cnt to 7 to ensure data can be sampled properly */
 947        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
 948
 949        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
 950        /* Disable card clock */
 951        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
 952        /* Reset ASPM state to default value */
 953        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
 954        /* Reset delink mode */
 955        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
 956        /* Card driving select */
 957        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
 958                        0x07, DRIVER_TYPE_D);
 959        /* Enable SSC Clock */
 960        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
 961                        0xFF, SSC_8X_EN | SSC_SEL_4M);
 962        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
 963        /* Disable cd_pwr_save */
 964        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
 965        /* Clear Link Ready Interrupt */
 966        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
 967                        LINK_RDY_INT, LINK_RDY_INT);
 968        /* Enlarge the estimation window of PERST# glitch
 969         * to reduce the chance of invalid card interrupt
 970         */
 971        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
 972        /* Update RC oscillator to 400k
 973         * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
 974         *                1: 2M  0: 400k
 975         */
 976        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
 977        /* Set interrupt write clear
 978         * bit 1: U_elbi_if_rd_clr_en
 979         *      1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
 980         *      0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
 981         */
 982        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
 983        /* Force CLKREQ# PIN to drive 0 to request clock */
 984        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08);
 985
 986        err = rtsx_pci_send_cmd(pcr, 100);
 987        if (err < 0)
 988                return err;
 989
 990        /* Enable clk_request_n to enable clock power management */
 991        rtsx_pci_write_config_byte(pcr, 0x81, 1);
 992        /* Enter L1 when host tx idle */
 993        rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B);
 994
 995        if (pcr->ops->extra_init_hw) {
 996                err = pcr->ops->extra_init_hw(pcr);
 997                if (err < 0)
 998                        return err;
 999        }
1000
1001        /* No CD interrupt if probing driver with card inserted.
1002         * So we need to initialize pcr->card_exist here.
1003         */
1004        if (pcr->ops->cd_deglitch)
1005                pcr->card_exist = pcr->ops->cd_deglitch(pcr);
1006        else
1007                pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST;
1008
1009        return 0;
1010}
1011
1012static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
1013{
1014        int err;
1015
1016        spin_lock_init(&pcr->lock);
1017        mutex_init(&pcr->pcr_mutex);
1018
1019        switch (PCI_PID(pcr)) {
1020        default:
1021        case 0x5209:
1022                rts5209_init_params(pcr);
1023                break;
1024
1025        case 0x5229:
1026                rts5229_init_params(pcr);
1027                break;
1028
1029        case 0x5289:
1030                rtl8411_init_params(pcr);
1031                break;
1032
1033        case 0x5227:
1034                rts5227_init_params(pcr);
1035                break;
1036        }
1037
1038        dev_dbg(&(pcr->pci->dev), "PID: 0x%04x, IC version: 0x%02x\n",
1039                        PCI_PID(pcr), pcr->ic_version);
1040
1041        pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
1042                        GFP_KERNEL);
1043        if (!pcr->slots)
1044                return -ENOMEM;
1045
1046        pcr->state = PDEV_STAT_IDLE;
1047        err = rtsx_pci_init_hw(pcr);
1048        if (err < 0) {
1049                kfree(pcr->slots);
1050                return err;
1051        }
1052
1053        return 0;
1054}
1055
1056static int rtsx_pci_probe(struct pci_dev *pcidev,
1057                          const struct pci_device_id *id)
1058{
1059        struct rtsx_pcr *pcr;
1060        struct pcr_handle *handle;
1061        u32 base, len;
1062        int ret, i;
1063
1064        dev_dbg(&(pcidev->dev),
1065                ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
1066                pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1067                (int)pcidev->revision);
1068
1069        ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
1070        if (ret < 0)
1071                return ret;
1072
1073        ret = pci_enable_device(pcidev);
1074        if (ret)
1075                return ret;
1076
1077        ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI);
1078        if (ret)
1079                goto disable;
1080
1081        pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
1082        if (!pcr) {
1083                ret = -ENOMEM;
1084                goto release_pci;
1085        }
1086
1087        handle = kzalloc(sizeof(*handle), GFP_KERNEL);
1088        if (!handle) {
1089                ret = -ENOMEM;
1090                goto free_pcr;
1091        }
1092        handle->pcr = pcr;
1093
1094        idr_preload(GFP_KERNEL);
1095        spin_lock(&rtsx_pci_lock);
1096        ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT);
1097        if (ret >= 0)
1098                pcr->id = ret;
1099        spin_unlock(&rtsx_pci_lock);
1100        idr_preload_end();
1101        if (ret < 0)
1102                goto free_handle;
1103
1104        pcr->pci = pcidev;
1105        dev_set_drvdata(&pcidev->dev, handle);
1106
1107        len = pci_resource_len(pcidev, 0);
1108        base = pci_resource_start(pcidev, 0);
1109        pcr->remap_addr = ioremap_nocache(base, len);
1110        if (!pcr->remap_addr) {
1111                ret = -ENOMEM;
1112                goto free_host;
1113        }
1114
1115        pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
1116                        RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
1117                        GFP_KERNEL);
1118        if (pcr->rtsx_resv_buf == NULL) {
1119                ret = -ENXIO;
1120                goto unmap;
1121        }
1122        pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
1123        pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
1124        pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
1125        pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
1126
1127        pcr->card_inserted = 0;
1128        pcr->card_removed = 0;
1129        INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
1130        INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work);
1131
1132        pcr->msi_en = msi_en;
1133        if (pcr->msi_en) {
1134                ret = pci_enable_msi(pcidev);
1135                if (ret < 0)
1136                        pcr->msi_en = false;
1137        }
1138
1139        ret = rtsx_pci_acquire_irq(pcr);
1140        if (ret < 0)
1141                goto free_dma;
1142
1143        pci_set_master(pcidev);
1144        synchronize_irq(pcr->irq);
1145
1146        ret = rtsx_pci_init_chip(pcr);
1147        if (ret < 0)
1148                goto disable_irq;
1149
1150        for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) {
1151                rtsx_pcr_cells[i].platform_data = handle;
1152                rtsx_pcr_cells[i].pdata_size = sizeof(*handle);
1153        }
1154        ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
1155                        ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL);
1156        if (ret < 0)
1157                goto disable_irq;
1158
1159        schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1160
1161        return 0;
1162
1163disable_irq:
1164        free_irq(pcr->irq, (void *)pcr);
1165free_dma:
1166        dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1167                        pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1168unmap:
1169        iounmap(pcr->remap_addr);
1170free_host:
1171        dev_set_drvdata(&pcidev->dev, NULL);
1172free_handle:
1173        kfree(handle);
1174free_pcr:
1175        kfree(pcr);
1176release_pci:
1177        pci_release_regions(pcidev);
1178disable:
1179        pci_disable_device(pcidev);
1180
1181        return ret;
1182}
1183
1184static void rtsx_pci_remove(struct pci_dev *pcidev)
1185{
1186        struct pcr_handle *handle = pci_get_drvdata(pcidev);
1187        struct rtsx_pcr *pcr = handle->pcr;
1188
1189        pcr->remove_pci = true;
1190
1191        cancel_delayed_work(&pcr->carddet_work);
1192        cancel_delayed_work(&pcr->idle_work);
1193
1194        mfd_remove_devices(&pcidev->dev);
1195
1196        dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1197                        pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1198        free_irq(pcr->irq, (void *)pcr);
1199        if (pcr->msi_en)
1200                pci_disable_msi(pcr->pci);
1201        iounmap(pcr->remap_addr);
1202
1203        dev_set_drvdata(&pcidev->dev, NULL);
1204        pci_release_regions(pcidev);
1205        pci_disable_device(pcidev);
1206
1207        spin_lock(&rtsx_pci_lock);
1208        idr_remove(&rtsx_pci_idr, pcr->id);
1209        spin_unlock(&rtsx_pci_lock);
1210
1211        kfree(pcr->slots);
1212        kfree(pcr);
1213        kfree(handle);
1214
1215        dev_dbg(&(pcidev->dev),
1216                ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
1217                pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1218}
1219
1220#ifdef CONFIG_PM
1221
1222static int rtsx_pci_suspend(struct pci_dev *pcidev, pm_message_t state)
1223{
1224        struct pcr_handle *handle;
1225        struct rtsx_pcr *pcr;
1226        int ret = 0;
1227
1228        dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1229
1230        handle = pci_get_drvdata(pcidev);
1231        pcr = handle->pcr;
1232
1233        cancel_delayed_work(&pcr->carddet_work);
1234        cancel_delayed_work(&pcr->idle_work);
1235
1236        mutex_lock(&pcr->pcr_mutex);
1237
1238        if (pcr->ops->turn_off_led)
1239                pcr->ops->turn_off_led(pcr);
1240
1241        rtsx_pci_writel(pcr, RTSX_BIER, 0);
1242        pcr->bier = 0;
1243
1244        rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
1245        rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x02);
1246
1247        pci_save_state(pcidev);
1248        pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1249        pci_disable_device(pcidev);
1250        pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1251
1252        mutex_unlock(&pcr->pcr_mutex);
1253        return ret;
1254}
1255
1256static int rtsx_pci_resume(struct pci_dev *pcidev)
1257{
1258        struct pcr_handle *handle;
1259        struct rtsx_pcr *pcr;
1260        int ret = 0;
1261
1262        dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1263
1264        handle = pci_get_drvdata(pcidev);
1265        pcr = handle->pcr;
1266
1267        mutex_lock(&pcr->pcr_mutex);
1268
1269        pci_set_power_state(pcidev, PCI_D0);
1270        pci_restore_state(pcidev);
1271        ret = pci_enable_device(pcidev);
1272        if (ret)
1273                goto out;
1274        pci_set_master(pcidev);
1275
1276        ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1277        if (ret)
1278                goto out;
1279
1280        ret = rtsx_pci_init_hw(pcr);
1281        if (ret)
1282                goto out;
1283
1284        schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1285
1286out:
1287        mutex_unlock(&pcr->pcr_mutex);
1288        return ret;
1289}
1290
1291#else /* CONFIG_PM */
1292
1293#define rtsx_pci_suspend NULL
1294#define rtsx_pci_resume NULL
1295
1296#endif /* CONFIG_PM */
1297
1298static struct pci_driver rtsx_pci_driver = {
1299        .name = DRV_NAME_RTSX_PCI,
1300        .id_table = rtsx_pci_ids,
1301        .probe = rtsx_pci_probe,
1302        .remove = rtsx_pci_remove,
1303        .suspend = rtsx_pci_suspend,
1304        .resume = rtsx_pci_resume,
1305};
1306module_pci_driver(rtsx_pci_driver);
1307
1308MODULE_LICENSE("GPL");
1309MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1310MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");
1311
lxr.linux.no kindly hosted by Redpill Linpro AS, provider of Linux consulting and operations services since 1995.