linux/drivers/irqchip/irq-bcm2835.c
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   1/*
   2 * Copyright 2010 Broadcom
   3 * Copyright 2012 Simon Arlott, Chris Boot, Stephen Warren
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License as published by
   7 * the Free Software Foundation; either version 2 of the License, or
   8 * (at your option) any later version.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * Quirk 1: Shortcut interrupts don't set the bank 1/2 register pending bits
  16 *
  17 * If an interrupt fires on bank 1 that isn't in the shortcuts list, bit 8
  18 * on bank 0 is set to signify that an interrupt in bank 1 has fired, and
  19 * to look in the bank 1 status register for more information.
  20 *
  21 * If an interrupt fires on bank 1 that _is_ in the shortcuts list, its
  22 * shortcut bit in bank 0 is set as well as its interrupt bit in the bank 1
  23 * status register, but bank 0 bit 8 is _not_ set.
  24 *
  25 * Quirk 2: You can't mask the register 1/2 pending interrupts
  26 *
  27 * In a proper cascaded interrupt controller, the interrupt lines with
  28 * cascaded interrupt controllers on them are just normal interrupt lines.
  29 * You can mask the interrupts and get on with things. With this controller
  30 * you can't do that.
  31 *
  32 * Quirk 3: The shortcut interrupts can't be (un)masked in bank 0
  33 *
  34 * Those interrupts that have shortcuts can only be masked/unmasked in
  35 * their respective banks' enable/disable registers. Doing so in the bank 0
  36 * enable/disable registers has no effect.
  37 *
  38 * The FIQ control register:
  39 *  Bits 0-6: IRQ (index in order of interrupts from banks 1, 2, then 0)
  40 *  Bit    7: Enable FIQ generation
  41 *  Bits  8+: Unused
  42 *
  43 * An interrupt must be disabled before configuring it for FIQ generation
  44 * otherwise both handlers will fire at the same time!
  45 */
  46
  47#include <linux/io.h>
  48#include <linux/slab.h>
  49#include <linux/of_address.h>
  50#include <linux/of_irq.h>
  51#include <linux/irqdomain.h>
  52#include <linux/irqchip/bcm2835.h>
  53
  54#include <asm/exception.h>
  55
  56/* Put the bank and irq (32 bits) into the hwirq */
  57#define MAKE_HWIRQ(b, n)        ((b << 5) | (n))
  58#define HWIRQ_BANK(i)           (i >> 5)
  59#define HWIRQ_BIT(i)            BIT(i & 0x1f)
  60
  61#define NR_IRQS_BANK0           8
  62#define BANK0_HWIRQ_MASK        0xff
  63/* Shortcuts can't be disabled so any unknown new ones need to be masked */
  64#define SHORTCUT1_MASK          0x00007c00
  65#define SHORTCUT2_MASK          0x001f8000
  66#define SHORTCUT_SHIFT          10
  67#define BANK1_HWIRQ             BIT(8)
  68#define BANK2_HWIRQ             BIT(9)
  69#define BANK0_VALID_MASK        (BANK0_HWIRQ_MASK | BANK1_HWIRQ | BANK2_HWIRQ \
  70                                        | SHORTCUT1_MASK | SHORTCUT2_MASK)
  71
  72#define REG_FIQ_CONTROL         0x0c
  73
  74#define NR_BANKS                3
  75#define IRQS_PER_BANK           32
  76
  77static int reg_pending[] __initconst = { 0x00, 0x04, 0x08 };
  78static int reg_enable[] __initconst = { 0x18, 0x10, 0x14 };
  79static int reg_disable[] __initconst = { 0x24, 0x1c, 0x20 };
  80static int bank_irqs[] __initconst = { 8, 32, 32 };
  81
  82static const int shortcuts[] = {
  83        7, 9, 10, 18, 19,               /* Bank 1 */
  84        21, 22, 23, 24, 25, 30          /* Bank 2 */
  85};
  86
  87struct armctrl_ic {
  88        void __iomem *base;
  89        void __iomem *pending[NR_BANKS];
  90        void __iomem *enable[NR_BANKS];
  91        void __iomem *disable[NR_BANKS];
  92        struct irq_domain *domain;
  93};
  94
  95static struct armctrl_ic intc __read_mostly;
  96
  97static void armctrl_mask_irq(struct irq_data *d)
  98{
  99        writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]);
 100}
 101
 102static void armctrl_unmask_irq(struct irq_data *d)
 103{
 104        writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]);
 105}
 106
 107static struct irq_chip armctrl_chip = {
 108        .name = "ARMCTRL-level",
 109        .irq_mask = armctrl_mask_irq,
 110        .irq_unmask = armctrl_unmask_irq
 111};
 112
 113static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
 114        const u32 *intspec, unsigned int intsize,
 115        unsigned long *out_hwirq, unsigned int *out_type)
 116{
 117        if (WARN_ON(intsize != 2))
 118                return -EINVAL;
 119
 120        if (WARN_ON(intspec[0] >= NR_BANKS))
 121                return -EINVAL;
 122
 123        if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
 124                return -EINVAL;
 125
 126        if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
 127                return -EINVAL;
 128
 129        *out_hwirq = MAKE_HWIRQ(intspec[0], intspec[1]);
 130        *out_type = IRQ_TYPE_NONE;
 131        return 0;
 132}
 133
 134static struct irq_domain_ops armctrl_ops = {
 135        .xlate = armctrl_xlate
 136};
 137
 138static int __init armctrl_of_init(struct device_node *node,
 139        struct device_node *parent)
 140{
 141        void __iomem *base;
 142        int irq, b, i;
 143
 144        base = of_iomap(node, 0);
 145        if (!base)
 146                panic("%s: unable to map IC registers\n",
 147                        node->full_name);
 148
 149        intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0),
 150                        &armctrl_ops, NULL);
 151        if (!intc.domain)
 152                panic("%s: unable to create IRQ domain\n", node->full_name);
 153
 154        for (b = 0; b < NR_BANKS; b++) {
 155                intc.pending[b] = base + reg_pending[b];
 156                intc.enable[b] = base + reg_enable[b];
 157                intc.disable[b] = base + reg_disable[b];
 158
 159                for (i = 0; i < bank_irqs[b]; i++) {
 160                        irq = irq_create_mapping(intc.domain, MAKE_HWIRQ(b, i));
 161                        BUG_ON(irq <= 0);
 162                        irq_set_chip_and_handler(irq, &armctrl_chip,
 163                                handle_level_irq);
 164                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 165                }
 166        }
 167        return 0;
 168}
 169
 170static struct of_device_id irq_of_match[] __initconst = {
 171        { .compatible = "brcm,bcm2835-armctrl-ic", .data = armctrl_of_init },
 172        { }
 173};
 174
 175void __init bcm2835_init_irq(void)
 176{
 177        of_irq_init(irq_of_match);
 178}
 179
 180/*
 181 * Handle each interrupt across the entire interrupt controller.  This reads the
 182 * status register before handling each interrupt, which is necessary given that
 183 * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
 184 */
 185
 186static void armctrl_handle_bank(int bank, struct pt_regs *regs)
 187{
 188        u32 stat, irq;
 189
 190        while ((stat = readl_relaxed(intc.pending[bank]))) {
 191                irq = MAKE_HWIRQ(bank, ffs(stat) - 1);
 192                handle_IRQ(irq_linear_revmap(intc.domain, irq), regs);
 193        }
 194}
 195
 196static void armctrl_handle_shortcut(int bank, struct pt_regs *regs,
 197        u32 stat)
 198{
 199        u32 irq = MAKE_HWIRQ(bank, shortcuts[ffs(stat >> SHORTCUT_SHIFT) - 1]);
 200        handle_IRQ(irq_linear_revmap(intc.domain, irq), regs);
 201}
 202
 203asmlinkage void __exception_irq_entry bcm2835_handle_irq(
 204        struct pt_regs *regs)
 205{
 206        u32 stat, irq;
 207
 208        while ((stat = readl_relaxed(intc.pending[0]) & BANK0_VALID_MASK)) {
 209                if (stat & BANK0_HWIRQ_MASK) {
 210                        irq = MAKE_HWIRQ(0, ffs(stat & BANK0_HWIRQ_MASK) - 1);
 211                        handle_IRQ(irq_linear_revmap(intc.domain, irq), regs);
 212                } else if (stat & SHORTCUT1_MASK) {
 213                        armctrl_handle_shortcut(1, regs, stat & SHORTCUT1_MASK);
 214                } else if (stat & SHORTCUT2_MASK) {
 215                        armctrl_handle_shortcut(2, regs, stat & SHORTCUT2_MASK);
 216                } else if (stat & BANK1_HWIRQ) {
 217                        armctrl_handle_bank(1, regs);
 218                } else if (stat & BANK2_HWIRQ) {
 219                        armctrl_handle_bank(2, regs);
 220                } else {
 221                        BUG();
 222                }
 223        }
 224}
 225
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