linux/include/linux/pci.h
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   1/*
   2 *      pci.h
   3 *
   4 *      PCI defines and function prototypes
   5 *      Copyright 1994, Drew Eckhardt
   6 *      Copyright 1997--1999 Martin Mares <mj@ucw.cz>
   7 *
   8 *      For more information, please consult the following manuals (look at
   9 *      http://www.pcisig.com/ for how to get them):
  10 *
  11 *      PCI BIOS Specification
  12 *      PCI Local Bus Specification
  13 *      PCI to PCI Bridge Specification
  14 *      PCI System Design Guide
  15 */
  16#ifndef LINUX_PCI_H
  17#define LINUX_PCI_H
  18
  19
  20#include <linux/mod_devicetable.h>
  21
  22#include <linux/types.h>
  23#include <linux/init.h>
  24#include <linux/ioport.h>
  25#include <linux/list.h>
  26#include <linux/compiler.h>
  27#include <linux/errno.h>
  28#include <linux/kobject.h>
  29#include <linux/atomic.h>
  30#include <linux/device.h>
  31#include <linux/io.h>
  32#include <linux/irqreturn.h>
  33#include <uapi/linux/pci.h>
  34
  35/* Include the ID list */
  36#include <linux/pci_ids.h>
  37
  38/* pci_slot represents a physical slot */
  39struct pci_slot {
  40        struct pci_bus *bus;            /* The bus this slot is on */
  41        struct list_head list;          /* node in list of slots on this bus */
  42        struct hotplug_slot *hotplug;   /* Hotplug info (migrate over time) */
  43        unsigned char number;           /* PCI_SLOT(pci_dev->devfn) */
  44        struct kobject kobj;
  45};
  46
  47static inline const char *pci_slot_name(const struct pci_slot *slot)
  48{
  49        return kobject_name(&slot->kobj);
  50}
  51
  52/* File state for mmap()s on /proc/bus/pci/X/Y */
  53enum pci_mmap_state {
  54        pci_mmap_io,
  55        pci_mmap_mem
  56};
  57
  58/* This defines the direction arg to the DMA mapping routines. */
  59#define PCI_DMA_BIDIRECTIONAL   0
  60#define PCI_DMA_TODEVICE        1
  61#define PCI_DMA_FROMDEVICE      2
  62#define PCI_DMA_NONE            3
  63
  64/*
  65 *  For PCI devices, the region numbers are assigned this way:
  66 */
  67enum {
  68        /* #0-5: standard PCI resources */
  69        PCI_STD_RESOURCES,
  70        PCI_STD_RESOURCE_END = 5,
  71
  72        /* #6: expansion ROM resource */
  73        PCI_ROM_RESOURCE,
  74
  75        /* device specific resources */
  76#ifdef CONFIG_PCI_IOV
  77        PCI_IOV_RESOURCES,
  78        PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
  79#endif
  80
  81        /* resources assigned to buses behind the bridge */
  82#define PCI_BRIDGE_RESOURCE_NUM 4
  83
  84        PCI_BRIDGE_RESOURCES,
  85        PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
  86                                  PCI_BRIDGE_RESOURCE_NUM - 1,
  87
  88        /* total resources associated with a PCI device */
  89        PCI_NUM_RESOURCES,
  90
  91        /* preserve this for compatibility */
  92        DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
  93};
  94
  95typedef int __bitwise pci_power_t;
  96
  97#define PCI_D0          ((pci_power_t __force) 0)
  98#define PCI_D1          ((pci_power_t __force) 1)
  99#define PCI_D2          ((pci_power_t __force) 2)
 100#define PCI_D3hot       ((pci_power_t __force) 3)
 101#define PCI_D3cold      ((pci_power_t __force) 4)
 102#define PCI_UNKNOWN     ((pci_power_t __force) 5)
 103#define PCI_POWER_ERROR ((pci_power_t __force) -1)
 104
 105/* Remember to update this when the list above changes! */
 106extern const char *pci_power_names[];
 107
 108static inline const char *pci_power_name(pci_power_t state)
 109{
 110        return pci_power_names[1 + (int) state];
 111}
 112
 113#define PCI_PM_D2_DELAY         200
 114#define PCI_PM_D3_WAIT          10
 115#define PCI_PM_D3COLD_WAIT      100
 116#define PCI_PM_BUS_WAIT         50
 117
 118/** The pci_channel state describes connectivity between the CPU and
 119 *  the pci device.  If some PCI bus between here and the pci device
 120 *  has crashed or locked up, this info is reflected here.
 121 */
 122typedef unsigned int __bitwise pci_channel_state_t;
 123
 124enum pci_channel_state {
 125        /* I/O channel is in normal state */
 126        pci_channel_io_normal = (__force pci_channel_state_t) 1,
 127
 128        /* I/O to channel is blocked */
 129        pci_channel_io_frozen = (__force pci_channel_state_t) 2,
 130
 131        /* PCI card is dead */
 132        pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
 133};
 134
 135typedef unsigned int __bitwise pcie_reset_state_t;
 136
 137enum pcie_reset_state {
 138        /* Reset is NOT asserted (Use to deassert reset) */
 139        pcie_deassert_reset = (__force pcie_reset_state_t) 1,
 140
 141        /* Use #PERST to reset PCI-E device */
 142        pcie_warm_reset = (__force pcie_reset_state_t) 2,
 143
 144        /* Use PCI-E Hot Reset to reset device */
 145        pcie_hot_reset = (__force pcie_reset_state_t) 3
 146};
 147
 148typedef unsigned short __bitwise pci_dev_flags_t;
 149enum pci_dev_flags {
 150        /* INTX_DISABLE in PCI_COMMAND register disables MSI
 151         * generation too.
 152         */
 153        PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
 154        /* Device configuration is irrevocably lost if disabled into D3 */
 155        PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
 156        /* Provide indication device is assigned by a Virtual Machine Manager */
 157        PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4,
 158};
 159
 160enum pci_irq_reroute_variant {
 161        INTEL_IRQ_REROUTE_VARIANT = 1,
 162        MAX_IRQ_REROUTE_VARIANTS = 3
 163};
 164
 165typedef unsigned short __bitwise pci_bus_flags_t;
 166enum pci_bus_flags {
 167        PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
 168        PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
 169};
 170
 171/* Based on the PCI Hotplug Spec, but some values are made up by us */
 172enum pci_bus_speed {
 173        PCI_SPEED_33MHz                 = 0x00,
 174        PCI_SPEED_66MHz                 = 0x01,
 175        PCI_SPEED_66MHz_PCIX            = 0x02,
 176        PCI_SPEED_100MHz_PCIX           = 0x03,
 177        PCI_SPEED_133MHz_PCIX           = 0x04,
 178        PCI_SPEED_66MHz_PCIX_ECC        = 0x05,
 179        PCI_SPEED_100MHz_PCIX_ECC       = 0x06,
 180        PCI_SPEED_133MHz_PCIX_ECC       = 0x07,
 181        PCI_SPEED_66MHz_PCIX_266        = 0x09,
 182        PCI_SPEED_100MHz_PCIX_266       = 0x0a,
 183        PCI_SPEED_133MHz_PCIX_266       = 0x0b,
 184        AGP_UNKNOWN                     = 0x0c,
 185        AGP_1X                          = 0x0d,
 186        AGP_2X                          = 0x0e,
 187        AGP_4X                          = 0x0f,
 188        AGP_8X                          = 0x10,
 189        PCI_SPEED_66MHz_PCIX_533        = 0x11,
 190        PCI_SPEED_100MHz_PCIX_533       = 0x12,
 191        PCI_SPEED_133MHz_PCIX_533       = 0x13,
 192        PCIE_SPEED_2_5GT                = 0x14,
 193        PCIE_SPEED_5_0GT                = 0x15,
 194        PCIE_SPEED_8_0GT                = 0x16,
 195        PCI_SPEED_UNKNOWN               = 0xff,
 196};
 197
 198struct pci_cap_saved_data {
 199        char cap_nr;
 200        unsigned int size;
 201        u32 data[0];
 202};
 203
 204struct pci_cap_saved_state {
 205        struct hlist_node next;
 206        struct pci_cap_saved_data cap;
 207};
 208
 209struct pcie_link_state;
 210struct pci_vpd;
 211struct pci_sriov;
 212struct pci_ats;
 213
 214/*
 215 * The pci_dev structure is used to describe PCI devices.
 216 */
 217struct pci_dev {
 218        struct list_head bus_list;      /* node in per-bus list */
 219        struct pci_bus  *bus;           /* bus this device is on */
 220        struct pci_bus  *subordinate;   /* bus this device bridges to */
 221
 222        void            *sysdata;       /* hook for sys-specific extension */
 223        struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
 224        struct pci_slot *slot;          /* Physical slot this device is in */
 225
 226        unsigned int    devfn;          /* encoded device & function index */
 227        unsigned short  vendor;
 228        unsigned short  device;
 229        unsigned short  subsystem_vendor;
 230        unsigned short  subsystem_device;
 231        unsigned int    class;          /* 3 bytes: (base,sub,prog-if) */
 232        u8              revision;       /* PCI revision, low byte of class word */
 233        u8              hdr_type;       /* PCI header type (`multi' flag masked out) */
 234        u8              pcie_cap;       /* PCI-E capability offset */
 235        u8              pcie_mpss:3;    /* PCI-E Max Payload Size Supported */
 236        u8              rom_base_reg;   /* which config register controls the ROM */
 237        u8              pin;            /* which interrupt pin this device uses */
 238        u16             pcie_flags_reg; /* cached PCI-E Capabilities Register */
 239
 240        struct pci_driver *driver;      /* which driver has allocated this device */
 241        u64             dma_mask;       /* Mask of the bits of bus address this
 242                                           device implements.  Normally this is
 243                                           0xffffffff.  You only need to change
 244                                           this if your device has broken DMA
 245                                           or supports 64-bit transfers.  */
 246
 247        struct device_dma_parameters dma_parms;
 248
 249        pci_power_t     current_state;  /* Current operating state. In ACPI-speak,
 250                                           this is D0-D3, D0 being fully functional,
 251                                           and D3 being off. */
 252        int             pm_cap;         /* PM capability offset in the
 253                                           configuration space */
 254        unsigned int    pme_support:5;  /* Bitmask of states from which PME#
 255                                           can be generated */
 256        unsigned int    pme_interrupt:1;
 257        unsigned int    pme_poll:1;     /* Poll device's PME status bit */
 258        unsigned int    d1_support:1;   /* Low power state D1 is supported */
 259        unsigned int    d2_support:1;   /* Low power state D2 is supported */
 260        unsigned int    no_d1d2:1;      /* D1 and D2 are forbidden */
 261        unsigned int    no_d3cold:1;    /* D3cold is forbidden */
 262        unsigned int    d3cold_allowed:1;       /* D3cold is allowed by user */
 263        unsigned int    mmio_always_on:1;       /* disallow turning off io/mem
 264                                                   decoding during bar sizing */
 265        unsigned int    wakeup_prepared:1;
 266        unsigned int    runtime_d3cold:1;       /* whether go through runtime
 267                                                   D3cold, not set for devices
 268                                                   powered on/off by the
 269                                                   corresponding bridge */
 270        unsigned int    d3_delay;       /* D3->D0 transition time in ms */
 271        unsigned int    d3cold_delay;   /* D3cold->D0 transition time in ms */
 272
 273#ifdef CONFIG_PCIEASPM
 274        struct pcie_link_state  *link_state;    /* ASPM link state. */
 275#endif
 276
 277        pci_channel_state_t error_state;        /* current connectivity state */
 278        struct  device  dev;            /* Generic device interface */
 279
 280        int             cfg_size;       /* Size of configuration space */
 281
 282        /*
 283         * Instead of touching interrupt line and base address registers
 284         * directly, use the values stored here. They might be different!
 285         */
 286        unsigned int    irq;
 287        struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
 288
 289        /* These fields are used by common fixups */
 290        unsigned int    transparent:1;  /* Transparent PCI bridge */
 291        unsigned int    multifunction:1;/* Part of multi-function device */
 292        /* keep track of device state */
 293        unsigned int    is_added:1;
 294        unsigned int    is_busmaster:1; /* device is busmaster */
 295        unsigned int    no_msi:1;       /* device may not use msi */
 296        unsigned int    block_cfg_access:1;     /* config space access is blocked */
 297        unsigned int    broken_parity_status:1; /* Device generates false positive parity */
 298        unsigned int    irq_reroute_variant:2;  /* device needs IRQ rerouting variant */
 299        unsigned int    msi_enabled:1;
 300        unsigned int    msix_enabled:1;
 301        unsigned int    ari_enabled:1;  /* ARI forwarding */
 302        unsigned int    is_managed:1;
 303        unsigned int    is_pcie:1;      /* Obsolete. Will be removed.
 304                                           Use pci_is_pcie() instead */
 305        unsigned int    needs_freset:1; /* Dev requires fundamental reset */
 306        unsigned int    state_saved:1;
 307        unsigned int    is_physfn:1;
 308        unsigned int    is_virtfn:1;
 309        unsigned int    reset_fn:1;
 310        unsigned int    is_hotplug_bridge:1;
 311        unsigned int    __aer_firmware_first_valid:1;
 312        unsigned int    __aer_firmware_first:1;
 313        unsigned int    broken_intx_masking:1;
 314        unsigned int    io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
 315        pci_dev_flags_t dev_flags;
 316        atomic_t        enable_cnt;     /* pci_enable_device has been called */
 317
 318        u32             saved_config_space[16]; /* config space saved at suspend time */
 319        struct hlist_head saved_cap_space;
 320        struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
 321        int rom_attr_enabled;           /* has display of the rom attribute been enabled? */
 322        struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
 323        struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
 324#ifdef CONFIG_PCI_MSI
 325        struct list_head msi_list;
 326        struct kset *msi_kset;
 327#endif
 328        struct pci_vpd *vpd;
 329#ifdef CONFIG_PCI_ATS
 330        union {
 331                struct pci_sriov *sriov;        /* SR-IOV capability related */
 332                struct pci_dev *physfn; /* the PF this VF is associated with */
 333        };
 334        struct pci_ats  *ats;   /* Address Translation Service */
 335#endif
 336        phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
 337        size_t romlen; /* Length of ROM if it's not from the BAR */
 338};
 339
 340static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
 341{
 342#ifdef CONFIG_PCI_IOV
 343        if (dev->is_virtfn)
 344                dev = dev->physfn;
 345#endif
 346
 347        return dev;
 348}
 349
 350extern struct pci_dev *alloc_pci_dev(void);
 351
 352#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
 353#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
 354
 355static inline int pci_channel_offline(struct pci_dev *pdev)
 356{
 357        return (pdev->error_state != pci_channel_io_normal);
 358}
 359
 360extern struct resource busn_resource;
 361
 362struct pci_host_bridge_window {
 363        struct list_head list;
 364        struct resource *res;           /* host bridge aperture (CPU address) */
 365        resource_size_t offset;         /* bus address + offset = CPU address */
 366};
 367
 368struct pci_host_bridge {
 369        struct device dev;
 370        struct pci_bus *bus;            /* root bus */
 371        struct list_head windows;       /* pci_host_bridge_windows */
 372        void (*release_fn)(struct pci_host_bridge *);
 373        void *release_data;
 374};
 375
 376#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
 377void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
 378                     void (*release_fn)(struct pci_host_bridge *),
 379                     void *release_data);
 380
 381/*
 382 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
 383 * to P2P or CardBus bridge windows) go in a table.  Additional ones (for
 384 * buses below host bridges or subtractive decode bridges) go in the list.
 385 * Use pci_bus_for_each_resource() to iterate through all the resources.
 386 */
 387
 388/*
 389 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
 390 * and there's no way to program the bridge with the details of the window.
 391 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
 392 * decode bit set, because they are explicit and can be programmed with _SRS.
 393 */
 394#define PCI_SUBTRACTIVE_DECODE  0x1
 395
 396struct pci_bus_resource {
 397        struct list_head list;
 398        struct resource *res;
 399        unsigned int flags;
 400};
 401
 402#define PCI_REGION_FLAG_MASK    0x0fU   /* These bits of resource flags tell us the PCI region flags */
 403
 404struct pci_bus {
 405        struct list_head node;          /* node in list of buses */
 406        struct pci_bus  *parent;        /* parent bus this bridge is on */
 407        struct list_head children;      /* list of child buses */
 408        struct list_head devices;       /* list of devices on this bus */
 409        struct pci_dev  *self;          /* bridge device as seen by parent */
 410        struct list_head slots;         /* list of slots on this bus */
 411        struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
 412        struct list_head resources;     /* address space routed to this bus */
 413        struct resource busn_res;       /* bus numbers routed to this bus */
 414
 415        struct pci_ops  *ops;           /* configuration access functions */
 416        void            *sysdata;       /* hook for sys-specific extension */
 417        struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
 418
 419        unsigned char   number;         /* bus number */
 420        unsigned char   primary;        /* number of primary bridge */
 421        unsigned char   max_bus_speed;  /* enum pci_bus_speed */
 422        unsigned char   cur_bus_speed;  /* enum pci_bus_speed */
 423
 424        char            name[48];
 425
 426        unsigned short  bridge_ctl;     /* manage NO_ISA/FBB/et al behaviors */
 427        pci_bus_flags_t bus_flags;      /* Inherited by child busses */
 428        struct device           *bridge;
 429        struct device           dev;
 430        struct bin_attribute    *legacy_io; /* legacy I/O for this bus */
 431        struct bin_attribute    *legacy_mem; /* legacy mem */
 432        unsigned int            is_added:1;
 433};
 434
 435#define pci_bus_b(n)    list_entry(n, struct pci_bus, node)
 436#define to_pci_bus(n)   container_of(n, struct pci_bus, dev)
 437
 438/*
 439 * Returns true if the pci bus is root (behind host-pci bridge),
 440 * false otherwise
 441 */
 442static inline bool pci_is_root_bus(struct pci_bus *pbus)
 443{
 444        return !(pbus->parent);
 445}
 446
 447#ifdef CONFIG_PCI_MSI
 448static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
 449{
 450        return pci_dev->msi_enabled || pci_dev->msix_enabled;
 451}
 452#else
 453static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
 454#endif
 455
 456/*
 457 * Error values that may be returned by PCI functions.
 458 */
 459#define PCIBIOS_SUCCESSFUL              0x00
 460#define PCIBIOS_FUNC_NOT_SUPPORTED      0x81
 461#define PCIBIOS_BAD_VENDOR_ID           0x83
 462#define PCIBIOS_DEVICE_NOT_FOUND        0x86
 463#define PCIBIOS_BAD_REGISTER_NUMBER     0x87
 464#define PCIBIOS_SET_FAILED              0x88
 465#define PCIBIOS_BUFFER_TOO_SMALL        0x89
 466
 467/*
 468 * Translate above to generic errno for passing back through non-pci.
 469 */
 470static inline int pcibios_err_to_errno(int err)
 471{
 472        if (err <= PCIBIOS_SUCCESSFUL)
 473                return err; /* Assume already errno */
 474
 475        switch (err) {
 476        case PCIBIOS_FUNC_NOT_SUPPORTED:
 477                return -ENOENT;
 478        case PCIBIOS_BAD_VENDOR_ID:
 479                return -EINVAL;
 480        case PCIBIOS_DEVICE_NOT_FOUND:
 481                return -ENODEV;
 482        case PCIBIOS_BAD_REGISTER_NUMBER:
 483                return -EFAULT;
 484        case PCIBIOS_SET_FAILED:
 485                return -EIO;
 486        case PCIBIOS_BUFFER_TOO_SMALL:
 487                return -ENOSPC;
 488        }
 489
 490        return -ENOTTY;
 491}
 492
 493/* Low-level architecture-dependent routines */
 494
 495struct pci_ops {
 496        int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
 497        int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
 498};
 499
 500/*
 501 * ACPI needs to be able to access PCI config space before we've done a
 502 * PCI bus scan and created pci_bus structures.
 503 */
 504extern int raw_pci_read(unsigned int domain, unsigned int bus,
 505                        unsigned int devfn, int reg, int len, u32 *val);
 506extern int raw_pci_write(unsigned int domain, unsigned int bus,
 507                        unsigned int devfn, int reg, int len, u32 val);
 508
 509struct pci_bus_region {
 510        resource_size_t start;
 511        resource_size_t end;
 512};
 513
 514struct pci_dynids {
 515        spinlock_t lock;            /* protects list, index */
 516        struct list_head list;      /* for IDs added at runtime */
 517};
 518
 519/* ---------------------------------------------------------------- */
 520/** PCI Error Recovery System (PCI-ERS).  If a PCI device driver provides
 521 *  a set of callbacks in struct pci_error_handlers, then that device driver
 522 *  will be notified of PCI bus errors, and will be driven to recovery
 523 *  when an error occurs.
 524 */
 525
 526typedef unsigned int __bitwise pci_ers_result_t;
 527
 528enum pci_ers_result {
 529        /* no result/none/not supported in device driver */
 530        PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
 531
 532        /* Device driver can recover without slot reset */
 533        PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
 534
 535        /* Device driver wants slot to be reset. */
 536        PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
 537
 538        /* Device has completely failed, is unrecoverable */
 539        PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
 540
 541        /* Device driver is fully recovered and operational */
 542        PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
 543
 544        /* No AER capabilities registered for the driver */
 545        PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
 546};
 547
 548/* PCI bus error event callbacks */
 549struct pci_error_handlers {
 550        /* PCI bus error detected on this device */
 551        pci_ers_result_t (*error_detected)(struct pci_dev *dev,
 552                                           enum pci_channel_state error);
 553
 554        /* MMIO has been re-enabled, but not DMA */
 555        pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
 556
 557        /* PCI Express link has been reset */
 558        pci_ers_result_t (*link_reset)(struct pci_dev *dev);
 559
 560        /* PCI slot has been reset */
 561        pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
 562
 563        /* Device driver may resume normal operations */
 564        void (*resume)(struct pci_dev *dev);
 565};
 566
 567/* ---------------------------------------------------------------- */
 568
 569struct module;
 570struct pci_driver {
 571        struct list_head node;
 572        const char *name;
 573        const struct pci_device_id *id_table;   /* must be non-NULL for probe to be called */
 574        int  (*probe)  (struct pci_dev *dev, const struct pci_device_id *id);   /* New device inserted */
 575        void (*remove) (struct pci_dev *dev);   /* Device removed (NULL if not a hot-plug capable driver) */
 576        int  (*suspend) (struct pci_dev *dev, pm_message_t state);      /* Device suspended */
 577        int  (*suspend_late) (struct pci_dev *dev, pm_message_t state);
 578        int  (*resume_early) (struct pci_dev *dev);
 579        int  (*resume) (struct pci_dev *dev);                   /* Device woken up */
 580        void (*shutdown) (struct pci_dev *dev);
 581        int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
 582        const struct pci_error_handlers *err_handler;
 583        struct device_driver    driver;
 584        struct pci_dynids dynids;
 585};
 586
 587#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
 588
 589/**
 590 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
 591 * @_table: device table name
 592 *
 593 * This macro is used to create a struct pci_device_id array (a device table)
 594 * in a generic manner.
 595 */
 596#define DEFINE_PCI_DEVICE_TABLE(_table) \
 597        const struct pci_device_id _table[]
 598
 599/**
 600 * PCI_DEVICE - macro used to describe a specific pci device
 601 * @vend: the 16 bit PCI Vendor ID
 602 * @dev: the 16 bit PCI Device ID
 603 *
 604 * This macro is used to create a struct pci_device_id that matches a
 605 * specific device.  The subvendor and subdevice fields will be set to
 606 * PCI_ANY_ID.
 607 */
 608#define PCI_DEVICE(vend,dev) \
 609        .vendor = (vend), .device = (dev), \
 610        .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
 611
 612/**
 613 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
 614 * @vend: the 16 bit PCI Vendor ID
 615 * @dev: the 16 bit PCI Device ID
 616 * @subvend: the 16 bit PCI Subvendor ID
 617 * @subdev: the 16 bit PCI Subdevice ID
 618 *
 619 * This macro is used to create a struct pci_device_id that matches a
 620 * specific device with subsystem information.
 621 */
 622#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
 623        .vendor = (vend), .device = (dev), \
 624        .subvendor = (subvend), .subdevice = (subdev)
 625
 626/**
 627 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
 628 * @dev_class: the class, subclass, prog-if triple for this device
 629 * @dev_class_mask: the class mask for this device
 630 *
 631 * This macro is used to create a struct pci_device_id that matches a
 632 * specific PCI class.  The vendor, device, subvendor, and subdevice
 633 * fields will be set to PCI_ANY_ID.
 634 */
 635#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
 636        .class = (dev_class), .class_mask = (dev_class_mask), \
 637        .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
 638        .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
 639
 640/**
 641 * PCI_VDEVICE - macro used to describe a specific pci device in short form
 642 * @vendor: the vendor name
 643 * @device: the 16 bit PCI Device ID
 644 *
 645 * This macro is used to create a struct pci_device_id that matches a
 646 * specific PCI device.  The subvendor, and subdevice fields will be set
 647 * to PCI_ANY_ID. The macro allows the next field to follow as the device
 648 * private data.
 649 */
 650
 651#define PCI_VDEVICE(vendor, device)             \
 652        PCI_VENDOR_ID_##vendor, (device),       \
 653        PCI_ANY_ID, PCI_ANY_ID, 0, 0
 654
 655/* these external functions are only available when PCI support is enabled */
 656#ifdef CONFIG_PCI
 657
 658extern void pcie_bus_configure_settings(struct pci_bus *bus, u8 smpss);
 659
 660enum pcie_bus_config_types {
 661        PCIE_BUS_TUNE_OFF,
 662        PCIE_BUS_SAFE,
 663        PCIE_BUS_PERFORMANCE,
 664        PCIE_BUS_PEER2PEER,
 665};
 666
 667extern enum pcie_bus_config_types pcie_bus_config;
 668
 669extern struct bus_type pci_bus_type;
 670
 671/* Do NOT directly access these two variables, unless you are arch specific pci
 672 * code, or pci core code. */
 673extern struct list_head pci_root_buses; /* list of all known PCI buses */
 674/* Some device drivers need know if pci is initiated */
 675extern int no_pci_devices(void);
 676
 677void pcibios_fixup_bus(struct pci_bus *);
 678int __must_check pcibios_enable_device(struct pci_dev *, int mask);
 679/* Architecture specific versions may override this (weak) */
 680char *pcibios_setup(char *str);
 681
 682/* Used only when drivers/pci/setup.c is used */
 683resource_size_t pcibios_align_resource(void *, const struct resource *,
 684                                resource_size_t,
 685                                resource_size_t);
 686void pcibios_update_irq(struct pci_dev *, int irq);
 687
 688/* Weak but can be overriden by arch */
 689void pci_fixup_cardbus(struct pci_bus *);
 690
 691/* Generic PCI functions used internally */
 692
 693void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
 694                             struct resource *res);
 695void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
 696                             struct pci_bus_region *region);
 697void pcibios_scan_specific_bus(int busn);
 698extern struct pci_bus *pci_find_bus(int domain, int busnr);
 699void pci_bus_add_devices(const struct pci_bus *bus);
 700struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
 701                                      struct pci_ops *ops, void *sysdata);
 702struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
 703struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
 704                                    struct pci_ops *ops, void *sysdata,
 705                                    struct list_head *resources);
 706int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
 707int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
 708void pci_bus_release_busn_res(struct pci_bus *b);
 709struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
 710                                             struct pci_ops *ops, void *sysdata,
 711                                             struct list_head *resources);
 712struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
 713                                int busnr);
 714void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
 715struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
 716                                 const char *name,
 717                                 struct hotplug_slot *hotplug);
 718void pci_destroy_slot(struct pci_slot *slot);
 719void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
 720int pci_scan_slot(struct pci_bus *bus, int devfn);
 721struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
 722void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
 723unsigned int pci_scan_child_bus(struct pci_bus *bus);
 724int __must_check pci_bus_add_device(struct pci_dev *dev);
 725void pci_read_bridge_bases(struct pci_bus *child);
 726struct resource *pci_find_parent_resource(const struct pci_dev *dev,
 727                                          struct resource *res);
 728u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
 729int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
 730u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
 731extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
 732extern void pci_dev_put(struct pci_dev *dev);
 733extern void pci_remove_bus(struct pci_bus *b);
 734extern void pci_stop_and_remove_bus_device(struct pci_dev *dev);
 735void pci_stop_root_bus(struct pci_bus *bus);
 736void pci_remove_root_bus(struct pci_bus *bus);
 737void pci_setup_cardbus(struct pci_bus *bus);
 738extern void pci_sort_breadthfirst(void);
 739#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
 740#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
 741#define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
 742
 743/* Generic PCI functions exported to card drivers */
 744
 745enum pci_lost_interrupt_reason {
 746        PCI_LOST_IRQ_NO_INFORMATION = 0,
 747        PCI_LOST_IRQ_DISABLE_MSI,
 748        PCI_LOST_IRQ_DISABLE_MSIX,
 749        PCI_LOST_IRQ_DISABLE_ACPI,
 750};
 751enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
 752int pci_find_capability(struct pci_dev *dev, int cap);
 753int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
 754int pci_find_ext_capability(struct pci_dev *dev, int cap);
 755int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
 756int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
 757int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
 758struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
 759
 760struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
 761                                struct pci_dev *from);
 762struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
 763                                unsigned int ss_vendor, unsigned int ss_device,
 764                                struct pci_dev *from);
 765struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
 766struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
 767                                            unsigned int devfn);
 768static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
 769                                                   unsigned int devfn)
 770{
 771        return pci_get_domain_bus_and_slot(0, bus, devfn);
 772}
 773struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
 774int pci_dev_present(const struct pci_device_id *ids);
 775
 776int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
 777                             int where, u8 *val);
 778int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
 779                             int where, u16 *val);
 780int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
 781                              int where, u32 *val);
 782int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
 783                              int where, u8 val);
 784int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
 785                              int where, u16 val);
 786int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
 787                               int where, u32 val);
 788struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
 789
 790static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
 791{
 792        return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
 793}
 794static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
 795{
 796        return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
 797}
 798static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
 799                                        u32 *val)
 800{
 801        return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
 802}
 803static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
 804{
 805        return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
 806}
 807static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
 808{
 809        return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
 810}
 811static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
 812                                         u32 val)
 813{
 814        return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
 815}
 816
 817int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
 818int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
 819int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
 820int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
 821int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
 822                                       u16 clear, u16 set);
 823int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
 824                                        u32 clear, u32 set);
 825
 826static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
 827                                           u16 set)
 828{
 829        return pcie_capability_clear_and_set_word(dev, pos, 0, set);
 830}
 831
 832static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
 833                                            u32 set)
 834{
 835        return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
 836}
 837
 838static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
 839                                             u16 clear)
 840{
 841        return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
 842}
 843
 844static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
 845                                              u32 clear)
 846{
 847        return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
 848}
 849
 850/* user-space driven config access */
 851int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
 852int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
 853int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
 854int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
 855int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
 856int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
 857
 858int __must_check pci_enable_device(struct pci_dev *dev);
 859int __must_check pci_enable_device_io(struct pci_dev *dev);
 860int __must_check pci_enable_device_mem(struct pci_dev *dev);
 861int __must_check pci_reenable_device(struct pci_dev *);
 862int __must_check pcim_enable_device(struct pci_dev *pdev);
 863void pcim_pin_device(struct pci_dev *pdev);
 864
 865static inline int pci_is_enabled(struct pci_dev *pdev)
 866{
 867        return (atomic_read(&pdev->enable_cnt) > 0);
 868}
 869
 870static inline int pci_is_managed(struct pci_dev *pdev)
 871{
 872        return pdev->is_managed;
 873}
 874
 875void pci_disable_device(struct pci_dev *dev);
 876
 877extern unsigned int pcibios_max_latency;
 878void pci_set_master(struct pci_dev *dev);
 879void pci_clear_master(struct pci_dev *dev);
 880
 881int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
 882int pci_set_cacheline_size(struct pci_dev *dev);
 883#define HAVE_PCI_SET_MWI
 884int __must_check pci_set_mwi(struct pci_dev *dev);
 885int pci_try_set_mwi(struct pci_dev *dev);
 886void pci_clear_mwi(struct pci_dev *dev);
 887void pci_intx(struct pci_dev *dev, int enable);
 888bool pci_intx_mask_supported(struct pci_dev *dev);
 889bool pci_check_and_mask_intx(struct pci_dev *dev);
 890bool pci_check_and_unmask_intx(struct pci_dev *dev);
 891void pci_msi_off(struct pci_dev *dev);
 892int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
 893int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
 894int pcix_get_max_mmrbc(struct pci_dev *dev);
 895int pcix_get_mmrbc(struct pci_dev *dev);
 896int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
 897int pcie_get_readrq(struct pci_dev *dev);
 898int pcie_set_readrq(struct pci_dev *dev, int rq);
 899int pcie_get_mps(struct pci_dev *dev);
 900int pcie_set_mps(struct pci_dev *dev, int mps);
 901int __pci_reset_function(struct pci_dev *dev);
 902int __pci_reset_function_locked(struct pci_dev *dev);
 903int pci_reset_function(struct pci_dev *dev);
 904void pci_update_resource(struct pci_dev *dev, int resno);
 905int __must_check pci_assign_resource(struct pci_dev *dev, int i);
 906int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
 907int pci_select_bars(struct pci_dev *dev, unsigned long flags);
 908
 909/* ROM control related routines */
 910int pci_enable_rom(struct pci_dev *pdev);
 911void pci_disable_rom(struct pci_dev *pdev);
 912void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
 913void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
 914size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
 915
 916/* Power management related routines */
 917int pci_save_state(struct pci_dev *dev);
 918void pci_restore_state(struct pci_dev *dev);
 919struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
 920int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state);
 921int pci_load_and_free_saved_state(struct pci_dev *dev,
 922                                  struct pci_saved_state **state);
 923int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
 924int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
 925pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
 926bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
 927void pci_pme_active(struct pci_dev *dev, bool enable);
 928int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
 929                      bool runtime, bool enable);
 930int pci_wake_from_d3(struct pci_dev *dev, bool enable);
 931pci_power_t pci_target_state(struct pci_dev *dev);
 932int pci_prepare_to_sleep(struct pci_dev *dev);
 933int pci_back_from_sleep(struct pci_dev *dev);
 934bool pci_dev_run_wake(struct pci_dev *dev);
 935bool pci_check_pme_status(struct pci_dev *dev);
 936void pci_pme_wakeup_bus(struct pci_bus *bus);
 937
 938static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
 939                                  bool enable)
 940{
 941        return __pci_enable_wake(dev, state, false, enable);
 942}
 943
 944#define PCI_EXP_IDO_REQUEST     (1<<0)
 945#define PCI_EXP_IDO_COMPLETION  (1<<1)
 946void pci_enable_ido(struct pci_dev *dev, unsigned long type);
 947void pci_disable_ido(struct pci_dev *dev, unsigned long type);
 948
 949enum pci_obff_signal_type {
 950        PCI_EXP_OBFF_SIGNAL_L0 = 0,
 951        PCI_EXP_OBFF_SIGNAL_ALWAYS = 1,
 952};
 953int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
 954void pci_disable_obff(struct pci_dev *dev);
 955
 956int pci_enable_ltr(struct pci_dev *dev);
 957void pci_disable_ltr(struct pci_dev *dev);
 958int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
 959
 960/* For use by arch with custom probe code */
 961void set_pcie_port_type(struct pci_dev *pdev);
 962void set_pcie_hotplug_bridge(struct pci_dev *pdev);
 963
 964/* Functions for PCI Hotplug drivers to use */
 965int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
 966unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
 967unsigned int pci_rescan_bus(struct pci_bus *bus);
 968
 969/* Vital product data routines */
 970ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
 971ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
 972int pci_vpd_truncate(struct pci_dev *dev, size_t size);
 973
 974/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
 975resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
 976void pci_bus_assign_resources(const struct pci_bus *bus);
 977void pci_bus_size_bridges(struct pci_bus *bus);
 978int pci_claim_resource(struct pci_dev *, int);
 979void pci_assign_unassigned_resources(void);
 980void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
 981void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
 982void pdev_enable_device(struct pci_dev *);
 983int pci_enable_resources(struct pci_dev *, int mask);
 984void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
 985                    int (*)(const struct pci_dev *, u8, u8));
 986#define HAVE_PCI_REQ_REGIONS    2
 987int __must_check pci_request_regions(struct pci_dev *, const char *);
 988int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
 989void pci_release_regions(struct pci_dev *);
 990int __must_check pci_request_region(struct pci_dev *, int, const char *);
 991int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
 992void pci_release_region(struct pci_dev *, int);
 993int pci_request_selected_regions(struct pci_dev *, int, const char *);
 994int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
 995void pci_release_selected_regions(struct pci_dev *, int);
 996
 997/* drivers/pci/bus.c */
 998void pci_add_resource(struct list_head *resources, struct resource *res);
 999void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1000                             resource_size_t offset);
1001void pci_free_resource_list(struct list_head *resources);
1002void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
1003struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1004void pci_bus_remove_resources(struct pci_bus *bus);
1005
1006#define pci_bus_for_each_resource(bus, res, i)                          \
1007        for (i = 0;                                                     \
1008            (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1009             i++)
1010
1011int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1012                        struct resource *res, resource_size_t size,
1013                        resource_size_t align, resource_size_t min,
1014                        unsigned int type_mask,
1015                        resource_size_t (*alignf)(void *,
1016                                                  const struct resource *,
1017                                                  resource_size_t,
1018                                                  resource_size_t),
1019                        void *alignf_data);
1020void pci_enable_bridges(struct pci_bus *bus);
1021
1022/* Proper probing supporting hot-pluggable devices */
1023int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1024                                       const char *mod_name);
1025
1026/*
1027 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1028 */
1029#define pci_register_driver(driver)             \
1030        __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1031
1032void pci_unregister_driver(struct pci_driver *dev);
1033
1034/**
1035 * module_pci_driver() - Helper macro for registering a PCI driver
1036 * @__pci_driver: pci_driver struct
1037 *
1038 * Helper macro for PCI drivers which do not do anything special in module
1039 * init/exit. This eliminates a lot of boilerplate. Each module may only
1040 * use this macro once, and calling it replaces module_init() and module_exit()
1041 */
1042#define module_pci_driver(__pci_driver) \
1043        module_driver(__pci_driver, pci_register_driver, \
1044                       pci_unregister_driver)
1045
1046struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1047int pci_add_dynid(struct pci_driver *drv,
1048                  unsigned int vendor, unsigned int device,
1049                  unsigned int subvendor, unsigned int subdevice,
1050                  unsigned int class, unsigned int class_mask,
1051                  unsigned long driver_data);
1052const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1053                                         struct pci_dev *dev);
1054int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1055                    int pass);
1056
1057void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1058                  void *userdata);
1059int pci_cfg_space_size_ext(struct pci_dev *dev);
1060int pci_cfg_space_size(struct pci_dev *dev);
1061unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1062void pci_setup_bridge(struct pci_bus *bus);
1063resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1064                                         unsigned long type);
1065
1066#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1067#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1068
1069int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1070                      unsigned int command_bits, u32 flags);
1071/* kmem_cache style wrapper around pci_alloc_consistent() */
1072
1073#include <linux/pci-dma.h>
1074#include <linux/dmapool.h>
1075
1076#define pci_pool dma_pool
1077#define pci_pool_create(name, pdev, size, align, allocation) \
1078                dma_pool_create(name, &pdev->dev, size, align, allocation)
1079#define pci_pool_destroy(pool) dma_pool_destroy(pool)
1080#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1081#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1082
1083enum pci_dma_burst_strategy {
1084        PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
1085                                   strategy_parameter is N/A */
1086        PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
1087                                   byte boundaries */
1088        PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
1089                                   strategy_parameter byte boundaries */
1090};
1091
1092struct msix_entry {
1093        u32     vector; /* kernel uses to write allocated vector */
1094        u16     entry;  /* driver uses to specify entry, OS writes */
1095};
1096
1097
1098#ifndef CONFIG_PCI_MSI
1099static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
1100{
1101        return -1;
1102}
1103
1104static inline void pci_msi_shutdown(struct pci_dev *dev)
1105{ }
1106static inline void pci_disable_msi(struct pci_dev *dev)
1107{ }
1108
1109static inline int pci_msix_table_size(struct pci_dev *dev)
1110{
1111        return 0;
1112}
1113static inline int pci_enable_msix(struct pci_dev *dev,
1114                                  struct msix_entry *entries, int nvec)
1115{
1116        return -1;
1117}
1118
1119static inline void pci_msix_shutdown(struct pci_dev *dev)
1120{ }
1121static inline void pci_disable_msix(struct pci_dev *dev)
1122{ }
1123
1124static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1125{ }
1126
1127static inline void pci_restore_msi_state(struct pci_dev *dev)
1128{ }
1129static inline int pci_msi_enabled(void)
1130{
1131        return 0;
1132}
1133#else
1134extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
1135extern void pci_msi_shutdown(struct pci_dev *dev);
1136extern void pci_disable_msi(struct pci_dev *dev);
1137extern int pci_msix_table_size(struct pci_dev *dev);
1138extern int pci_enable_msix(struct pci_dev *dev,
1139        struct msix_entry *entries, int nvec);
1140extern void pci_msix_shutdown(struct pci_dev *dev);
1141extern void pci_disable_msix(struct pci_dev *dev);
1142extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
1143extern void pci_restore_msi_state(struct pci_dev *dev);
1144extern int pci_msi_enabled(void);
1145#endif
1146
1147#ifdef CONFIG_PCIEPORTBUS
1148extern bool pcie_ports_disabled;
1149extern bool pcie_ports_auto;
1150#else
1151#define pcie_ports_disabled     true
1152#define pcie_ports_auto         false
1153#endif
1154
1155#ifndef CONFIG_PCIEASPM
1156static inline int pcie_aspm_enabled(void) { return 0; }
1157static inline bool pcie_aspm_support_enabled(void) { return false; }
1158#else
1159extern int pcie_aspm_enabled(void);
1160extern bool pcie_aspm_support_enabled(void);
1161#endif
1162
1163#ifdef CONFIG_PCIEAER
1164void pci_no_aer(void);
1165bool pci_aer_available(void);
1166#else
1167static inline void pci_no_aer(void) { }
1168static inline bool pci_aer_available(void) { return false; }
1169#endif
1170
1171#ifndef CONFIG_PCIE_ECRC
1172static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1173{
1174        return;
1175}
1176static inline void pcie_ecrc_get_policy(char *str) {};
1177#else
1178extern void pcie_set_ecrc_checking(struct pci_dev *dev);
1179extern void pcie_ecrc_get_policy(char *str);
1180#endif
1181
1182#define pci_enable_msi(pdev)    pci_enable_msi_block(pdev, 1)
1183
1184#ifdef CONFIG_HT_IRQ
1185/* The functions a driver should call */
1186int  ht_create_irq(struct pci_dev *dev, int idx);
1187void ht_destroy_irq(unsigned int irq);
1188#endif /* CONFIG_HT_IRQ */
1189
1190extern void pci_cfg_access_lock(struct pci_dev *dev);
1191extern bool pci_cfg_access_trylock(struct pci_dev *dev);
1192extern void pci_cfg_access_unlock(struct pci_dev *dev);
1193
1194/*
1195 * PCI domain support.  Sometimes called PCI segment (eg by ACPI),
1196 * a PCI domain is defined to be a set of PCI busses which share
1197 * configuration space.
1198 */
1199#ifdef CONFIG_PCI_DOMAINS
1200extern int pci_domains_supported;
1201#else
1202enum { pci_domains_supported = 0 };
1203static inline int pci_domain_nr(struct pci_bus *bus)
1204{
1205        return 0;
1206}
1207
1208static inline int pci_proc_domain(struct pci_bus *bus)
1209{
1210        return 0;
1211}
1212#endif /* CONFIG_PCI_DOMAINS */
1213
1214/* some architectures require additional setup to direct VGA traffic */
1215typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1216                      unsigned int command_bits, u32 flags);
1217extern void pci_register_set_vga_state(arch_set_vga_state_t func);
1218
1219#else /* CONFIG_PCI is not enabled */
1220
1221/*
1222 *  If the system does not have PCI, clearly these return errors.  Define
1223 *  these as simple inline functions to avoid hair in drivers.
1224 */
1225
1226#define _PCI_NOP(o, s, t) \
1227        static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1228                                                int where, t val) \
1229                { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1230
1231#define _PCI_NOP_ALL(o, x)      _PCI_NOP(o, byte, u8 x) \
1232                                _PCI_NOP(o, word, u16 x) \
1233                                _PCI_NOP(o, dword, u32 x)
1234_PCI_NOP_ALL(read, *)
1235_PCI_NOP_ALL(write,)
1236
1237static inline struct pci_dev *pci_get_device(unsigned int vendor,
1238                                             unsigned int device,
1239                                             struct pci_dev *from)
1240{
1241        return NULL;
1242}
1243
1244static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1245                                             unsigned int device,
1246                                             unsigned int ss_vendor,
1247                                             unsigned int ss_device,
1248                                             struct pci_dev *from)
1249{
1250        return NULL;
1251}
1252
1253static inline struct pci_dev *pci_get_class(unsigned int class,
1254                                            struct pci_dev *from)
1255{
1256        return NULL;
1257}
1258
1259#define pci_dev_present(ids)    (0)
1260#define no_pci_devices()        (1)
1261#define pci_dev_put(dev)        do { } while (0)
1262
1263static inline void pci_set_master(struct pci_dev *dev)
1264{ }
1265
1266static inline int pci_enable_device(struct pci_dev *dev)
1267{
1268        return -EIO;
1269}
1270
1271static inline void pci_disable_device(struct pci_dev *dev)
1272{ }
1273
1274static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1275{
1276        return -EIO;
1277}
1278
1279static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1280{
1281        return -EIO;
1282}
1283
1284static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1285                                        unsigned int size)
1286{
1287        return -EIO;
1288}
1289
1290static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1291                                        unsigned long mask)
1292{
1293        return -EIO;
1294}
1295
1296static inline int pci_assign_resource(struct pci_dev *dev, int i)
1297{
1298        return -EBUSY;
1299}
1300
1301static inline int __pci_register_driver(struct pci_driver *drv,
1302                                        struct module *owner)
1303{
1304        return 0;
1305}
1306
1307static inline int pci_register_driver(struct pci_driver *drv)
1308{
1309        return 0;
1310}
1311
1312static inline void pci_unregister_driver(struct pci_driver *drv)
1313{ }
1314
1315static inline int pci_find_capability(struct pci_dev *dev, int cap)
1316{
1317        return 0;
1318}
1319
1320static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1321                                           int cap)
1322{
1323        return 0;
1324}
1325
1326static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1327{
1328        return 0;
1329}
1330
1331/* Power management related routines */
1332static inline int pci_save_state(struct pci_dev *dev)
1333{
1334        return 0;
1335}
1336
1337static inline void pci_restore_state(struct pci_dev *dev)
1338{ }
1339
1340static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1341{
1342        return 0;
1343}
1344
1345static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1346{
1347        return 0;
1348}
1349
1350static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1351                                           pm_message_t state)
1352{
1353        return PCI_D0;
1354}
1355
1356static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1357                                  int enable)
1358{
1359        return 0;
1360}
1361
1362static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1363{
1364}
1365
1366static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1367{
1368}
1369
1370static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type)
1371{
1372        return 0;
1373}
1374
1375static inline void pci_disable_obff(struct pci_dev *dev)
1376{
1377}
1378
1379static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1380{
1381        return -EIO;
1382}
1383
1384static inline void pci_release_regions(struct pci_dev *dev)
1385{ }
1386
1387#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1388
1389static inline void pci_block_cfg_access(struct pci_dev *dev)
1390{ }
1391
1392static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1393{ return 0; }
1394
1395static inline void pci_unblock_cfg_access(struct pci_dev *dev)
1396{ }
1397
1398static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1399{ return NULL; }
1400
1401static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1402                                                unsigned int devfn)
1403{ return NULL; }
1404
1405static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1406                                                unsigned int devfn)
1407{ return NULL; }
1408
1409static inline int pci_domain_nr(struct pci_bus *bus)
1410{ return 0; }
1411
1412static inline struct pci_dev *pci_dev_get(struct pci_dev *dev)
1413{ return NULL; }
1414
1415#define dev_is_pci(d) (false)
1416#define dev_is_pf(d) (false)
1417#define dev_num_vf(d) (0)
1418#endif /* CONFIG_PCI */
1419
1420/* Include architecture-dependent settings and functions */
1421
1422#include <asm/pci.h>
1423
1424#ifndef PCIBIOS_MAX_MEM_32
1425#define PCIBIOS_MAX_MEM_32 (-1)
1426#endif
1427
1428/* these helpers provide future and backwards compatibility
1429 * for accessing popular PCI BAR info */
1430#define pci_resource_start(dev, bar)    ((dev)->resource[(bar)].start)
1431#define pci_resource_end(dev, bar)      ((dev)->resource[(bar)].end)
1432#define pci_resource_flags(dev, bar)    ((dev)->resource[(bar)].flags)
1433#define pci_resource_len(dev,bar) \
1434        ((pci_resource_start((dev), (bar)) == 0 &&      \
1435          pci_resource_end((dev), (bar)) ==             \
1436          pci_resource_start((dev), (bar))) ? 0 :       \
1437                                                        \
1438         (pci_resource_end((dev), (bar)) -              \
1439          pci_resource_start((dev), (bar)) + 1))
1440
1441/* Similar to the helpers above, these manipulate per-pci_dev
1442 * driver-specific data.  They are really just a wrapper around
1443 * the generic device structure functions of these calls.
1444 */
1445static inline void *pci_get_drvdata(struct pci_dev *pdev)
1446{
1447        return dev_get_drvdata(&pdev->dev);
1448}
1449
1450static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1451{
1452        dev_set_drvdata(&pdev->dev, data);
1453}
1454
1455/* If you want to know what to call your pci_dev, ask this function.
1456 * Again, it's a wrapper around the generic device.
1457 */
1458static inline const char *pci_name(const struct pci_dev *pdev)
1459{
1460        return dev_name(&pdev->dev);
1461}
1462
1463
1464/* Some archs don't want to expose struct resource to userland as-is
1465 * in sysfs and /proc
1466 */
1467#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1468static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1469                const struct resource *rsrc, resource_size_t *start,
1470                resource_size_t *end)
1471{
1472        *start = rsrc->start;
1473        *end = rsrc->end;
1474}
1475#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1476
1477
1478/*
1479 *  The world is not perfect and supplies us with broken PCI devices.
1480 *  For at least a part of these bugs we need a work-around, so both
1481 *  generic (drivers/pci/quirks.c) and per-architecture code can define
1482 *  fixup hooks to be called for particular buggy devices.
1483 */
1484
1485struct pci_fixup {
1486        u16 vendor;             /* You can use PCI_ANY_ID here of course */
1487        u16 device;             /* You can use PCI_ANY_ID here of course */
1488        u32 class;              /* You can use PCI_ANY_ID here too */
1489        unsigned int class_shift;       /* should be 0, 8, 16 */
1490        void (*hook)(struct pci_dev *dev);
1491};
1492
1493enum pci_fixup_pass {
1494        pci_fixup_early,        /* Before probing BARs */
1495        pci_fixup_header,       /* After reading configuration header */
1496        pci_fixup_final,        /* Final phase of device fixups */
1497        pci_fixup_enable,       /* pci_enable_device() time */
1498        pci_fixup_resume,       /* pci_device_resume() */
1499        pci_fixup_suspend,      /* pci_device_suspend */
1500        pci_fixup_resume_early, /* pci_device_resume_early() */
1501};
1502
1503/* Anonymous variables would be nice... */
1504#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1505                                  class_shift, hook)                    \
1506        static const struct pci_fixup __pci_fixup_##name __used         \
1507        __attribute__((__section__(#section), aligned((sizeof(void *)))))    \
1508                = { vendor, device, class, class_shift, hook };
1509
1510#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class,            \
1511                                         class_shift, hook)             \
1512        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,                     \
1513                vendor##device##hook, vendor, device, class, class_shift, hook)
1514#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class,           \
1515                                         class_shift, hook)             \
1516        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header,                    \
1517                vendor##device##hook, vendor, device, class, class_shift, hook)
1518#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class,            \
1519                                         class_shift, hook)             \
1520        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final,                     \
1521                vendor##device##hook, vendor, device, class, class_shift, hook)
1522#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class,           \
1523                                         class_shift, hook)             \
1524        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable,                    \
1525                vendor##device##hook, vendor, device, class, class_shift, hook)
1526#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class,           \
1527                                         class_shift, hook)             \
1528        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume,                    \
1529                resume##vendor##device##hook, vendor, device, class,    \
1530                class_shift, hook)
1531#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class,     \
1532                                         class_shift, hook)             \
1533        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early,              \
1534                resume_early##vendor##device##hook, vendor, device,     \
1535                class, class_shift, hook)
1536#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class,          \
1537                                         class_shift, hook)             \
1538        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend,                   \
1539                suspend##vendor##device##hook, vendor, device, class,   \
1540                class_shift, hook)
1541
1542#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook)                   \
1543        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,                     \
1544                vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1545#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook)                  \
1546        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header,                    \
1547                vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1548#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook)                   \
1549        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final,                     \
1550                vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1551#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook)                  \
1552        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable,                    \
1553                vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1554#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook)                  \
1555        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume,                    \
1556                resume##vendor##device##hook, vendor, device,           \
1557                PCI_ANY_ID, 0, hook)
1558#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook)            \
1559        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early,              \
1560                resume_early##vendor##device##hook, vendor, device,     \
1561                PCI_ANY_ID, 0, hook)
1562#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook)                 \
1563        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend,                   \
1564                suspend##vendor##device##hook, vendor, device,          \
1565                PCI_ANY_ID, 0, hook)
1566
1567#ifdef CONFIG_PCI_QUIRKS
1568void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1569struct pci_dev *pci_get_dma_source(struct pci_dev *dev);
1570int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1571#else
1572static inline void pci_fixup_device(enum pci_fixup_pass pass,
1573                                    struct pci_dev *dev) {}
1574static inline struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
1575{
1576        return pci_dev_get(dev);
1577}
1578static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1579                                               u16 acs_flags)
1580{
1581        return -ENOTTY;
1582}
1583#endif
1584
1585void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1586void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1587void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1588int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1589int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1590                                   const char *name);
1591void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1592
1593extern int pci_pci_problems;
1594#define PCIPCI_FAIL             1       /* No PCI PCI DMA */
1595#define PCIPCI_TRITON           2
1596#define PCIPCI_NATOMA           4
1597#define PCIPCI_VIAETBF          8
1598#define PCIPCI_VSFX             16
1599#define PCIPCI_ALIMAGIK         32      /* Need low latency setting */
1600#define PCIAGP_FAIL             64      /* No PCI to AGP DMA */
1601
1602extern unsigned long pci_cardbus_io_size;
1603extern unsigned long pci_cardbus_mem_size;
1604extern u8 pci_dfl_cache_line_size;
1605extern u8 pci_cache_line_size;
1606
1607extern unsigned long pci_hotplug_io_size;
1608extern unsigned long pci_hotplug_mem_size;
1609
1610/* Architecture specific versions may override these (weak) */
1611int pcibios_add_platform_entries(struct pci_dev *dev);
1612void pcibios_disable_device(struct pci_dev *dev);
1613void pcibios_set_master(struct pci_dev *dev);
1614int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1615                                 enum pcie_reset_state state);
1616int pcibios_add_device(struct pci_dev *dev);
1617
1618#ifdef CONFIG_PCI_MMCONFIG
1619extern void __init pci_mmcfg_early_init(void);
1620extern void __init pci_mmcfg_late_init(void);
1621#else
1622static inline void pci_mmcfg_early_init(void) { }
1623static inline void pci_mmcfg_late_init(void) { }
1624#endif
1625
1626int pci_ext_cfg_avail(void);
1627
1628void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1629
1630#ifdef CONFIG_PCI_IOV
1631extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1632extern void pci_disable_sriov(struct pci_dev *dev);
1633extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1634extern int pci_num_vf(struct pci_dev *dev);
1635extern int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1636extern int pci_sriov_get_totalvfs(struct pci_dev *dev);
1637#else
1638static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1639{
1640        return -ENODEV;
1641}
1642static inline void pci_disable_sriov(struct pci_dev *dev)
1643{
1644}
1645static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1646{
1647        return IRQ_NONE;
1648}
1649static inline int pci_num_vf(struct pci_dev *dev)
1650{
1651        return 0;
1652}
1653static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1654{
1655        return 0;
1656}
1657static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1658{
1659        return 0;
1660}
1661#endif
1662
1663#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1664extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1665extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1666#endif
1667
1668/**
1669 * pci_pcie_cap - get the saved PCIe capability offset
1670 * @dev: PCI device
1671 *
1672 * PCIe capability offset is calculated at PCI device initialization
1673 * time and saved in the data structure. This function returns saved
1674 * PCIe capability offset. Using this instead of pci_find_capability()
1675 * reduces unnecessary search in the PCI configuration space. If you
1676 * need to calculate PCIe capability offset from raw device for some
1677 * reasons, please use pci_find_capability() instead.
1678 */
1679static inline int pci_pcie_cap(struct pci_dev *dev)
1680{
1681        return dev->pcie_cap;
1682}
1683
1684/**
1685 * pci_is_pcie - check if the PCI device is PCI Express capable
1686 * @dev: PCI device
1687 *
1688 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1689 */
1690static inline bool pci_is_pcie(struct pci_dev *dev)
1691{
1692        return !!pci_pcie_cap(dev);
1693}
1694
1695/**
1696 * pci_pcie_type - get the PCIe device/port type
1697 * @dev: PCI device
1698 */
1699static inline int pci_pcie_type(const struct pci_dev *dev)
1700{
1701        return (dev->pcie_flags_reg & PCI_EXP_FLAGS_TYPE) >> 4;
1702}
1703
1704void pci_request_acs(void);
1705bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1706bool pci_acs_path_enabled(struct pci_dev *start,
1707                          struct pci_dev *end, u16 acs_flags);
1708
1709#define PCI_VPD_LRDT                    0x80    /* Large Resource Data Type */
1710#define PCI_VPD_LRDT_ID(x)              (x | PCI_VPD_LRDT)
1711
1712/* Large Resource Data Type Tag Item Names */
1713#define PCI_VPD_LTIN_ID_STRING          0x02    /* Identifier String */
1714#define PCI_VPD_LTIN_RO_DATA            0x10    /* Read-Only Data */
1715#define PCI_VPD_LTIN_RW_DATA            0x11    /* Read-Write Data */
1716
1717#define PCI_VPD_LRDT_ID_STRING          PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1718#define PCI_VPD_LRDT_RO_DATA            PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1719#define PCI_VPD_LRDT_RW_DATA            PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1720
1721/* Small Resource Data Type Tag Item Names */
1722#define PCI_VPD_STIN_END                0x78    /* End */
1723
1724#define PCI_VPD_SRDT_END                PCI_VPD_STIN_END
1725
1726#define PCI_VPD_SRDT_TIN_MASK           0x78
1727#define PCI_VPD_SRDT_LEN_MASK           0x07
1728
1729#define PCI_VPD_LRDT_TAG_SIZE           3
1730#define PCI_VPD_SRDT_TAG_SIZE           1
1731
1732#define PCI_VPD_INFO_FLD_HDR_SIZE       3
1733
1734#define PCI_VPD_RO_KEYWORD_PARTNO       "PN"
1735#define PCI_VPD_RO_KEYWORD_MFR_ID       "MN"
1736#define PCI_VPD_RO_KEYWORD_VENDOR0      "V0"
1737#define PCI_VPD_RO_KEYWORD_CHKSUM       "RV"
1738
1739/**
1740 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1741 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1742 *
1743 * Returns the extracted Large Resource Data Type length.
1744 */
1745static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1746{
1747        return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1748}
1749
1750/**
1751 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1752 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1753 *
1754 * Returns the extracted Small Resource Data Type length.
1755 */
1756static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1757{
1758        return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1759}
1760
1761/**
1762 * pci_vpd_info_field_size - Extracts the information field length
1763 * @lrdt: Pointer to the beginning of an information field header
1764 *
1765 * Returns the extracted information field length.
1766 */
1767static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1768{
1769        return info_field[2];
1770}
1771
1772/**
1773 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1774 * @buf: Pointer to buffered vpd data
1775 * @off: The offset into the buffer at which to begin the search
1776 * @len: The length of the vpd buffer
1777 * @rdt: The Resource Data Type to search for
1778 *
1779 * Returns the index where the Resource Data Type was found or
1780 * -ENOENT otherwise.
1781 */
1782int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1783
1784/**
1785 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1786 * @buf: Pointer to buffered vpd data
1787 * @off: The offset into the buffer at which to begin the search
1788 * @len: The length of the buffer area, relative to off, in which to search
1789 * @kw: The keyword to search for
1790 *
1791 * Returns the index where the information field keyword was found or
1792 * -ENOENT otherwise.
1793 */
1794int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1795                              unsigned int len, const char *kw);
1796
1797/* PCI <-> OF binding helpers */
1798#ifdef CONFIG_OF
1799struct device_node;
1800extern void pci_set_of_node(struct pci_dev *dev);
1801extern void pci_release_of_node(struct pci_dev *dev);
1802extern void pci_set_bus_of_node(struct pci_bus *bus);
1803extern void pci_release_bus_of_node(struct pci_bus *bus);
1804
1805/* Arch may override this (weak) */
1806extern struct device_node * __weak pcibios_get_phb_of_node(struct pci_bus *bus);
1807
1808static inline struct device_node *
1809pci_device_to_OF_node(const struct pci_dev *pdev)
1810{
1811        return pdev ? pdev->dev.of_node : NULL;
1812}
1813
1814static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1815{
1816        return bus ? bus->dev.of_node : NULL;
1817}
1818
1819#else /* CONFIG_OF */
1820static inline void pci_set_of_node(struct pci_dev *dev) { }
1821static inline void pci_release_of_node(struct pci_dev *dev) { }
1822static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1823static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1824#endif  /* CONFIG_OF */
1825
1826#ifdef CONFIG_EEH
1827static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
1828{
1829        return pdev->dev.archdata.edev;
1830}
1831#endif
1832
1833/**
1834 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1835 * @pdev: the PCI device
1836 *
1837 * if the device is PCIE, return NULL
1838 * if the device isn't connected to a PCIe bridge (that is its parent is a
1839 * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1840 * parent
1841 */
1842struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
1843
1844#endif /* LINUX_PCI_H */
1845
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