linux/include/linux/omap-dma.h
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   1/*
   2 * OMAP DMA Engine support
   3 *
   4 * This program is free software; you can redistribute it and/or modify
   5 * it under the terms of the GNU General Public License version 2 as
   6 * published by the Free Software Foundation.
   7 */
   8#ifndef __LINUX_OMAP_DMA_H
   9#define __LINUX_OMAP_DMA_H
  10
  11struct dma_chan;
  12
  13#if defined(CONFIG_DMA_OMAP) || defined(CONFIG_DMA_OMAP_MODULE)
  14bool omap_dma_filter_fn(struct dma_chan *, void *);
  15#else
  16static inline bool omap_dma_filter_fn(struct dma_chan *c, void *d)
  17{
  18        return false;
  19}
  20#endif
  21
  22/*
  23 *  Legacy OMAP DMA handling defines and functions
  24 *
  25 *  NOTE: Do not use these any longer.
  26 *
  27 *  Use the generic dmaengine functions as defined in
  28 *  include/linux/dmaengine.h.
  29 *
  30 *  Copyright (C) 2003 Nokia Corporation
  31 *  Author: Juha Yrjölä <juha.yrjola@nokia.com>
  32 *
  33 */
  34
  35#include <linux/platform_device.h>
  36
  37#define INT_DMA_LCD                     25
  38
  39#define OMAP1_DMA_TOUT_IRQ              (1 << 0)
  40#define OMAP_DMA_DROP_IRQ               (1 << 1)
  41#define OMAP_DMA_HALF_IRQ               (1 << 2)
  42#define OMAP_DMA_FRAME_IRQ              (1 << 3)
  43#define OMAP_DMA_LAST_IRQ               (1 << 4)
  44#define OMAP_DMA_BLOCK_IRQ              (1 << 5)
  45#define OMAP1_DMA_SYNC_IRQ              (1 << 6)
  46#define OMAP2_DMA_PKT_IRQ               (1 << 7)
  47#define OMAP2_DMA_TRANS_ERR_IRQ         (1 << 8)
  48#define OMAP2_DMA_SECURE_ERR_IRQ        (1 << 9)
  49#define OMAP2_DMA_SUPERVISOR_ERR_IRQ    (1 << 10)
  50#define OMAP2_DMA_MISALIGNED_ERR_IRQ    (1 << 11)
  51
  52#define OMAP_DMA_CCR_EN                 (1 << 7)
  53#define OMAP_DMA_CCR_RD_ACTIVE          (1 << 9)
  54#define OMAP_DMA_CCR_WR_ACTIVE          (1 << 10)
  55#define OMAP_DMA_CCR_SEL_SRC_DST_SYNC   (1 << 24)
  56#define OMAP_DMA_CCR_BUFFERING_DISABLE  (1 << 25)
  57
  58#define OMAP_DMA_DATA_TYPE_S8           0x00
  59#define OMAP_DMA_DATA_TYPE_S16          0x01
  60#define OMAP_DMA_DATA_TYPE_S32          0x02
  61
  62#define OMAP_DMA_SYNC_ELEMENT           0x00
  63#define OMAP_DMA_SYNC_FRAME             0x01
  64#define OMAP_DMA_SYNC_BLOCK             0x02
  65#define OMAP_DMA_SYNC_PACKET            0x03
  66
  67#define OMAP_DMA_DST_SYNC_PREFETCH      0x02
  68#define OMAP_DMA_SRC_SYNC               0x01
  69#define OMAP_DMA_DST_SYNC               0x00
  70
  71#define OMAP_DMA_PORT_EMIFF             0x00
  72#define OMAP_DMA_PORT_EMIFS             0x01
  73#define OMAP_DMA_PORT_OCP_T1            0x02
  74#define OMAP_DMA_PORT_TIPB              0x03
  75#define OMAP_DMA_PORT_OCP_T2            0x04
  76#define OMAP_DMA_PORT_MPUI              0x05
  77
  78#define OMAP_DMA_AMODE_CONSTANT         0x00
  79#define OMAP_DMA_AMODE_POST_INC         0x01
  80#define OMAP_DMA_AMODE_SINGLE_IDX       0x02
  81#define OMAP_DMA_AMODE_DOUBLE_IDX       0x03
  82
  83#define DMA_DEFAULT_FIFO_DEPTH          0x10
  84#define DMA_DEFAULT_ARB_RATE            0x01
  85/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
  86#define DMA_THREAD_RESERVE_NORM         (0x00 << 12) /* Def */
  87#define DMA_THREAD_RESERVE_ONET         (0x01 << 12)
  88#define DMA_THREAD_RESERVE_TWOT         (0x02 << 12)
  89#define DMA_THREAD_RESERVE_THREET       (0x03 << 12)
  90#define DMA_THREAD_FIFO_NONE            (0x00 << 14) /* Def */
  91#define DMA_THREAD_FIFO_75              (0x01 << 14)
  92#define DMA_THREAD_FIFO_25              (0x02 << 14)
  93#define DMA_THREAD_FIFO_50              (0x03 << 14)
  94
  95/* DMA4_OCP_SYSCONFIG bits */
  96#define DMA_SYSCONFIG_MIDLEMODE_MASK            (3 << 12)
  97#define DMA_SYSCONFIG_CLOCKACTIVITY_MASK        (3 << 8)
  98#define DMA_SYSCONFIG_EMUFREE                   (1 << 5)
  99#define DMA_SYSCONFIG_SIDLEMODE_MASK            (3 << 3)
 100#define DMA_SYSCONFIG_SOFTRESET                 (1 << 2)
 101#define DMA_SYSCONFIG_AUTOIDLE                  (1 << 0)
 102
 103#define DMA_SYSCONFIG_MIDLEMODE(n)              ((n) << 12)
 104#define DMA_SYSCONFIG_SIDLEMODE(n)              ((n) << 3)
 105
 106#define DMA_IDLEMODE_SMARTIDLE                  0x2
 107#define DMA_IDLEMODE_NO_IDLE                    0x1
 108#define DMA_IDLEMODE_FORCE_IDLE                 0x0
 109
 110/* Chaining modes*/
 111#ifndef CONFIG_ARCH_OMAP1
 112#define OMAP_DMA_STATIC_CHAIN           0x1
 113#define OMAP_DMA_DYNAMIC_CHAIN          0x2
 114#define OMAP_DMA_CHAIN_ACTIVE           0x1
 115#define OMAP_DMA_CHAIN_INACTIVE         0x0
 116#endif
 117
 118#define DMA_CH_PRIO_HIGH                0x1
 119#define DMA_CH_PRIO_LOW                 0x0 /* Def */
 120
 121/* Errata handling */
 122#define IS_DMA_ERRATA(id)               (errata & (id))
 123#define SET_DMA_ERRATA(id)              (errata |= (id))
 124
 125#define DMA_ERRATA_IFRAME_BUFFERING     BIT(0x0)
 126#define DMA_ERRATA_PARALLEL_CHANNELS    BIT(0x1)
 127#define DMA_ERRATA_i378                 BIT(0x2)
 128#define DMA_ERRATA_i541                 BIT(0x3)
 129#define DMA_ERRATA_i88                  BIT(0x4)
 130#define DMA_ERRATA_3_3                  BIT(0x5)
 131#define DMA_ROMCODE_BUG                 BIT(0x6)
 132
 133/* Attributes for OMAP DMA Contrller */
 134#define DMA_LINKED_LCH                  BIT(0x0)
 135#define GLOBAL_PRIORITY                 BIT(0x1)
 136#define RESERVE_CHANNEL                 BIT(0x2)
 137#define IS_CSSA_32                      BIT(0x3)
 138#define IS_CDSA_32                      BIT(0x4)
 139#define IS_RW_PRIORITY                  BIT(0x5)
 140#define ENABLE_1510_MODE                BIT(0x6)
 141#define SRC_PORT                        BIT(0x7)
 142#define DST_PORT                        BIT(0x8)
 143#define SRC_INDEX                       BIT(0x9)
 144#define DST_INDEX                       BIT(0xa)
 145#define IS_BURST_ONLY4                  BIT(0xb)
 146#define CLEAR_CSR_ON_READ               BIT(0xc)
 147#define IS_WORD_16                      BIT(0xd)
 148#define ENABLE_16XX_MODE                BIT(0xe)
 149#define HS_CHANNELS_RESERVED            BIT(0xf)
 150
 151/* Defines for DMA Capabilities */
 152#define DMA_HAS_TRANSPARENT_CAPS        (0x1 << 18)
 153#define DMA_HAS_CONSTANT_FILL_CAPS      (0x1 << 19)
 154#define DMA_HAS_DESCRIPTOR_CAPS         (0x3 << 20)
 155
 156enum omap_reg_offsets {
 157
 158GCR,            GSCR,           GRST1,          HW_ID,
 159PCH2_ID,        PCH0_ID,        PCH1_ID,        PCHG_ID,
 160PCHD_ID,        CAPS_0,         CAPS_1,         CAPS_2,
 161CAPS_3,         CAPS_4,         PCH2_SR,        PCH0_SR,
 162PCH1_SR,        PCHD_SR,        REVISION,       IRQSTATUS_L0,
 163IRQSTATUS_L1,   IRQSTATUS_L2,   IRQSTATUS_L3,   IRQENABLE_L0,
 164IRQENABLE_L1,   IRQENABLE_L2,   IRQENABLE_L3,   SYSSTATUS,
 165OCP_SYSCONFIG,
 166
 167/* omap1+ specific */
 168CPC, CCR2, LCH_CTRL,
 169
 170/* Common registers for all omap's */
 171CSDP,           CCR,            CICR,           CSR,
 172CEN,            CFN,            CSFI,           CSEI,
 173CSAC,           CDAC,           CDEI,
 174CDFI,           CLNK_CTRL,
 175
 176/* Channel specific registers */
 177CSSA,           CDSA,           COLOR,
 178CCEN,           CCFN,
 179
 180/* omap3630 and omap4 specific */
 181CDP,            CNDP,           CCDN,
 182
 183};
 184
 185enum omap_dma_burst_mode {
 186        OMAP_DMA_DATA_BURST_DIS = 0,
 187        OMAP_DMA_DATA_BURST_4,
 188        OMAP_DMA_DATA_BURST_8,
 189        OMAP_DMA_DATA_BURST_16,
 190};
 191
 192enum end_type {
 193        OMAP_DMA_LITTLE_ENDIAN = 0,
 194        OMAP_DMA_BIG_ENDIAN
 195};
 196
 197enum omap_dma_color_mode {
 198        OMAP_DMA_COLOR_DIS = 0,
 199        OMAP_DMA_CONSTANT_FILL,
 200        OMAP_DMA_TRANSPARENT_COPY
 201};
 202
 203enum omap_dma_write_mode {
 204        OMAP_DMA_WRITE_NON_POSTED = 0,
 205        OMAP_DMA_WRITE_POSTED,
 206        OMAP_DMA_WRITE_LAST_NON_POSTED
 207};
 208
 209enum omap_dma_channel_mode {
 210        OMAP_DMA_LCH_2D = 0,
 211        OMAP_DMA_LCH_G,
 212        OMAP_DMA_LCH_P,
 213        OMAP_DMA_LCH_PD
 214};
 215
 216struct omap_dma_channel_params {
 217        int data_type;          /* data type 8,16,32 */
 218        int elem_count;         /* number of elements in a frame */
 219        int frame_count;        /* number of frames in a element */
 220
 221        int src_port;           /* Only on OMAP1 REVISIT: Is this needed? */
 222        int src_amode;          /* constant, post increment, indexed,
 223                                        double indexed */
 224        unsigned long src_start;        /* source address : physical */
 225        int src_ei;             /* source element index */
 226        int src_fi;             /* source frame index */
 227
 228        int dst_port;           /* Only on OMAP1 REVISIT: Is this needed? */
 229        int dst_amode;          /* constant, post increment, indexed,
 230                                        double indexed */
 231        unsigned long dst_start;        /* source address : physical */
 232        int dst_ei;             /* source element index */
 233        int dst_fi;             /* source frame index */
 234
 235        int trigger;            /* trigger attached if the channel is
 236                                        synchronized */
 237        int sync_mode;          /* sycn on element, frame , block or packet */
 238        int src_or_dst_synch;   /* source synch(1) or destination synch(0) */
 239
 240        int ie;                 /* interrupt enabled */
 241
 242        unsigned char read_prio;/* read priority */
 243        unsigned char write_prio;/* write priority */
 244
 245#ifndef CONFIG_ARCH_OMAP1
 246        enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
 247#endif
 248};
 249
 250struct omap_dma_lch {
 251        int next_lch;
 252        int dev_id;
 253        u16 saved_csr;
 254        u16 enabled_irqs;
 255        const char *dev_name;
 256        void (*callback)(int lch, u16 ch_status, void *data);
 257        void *data;
 258        long flags;
 259        /* required for Dynamic chaining */
 260        int prev_linked_ch;
 261        int next_linked_ch;
 262        int state;
 263        int chain_id;
 264        int status;
 265};
 266
 267struct omap_dma_dev_attr {
 268        u32 dev_caps;
 269        u16 lch_count;
 270        u16 chan_count;
 271        struct omap_dma_lch *chan;
 272};
 273
 274/* System DMA platform data structure */
 275struct omap_system_dma_plat_info {
 276        struct omap_dma_dev_attr *dma_attr;
 277        u32 errata;
 278        void (*disable_irq_lch)(int lch);
 279        void (*show_dma_caps)(void);
 280        void (*clear_lch_regs)(int lch);
 281        void (*clear_dma)(int lch);
 282        void (*dma_write)(u32 val, int reg, int lch);
 283        u32 (*dma_read)(int reg, int lch);
 284};
 285
 286#ifdef CONFIG_ARCH_OMAP2PLUS
 287#define dma_omap2plus() 1
 288#else
 289#define dma_omap2plus() 0
 290#endif
 291#define dma_omap1()     (!dma_omap2plus())
 292#define dma_omap15xx()  ((dma_omap1() && (d->dev_caps & ENABLE_1510_MODE)))
 293#define dma_omap16xx()  ((dma_omap1() && (d->dev_caps & ENABLE_16XX_MODE)))
 294
 295extern void omap_set_dma_priority(int lch, int dst_port, int priority);
 296extern int omap_request_dma(int dev_id, const char *dev_name,
 297                        void (*callback)(int lch, u16 ch_status, void *data),
 298                        void *data, int *dma_ch);
 299extern void omap_enable_dma_irq(int ch, u16 irq_bits);
 300extern void omap_disable_dma_irq(int ch, u16 irq_bits);
 301extern void omap_free_dma(int ch);
 302extern void omap_start_dma(int lch);
 303extern void omap_stop_dma(int lch);
 304extern void omap_set_dma_transfer_params(int lch, int data_type,
 305                                         int elem_count, int frame_count,
 306                                         int sync_mode,
 307                                         int dma_trigger, int src_or_dst_synch);
 308extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
 309                                    u32 color);
 310extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
 311extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
 312
 313extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 314                                    unsigned long src_start,
 315                                    int src_ei, int src_fi);
 316extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
 317extern void omap_set_dma_src_data_pack(int lch, int enable);
 318extern void omap_set_dma_src_burst_mode(int lch,
 319                                        enum omap_dma_burst_mode burst_mode);
 320
 321extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 322                                     unsigned long dest_start,
 323                                     int dst_ei, int dst_fi);
 324extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
 325extern void omap_set_dma_dest_data_pack(int lch, int enable);
 326extern void omap_set_dma_dest_burst_mode(int lch,
 327                                         enum omap_dma_burst_mode burst_mode);
 328
 329extern void omap_set_dma_params(int lch,
 330                                struct omap_dma_channel_params *params);
 331
 332extern void omap_dma_link_lch(int lch_head, int lch_queue);
 333extern void omap_dma_unlink_lch(int lch_head, int lch_queue);
 334
 335extern int omap_set_dma_callback(int lch,
 336                        void (*callback)(int lch, u16 ch_status, void *data),
 337                        void *data);
 338extern dma_addr_t omap_get_dma_src_pos(int lch);
 339extern dma_addr_t omap_get_dma_dst_pos(int lch);
 340extern void omap_clear_dma(int lch);
 341extern int omap_get_dma_active_status(int lch);
 342extern int omap_dma_running(void);
 343extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
 344                                       int tparams);
 345extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
 346                                 unsigned char write_prio);
 347extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
 348extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
 349extern int omap_get_dma_index(int lch, int *ei, int *fi);
 350
 351void omap_dma_global_context_save(void);
 352void omap_dma_global_context_restore(void);
 353
 354extern void omap_dma_disable_irq(int lch);
 355
 356/* Chaining APIs */
 357#ifndef CONFIG_ARCH_OMAP1
 358extern int omap_request_dma_chain(int dev_id, const char *dev_name,
 359                                  void (*callback) (int lch, u16 ch_status,
 360                                                    void *data),
 361                                  int *chain_id, int no_of_chans,
 362                                  int chain_mode,
 363                                  struct omap_dma_channel_params params);
 364extern int omap_free_dma_chain(int chain_id);
 365extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
 366                                     int dest_start, int elem_count,
 367                                     int frame_count, void *callbk_data);
 368extern int omap_start_dma_chain_transfers(int chain_id);
 369extern int omap_stop_dma_chain_transfers(int chain_id);
 370extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi);
 371extern int omap_get_dma_chain_dst_pos(int chain_id);
 372extern int omap_get_dma_chain_src_pos(int chain_id);
 373
 374extern int omap_modify_dma_chain_params(int chain_id,
 375                                        struct omap_dma_channel_params params);
 376extern int omap_dma_chain_status(int chain_id);
 377#endif
 378
 379#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_FB_OMAP)
 380#include <mach/lcd_dma.h>
 381#else
 382static inline int omap_lcd_dma_running(void)
 383{
 384        return 0;
 385}
 386#endif
 387
 388#endif /* __LINUX_OMAP_DMA_H */
 389
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