linux/drivers/video/mxsfb.c
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   1/*
   2 * Copyright (C) 2010 Juergen Beisert, Pengutronix
   3 *
   4 * This code is based on:
   5 * Author: Vitaly Wool <vital@embeddedalley.com>
   6 *
   7 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
   8 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
   9 *
  10 * This program is free software; you can redistribute it and/or
  11 * modify it under the terms of the GNU General Public License
  12 * as published by the Free Software Foundation; either version 2
  13 * of the License, or (at your option) any later version.
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 */
  19
  20#define DRIVER_NAME "mxsfb"
  21
  22/**
  23 * @file
  24 * @brief LCDIF driver for i.MX23 and i.MX28
  25 *
  26 * The LCDIF support four modes of operation
  27 * - MPU interface (to drive smart displays) -> not supported yet
  28 * - VSYNC interface (like MPU interface plus Vsync) -> not supported yet
  29 * - Dotclock interface (to drive LC displays with RGB data and sync signals)
  30 * - DVI (to drive ITU-R BT656)  -> not supported yet
  31 *
  32 * This driver depends on a correct setup of the pins used for this purpose
  33 * (platform specific).
  34 *
  35 * For the developer: Don't forget to set the data bus width to the display
  36 * in the imx_fb_videomode structure. You will else end up with ugly colours.
  37 * If you fight against jitter you can vary the clock delay. This is a feature
  38 * of the i.MX28 and you can vary it between 2 ns ... 8 ns in 2 ns steps. Give
  39 * the required value in the imx_fb_videomode structure.
  40 */
  41
  42#include <linux/module.h>
  43#include <linux/kernel.h>
  44#include <linux/of_device.h>
  45#include <linux/of_gpio.h>
  46#include <linux/platform_device.h>
  47#include <linux/clk.h>
  48#include <linux/dma-mapping.h>
  49#include <linux/io.h>
  50#include <linux/pinctrl/consumer.h>
  51#include <linux/mxsfb.h>
  52
  53#define REG_SET 4
  54#define REG_CLR 8
  55
  56#define LCDC_CTRL                       0x00
  57#define LCDC_CTRL1                      0x10
  58#define LCDC_V4_CTRL2                   0x20
  59#define LCDC_V3_TRANSFER_COUNT          0x20
  60#define LCDC_V4_TRANSFER_COUNT          0x30
  61#define LCDC_V4_CUR_BUF                 0x40
  62#define LCDC_V4_NEXT_BUF                0x50
  63#define LCDC_V3_CUR_BUF                 0x30
  64#define LCDC_V3_NEXT_BUF                0x40
  65#define LCDC_TIMING                     0x60
  66#define LCDC_VDCTRL0                    0x70
  67#define LCDC_VDCTRL1                    0x80
  68#define LCDC_VDCTRL2                    0x90
  69#define LCDC_VDCTRL3                    0xa0
  70#define LCDC_VDCTRL4                    0xb0
  71#define LCDC_DVICTRL0                   0xc0
  72#define LCDC_DVICTRL1                   0xd0
  73#define LCDC_DVICTRL2                   0xe0
  74#define LCDC_DVICTRL3                   0xf0
  75#define LCDC_DVICTRL4                   0x100
  76#define LCDC_V4_DATA                    0x180
  77#define LCDC_V3_DATA                    0x1b0
  78#define LCDC_V4_DEBUG0                  0x1d0
  79#define LCDC_V3_DEBUG0                  0x1f0
  80
  81#define CTRL_SFTRST                     (1 << 31)
  82#define CTRL_CLKGATE                    (1 << 30)
  83#define CTRL_BYPASS_COUNT               (1 << 19)
  84#define CTRL_VSYNC_MODE                 (1 << 18)
  85#define CTRL_DOTCLK_MODE                (1 << 17)
  86#define CTRL_DATA_SELECT                (1 << 16)
  87#define CTRL_SET_BUS_WIDTH(x)           (((x) & 0x3) << 10)
  88#define CTRL_GET_BUS_WIDTH(x)           (((x) >> 10) & 0x3)
  89#define CTRL_SET_WORD_LENGTH(x)         (((x) & 0x3) << 8)
  90#define CTRL_GET_WORD_LENGTH(x)         (((x) >> 8) & 0x3)
  91#define CTRL_MASTER                     (1 << 5)
  92#define CTRL_DF16                       (1 << 3)
  93#define CTRL_DF18                       (1 << 2)
  94#define CTRL_DF24                       (1 << 1)
  95#define CTRL_RUN                        (1 << 0)
  96
  97#define CTRL1_FIFO_CLEAR                (1 << 21)
  98#define CTRL1_SET_BYTE_PACKAGING(x)     (((x) & 0xf) << 16)
  99#define CTRL1_GET_BYTE_PACKAGING(x)     (((x) >> 16) & 0xf)
 100
 101#define TRANSFER_COUNT_SET_VCOUNT(x)    (((x) & 0xffff) << 16)
 102#define TRANSFER_COUNT_GET_VCOUNT(x)    (((x) >> 16) & 0xffff)
 103#define TRANSFER_COUNT_SET_HCOUNT(x)    ((x) & 0xffff)
 104#define TRANSFER_COUNT_GET_HCOUNT(x)    ((x) & 0xffff)
 105
 106
 107#define VDCTRL0_ENABLE_PRESENT          (1 << 28)
 108#define VDCTRL0_VSYNC_ACT_HIGH          (1 << 27)
 109#define VDCTRL0_HSYNC_ACT_HIGH          (1 << 26)
 110#define VDCTRL0_DOTCLK_ACT_FAILING      (1 << 25)
 111#define VDCTRL0_ENABLE_ACT_HIGH         (1 << 24)
 112#define VDCTRL0_VSYNC_PERIOD_UNIT       (1 << 21)
 113#define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT  (1 << 20)
 114#define VDCTRL0_HALF_LINE               (1 << 19)
 115#define VDCTRL0_HALF_LINE_MODE          (1 << 18)
 116#define VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
 117#define VDCTRL0_GET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
 118
 119#define VDCTRL2_SET_HSYNC_PERIOD(x)     ((x) & 0x3ffff)
 120#define VDCTRL2_GET_HSYNC_PERIOD(x)     ((x) & 0x3ffff)
 121
 122#define VDCTRL3_MUX_SYNC_SIGNALS        (1 << 29)
 123#define VDCTRL3_VSYNC_ONLY              (1 << 28)
 124#define SET_HOR_WAIT_CNT(x)             (((x) & 0xfff) << 16)
 125#define GET_HOR_WAIT_CNT(x)             (((x) >> 16) & 0xfff)
 126#define SET_VERT_WAIT_CNT(x)            ((x) & 0xffff)
 127#define GET_VERT_WAIT_CNT(x)            ((x) & 0xffff)
 128
 129#define VDCTRL4_SET_DOTCLK_DLY(x)       (((x) & 0x7) << 29) /* v4 only */
 130#define VDCTRL4_GET_DOTCLK_DLY(x)       (((x) >> 29) & 0x7) /* v4 only */
 131#define VDCTRL4_SYNC_SIGNALS_ON         (1 << 18)
 132#define SET_DOTCLK_H_VALID_DATA_CNT(x)  ((x) & 0x3ffff)
 133
 134#define DEBUG0_HSYNC                    (1 < 26)
 135#define DEBUG0_VSYNC                    (1 < 25)
 136
 137#define MIN_XRES                        120
 138#define MIN_YRES                        120
 139
 140#define RED 0
 141#define GREEN 1
 142#define BLUE 2
 143#define TRANSP 3
 144
 145enum mxsfb_devtype {
 146        MXSFB_V3,
 147        MXSFB_V4,
 148};
 149
 150/* CPU dependent register offsets */
 151struct mxsfb_devdata {
 152        unsigned transfer_count;
 153        unsigned cur_buf;
 154        unsigned next_buf;
 155        unsigned debug0;
 156        unsigned hs_wdth_mask;
 157        unsigned hs_wdth_shift;
 158        unsigned ipversion;
 159};
 160
 161struct mxsfb_info {
 162        struct fb_info fb_info;
 163        struct platform_device *pdev;
 164        struct clk *clk;
 165        void __iomem *base;     /* registers */
 166        unsigned allocated_size;
 167        int enabled;
 168        unsigned ld_intf_width;
 169        unsigned dotclk_delay;
 170        const struct mxsfb_devdata *devdata;
 171        int mapped;
 172};
 173
 174#define mxsfb_is_v3(host) (host->devdata->ipversion == 3)
 175#define mxsfb_is_v4(host) (host->devdata->ipversion == 4)
 176
 177static const struct mxsfb_devdata mxsfb_devdata[] = {
 178        [MXSFB_V3] = {
 179                .transfer_count = LCDC_V3_TRANSFER_COUNT,
 180                .cur_buf = LCDC_V3_CUR_BUF,
 181                .next_buf = LCDC_V3_NEXT_BUF,
 182                .debug0 = LCDC_V3_DEBUG0,
 183                .hs_wdth_mask = 0xff,
 184                .hs_wdth_shift = 24,
 185                .ipversion = 3,
 186        },
 187        [MXSFB_V4] = {
 188                .transfer_count = LCDC_V4_TRANSFER_COUNT,
 189                .cur_buf = LCDC_V4_CUR_BUF,
 190                .next_buf = LCDC_V4_NEXT_BUF,
 191                .debug0 = LCDC_V4_DEBUG0,
 192                .hs_wdth_mask = 0x3fff,
 193                .hs_wdth_shift = 18,
 194                .ipversion = 4,
 195        },
 196};
 197
 198#define to_imxfb_host(x) (container_of(x, struct mxsfb_info, fb_info))
 199
 200/* mask and shift depends on architecture */
 201static inline u32 set_hsync_pulse_width(struct mxsfb_info *host, unsigned val)
 202{
 203        return (val & host->devdata->hs_wdth_mask) <<
 204                host->devdata->hs_wdth_shift;
 205}
 206
 207static inline u32 get_hsync_pulse_width(struct mxsfb_info *host, unsigned val)
 208{
 209        return (val >> host->devdata->hs_wdth_shift) &
 210                host->devdata->hs_wdth_mask;
 211}
 212
 213static const struct fb_bitfield def_rgb565[] = {
 214        [RED] = {
 215                .offset = 11,
 216                .length = 5,
 217        },
 218        [GREEN] = {
 219                .offset = 5,
 220                .length = 6,
 221        },
 222        [BLUE] = {
 223                .offset = 0,
 224                .length = 5,
 225        },
 226        [TRANSP] = {    /* no support for transparency */
 227                .length = 0,
 228        }
 229};
 230
 231static const struct fb_bitfield def_rgb666[] = {
 232        [RED] = {
 233                .offset = 16,
 234                .length = 6,
 235        },
 236        [GREEN] = {
 237                .offset = 8,
 238                .length = 6,
 239        },
 240        [BLUE] = {
 241                .offset = 0,
 242                .length = 6,
 243        },
 244        [TRANSP] = {    /* no support for transparency */
 245                .length = 0,
 246        }
 247};
 248
 249static const struct fb_bitfield def_rgb888[] = {
 250        [RED] = {
 251                .offset = 16,
 252                .length = 8,
 253        },
 254        [GREEN] = {
 255                .offset = 8,
 256                .length = 8,
 257        },
 258        [BLUE] = {
 259                .offset = 0,
 260                .length = 8,
 261        },
 262        [TRANSP] = {    /* no support for transparency */
 263                .length = 0,
 264        }
 265};
 266
 267static inline unsigned chan_to_field(unsigned chan, struct fb_bitfield *bf)
 268{
 269        chan &= 0xffff;
 270        chan >>= 16 - bf->length;
 271        return chan << bf->offset;
 272}
 273
 274static int mxsfb_check_var(struct fb_var_screeninfo *var,
 275                struct fb_info *fb_info)
 276{
 277        struct mxsfb_info *host = to_imxfb_host(fb_info);
 278        const struct fb_bitfield *rgb = NULL;
 279
 280        if (var->xres < MIN_XRES)
 281                var->xres = MIN_XRES;
 282        if (var->yres < MIN_YRES)
 283                var->yres = MIN_YRES;
 284
 285        var->xres_virtual = var->xres;
 286
 287        var->yres_virtual = var->yres;
 288
 289        switch (var->bits_per_pixel) {
 290        case 16:
 291                /* always expect RGB 565 */
 292                rgb = def_rgb565;
 293                break;
 294        case 32:
 295                switch (host->ld_intf_width) {
 296                case STMLCDIF_8BIT:
 297                        pr_debug("Unsupported LCD bus width mapping\n");
 298                        break;
 299                case STMLCDIF_16BIT:
 300                case STMLCDIF_18BIT:
 301                        /* 24 bit to 18 bit mapping */
 302                        rgb = def_rgb666;
 303                        break;
 304                case STMLCDIF_24BIT:
 305                        /* real 24 bit */
 306                        rgb = def_rgb888;
 307                        break;
 308                }
 309                break;
 310        default:
 311                pr_debug("Unsupported colour depth: %u\n", var->bits_per_pixel);
 312                return -EINVAL;
 313        }
 314
 315        /*
 316         * Copy the RGB parameters for this display
 317         * from the machine specific parameters.
 318         */
 319        var->red    = rgb[RED];
 320        var->green  = rgb[GREEN];
 321        var->blue   = rgb[BLUE];
 322        var->transp = rgb[TRANSP];
 323
 324        return 0;
 325}
 326
 327static void mxsfb_enable_controller(struct fb_info *fb_info)
 328{
 329        struct mxsfb_info *host = to_imxfb_host(fb_info);
 330        u32 reg;
 331
 332        dev_dbg(&host->pdev->dev, "%s\n", __func__);
 333
 334        clk_prepare_enable(host->clk);
 335        clk_set_rate(host->clk, PICOS2KHZ(fb_info->var.pixclock) * 1000U);
 336
 337        /* if it was disabled, re-enable the mode again */
 338        writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_SET);
 339
 340        /* enable the SYNC signals first, then the DMA engine */
 341        reg = readl(host->base + LCDC_VDCTRL4);
 342        reg |= VDCTRL4_SYNC_SIGNALS_ON;
 343        writel(reg, host->base + LCDC_VDCTRL4);
 344
 345        writel(CTRL_RUN, host->base + LCDC_CTRL + REG_SET);
 346
 347        host->enabled = 1;
 348}
 349
 350static void mxsfb_disable_controller(struct fb_info *fb_info)
 351{
 352        struct mxsfb_info *host = to_imxfb_host(fb_info);
 353        unsigned loop;
 354        u32 reg;
 355
 356        dev_dbg(&host->pdev->dev, "%s\n", __func__);
 357
 358        /*
 359         * Even if we disable the controller here, it will still continue
 360         * until its FIFOs are running out of data
 361         */
 362        writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_CLR);
 363
 364        loop = 1000;
 365        while (loop) {
 366                reg = readl(host->base + LCDC_CTRL);
 367                if (!(reg & CTRL_RUN))
 368                        break;
 369                loop--;
 370        }
 371
 372        reg = readl(host->base + LCDC_VDCTRL4);
 373        writel(reg & ~VDCTRL4_SYNC_SIGNALS_ON, host->base + LCDC_VDCTRL4);
 374
 375        clk_disable_unprepare(host->clk);
 376
 377        host->enabled = 0;
 378}
 379
 380static int mxsfb_set_par(struct fb_info *fb_info)
 381{
 382        struct mxsfb_info *host = to_imxfb_host(fb_info);
 383        u32 ctrl, vdctrl0, vdctrl4;
 384        int line_size, fb_size;
 385        int reenable = 0;
 386
 387        line_size =  fb_info->var.xres * (fb_info->var.bits_per_pixel >> 3);
 388        fb_size = fb_info->var.yres_virtual * line_size;
 389
 390        if (fb_size > fb_info->fix.smem_len)
 391                return -ENOMEM;
 392
 393        fb_info->fix.line_length = line_size;
 394
 395        /*
 396         * It seems, you can't re-program the controller if it is still running.
 397         * This may lead into shifted pictures (FIFO issue?).
 398         * So, first stop the controller and drain its FIFOs
 399         */
 400        if (host->enabled) {
 401                reenable = 1;
 402                mxsfb_disable_controller(fb_info);
 403        }
 404
 405        /* clear the FIFOs */
 406        writel(CTRL1_FIFO_CLEAR, host->base + LCDC_CTRL1 + REG_SET);
 407
 408        ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER |
 409                CTRL_SET_BUS_WIDTH(host->ld_intf_width);
 410
 411        switch (fb_info->var.bits_per_pixel) {
 412        case 16:
 413                dev_dbg(&host->pdev->dev, "Setting up RGB565 mode\n");
 414                ctrl |= CTRL_SET_WORD_LENGTH(0);
 415                writel(CTRL1_SET_BYTE_PACKAGING(0xf), host->base + LCDC_CTRL1);
 416                break;
 417        case 32:
 418                dev_dbg(&host->pdev->dev, "Setting up RGB888/666 mode\n");
 419                ctrl |= CTRL_SET_WORD_LENGTH(3);
 420                switch (host->ld_intf_width) {
 421                case STMLCDIF_8BIT:
 422                        dev_dbg(&host->pdev->dev,
 423                                        "Unsupported LCD bus width mapping\n");
 424                        return -EINVAL;
 425                case STMLCDIF_16BIT:
 426                case STMLCDIF_18BIT:
 427                        /* 24 bit to 18 bit mapping */
 428                        ctrl |= CTRL_DF24; /* ignore the upper 2 bits in
 429                                            *  each colour component
 430                                            */
 431                        break;
 432                case STMLCDIF_24BIT:
 433                        /* real 24 bit */
 434                        break;
 435                }
 436                /* do not use packed pixels = one pixel per word instead */
 437                writel(CTRL1_SET_BYTE_PACKAGING(0x7), host->base + LCDC_CTRL1);
 438                break;
 439        default:
 440                dev_dbg(&host->pdev->dev, "Unhandled color depth of %u\n",
 441                                fb_info->var.bits_per_pixel);
 442                return -EINVAL;
 443        }
 444
 445        writel(ctrl, host->base + LCDC_CTRL);
 446
 447        writel(TRANSFER_COUNT_SET_VCOUNT(fb_info->var.yres) |
 448                        TRANSFER_COUNT_SET_HCOUNT(fb_info->var.xres),
 449                        host->base + host->devdata->transfer_count);
 450
 451        vdctrl0 = VDCTRL0_ENABLE_PRESENT |      /* always in DOTCLOCK mode */
 452                VDCTRL0_VSYNC_PERIOD_UNIT |
 453                VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
 454                VDCTRL0_SET_VSYNC_PULSE_WIDTH(fb_info->var.vsync_len);
 455        if (fb_info->var.sync & FB_SYNC_HOR_HIGH_ACT)
 456                vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH;
 457        if (fb_info->var.sync & FB_SYNC_VERT_HIGH_ACT)
 458                vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH;
 459        if (fb_info->var.sync & FB_SYNC_DATA_ENABLE_HIGH_ACT)
 460                vdctrl0 |= VDCTRL0_ENABLE_ACT_HIGH;
 461        if (fb_info->var.sync & FB_SYNC_DOTCLK_FAILING_ACT)
 462                vdctrl0 |= VDCTRL0_DOTCLK_ACT_FAILING;
 463
 464        writel(vdctrl0, host->base + LCDC_VDCTRL0);
 465
 466        /* frame length in lines */
 467        writel(fb_info->var.upper_margin + fb_info->var.vsync_len +
 468                fb_info->var.lower_margin + fb_info->var.yres,
 469                host->base + LCDC_VDCTRL1);
 470
 471        /* line length in units of clocks or pixels */
 472        writel(set_hsync_pulse_width(host, fb_info->var.hsync_len) |
 473                VDCTRL2_SET_HSYNC_PERIOD(fb_info->var.left_margin +
 474                fb_info->var.hsync_len + fb_info->var.right_margin +
 475                fb_info->var.xres),
 476                host->base + LCDC_VDCTRL2);
 477
 478        writel(SET_HOR_WAIT_CNT(fb_info->var.left_margin +
 479                fb_info->var.hsync_len) |
 480                SET_VERT_WAIT_CNT(fb_info->var.upper_margin +
 481                        fb_info->var.vsync_len),
 482                host->base + LCDC_VDCTRL3);
 483
 484        vdctrl4 = SET_DOTCLK_H_VALID_DATA_CNT(fb_info->var.xres);
 485        if (mxsfb_is_v4(host))
 486                vdctrl4 |= VDCTRL4_SET_DOTCLK_DLY(host->dotclk_delay);
 487        writel(vdctrl4, host->base + LCDC_VDCTRL4);
 488
 489        writel(fb_info->fix.smem_start +
 490                        fb_info->fix.line_length * fb_info->var.yoffset,
 491                        host->base + host->devdata->next_buf);
 492
 493        if (reenable)
 494                mxsfb_enable_controller(fb_info);
 495
 496        return 0;
 497}
 498
 499static int mxsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 500                u_int transp, struct fb_info *fb_info)
 501{
 502        unsigned int val;
 503        int ret = -EINVAL;
 504
 505        /*
 506         * If greyscale is true, then we convert the RGB value
 507         * to greyscale no matter what visual we are using.
 508         */
 509        if (fb_info->var.grayscale)
 510                red = green = blue = (19595 * red + 38470 * green +
 511                                        7471 * blue) >> 16;
 512
 513        switch (fb_info->fix.visual) {
 514        case FB_VISUAL_TRUECOLOR:
 515                /*
 516                 * 12 or 16-bit True Colour.  We encode the RGB value
 517                 * according to the RGB bitfield information.
 518                 */
 519                if (regno < 16) {
 520                        u32 *pal = fb_info->pseudo_palette;
 521
 522                        val  = chan_to_field(red, &fb_info->var.red);
 523                        val |= chan_to_field(green, &fb_info->var.green);
 524                        val |= chan_to_field(blue, &fb_info->var.blue);
 525
 526                        pal[regno] = val;
 527                        ret = 0;
 528                }
 529                break;
 530
 531        case FB_VISUAL_STATIC_PSEUDOCOLOR:
 532        case FB_VISUAL_PSEUDOCOLOR:
 533                break;
 534        }
 535
 536        return ret;
 537}
 538
 539static int mxsfb_blank(int blank, struct fb_info *fb_info)
 540{
 541        struct mxsfb_info *host = to_imxfb_host(fb_info);
 542
 543        switch (blank) {
 544        case FB_BLANK_POWERDOWN:
 545        case FB_BLANK_VSYNC_SUSPEND:
 546        case FB_BLANK_HSYNC_SUSPEND:
 547        case FB_BLANK_NORMAL:
 548                if (host->enabled)
 549                        mxsfb_disable_controller(fb_info);
 550                break;
 551
 552        case FB_BLANK_UNBLANK:
 553                if (!host->enabled)
 554                        mxsfb_enable_controller(fb_info);
 555                break;
 556        }
 557        return 0;
 558}
 559
 560static int mxsfb_pan_display(struct fb_var_screeninfo *var,
 561                struct fb_info *fb_info)
 562{
 563        struct mxsfb_info *host = to_imxfb_host(fb_info);
 564        unsigned offset;
 565
 566        if (var->xoffset != 0)
 567                return -EINVAL;
 568
 569        offset = fb_info->fix.line_length * var->yoffset;
 570
 571        /* update on next VSYNC */
 572        writel(fb_info->fix.smem_start + offset,
 573                        host->base + host->devdata->next_buf);
 574
 575        return 0;
 576}
 577
 578static struct fb_ops mxsfb_ops = {
 579        .owner = THIS_MODULE,
 580        .fb_check_var = mxsfb_check_var,
 581        .fb_set_par = mxsfb_set_par,
 582        .fb_setcolreg = mxsfb_setcolreg,
 583        .fb_blank = mxsfb_blank,
 584        .fb_pan_display = mxsfb_pan_display,
 585        .fb_fillrect = cfb_fillrect,
 586        .fb_copyarea = cfb_copyarea,
 587        .fb_imageblit = cfb_imageblit,
 588};
 589
 590static int mxsfb_restore_mode(struct mxsfb_info *host)
 591{
 592        struct fb_info *fb_info = &host->fb_info;
 593        unsigned line_count;
 594        unsigned period;
 595        unsigned long pa, fbsize;
 596        int bits_per_pixel, ofs;
 597        u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl;
 598        struct fb_videomode vmode;
 599
 600        /* Only restore the mode when the controller is running */
 601        ctrl = readl(host->base + LCDC_CTRL);
 602        if (!(ctrl & CTRL_RUN))
 603                return -EINVAL;
 604
 605        vdctrl0 = readl(host->base + LCDC_VDCTRL0);
 606        vdctrl2 = readl(host->base + LCDC_VDCTRL2);
 607        vdctrl3 = readl(host->base + LCDC_VDCTRL3);
 608        vdctrl4 = readl(host->base + LCDC_VDCTRL4);
 609
 610        transfer_count = readl(host->base + host->devdata->transfer_count);
 611
 612        vmode.xres = TRANSFER_COUNT_GET_HCOUNT(transfer_count);
 613        vmode.yres = TRANSFER_COUNT_GET_VCOUNT(transfer_count);
 614
 615        switch (CTRL_GET_WORD_LENGTH(ctrl)) {
 616        case 0:
 617                bits_per_pixel = 16;
 618                break;
 619        case 3:
 620                bits_per_pixel = 32;
 621        case 1:
 622        default:
 623                return -EINVAL;
 624        }
 625
 626        fb_info->var.bits_per_pixel = bits_per_pixel;
 627
 628        vmode.pixclock = KHZ2PICOS(clk_get_rate(host->clk) / 1000U);
 629        vmode.hsync_len = get_hsync_pulse_width(host, vdctrl2);
 630        vmode.left_margin = GET_HOR_WAIT_CNT(vdctrl3) - vmode.hsync_len;
 631        vmode.right_margin = VDCTRL2_GET_HSYNC_PERIOD(vdctrl2) - vmode.hsync_len -
 632                vmode.left_margin - vmode.xres;
 633        vmode.vsync_len = VDCTRL0_GET_VSYNC_PULSE_WIDTH(vdctrl0);
 634        period = readl(host->base + LCDC_VDCTRL1);
 635        vmode.upper_margin = GET_VERT_WAIT_CNT(vdctrl3) - vmode.vsync_len;
 636        vmode.lower_margin = period - vmode.vsync_len - vmode.upper_margin - vmode.yres;
 637
 638        vmode.vmode = FB_VMODE_NONINTERLACED;
 639
 640        vmode.sync = 0;
 641        if (vdctrl0 & VDCTRL0_HSYNC_ACT_HIGH)
 642                vmode.sync |= FB_SYNC_HOR_HIGH_ACT;
 643        if (vdctrl0 & VDCTRL0_VSYNC_ACT_HIGH)
 644                vmode.sync |= FB_SYNC_VERT_HIGH_ACT;
 645
 646        pr_debug("Reconstructed video mode:\n");
 647        pr_debug("%dx%d, hsync: %u left: %u, right: %u, vsync: %u, upper: %u, lower: %u\n",
 648                        vmode.xres, vmode.yres,
 649                        vmode.hsync_len, vmode.left_margin, vmode.right_margin,
 650                        vmode.vsync_len, vmode.upper_margin, vmode.lower_margin);
 651        pr_debug("pixclk: %ldkHz\n", PICOS2KHZ(vmode.pixclock));
 652
 653        fb_add_videomode(&vmode, &fb_info->modelist);
 654
 655        host->ld_intf_width = CTRL_GET_BUS_WIDTH(ctrl);
 656        host->dotclk_delay = VDCTRL4_GET_DOTCLK_DLY(vdctrl4);
 657
 658        fb_info->fix.line_length = vmode.xres * (bits_per_pixel >> 3);
 659
 660        pa = readl(host->base + host->devdata->cur_buf);
 661        fbsize = fb_info->fix.line_length * vmode.yres;
 662        if (pa < fb_info->fix.smem_start)
 663                return -EINVAL;
 664        if (pa + fbsize > fb_info->fix.smem_start + fb_info->fix.smem_len)
 665                return -EINVAL;
 666        ofs = pa - fb_info->fix.smem_start;
 667        if (ofs) {
 668                memmove(fb_info->screen_base, fb_info->screen_base + ofs, fbsize);
 669                writel(fb_info->fix.smem_start, host->base + host->devdata->next_buf);
 670        }
 671
 672        line_count = fb_info->fix.smem_len / fb_info->fix.line_length;
 673        fb_info->fix.ypanstep = 1;
 674
 675        clk_prepare_enable(host->clk);
 676        host->enabled = 1;
 677
 678        return 0;
 679}
 680
 681static int mxsfb_init_fbinfo(struct mxsfb_info *host)
 682{
 683        struct fb_info *fb_info = &host->fb_info;
 684        struct fb_var_screeninfo *var = &fb_info->var;
 685        struct mxsfb_platform_data *pdata = host->pdev->dev.platform_data;
 686        dma_addr_t fb_phys;
 687        void *fb_virt;
 688        unsigned fb_size = pdata->fb_size;
 689
 690        fb_info->fbops = &mxsfb_ops;
 691        fb_info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST;
 692        strlcpy(fb_info->fix.id, "mxs", sizeof(fb_info->fix.id));
 693        fb_info->fix.type = FB_TYPE_PACKED_PIXELS;
 694        fb_info->fix.ypanstep = 1;
 695        fb_info->fix.visual = FB_VISUAL_TRUECOLOR,
 696        fb_info->fix.accel = FB_ACCEL_NONE;
 697
 698        var->bits_per_pixel = pdata->default_bpp ? pdata->default_bpp : 16;
 699        var->nonstd = 0;
 700        var->activate = FB_ACTIVATE_NOW;
 701        var->accel_flags = 0;
 702        var->vmode = FB_VMODE_NONINTERLACED;
 703
 704        host->dotclk_delay = pdata->dotclk_delay;
 705        host->ld_intf_width = pdata->ld_intf_width;
 706
 707        /* Memory allocation for framebuffer */
 708        if (pdata->fb_phys) {
 709                if (!fb_size)
 710                        return -EINVAL;
 711
 712                fb_phys = pdata->fb_phys;
 713
 714                if (!request_mem_region(fb_phys, fb_size, host->pdev->name))
 715                        return -ENOMEM;
 716
 717                fb_virt = ioremap(fb_phys, fb_size);
 718                if (!fb_virt) {
 719                        release_mem_region(fb_phys, fb_size);
 720                        return -ENOMEM;
 721                }
 722                host->mapped = 1;
 723        } else {
 724                if (!fb_size)
 725                        fb_size = SZ_2M; /* default */
 726                fb_virt = alloc_pages_exact(fb_size, GFP_DMA);
 727                if (!fb_virt)
 728                        return -ENOMEM;
 729
 730                fb_phys = virt_to_phys(fb_virt);
 731        }
 732
 733        fb_info->fix.smem_start = fb_phys;
 734        fb_info->screen_base = fb_virt;
 735        fb_info->screen_size = fb_info->fix.smem_len = fb_size;
 736
 737        if (mxsfb_restore_mode(host))
 738                memset(fb_virt, 0, fb_size);
 739
 740        return 0;
 741}
 742
 743static void mxsfb_free_videomem(struct mxsfb_info *host)
 744{
 745        struct fb_info *fb_info = &host->fb_info;
 746
 747        if (host->mapped) {
 748                iounmap(fb_info->screen_base);
 749                release_mem_region(fb_info->fix.smem_start,
 750                                fb_info->screen_size);
 751        } else {
 752                free_pages_exact(fb_info->screen_base, fb_info->fix.smem_len);
 753        }
 754}
 755
 756static struct platform_device_id mxsfb_devtype[] = {
 757        {
 758                .name = "imx23-fb",
 759                .driver_data = MXSFB_V3,
 760        }, {
 761                .name = "imx28-fb",
 762                .driver_data = MXSFB_V4,
 763        }, {
 764                /* sentinel */
 765        }
 766};
 767MODULE_DEVICE_TABLE(platform, mxsfb_devtype);
 768
 769static const struct of_device_id mxsfb_dt_ids[] = {
 770        { .compatible = "fsl,imx23-lcdif", .data = &mxsfb_devtype[0], },
 771        { .compatible = "fsl,imx28-lcdif", .data = &mxsfb_devtype[1], },
 772        { /* sentinel */ }
 773};
 774MODULE_DEVICE_TABLE(of, mxsfb_dt_ids);
 775
 776static int mxsfb_probe(struct platform_device *pdev)
 777{
 778        const struct of_device_id *of_id =
 779                        of_match_device(mxsfb_dt_ids, &pdev->dev);
 780        struct mxsfb_platform_data *pdata = pdev->dev.platform_data;
 781        struct resource *res;
 782        struct mxsfb_info *host;
 783        struct fb_info *fb_info;
 784        struct fb_modelist *modelist;
 785        struct pinctrl *pinctrl;
 786        int panel_enable;
 787        enum of_gpio_flags flags;
 788        int i, ret;
 789
 790        if (of_id)
 791                pdev->id_entry = of_id->data;
 792
 793        if (!pdata) {
 794                dev_err(&pdev->dev, "No platformdata. Giving up\n");
 795                return -ENODEV;
 796        }
 797
 798        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 799        if (!res) {
 800                dev_err(&pdev->dev, "Cannot get memory IO resource\n");
 801                return -ENODEV;
 802        }
 803
 804        if (!request_mem_region(res->start, resource_size(res), pdev->name))
 805                return -EBUSY;
 806
 807        fb_info = framebuffer_alloc(sizeof(struct mxsfb_info), &pdev->dev);
 808        if (!fb_info) {
 809                dev_err(&pdev->dev, "Failed to allocate fbdev\n");
 810                ret = -ENOMEM;
 811                goto error_alloc_info;
 812        }
 813
 814        host = to_imxfb_host(fb_info);
 815
 816        host->base = ioremap(res->start, resource_size(res));
 817        if (!host->base) {
 818                dev_err(&pdev->dev, "ioremap failed\n");
 819                ret = -ENOMEM;
 820                goto error_ioremap;
 821        }
 822
 823        host->pdev = pdev;
 824        platform_set_drvdata(pdev, host);
 825
 826        host->devdata = &mxsfb_devdata[pdev->id_entry->driver_data];
 827
 828        pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
 829        if (IS_ERR(pinctrl)) {
 830                ret = PTR_ERR(pinctrl);
 831                goto error_getpin;
 832        }
 833
 834        host->clk = clk_get(&host->pdev->dev, NULL);
 835        if (IS_ERR(host->clk)) {
 836                ret = PTR_ERR(host->clk);
 837                goto error_getclock;
 838        }
 839
 840        panel_enable = of_get_named_gpio_flags(pdev->dev.of_node,
 841                                               "panel-enable-gpios", 0, &flags);
 842        if (gpio_is_valid(panel_enable)) {
 843                unsigned long f = GPIOF_OUT_INIT_HIGH;
 844                if (flags == OF_GPIO_ACTIVE_LOW)
 845                        f = GPIOF_OUT_INIT_LOW;
 846                ret = devm_gpio_request_one(&pdev->dev, panel_enable,
 847                                            f, "panel-enable");
 848                if (ret) {
 849                        dev_err(&pdev->dev,
 850                                "failed to request gpio %d: %d\n",
 851                                panel_enable, ret);
 852                        goto error_panel_enable;
 853                }
 854        }
 855
 856        fb_info->pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL);
 857        if (!fb_info->pseudo_palette) {
 858                ret = -ENOMEM;
 859                goto error_pseudo_pallette;
 860        }
 861
 862        INIT_LIST_HEAD(&fb_info->modelist);
 863
 864        ret = mxsfb_init_fbinfo(host);
 865        if (ret != 0)
 866                goto error_init_fb;
 867
 868        for (i = 0; i < pdata->mode_count; i++)
 869                fb_add_videomode(&pdata->mode_list[i], &fb_info->modelist);
 870
 871        modelist = list_first_entry(&fb_info->modelist,
 872                        struct fb_modelist, list);
 873        fb_videomode_to_var(&fb_info->var, &modelist->mode);
 874
 875        /* init the color fields */
 876        mxsfb_check_var(&fb_info->var, fb_info);
 877
 878        platform_set_drvdata(pdev, fb_info);
 879
 880        ret = register_framebuffer(fb_info);
 881        if (ret != 0) {
 882                dev_err(&pdev->dev,"Failed to register framebuffer\n");
 883                goto error_register;
 884        }
 885
 886        if (!host->enabled) {
 887                writel(0, host->base + LCDC_CTRL);
 888                mxsfb_set_par(fb_info);
 889                mxsfb_enable_controller(fb_info);
 890        }
 891
 892        dev_info(&pdev->dev, "initialized\n");
 893
 894        return 0;
 895
 896error_register:
 897        if (host->enabled)
 898                clk_disable_unprepare(host->clk);
 899        fb_destroy_modelist(&fb_info->modelist);
 900error_init_fb:
 901        kfree(fb_info->pseudo_palette);
 902error_pseudo_pallette:
 903error_panel_enable:
 904        clk_put(host->clk);
 905error_getclock:
 906error_getpin:
 907        iounmap(host->base);
 908error_ioremap:
 909        framebuffer_release(fb_info);
 910error_alloc_info:
 911        release_mem_region(res->start, resource_size(res));
 912
 913        return ret;
 914}
 915
 916static int mxsfb_remove(struct platform_device *pdev)
 917{
 918        struct fb_info *fb_info = platform_get_drvdata(pdev);
 919        struct mxsfb_info *host = to_imxfb_host(fb_info);
 920        struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 921
 922        if (host->enabled)
 923                mxsfb_disable_controller(fb_info);
 924
 925        unregister_framebuffer(fb_info);
 926        kfree(fb_info->pseudo_palette);
 927        mxsfb_free_videomem(host);
 928        iounmap(host->base);
 929        clk_put(host->clk);
 930
 931        framebuffer_release(fb_info);
 932        release_mem_region(res->start, resource_size(res));
 933
 934        platform_set_drvdata(pdev, NULL);
 935
 936        return 0;
 937}
 938
 939static void mxsfb_shutdown(struct platform_device *pdev)
 940{
 941        struct fb_info *fb_info = platform_get_drvdata(pdev);
 942        struct mxsfb_info *host = to_imxfb_host(fb_info);
 943
 944        /*
 945         * Force stop the LCD controller as keeping it running during reboot
 946         * might interfere with the BootROM's boot mode pads sampling.
 947         */
 948        writel(CTRL_RUN, host->base + LCDC_CTRL + REG_CLR);
 949}
 950
 951static struct platform_driver mxsfb_driver = {
 952        .probe = mxsfb_probe,
 953        .remove = mxsfb_remove,
 954        .shutdown = mxsfb_shutdown,
 955        .id_table = mxsfb_devtype,
 956        .driver = {
 957                   .name = DRIVER_NAME,
 958                   .of_match_table = mxsfb_dt_ids,
 959        },
 960};
 961
 962module_platform_driver(mxsfb_driver);
 963
 964MODULE_DESCRIPTION("Freescale mxs framebuffer driver");
 965MODULE_AUTHOR("Sascha Hauer, Pengutronix");
 966MODULE_LICENSE("GPL");
 967
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