linux/drivers/spi/spi-mpc52xx.c
<<
/opt.6./spaue= .6./forme= .6.a /opt.6 href="../linux+v3.8.6/drivers/spi/spi-mpc52xx.c">/opt.6.img src="../.static/gfx/right.png" alt=">>">/o./spaue=/o.spau class="lxr_search">/opt/opt.6.input typ hidden" nam navtarget" > ">/opt.6.input typ text" nam search" id search">/opt.6.butt2" typ submit">Search/opt.6Prefs= .6./a>/o./spaue=pt.6 6./dive=pt.6 6.form acvalu="ajax+*" method="post" onsubmit="return false;">/o.input typ hidden" nam ajax_lookup" id ajax_lookup" > ">/pt.6 6./forme=/pt.6 6.div class="headingbott2m">= .div id file_contents"e
6 61./a>.spau class="comment">/*./spaue=6 62./a>.spau class="comment"> * MPC52xx SPI bus driver../spaue=6 63./a>.spau class="comment"> *./spaue=6 64./a>.spau class="comment"> * Copyright (C) 2008 Secret Lab Technologies Ltd../spaue=6 65./a>.spau class="comment"> *./spaue=6 66./a>.spau class="comment"> * This file is released under the GPLv2./spaue=6 67./a>.spau class="comment"> *./spaue=6 68./a>.spau class="comment"> * This is the driver for the MPC5200's dedicated SPI controller../spaue=6 69./a>.spau class="comment"> *./spaue=6  
  a>.spau class="comment"> * Note: this driver does not support the MPC5200 PSC in SPI mode.  For./spaue=6 11./a>.spau class="comment"> * that driver see drivers/spi/mpc52xx_psc_spi.c./spaue=6 12./a>.spau class="comment"> */./spaue=6 13./a>=6 14./a>#include <linux/module.h./a>>=6 15./a>#include <linux/init.h./a>>=6 16./a>#include <linux/errno.h./a>>=6 17./a>#include <linux/of_platform.h./a>>=6 18./a>#include <linux/interrupt.h./a>>=6 19./a>#include <linux/delay.h./a>>=6 20./a>#include <linux/spi/spi.h./a>>=6 21./a>#include <linux/io.h./a>>=6 22./a>#include <linux/of_gpio.h./a>>=6 23./a>#include <linux/slab.h./a>>=6 24./a>#include <asm/time.h./a>>=6 25./a>#include <asm/mpc52xx.h./a>>=6 26./a>=6 27./a>.a href="+code=MODULE_AUTHOR" class="sref">MODULE_AUTHOR./a>(.spau class="string">"Grant Likely <grant.likely@secretlab.ca>"./spaue);=6 28./a>.a href="+code=MODULE_DESCRIPTION" class="sref">MODULE_DESCRIPTION./a>(.spau class="string">"MPC52xx SPI (non-PSC) Driver"./spaue);=6 29./a>.a href="+code=MODULE_LICENSE" class="sref">MODULE_LICENSE./a>(.spau class="string">"GPL"./spaue);=6 30./a>=6 31./a>.spau class="comment">/* Register offsets */./spaue=6 32./a>#define .a href="+code=SPI_CTRL1" class="sref">SPI_CTRL1./a>pt.6 6 0x00=6 33./a>#define .a href="+code=SPI_CTRL1_SPIE" class="sref">SPI_CTRL1_SPIE./a>pt.6 6    (1 << 7)=6 34./a>#define .a href="+code=SPI_CTRL1_SPE" class="sref">SPI_CTRL1_SPE./a>pt.6 6     (1 << 6)=6 35./a>#define .a href="+code=SPI_CTRL1_MSTR" class="sref">SPI_CTRL1_MSTR./a>pt.6 6    (1 << 4)=6 36./a>#define .a href="+code=SPI_CTRL1_CPOL" class="sref">SPI_CTRL1_CPOL./a>pt.6 6    (1 << 3)=6 37./a>#define .a href="+code=SPI_CTRL1_CPHA" class="sref">SPI_CTRL1_CPHA./a>pt.6 6    (1 << 2)=6 38./a>#define .a href="+code=SPI_CTRL1_SSOE" class="sref">SPI_CTRL1_SSOE./a>pt.6 6    (1 << 1)=6 39./a>#define .a href="+code=SPI_CTRL1_LSBFE" class="sref">SPI_CTRL1_LSBFE./a>pt.6 6   (1 << 0)=6 40./a>=6 41./a>#define .a href="+code=SPI_CTRL2" class="sref">SPI_CTRL2./a>pt.6 6 0x01=6 42./a>#define .a href="+code=SPI_BRR" class="sref">SPI_BRR./a>pt.6 6   0x04=6 43./a>=6 44./a>#define .a href="+code=SPI_STATUS" class="sref">SPI_STATUS./a>pt.6 60x05=6 45./a>#define .a href="+code=SPI_STATUS_SPIF" class="sref">SPI_STATUS_SPIF./a>pt.6 6   (1 << 7)=6 46./a>#define .a href="+code=SPI_STATUS_WCOL" class="sref">SPI_STATUS_WCOL./a>pt.6 6   (1 << 6)=6 47./a>#define .a href="+code=SPI_STATUS_MODF" class="sref">SPI_STATUS_MODF./a>pt.6 6   (1 << 4)=6 48./a>=6 49./a>#define .a href="+code=SPI_DATA" class="sref">SPI_DATA./a>pt.6 6  0x09=6 50./a>#define .a href="+code=SPI_PORTDATA" class="sref">SPI_PORTDATA./a>pt.60x0d=6 51./a>#define .a href="+code=SPI_DATADIR" class="sref">SPI_DATADIR./a>pt.6 0x10=6 52./a>=6 53./a>.spau class="comment">/* FSM state return 	  >
s */./spaue=6 54./a>#define .a href="+code=FSM_STOP" class="sref">FSM_STOP./a>pt.6 6  0t.6 6  .spau class="comment">/* Nothing more for the state machine to */./spaue=6 55./a>pt.6 6                          .spau class="comment">/* do.  If something interesting happens */./spaue=6 56./a>pt.6 6                          .spau class="comment">/* then au IRQ will be received */./spaue=6 57./a>#define .a href="+code=FSM_POLL" class="sref">FSM_POLL./a>pt.6 6  1       .spau class="comment">/* need to poll for complevalu, au IRQ is */./spaue=6 58./a>pt.6 6                          .spau class="comment">/* not expected */./spaue=6 59./a>#define .a href="+code=FSM_CONTINUE" class="sref">FSM_CONTINUE./a>pt.62       .spau class="comment">/* Keep iterating the state machine */./spaue=6 60./a>=6 61./a>.spau class="comment">/* Driver internal data */./spaue=6 62./a>struct .a href="+code=mpc52xx_spi" class="sref">mpc52xx_spi./a>p{=6 63./a>pt.6 6  struct .a href="+code=spi_master" class="sref">spi_master./a>p*.a href="+code=master" class="sref">master./a>;=6 64./a>pt.6 6  void .a href="+code=__iomem" class="sref">__iomem./a>p*.a href="+code=regs" class="sref">regs./a>;=6 65./a>pt.6 6  int .a href="+code=irq0" class="sref">irq0./a>;       .spau class="comment">/* MODF irq */./spaue=6 66./a>pt.6 6  int .a href="+code=irq1" class="sref">irq1./a>;       .spau class="comment">/* SPIF irq */./spaue=6 67./a>pt.6 6  unsigned int .a href="+code=ipb_freq" class="sref">ipb_freq./a>;=6 68./a>=6 69./a>pt.6 6  .spau class="comment">/* Statistics; not used now, but will be reintroduced for debugfs */./spaue=6 70./a>pt.6 6  int .a href="+code=msg_count" class="sref">msg_count./a>;=6 71./a>pt.6 6  int .a href="+code=wcol_count" class="sref">wcol_count./a>;=6 72./a>pt.6 6  int .a href="+code=wcol_ticks" class="sref">wcol_ticks./a>;=6 73./a>pt.6 6  .a href="+code=u32" class="sref">u32./a> .a href="+code=wcol_tx_timestamp" class="sref">wcol_tx_timestamp./a>;=6 74./a>pt.6 6  int .a href="+code=modf_count" class="sref">modf_count./a>;=6 75./a>pt.6 6  int .a href="+code=byte_count" class="sref">byte_count./a>;=6 76./a>=6 77./a>pt.6 6  struct .a href="+code=list_head" class="sref">list_head./a> .a href="+code=queue" class="sref">queue./a>;         .spau class="comment">/* queue of pending messag
s */./spaue=6 78./a>pt.6 6  .a href="+code=spinlock_t" class="sref">spinlock_t./a> .a href="+code=lock" class="sref">lock./a>;=6 79./a>pt.6 6  struct .a href="+code=work_struct" class="sref">work_struct./a> .a href="+code=work" class="sref">work./a>;=6 80./a>=6 81./a>pt.6 6  .spau class="comment">/* Details of current transfer (length, aud buffer pointers) */./spaue=6 82./a>pt.6 6  struct .a href="+code=spi_messag
" class="sref">spi_messag
./a>p*.a href="+code=messag
" class="sref">messag
./a>; 6  .spau class="comment">/* current messag
 */./spaue=6 83./a>pt.6 6  struct .a href="+code=spi_transfer" class="sref">spi_transfer./a>p*.a href="+code=transfer" class="sref">transfer./a>;  .spau class="comment">/* current transfer */./spaue=6 84./a>pt.6 6  int (*.a href="+code=state" class="sref">state./a>)(int .a href="+code=irq" class="sref">irq./a>, struct .a href="+code=mpc52xx_spi" class="sref">mpc52xx_spi./a>p*.a href="+code=ms" class="sref">ms./a>, .a href="+code=u8" class="sref">u8./a> .a href="+code=status" class="sref">status./a>, .a href="+code=u8" class="sref">u8./a> .a href="+code=data" class="sref">data./a>);=6 85./a>pt.6 6  int .a href="+code=len" class="sref">len./a>;=6 86./a>pt.6 6  int .a href="+code=timestamp" class="sref">timestamp./a>;=6 87./a>pt.6 6  .a href="+code=u8" class="sref">u8./a> *.a href="+code=rx_buf" class="sref">rx_buf./a>;=6 88./a>pt.6 6  const .a href="+code=u8" class="sref">u8./a> *.a href="+code=tx_buf" class="sref">tx_buf./a>;=6 89./a>pt.6 6  int .a href="+code=cs_chang
" class="sref">cs_chang
./a>;=6 90./a>pt.6 6  int .a href="+code=gpio_cs_count" class="sref">gpio_cs_count./a>;=6 91./a>pt.6 6  unsigned int *.a href="+code=gpio_cs" class="sref">gpio_cs./a>;=6 92./a>};=6 93./a>=6 94./a>.spau class="comment">/*./spaue=6 95./a>.spau class="comment"> * CS control funcvalu./spaue=6 96./a>.spau class="comment"> */./spaue=6 97./a>static void .a href="+code=mpc52xx_spi_chipsel" class="sref">mpc52xx_spi_chipsel./a>(struct .a href="+code=mpc52xx_spi" class="sref">mpc52xx_spi./a>p*.a href="+code=ms" class="sref">ms./a>, int .a href="+code=	  >
" class="sref">	  >
./a>)=6 98./a>{=6 99./a>pt.6 6  int .a href="+code=cs" class="sref">cs./a>;=6100./a>=6101./a>pt.6 6  if (.a href="+code=ms" class="sref">ms./a>->.a href="+code=gpio_cs_count" class="sref">gpio_cs_count./a> > 0)p{=6102./a>pt.6 6  pt.6 6  .a href="+code=cs" class="sref">cs./a> = .a href="+code=ms" class="sref">ms./a>->.a href="+code=messag
" class="sref">messag
./a>->.a href="+code=spi" class="sref">spi./a>->.a href="+code=chip_select" class="sref">chip_select./a>;=6103./a>pt.6 6  pt.6 6  .a href="+code=gpio_set_	  >
" class="sref">gpio_set_	  >
./a>(.a href="+code=ms" class="sref">ms./a>->.a href="+code=gpio_cs" class="sref">gpio_cs./a>[.a href="+code=cs" class="sref">cs./a>], .a href="+code=	  >
" class="sref">	  >
./a> ? 0 : 1);=6104./a>pt.6 6  } else=6105./a>pt.6 6          .a href="+code=out_8" class="sref">out_8./a>(.a href="+code=ms" class="sref">ms./a>->.a href="+code=regs" class="sref">regs./a> + .a href="+code=SPI_PORTDATA" class="sref">SPI_PORTDATA./a>, .a href="+code=	  >
" class="sref">	  >
./a> ? 0 : 0x08);=6106./a>}=6107./a>=6108./a>.spau class="comment">/*./spaue=6109./a>.spau class="comment"> * Start a new transfer.  This is called both by the idle state./spaue=61 
  a>.spau class="comment"> * for the first transfer in a messag
, aud by the wait state when the./spaue=6111./a>.spau class="comment"> * previous transfer in a messag
 is compleve../spaue=6112./a>.spau class="comment"> */./spaue=6113./a>static void .a href="+code=mpc52xx_spi_start_transfer" class="sref">mpc52xx_spi_start_transfer./a>(struct .a href="+code=mpc52xx_spi" class="sref">mpc52xx_spi./a>p*.a href="+code=ms" class="sref">ms./a>)=6114./a>{=6115./a>pt.6 6  .a href="+code=ms" class="sref">ms./a>->.a href="+code=rx_buf" class="sref">rx_buf./a> = .a href="+code=ms" class="sref">ms./a>->.a href="+code=transfer" class="sref">transfer./a>->.a href="+code=rx_buf" class="sref">rx_buf./a>;=6116./a>pt.6 6  .a href="+code=ms" class="sref">ms./a>->.a href="+code=tx_buf" class="sref">tx_buf./a> = .a href="+code=ms" class="sref">ms./a>->.a href="+code=transfer" class="sref">transfer./a>->.a href="+code=tx_buf" class="sref">tx_buf./a>;=6117./a>pt.6 6  .a href="+code=ms" class="sref">ms./a>->.a href="+code=len" class="sref">len./a> = .a href="+code=ms" class="sref">ms./a>->.a href="+code=transfer" class="sref">transfer./a>->.a href="+code=len" class="sref">len./a>;=6118./a>=6119./a>pt.6 6  .spau class="comment">/* Activate the chip select */./spaue=6120./a>pt.6 6  if (.a href="+code=ms" class="sref">ms./a>->.a href="+code=cs_chang
" class="sref">cs_chang
./a>)=6121./a>pt.6 6  pt.6 6  .a href="+code=mpc52xx_spi_chipsel" class="sref">mpc52xx_spi_chipsel./a>(.a href="+code=ms" class="sref">ms./a>, 1);=6122./a>pt.6 6  .a href="+code=ms" class="sref">ms./a>->.a href="+code=cs_chang
" class="sref">cs_chang
./a> = .a href="+code=ms" class="sref">ms./a>->.a href="+code=transfer" class="sref">transfer./a>->.a href="+code=cs_chang
" class="sref">cs_chang
./a>;=6123./a>=6124./a>pt.6 6  .spau class="comment">/* Write out the first byte */./spaue=6125./a>pt.6 6  .a href="+code=ms" class="sref">ms./a>->.a href="+code=wcol_tx_timestamp" class="sref">wcol_tx_timestamp./a> = .a href="+code=get_tbl" class="sref">get_tbl./a>();=6126./a>pt.6 6  if (.a href="+code=ms" class="sref">ms./a>->.a href="+code=tx_buf" class="sref">tx_buf./a>)=6127./a>pt.6 6  pt.6 6  .a href="+code=out_8" class="sref">out_8./a>(.a href="+code=ms" class="sref">ms./a>->.a href="+code=regs" class="sref">regs./a> + .a href="+code=SPI_DATA" class="sref">SPI_DATA./a>,p*.a href="+code=ms" class="sref">ms./a>->.a href="+code=tx_buf" class="sref">tx_buf./a>++);=6128./a>pt.6 6  else=6129./a>pt.6 6  pt.6 6  .a href="+code=out_8" class="sref">out_8./a>(.a href="+code=ms" class="sref">ms./a>->.a href="+code=regs" class="sref">regs./a> + .a href="+code=SPI_DATA" class="sref">SPI_DATA./a>,p0);=6130./a>}=6131./a>=6132./a>.spau class="comment">/* Forward declaration of state handlers */./spaue=6133./a>static int .a href="+code=mpc52xx_spi_fsmstate_transfer" class="sref">mpc52xx_spi_fsmstate_transfer./a>(int .a href="+code=irq" class="sref">irq./a>, struct .a href="+code=mpc52xx_spi" class="sref">mpc52xx_spi./a>p*.a href="+code=ms" class="sref">ms./a>,=6134./a>pt.6 6  pt.6 6                           .a href="+code=u8" class="sref">u8./a> .a href="+code=status" class="sref">status./a>, .a href="+code=u8" class="sref">u8./a> .a href="+code=data" class="sref">data./a>);=6135./a>static int .a href="+code=mpc52xx_spi_fsmstate_wait" class="sref">mpc52xx_spi_fsmstate_wait./a>(int .a href="+code=irq" class="sref">irq./a>, struct .a href="+code=mpc52xx_spi" class="sref">mpc52xx_spi./a>p*.a href="+code=ms" class="sref">ms./a>,=6136./a>pt.6 6                               .a href="+code=u8" class="sref">u8./a> .a href="+code=status" class="sref">status./a>, .a href="+code=u8" class="sref">u8./a> .a href="+code=data" class="sref">data./a>);=6137./a>=6138./a>.spau class="comment">/*./spaue=6139./a>.spau class="comment"> * IDLE state./spaue=614
  a>.spau class="comment"> *./spaue=6141./a>.spau class="comment"> * No transfers are in progress; if another transfer is pending then retrieve./spaue=6142./a>.spau class="comment"> * it aud kick it off.  Otherwise, stop processing the state machine./spaue=6143./a>.spau class="comment"> */./spaue=6144./a>static int=6145./a>.a href="+code=mpc52xx_spi_fsmstate_idle" class="sref">mpc52xx_spi_fsmstate_idle./a>(int .a href="+code=irq" class="sref">irq./a>, struct .a href="+code=mpc52xx_spi" class="sref">mpc52xx_spi./a>p*.a href="+code=ms" class="sref">ms./a>, .a href="+code=u8" class="sref">u8./a> .a href="+code=status" class="sref">status./a>, .a href="+code=u8" class="sref">u8./a> .a href="+code=data" class="sref">data./a>)=6146./a>{=6147./a>pt.6 6  struct .a href="+code=spi_devic
" class="sref">spi_devic
./a>p*.a href="+code=spi" class="sref">spi./a>;=6148./a>pt.6 6  int .a href="+code=spr" class="sref">spr./a>, .a href="+code=sppr" class="sref">sppr./a>;=6149./a>pt.6 6  .a href="+code=u8" class="sref">u8./a> .a href="+code=ctrl1" class="sref">ctrl1./a>;=6150./a>=6151./a>pt.6 6  if (.a href="+code=status" class="sref">status./a> && (.a href="+code=irq" class="sref">irq./a> != .a href="+code=NO_IRQ" class="sref">NO_IRQ./a>))=6152./a>pt.6 6  pt.6 6  .a href="+code=dev_err" class="sref">dev_err./a>(&.a href="+code=ms" class="sref">ms./a>->.a href="+code=master" class="sref">master./a>->.a href="+code=dev" class="sref">dev./a>, .spau class="string">"spurious irq, status=0x%.2x\n"./spaue,=6153./a>pt.6 6  pt.6 6  pt.6 6  .a href="+code=status" class="sref">status./a>);=6154./a>=6155./a>pt.6 6  .spau class="comment">/* Check if ther
 is another transfer waiting. */./spaue=6156./a>pt.6 6  if (.a href="+code=list_empty" class="sref">list_empty./a>(&.a href="+code=ms" class="sref">ms./a>->.a href="+code=queue" class="sref">queue./a>))=6157./a>pt.6 6  pt.6 6  return .a href="+code=FSM_STOP" class="sref">FSM_STOP./a>;=6158./a>=6159./a>pt.6 6  .spau class="comment">/* get the head of the queue */./spaue=6160./a>pt.6 6  .a href="+code=ms" class="sref">ms./a>->.a href="+code=messag
" class="sref">messag
./a> = .a href="+code=list_first_entry" class="sref">list_first_entry./a>(&.a href="+code=ms" class="sref">ms./a>->.a href="+code=queue" class="sref">queue./a>, struct .a href="+code=spi_messag
" class="sref">spi_messag
./a>, .a href="+code=queue" class="sref">queue./a>);=6161./a>pt.6 6  .a href="+code=list_del_init" class="sref">list_del_init./a>(&.a href="+code=ms" class="sref">ms./a>->.a href="+code=messag
" class="sref">messag
./a>->.a href="+code=queue" class="sref">queue./a>);=6162./a>=6163./a>pt.6 6  .spau class="comment">/* Setup the controller param
ters */./spaue=6164./a>pt.6 6  .a href="+code=ctrl1" class="sref">ctrl1./a> = .a href="+code=SPI_CTRL1_SPIE" class="sref">SPI_CTRL1_SPIE./a>p| .a href="+code=SPI_CTRL1_SPE" class="sref">SPI_CTRL1_SPE./a>p| .a href="+code=SPI_CTRL1_MSTR" class="sref">SPI_CTRL1_MSTR./a>;=6165./a>pt.6 6  .a href="+code=spi" class="sref">spi./a> = .a href="+code=ms" class="sref">ms./a>->.a href="+code=messag
" class="sref">messag
./a>->.a href="+code=spi" class="sref">spi./a>;=6166./a>pt.6 6  if (.a href="+code=spi" class="sref">spi./a>->.a href="+code=mode" class="sref">mode./a> & .a href="+code=SPI_CPHA" class="sref">SPI_CPHA./a>)=6167./a>pt.6 6  pt.6 6  .a href="+code=ctrl1" class="sref">ctrl1./a> |= .a href="+code=SPI_CTRL1_CPHA" class="sref">SPI_CTRL1_CPHA./a>;=6168./a>pt.6 6  if (.a href="+code=spi" class="sref">spi./a>->.a href="+code=mode" class="sref">mode./a> & .a href="+code=SPI_CPOL" class="sref">SPI_CPOL./a>)=6169./a>pt.6 6  pt.6 6  .a href="+code=ctrl1" class="sref">ctrl1./a> |= .a href="+code=SPI_CTRL1_CPOL" class="sref">SPI_CTRL1_CPOL./a>;=6170./a>pt.6 6  if (.a href="+code=spi" class="sref">spi./a>->.a href="+code=mode" class="sref">mode./a> & .a href="+code=SPI_LSB_FIRST" class="sref">SPI_LSB_FIRST./a>)=6171./a>pt.6 6  pt.6 6  .a href="+code=ctrl1" class="sref">ctrl1./a> |= .a href="+code=SPI_CTRL1_LSBFE" class="sref">SPI_CTRL1_LSBFE./a>;=6172./a>pt.6 6  .a href="+code=out_8" class="sref">out_8./a>(.a href="+code=ms" class="sref">ms./a>->.a href="+code=regs" class="sref">regs./a> + .a href="+code=SPI_CTRL1" class="sref">SPI_CTRL1./a>, .a href="+code=ctrl1" class="sref">ctrl1./a>);=6173./a>=6174./a>pt.6 6  .spau class="comment">/* Setup the controller speed */./spaue=6175./a>pt.6 6  .spau class="comment">/* minimum divider is '2'.  Also, add '1' to force rounding the./spaue=6176./a>.spau class="comment">         * divider up. */./spaue=6177./a>pt.6 6  .a href="+code=sppr" class="sref">sppr./a> = ((.a href="+code=ms" class="sref">ms./a>->.a href="+code=ipb_freq" class="sref">ipb_freq./a> / .a href="+code=ms" class="sref">ms./a>->.a href="+code=messag
" class="sref">messag
./a>->.a href="+code=spi" class="sref">spi./a>->.a href="+code=max_speed_hz" class="sref">max_speed_hz./a>) + 1) >> 1;=6178./a>pt.6 6  .a href="+code=spr" class="sref">spr./a> = 0;=6179./a>pt.6 6  if (.a href="+code=sppr" class="sref">sppr./a> < 1)=6180./a>pt.6 6  pt.6 6  .a href="+code=sppr" class="sref">sppr./a> = 1;=6181./a>pt.6 6  while (((.a href="+code=sppr" class="sref">sppr./a> - 1) & ~0x7) != 0)p{=6182./a>pt.6 6  pt.6 6  .a href="+code=sppr" class="sref">sppr./a> = (.a href="+code=sppr" class="sref">sppr./a> + 1) >> 1; .spau class="comment">/* add '1' to force rounding up */./spaue=6183./a>pt.6 6  pt.6 6  .a href="+code=spr" class="sref">spr./a>++;=6184./a>pt.6 6  }=6185./a>pt.6 6  .a href="+code=sppr" class="sref">sppr./a>--;         .spau class="comment">/* sppr quantity in register is offset by 1 */./spaue=6186./a>pt.6 6  if (.a href="+code=spr" class="sref">spr./a> > 7)p{=6187./a>pt.6 6  pt.6 6  .spau class="comment">/* Don't overrun limits of SPI baudrate register */./spaue=6188./a>pt.6 6          .a href="+code=spr" class="sref">spr./a> = 7;=6189./a>pt.6 6  pt.6 6  .a href="+code=sppr" class="sref">sppr./a> = 7;=6190./a>pt.6 6  }=6191./a>pt.6 6  .a href="+code=out_8" class="sref">out_8./a>(.a href="+code=ms" class="sref">ms./a>->.a href="+code=regs" class="sref">regs./a> + .a href="+code=SPI_BRR" class="sref">SPI_BRR./a>, .a href="+code=sppr" class="sref">sppr./a> << 4p| .a href="+code=spr" class="sref">spr./a>); .spau class="comment">/* Set speed */./spaue=6192./a>=6193./a>pt.6 6  .a href="+code=ms" class="sref">ms./a>->.a href="+code=cs_chang
" class="sref">cs_chang
./a> = 1;=6194./a>pt.6 6  .a href="+code=ms" class="sref">ms./a>->.a href="+code=transfer" class="sref">transfer./a> = .a href="+code=container_of" class="sref">container_of./a>(.a href="+code=ms" class="sref">ms./a>->.a href="+code=messag
" class="sref">messag
./a>->.a href="+code=transfers" class="sref">transfers./a>..a href="+code=next" class="sref">next./a>,=6195./a>pt.6 6                              struct .a href="+code=spi_transfer" class="sref">spi_transfer./a>, .a href="+code=transfer_list" class="sref">transfer_list./a>);=6196./a>=6197./a>pt.6 6  .a href="+code=mpc52xx_spi_start_transfer" class="sref">mpc52xx_spi_start_transfer./a>(.a href="+code=ms" class="sref">ms./a>);=6198./a>pt.6 6  .a href="+code=ms" class="sref">ms./a>->.a href="+code=state" class="sref">state./a> = .a href="+code=mpc52xx_spi_fsmstate_transfer" class="sref">mpc52xx_spi_fsmstate_transfer./a>;=6199./a>=6200./a>pt.6 6  return .a href="+code=FSM_CONTINUE" class="sref">FSM_CONTINUE./a>;=6201./a>}=6202./a>=6203./a>.spau class="comment">/*./spaue=6204./a>.spau class="comment"> * TRANSFER state./spaue=6205./a>.spau class="comment"> *./spaue=6206./a>.spau class="comment"> * In the middle of a transfer.  If the SPI core has compleved processing./spaue=6207./a>.spau class="comment"> * a byte, then read out the received data aud write out the next byte./spaue=6208./a>.spau class="comment"> * (unless this transfer is finished; in which case go on to the wait./spaue=6209./a>.spau class="comment"> * state)./spaue=62 
  a>.spau class="comment"> */./spaue=6211./a>static int .a href="+code=mpc52xx_spi_fsmstate_transfer" class="sref">mpc52xx_spi_fsmstate_transfer./a>(int .a href="+code=irq" class="sref">irq./a>, struct .a href="+code=mpc52xx_spi" class="sref">mpc52xx_spi./a>p*.a href="+code=ms" class="sref">ms./a>,=6212./a>pt.6 6  pt.6 6                           .a href="+code=u8" class="sref">u8./a> .a href="+code=status" class="sref">status./a>, .a href="+code=u8" class="sref">u8./a> .a href="+code=data" class="sref">data./a>)=6213./a>{=6214./a>pt.6 6  if (!.a href="+code=status" class="sref">status./a>)=6215./a>pt.6 6          return .a href="+code=ms" class="sref">ms./a>->.a href="+code=irq0" class="sref">irq0./a> ? .a href="+code=FSM_STOP" class="sref">FSM_STOP./a> : .a href="+code=FSM_POLL" class="sref">FSM_POLL./a>;=6216./a>=6217./a>pt.6 6  if (.a href="+code=status" class="sref">status./a> & .a href="+code=SPI_STATUS_WCOL" class="sref">SPI_STATUS_WCOL./a>)p{=6218./a>pt.6 6          .spau class="comment">/* The SPI controller is stoopid.  At slower speeds, it may./spaue=6219./a>.spau class="comment">                 * raise the SPIF flag before the state machine is actually./spaue=622
  a>.spau class="comment">                 * finished, which causes a collision (internal to the state./spaue=6221./a>.spau class="comment">                 * machine only).  The manual recommends inserting a delay./spaue=6222./a>.spau class="comment">                 * between receiving the interrupt aud sending the next byte,./spaue=6223./a>.spau class="comment">                 * but it cau also be worked around simply by retrying the./spaue=6224./a>.spau class="comment">                 * transfer which is what we do her
. */./spaue=6225./a>pt.6 6          .a href="+code=ms" class="sref">ms./a>->.a href="+code=wcol_count" class="sref">wcol_count./a>++;=6226./a>pt.6 6          .a href="+code=ms" class="sref">ms./a>->.a href="+code=wcol_ticks" class="sref">wcol_ticks./a> += .a href="+code=get_tbl" class="sref">get_tbl./a>() - .a href="+code=ms" class="sref">ms./a>->.a href="+code=wcol_tx_timestamp" class="sref">wcol_tx_timestamp./a>;=6227./a>pt.6 6  pt.6 6  .a href="+code=ms" class="sref">ms./a>->.a href="+code=wcol_tx_timestamp" class="sref">wcol_tx_timestamp./a> = .a href="+code=get_tbl" class="sref">get_tbl./a>();=6228./a>pt.6 6          .a href="+code=data" class="sref">data./a> = 0;=6229./a>pt.6 6  pt.6 6  if (.a href="+code=ms" class="sref">ms./a>->.a href="+code=tx_buf" class="sref">tx_buf./a>)=6230./a>pt.6 6  pt.6 6          .a href="+code=data" class="sref">data./a> = *(.a href="+code=ms" class="sref">ms./a>->.a href="+code=tx_buf" class="sref">tx_buf./a> - 1);=6231./a>pt.6 6  pt.6 6  .a href="+code=out_8" class="sref">out_8./a>(.a href="+code=ms" class="sref">ms./a>->.a href="+code=regs" class="sref">regs./a> + .a href="+code=SPI_DATA" class="sref">SPI_DATA./a>,p.a href="+code=data" class="sref">data./a>); .spau class="comment">/* try again */./spaue=6232./a>pt.6 6  pt.6 6  return .a href="+code=FSM_CONTINUE" class="sref">FSM_CONTINUE./a>;=6233./a>pt.6 6  } else if (.a href="+code=status" class="sref">status./a> & .a href="+code=SPI_STATUS_MODF" class="sref">SPI_STATUS_MODF./a>)p{=6234./a>pt.6 6  pt.6 6  .a href="+code=ms" class="sref">ms./a>->.a href="+code=modf_count" class="sref">modf_count./a>++;=6235./a>pt.6 6          .a href="+code=dev_err" class="sref">dev_err./a>(&.a href="+code=ms" class="sref">ms./a>->.a href="+code=master" class="sref">master./a>->.a href="+code=dev" class="sref">dev./a>, .spau class="string">"mode fault\n"./spaue);=6236./a>pt.6 6          .a href="+code=mpc52xx_spi_chipsel" class="sref">mpc52xx_spi_chipsel./a>(.a href="+code=ms" class="sref">ms./a>, 0);=6237./a>pt.6 6  pt.6 6  .a href="+code=ms" class="sref">ms./a>->.a href="+code=messag
" class="sref">messag
./a>->.a href="+code=status" class="sref">status./a> = -.a href="+code=EIO" class="sref">EIO./a>;=6238./a>pt.6 6          .a href="+code=ms" class="sref">ms./a>->.a href="+code=messag
" class="sref">messag
./a>->.a href="+code=compleve" class="sref">compleve./a>(.a href="+code=ms" class="sref">ms./a>->.a href="+code=messag
" class="sref">messag
./a>->.a href="+code=context" class="sref">context./a>);=6239./a>pt.6 6  pt.6 6  .a href="+code=ms" class="sref">ms./a>->.a href="+code=state" class="sref">state./a> = .a href="+code=mpc52xx_spi_fsmstate_idle" class="sref">mpc52xx_spi_fsmstate_idle./a>;=6240./a>pt.6 6  pt.6 6  return .a href="+code=FSM_CONTINUE" class="sref">FSM_CONTINUE./a>;=6241./a>pt.6 6  }=6242./a>=6243./a>pt.6 6  .spau class="comment">/* Read data out of the spi devic
 */./spaue=6244./a>pt.6 6  .a href="+code=ms" class="sref">ms./a>->.a href="+code=byte_count" class="sref">byte_count./a>++;=6245./a>pt.6 6  if (.a href="+code=ms" class="sref">ms./a>->.a href="+code=rx_buf" class="sref">rx_buf./a>)=6246./a>pt.6 6          *.a href="+code=ms" class="sref">ms./a>->.a href="+code=rx_buf" class="sref">rx_buf./a>++ = .a href="+code=data" class="sref">data./a>;=6247./a>=6248./a>pt.6 6  .spau class="comment">/* Is the transfer compleve? */./spaue=6249./a>pt.6 6  .a href="+code=ms" class="sref">ms./a>->.a href="+code=len" class="sref">len./a>--;=6250./a>pt.6 6  if (.a href="+code=ms" class="sref">ms./a>->.a href="+code=len" class="sref">len./a> == 0)p{=6251./a>pt.6 6  pt.6 6  .a href="+code=ms" class="sref">ms./a>->.a href="+code=timestamp" class="sref">timestamp./a> = .a href="+code=get_tbl" class="sref">get_tbl./a>();=6252./a>pt.6 6  pt.6 6  .a href="+code=ms" class="sref">ms./a>->.a href="+code=timestamp" class="sref">timestamp./a> += .a href="+code=ms" class="sref">ms./a>->.a href="+code=transfer" class="sref">transfer./a>->.a href="+code=delay_usecs" class="sref">delay_usecs./a>p* .a href="+code=tb_ticks_per_usec" class="sref">tb_ticks_per_usec./a>;=6253./a>pt.6 6  pt.6 6  .a href="+code=ms" class="sref">ms./a>->.a href="+code=state" class="sref">state./a> = .a href="+code=mpc52xx_spi_fsmstate_wait" class="sref">mpc52xx_spi_fsmstate_wait./a>;=6254./a>pt.6 6  pt.6 6  return .a href="+code=FSM_CONTINUE" class="sref">FSM_CONTINUE./a>;=6255./a>pt.6 6  }=6256./a>=6257./a>pt.6 6  .spau class="comment">/* Write out the next byte */./spaue=6258./a>pt.6 6  .a href="+code=ms" class="sref">ms./a>->.a href="+code=wcol_tx_timestamp" class="sref">wcol_tx_timestamp./a> = .a href="+code=get_tbl" class="sref">get_tbl./a>();=6259./a>pt.6 6  if (.a href="+code=ms" class="sref">ms./a>->.a href="+code=tx_buf" class="sref">tx_buf./a>)=6260./a>pt.6 6  pt.6 6  .a href="+code=out_8" class="sref">out_8./a>(.a href="+code=ms" class="sref">ms./a>->.a href="+code=regs" class="sref">regs./a> + .a href="+code=SPI_DATA" class="sref">SPI_DATA./a>,p*.a href="+code=ms" class="sref">ms./a>->.a href="+code=tx_buf" class="sref">tx_buf./a>++);=6261./a>pt.6 6  else=6262./a>pt.6 6  pt.6 6  .a href="+code=out_8" class="sref">out_8./a>(.a href="+code=ms" class="sref">ms./a>->.a href="+code=regs" class="sref">regs./a> + .a href="+code=SPI_DATA" class="sref">SPI_DATA./a>,p0);=6263./a>=6264./a>pt.6 6  return .a href="+code=FSM_CONTINUE" class="sref">FSM_CONTINUE./a>;=6265./a>}=6266./a>=6267./a>.spau class="comment">/*./spaue=6268./a>.spau class="comment"> * WAIT state./spaue=6269./a>.spau class="comment"> *./spaue=627
  a>.spau class="comment"> * A transfer has compleved; need to wait for the delay period to compleve./spaue=6271./a>.spau class="comment"> * before starting the next transfer./spaue=6272./a>.spau class="comment"> */./spaue=6273./a>static int=6274./a>.a href="+code=mpc52xx_spi_fsmstate_wait" class="sref">mpc52xx_spi_fsmstate_wait./a>(int .a href="+code=irq" class="sref">irq./a>, struct .a href="+code=mpc52xx_spi" class="sref">mpc52xx_spi./a>p*.a href="+code=ms" class="sref">ms./a>, .a href="+code=u8" class="sref">u8./a> .a href="+code=status" class="sref">status./a>, .a href="+code=u8" class="sref">u8./a> .a href="+code=data" class="sref">data./a>)=6275./a>{=6276./a>pt.6 6  if (.a href="+code=status" class="sref">status./a> && .a href="+code=irq" class="sref">irq./a>)=6277./a>pt.6 6  pt.6 6  .a href="+code=dev_err" class="sref">dev_err./a>(&.a href="+code=ms" class="sref">ms./a>->.a href="+code=master" class="sref">master./a>->.a href="+code=dev" class="sref">dev./a>, .spau class="string">"spurious irq, status=0x%.2x\n"./spaue,=6278./a>pt.6 6          pt.6 6  .a href="+code=status" class="sref">status./a>);=6279./a>=6280./a>pt.6 6  if (((int).a href="+code=get_tbl" class="sref">get_tbl./a>()) - .a href="+code=ms" class="sref">ms./a>->.a href="+code=timestamp" class="sref">timestamp./a> < 0)=6281./a>pt.6 6  pt.6 6  return .a href="+code=FSM_POLL" class="sref">FSM_POLL./a>;=6282./a>=6283./a>pt.6 6  .a href="+code=ms" class="sref">ms./a>->.a href="+code=messag
" class="sref">messag
./a>->.a href="+code=actual_length" class="sref">actual_length./a> += .a href="+code=ms" class="sref">ms./a>->.a href="+code=transfer" class="sref">transfer./a>->.a href="+code=len" class="sref">len./a>;=6284./a>=6285./a>pt.6 6  .spau class="comment">/* Check if ther
 is another transfer in this messag
.  If thereltc#Lclass="line" nam
  L194">6194./a>pt.6 6 assclass="line" nam
  L194">6194./a>pt.6 6 alass="line" nam
  L177"ne" nam
  L278">e't ohen rdectuivte mCS, othifysendier,aud sdrop bak io cdle./a#Lclass="line" nam
  L194">6194./a>pt.6 6 as" id  L277" class="line" nam
  L127">6128./a>.spau class="comment"> *nam
  L278o ctartithe next tessag
.  /./spaue=6128./a>pt.6 6  if (.a href="+code=ss" class="sref">ms./a>->.a href="+code=transfer" class="sref">transfer./a>->.a href="+code=lransfer_list" class="sref">transfer_list./a>).a href="+code=next" class="sref">next./a>,== 0amp;.a href="+code=ms" class="sref">ms./a>->.a href="+code=messag
" class="sref">messag
./a>->.a href="+code=qransfers" class="sref">transfers./a>.p{=6129./a>pt.6 6  pt.6 6  .a href="+code=ss" class="sref">ms./a>->.a href="+code=mesgcount" class="sref">mosgcount"/a>++;=6129./a>pt.6 6  pt.6 6  .a href="+code=opc52xx_spi_chipsel" class="sref">mpc52xx_spi_chipsel./a>(.a href="+code=ms" class="sref">ms./a>, 0);=6129./a>pt.6 6  pt.6 6  .a href="+code=ms" class="sref">ms./a>->.a href="+code=tessag
" class="sref">messag
./a>->.a href="+code=status" class="sref">status./a> = -;=6129./a>pt.6 6  pt.6 6  .a href="+code=ms" class="sref">ms./a>->.a href="+code=tessag
" class="sref">messag
./a>->.a href="+code=compleve" class="sref">compleve./a>(.a href="+code=ms" class="sref">ms./a>->.a href="+code=messag
" class="sref">messag
./a>->.a href="+code=context" class="sref">context./a>);=6129./a>pt.6 6  pt.6 6  .a href="+code=ms" class="sref">ms./a>->.a href="+code=state" class="sref">state./a> = .a href="+code=mpc52xx_spi_fsmstate_wdle" class="sref">mpc52xx_spi_fsmstate_idle./a>;=6129./a>pt.6 6  pt.6 6  return .a href="+code=FSM_CONTINUE" class="sref">FSM_CONTINUE./a>;=6129./a>pt.6 6  }=6126./a>=6129./a>pt.6 6  .spau class="comment">/* WTer
 is another transfer ;kick it off. /./spaue=6129./a>=6129./a>pt.6 6  if (.a href="+code=ms" class="sref">ms./a>->.a href="+code=ts_chang
" class="sref">cs_chang
./a> =6230./a>pt.6 6  pt.6 6  .a href="+code=opc52xx_spi_chipsel" class="sref">mpc52xx_spi_chipsel./a>(.a href="+code=ms" class="sref">ms./a>, 0);=6231./a>}6230./a>pt.6 6  .a href="+code=os" class="sref">ms./a>->.a href="+code=transfer" class="sref">transfer./a> = .a href="+code=container_of" class="sref">container_of./a>(.a href="+code=ms" class="sref">ms./a>->.a href="+code=mransfer" class="sref">transfer./a>->.a href="+code=lransfer_list" class="sref">transfer_list./a>).a href="+code=next" class="sref">next./a>,=6230./a>pt.6 6  pt.6 6  pt.6 6  .............truct .a href="+code=spi_transfer" class="sref">spi_transfer./a>, .a href="+code=transfer_list" class="sref">transfer_list./a>);=6230./a>pt.6 6  .a href="+code=msc52xx_spi_ctart_transfer" class="sref">mpc52xx_spi_start_transfer./a>(.a href="+code=ms" class="sref">ms./a>);=6230./a>pt.6 6  .a href="+code=ss" class="sref">ms./a>->.a href="+code=state" class="sref">state./a> = .a href="+code=mpc52xx_spi_fsmstate_transfer" class="sref">mpc52xx_spi_fsmstate_transfer./a>;=6230./a>pt.6 6  ieturn .a href="+code=FSM_CONTINUE" class="sref">FSM_CONTINUE./a>;=6237./a>.=6230./a>=6239./a>.spau class="comment"> /*./spaue=623
  a>.spau class="comment"> */ pc52xx_spi_fsms_rocessi - Fnit.e Sate mMchine isteraton (functon /spaue=6231./a>.spau class="comment"> * b@irq:irq, numbr trat wtriggr
 dthe nSM_ or 0for tpllisg./spaue=6231./a>.spau class="comment"> */ @ms:tplnterr8o cpc52xx_spi_ rivers ata./apaue=6231./a>.spau class="comment">  /./spaue=6234./a>ptatic ivoid.a href="+code=mpc52xx_spi_fsms_rocessi class="sref">mpc52xx_spi_fsms_rocessi/a>(int .a href="+code=irq" class="sref">irq./a>, struct .a href="+code=mpc52xx_spi" class="sref">mpc52xx_spi./a>p*.a href="+code=ms" class="sref">ms./a>,=6231./a>{=6231./a>pt.6 6  ift .a href="+code=ir" class="sref">trc/a> = .a href="+code=mSM_CONTINUE" class="sref">FSM_CONTINUE./a>;=6231./a>pt.6 6  .a href="+code=m8" class="sref">u8./a> .a href="+code=status" class="sref">status./a>, .a href="+code=uata" class="sref">data./a>;=6231./a>=6231./a>pt.6 6  ihile ((a href="+code=ir" class="sref">trc/a> =  .a href="+code=mSM_CONTINUE" class="sref">FSM_CONTINUE./a>;p{=6232./a>pt.6 6  pt.6 6  .apau class="comment">/* Isterrupt aclea
 dty retd of tTATUS_forlowerdty /spaue=6231./a>.spau class="comment">                 * metd of tATA.register  */./spaue=6232./a>pt.6 6  pt.6 6  .a href="+code=spatus" class="sref">status./a> = -a href="+code=irn8" class="sref">orn8"/a>(.a href="+code=ms" class="sref">ms./a>->.a href="+code=megs" class="sref">regs./a> + .a href="+code=SPI_DTATUS_ class="sref">rPI_DTATUS_/a>);=6232./a>pt.6 6  pt.6 6  .a href="+code=mata" class="sref">data./a> = *a href="+code=irn8" class="sref">orn8"/a>(.a href="+code=ms" class="sref">ms./a>->.a href="+code=megs" class="sref">regs./a> + .a href="+code=SPI_DATA" class="sref">SPI_DATA./a>,;=6232./a>pt.6 6  pt.6 6  .a href="+code=mr" class="sref">trc/a> = .a href="+code=ms" class="sref">ms./a>->.a href="+code=state" class="sref">state./a> .a href="+code=mrq" class="sref">irq./a>, sa href="+code=ms" class="sref">ms./a>, 0a href="+code=status" class="sref">status./a>, .a href="+code=uata" class="sref">data./a>;;=6232./a>pt.6 6  }=6232./a>=6232./a>pt.6 6  if (.a href="+code=sr" class="sref">trc/a> =  .a href="+code=mSM_COLL" class="sref">FSM_POLL./a>;=6238./a>pt.6 6          .a href="+code=dschedule_orke class="sref">stchedule_orke/a> .amp;.a href="+code=ms" class="sref">ms./a>->.a href="+code=morke class="sref">sorke/a> ;=6239./a>p=6230./a>p6233./a>.spau class="comment"> /*./spaue=6233./a>.spau class="comment"> */ pc52xx_spi_frq, - IRQ handlr./spaue=6233./a>.spau class="comment">  /./spaue=6233./a>ptatic ia href="+code=mrq"eturn _" class="sref">trq"eturn _"/a> .a href="+code=spc52xx_spi_frq, class="sref">mpc52xx_spi_frq./a>,int .a href="+code=irq" class="sref">irq./a>, svoid..a href="+code=m_s" class="sref">m_s./a>,=6233./a>{=6236./a>pt.6 6   truct .a href="+code=mpc52xx_spi" class="sref">mpc52xx_spi./a>p*.a href="+code=ms" class="sref">ms./a>,= .a href="+code=m_s" class="sref">m_s./a>,=6233./a>pt.6 6  .a href="+code=spprn8loce class="sref">stprn8loce/a> .amp;.a href="+code=ms" class="sref">ms./a>->.a href="+code=mloce class="sref">sloce/a> ;=6233./a>pt.6 6  .a href="+code=msc52xx_spi_fsms_rocessi class="sref">mpc52xx_spi_fsms_rocessi/a>(ia href="+code=mrq" class="sref">irq./a>, sa href="+code=ms" class="sref">ms./a>,;=6233./a>pt.6 6  .a href="+code=mtprn8unloce class="sref">stprn8unloce/a> .amp;.a href="+code=ms" class="sref">ms./a>->.a href="+code=mloce class="sref">sloce/a> ;=6234./a>pt.6 6  return .a href="+code=FIRQ_HANDLED class="sref">sIRQ_HANDLED/a>,=6234./a>}=6232./a>=6234./a>.spau class="comment">/*../spaue=6234./a>.spau class="comment"> * Tpc52xx_spi_fw, - Wrkequeue(functon for tpllisg.the state machine /spaue=6234./a>.spau class="comment"> *../spaue=6236./a>ptatic ivoid.a href="+code=mpc52xx_spi_fw, class="sref">mpc52xx_spi_fw./a>,itruct .a href="+code=morke_truct  class="sref">sorke_truct /a>p*.a href="+code=morke class="sref">sorke/a> ;6237./a>==6238./a>pt.6 6  .truct .a href="+code=mpc52xx_spi" class="sref">mpc52xx_spi./a>p*.a href="+code=ms" class="sref">ms./a>,= .a href="+code=montainer_of" class="sref">container_of./a>(.a href="+code=morke class="sref">sorke/a>  struct .a href="+code=mpc52xx_spi" class="sref">mpc52xx_spi./a>p sa href="+code=morke class="sref">sorke/a> ;=6239./a>pt.6 6  .unsigned log.ta href="+code=mlag " class="sref">mlag "/a>,=6235./a>p6231./a>pt.6 6  pa href="+code=spprn8locefrq.sav" class="sref">stprn8locefrq.sav"/a> .amp;.a href="+code=ms" class="sref">ms./a>->.a href="+code=mloce class="sref">sloce/a>  sa href="+code=mlag " class="sref">mlag "/a>,;=6235./a>pt.6 6  .a href="+code=osc52xx_spi_fsms_rocessi class="sref">mpc52xx_spi_fsms_rocessi/a>(i0 sa href="+code=ms" class="sref">ms./a>,;=6233./a>pt.6 6  pa href="+code=mtprn8unloce_rq"etstor" class="sref">stprn8unloce_rq"etstor"/a> .amp;.a href="+code=ms" class="sref">ms./a>->.a href="+code=mloce class="sref">sloce/a>  sa href="+code=mlag " class="sref">mlag "/a>,;=6234./a>p=6235./a>p6235alass="line" nam
  L177"ne"*./spaue=6235./a>.spau class="comment"> * api_faster. ops/spaue=6235./a>.spau class="comment"> * ./spaue=6235./a>=6230./a>ptatic int .a href="+code=mpc52xx_spi_fstur" class="sref">tpc52xx_spi_fstur"/a>,itruct .a href="+code=mpi_fevic
  class="sref">stprfevic
 /a>p*.a href="+code=mpi" class="sref">mpi./a>p;6231./a>p=6232./a>pt.6 6  pf (.a href="+code=sti" class="sref">mpi./a>p>.a href="+code=byit_per_uorkd class="sref">myit_per_uorkd/a>pt#37;. 8;6236./a>pt.6 6  pt.6 6  .eturn ..a href="+code=EIONVA" class="sref">FIONVA"/a>,=6236./a>=6236./a>pt.6 6  if (.a href="+code=mti" class="sref">mpi./a>p>.a href="+code=bode  class="sref">tpde /a>pt#mp; .~.a href="+code=mPI_DCPL" class="sref">SPI_SCPL"/a>pt|.a href="+code=SPI_DCPH" class="sref">SPI_DCPH"/a>pt|.a href="+code=SPI_DLSB_FIRST class="sref">SPI_DLSB_FIRST/a>p;;6236./a>pt.6 6          *eturn ..a href="+code=EIONVA" class="sref">FIONVA"/a>,=6236./a>=6236./a>pt.6 6  if (.a href="+code=sti" class="sref">mpi./a>p>.a href="+code=bhipsfstlet  class="sref">shipsfstlet /a>pt#t;. .a href="+code=mti" class="sref">mpi./a>p>.a href="+code=boster" class="sref">master./a>->.a href="+code=dnumchipsel.et  class="sref">snumchipsel.et /a>p;6236./a>pt.6 6  pt.6 6  .eturn ..a href="+code=EIONVA" class="sref">FIONVA"/a>,=6237./a>p6237./a>pt.6 6  peturn .;=6232./a>.=6237./a>=62374/a>ptatic int .a href="+code=mpc52xx_spi_fransfer" class="sref">mpc52xx_spi_fransfer./a>(.truct .a href="+code=mpi_fevic
  class="sref">stprfevic
 /a>p*.a href="+code=mpi" class="sref">mpi./a>p struct .a href="+code=mpi_fassag
" class="sref">mpi_fassag
"/a>p*.a href="+code=ms class="sref">mp/a>p;6235./a>{=6237./a>pt.6 6   truct .a href="+code=mpc52xx_spi" class="sref">mpc52xx_spi./a>p*.a href="+code=ms" class="sref">ms./a>,= .a href="+code=mpi_faster._et_teviata" class="sref">dpi_faster._et_teviata"/a>(.a href="+code=mti" class="sref">mpi./a>p>.a href="+code=boster" class="sref">master./a>-;=6237./a>pt.6 6  punsigned log.ta href="+code=mlag " class="sref">mlag "/a>,=6237./a>=6237./a>pt.6 6  .a href="+code=ms class="sref">mp/a>p>.a href="+code=actual_length" class="sref">actual_length./a> + -;=6230./a>pt.6 6  ia href="+code=ms class="sref">mp/a>p>.a href="+code=atatus" class="sref">status./a> = -.a href="+code=EIONPROGRES_ class="sref">rIONPROGRES_/a>,=6238./a>}6238./a>pt.6 6  .a href="+code=opprn8locefrq.sav" class="sref">stprn8locefrq.sav"/a> .amp;.a href="+code=ms" class="sref">ms./a>->.a href="+code=mloce class="sref">sloce/a>  sa href="+code=mlag " class="sref">mlag "/a>,;=6233./a>pt.6 6  .a href="+code=mist._add_tai" class="sref">mist._add_tai"/a> .amp;.a href="+code=ms class="sref">mp/a>p>.a href="+code=aqueue class="sref">mqueue/a>  samp;.a href="+code=ms" class="sref">ms./a>->.a href="+code=mqueue class="sref">mqueue/a> ;=6238./a>pt.6 6  .a href="+code=mtprn8unloce_rq"etstor" class="sref">stprn8unloce_rq"etstor"/a> .amp;.a href="+code=ms" class="sref">ms./a>->.a href="+code=mloce class="sref">sloce/a>  sa href="+code=mlag " class="sref">mlag "/a>,;=6238./a>pt.6 6  .a href="+code=sschedule_orke class="sref">stchedule_orke/a> .amp;.a href="+code=ms" class="sref">ms./a>->.a href="+code=morke class="sref">sorke/a> ;=6194./a3pt.6 38./a>=6138./a>pt.6 6  peturn .;=6138./a>p=6138./a>=6139  a>.spau class="comment"> *./spaue=6139./a>.spau class="comment"> * bOF Platform Bus Biding /spaue=6139./a>.spau class="comment"> */./spaue=6139./a>static int=.a href="+code=mpc52xx_spi_fprob  class="sref">tpc52xx_spi_fprob /a>(.truct .a href="+code=mplatformfevic
  class="sref">splatformfevic
 /a>p*.a href="+code=mo" class="sref">top/a>p;6139./a>p=6139./a>pt.6 6  }truct .a href="+code=mpi_faster" class="sref">mpi_faster"/a>p*.a href="+code=msster" class="sref">master./a>-=6139./a>pt.6 6   truct .a href="+code=mpc52xx_spi" class="sref">mpc52xx_spi./a>p*.a href="+code=ms" class="sref">ms./a>,=6139./a>pt.6 6  .void.a href="+code=m__iomes class="sref">m__iomes/a>p*.a href="+code=megs" class="sref">regs./a> =6139./a>pt.6 6  .a href="+code=m8" class="sref">u8./a> .a href="+code=sctrl1 class="sref">uctrl1/a> =6139./a>pt.6 6  ift .a href="+code=ir" class="sref">trc/a>  sa href="+code=m" class="sref">mi/a> + -;=6240./a>pt.6 6  pft .a href="+code=igpio_s" class="sref">dgpio_s"/a> =6241./a>}6240./a>pt.6 6  .apau class="comment">/* IMMIOregister  */./spaue=6240./a>pt.6 6  .a href="+code=mev_edbg class="sref">dev_edbg/a> .amp;.a href="+code=mo" class="sref">top/a>p>.a href="+code=dev" class="sref">dev./a>, .spau class="string">"sprobsg.tpc52x00 SPIdevic
 n"./spaue);=6240./a>pt.6 6  .a href="+code=megs" class="sref">regs./a> + .a href="+code=mof_ioma" class="sref">tof_ioma"/a>(.a href="+code=mo" class="sref">top/a>p>.a href="+code=dev" class="sref">dev./a>,.a href="+code=nof_nde  class="sref">tof_nde /a>, .);=6240./a>pt.6 6  if (.!a href="+code=megs" class="sref">regs./a> ;6240./a>pt.6 6          *eturn ..a href="+code=EINODEV class="sref">rINODEV/a> =6240./a>=6240./a>pt.6 6  .spau class="comment">/* Init.ializethe delic
 */./spaue=6240./a>pt.6 6  .a href="+code=mctrl1 class="sref">uctrl1/a> + .a href="+code=mPI_DCTRL1_PI_" class="sref">FPI_DCTRL1_PI_"/a>pt|.a href="+code=SPI_DCTRL1_PI" class="sref">FPI_DCTRL1_PI"/a>pt|.a href="+code=SPI_DCTRL1_MSTR class="sref">FPI_DCTRL1_MSTR/a> =6241./a>pt.6 6  ia href="+code=mut_8" class="sref">out_8./a>(.a href="+code=megs" class="sref">regs./a> + .a href="+code=SPI_DCTRL1 class="sref">FPI_DCTRL1/a>  sa href="+code=mctrl1 class="sref">uctrl1/a> ;=6241./a>pt.6 6  pa href="+code=sut_8" class="sref">out_8./a>(.a href="+code=megs" class="sref">regs./a> + .a href="+code=SPI_DCTRL2 class="sref">FPI_DCTRL2/a>, .)x);=6241./a>pt.6 6  .a href="+code=out_8" class="sref">out_8./a>(.a href="+code=megs" class="sref">regs./a> + .a href="+code=SPI_DATA.DIR class="sref">FPI_DATA.DIR/a>, .)xe);.spau class="comment">/* ISetout put pin */./spaue=6241./a>pt.6 6  .a href="+code=mut_8" class="sref">out_8./a>(.a href="+code=megs" class="sref">regs./a> + .a href="+code=SPI_DPORTATA" class="sref">SPI_DPORTATA"/a>, .)x8);..6 6  .spau class="comment">/* IDess=ert /SS ="dralFPI_DATA.DIR/a>, .)xe);.spau class="comment">/* I="line" n4" class="line" nam
  L244">6241./a>=6241./a>pt.6 6  .spau class="comment">/* Chlea
the stateusregister aud sre-etd oitto coeck ior ta MODF_DATA.DIR/a>, .)xe);.spau class="comment">/* I" id  L246" class="line" nam
  L246">6241alass="line" nam
  L177"ne" nam
  L278failur.  ITis mrivers cannot curr7"nly handlr multiplr mster.s/spaue=6241./a>.spau class="comment"> *nam
  L278onthe sSPIdbus  ITis mfault will also occurif thersSPId="drals/spaue=6241./a>.spau class="comment"> *nam
  L278are not connectd to wany pin *(port_config seting )FPI_DATA.DIR/a>, .)xe);.spau class="comment">/* I" id  L249" class="line" nam
  L249">6241./a>pt.6 6  .a href="+code=mrn8" class="sref">orn8"/a>(.a href="+code=megs" class="sref">regs./a> + .a href="+code=SPI_DTATUS_ class="sref">rPI_DTATUS_/a>);=6242./a>pt.6 6  ia href="+code=mut_8" class="sref">out_8./a>(.a href="+code=megs" class="sref">regs./a> + .a href="+code=SPI_DCTRL1 class="sref">FPI_DCTRL1/a>  sa href="+code=mctrl1 class="sref">uctrl1/a> ;=6242./a>}6242./a>pt.6 6  .a href="+code=orn8" class="sref">orn8"/a>(.a href="+code=megs" class="sref">regs./a> + .a href="+code=SPI_DATA" class="sref">SPI_DATA./a>,;=6242./a>pt.6 6  pf (.a href="+code=srn8" class="sref">orn8"/a>(.a href="+code=megs" class="sref">regs./a> + .a href="+code=SPI_DTATUS_ class="sref">rPI_DTATUS_/a>); amp; .a href="+code=iPI_DTATUS__MODF class="sref">rPI_DTATUS__MODF_D>;p{=6242./a>pt.6 6  pt.6 6  .a href="+code=mev_err" class="sref">dev_err./a>(&.a href="+code=mo" class="sref">top/a>p>.a href="+code=dev" class="sref">dev./a>, .spau class="string">"spde mfault;is aport_config corr7ct?n"./spaue);=6242./a>pt.6 6  }t.6 6  .a href="+code=mr" class="sref">trc/a> = ..a href="+code=EIOO class="sref">rIOO/a> =6242./a>pt.6 6          *goo wa href="+code=Err._nit. class="sref">rrr._nit./a> =6242./a>pt.6 6  i=6242./a>=6242./a>pt.6 6  .a href="+code=mev_edbg class="sref">dev_edbg/a> .amp;.a href="+code=mo" class="sref">top/a>p>.a href="+code=dev" class="sref">dev./a>, .spau class="string">"sallocaing tpi_faster" truct n"./spaue);=6243./a>pt.6 6  ia href="+code=msster" class="sref">master./a>-= .a href="+code=mpi_fallocfaster" class="sref">mpi_fallocfaster"/a> .amp;.a href="+code=mo" class="sref">top/a>p>.a href="+code=dev" class="sref">dev./a>, .sizeof*.a href="+code=ms" class="sref">ms./a>,==62431/a>pt.6 6  pf (.!a href="+code=moster" class="sref">master./a>-;{=6243./a>pt.6 6  pt.6 6  .a href="+code=sr" class="sref">trc/a> = ..a href="+code=EINOMEM class="sref">rINOMEM/a> =6243./a>pt.6 6  pt.6 6  .goo wa href="+code=Err._alloc class="sref">rrr._alloc/a> =62434/a>pt.6 6  i=6243./a>p6246./a>pt.6 6   a href="+code=moster" class="sref">master./a>->.a href="+code=attur" class="sref">tstur"/a>,= .a href="+code=mpc52xx_spi_fstur" class="sref">tpc52xx_spi_fstur"/a>,=6243./a>pt.6 6  .a href="+code=soster" class="sref">master./a>->.a href="+code=aransfer" class="sref">transfer./a> = .a href="+code=cpc52xx_spi_fransfer" class="sref">mpc52xx_spi_fransfer./a>(=6243./a>pt.6 6  .a href="+code=msster" class="sref">master./a>->.a href="+code=apde _yit_ class="sref">made _yit_/a> + .a href="+code=mPI_DCPL" class="sref">SPI_SCPL"/a>pt|.a href="+code=SPI_DCPH" class="sref">SPI_DCPH"/a>pt|.a href="+code=SPI_DLSB_FIRST class="sref">SPI_DLSB_FIRST/a>p=6243./a>pt.6 6  .a href="+code=master" class="sref">master./a>->.a href="+code=dev" class="sref">dev./a>,.a href="+code=nof_nde  class="sref">tof_nde /a>,+ .a href="+code=mo" class="sref">top/a>p>.a href="+code=dev" class="sref">dev./a>,.a href="+code=nof_nde  class="sref">tof_nde /a>,=6244./a>p6244./a>pt.6 6  pa href="+code=sev_est_teriata" class="sref">dev_est_teriata"/a> .amp;.a href="+code=mo" class="sref">top/a>p>.a href="+code=dev" class="sref">dev./a>, .s href="+code=moster" class="sref">master./a>-;=6242./a>=6244./a>pt.6 6  .a href="+code=ms" class="sref">ms./a>-= .a href="+code=mpi_faster._et_teviata" class="sref">dpi_faster._et_teviata"/a>(.a href="+code=moster" class="sref">master./a>-;=6244./a>pt.6 6  .a href="+code=ms" class="sref">ms./a>->.a href="+code=master" class="sref">master./a>-= .a href="+code=cpster" class="sref">master./a>-=6244./a>pt.6 6  .a href="+code=ss" class="sref">ms./a>->.a href="+code=segs" class="sref">regs./a> + .a href="+code=megs" class="sref">regs./a> =6244./a>pt.6 6   a href="+code=mo" class="sref">ms./a>->.a href="+code=sirq0 class="sref">mirq0/a> + .a href="+code=mirq_of_parse_and_ma" class="sref">tirq_of_parse_and_ma"/a>(.a href="+code=mo" class="sref">top/a>p>.a href="+code=dev" class="sref">dev./a>,.a href="+code=nof_nde  class="sref">tof_nde /a>, .);=6244./a>pt.6 6  .a href="+code=so" class="sref">ms./a>->.a href="+code=sirq1 class="sref">uirq1/a> + .a href="+code=mirq_of_parse_and_ma" class="sref">tirq_of_parse_and_ma"/a>(.a href="+code=mo" class="sref">top/a>p>.a href="+code=dev" class="sref">dev./a>,.a href="+code=nof_nde  class="sref">tof_nde /a>, .1;=6244./a>pt.6 6  .a href="+code=ms" class="sref">ms./a>->.a href="+code=state" class="sref">state./a> = .a href="+code=mpc52xx_spi_fsmstate_wdle" class="sref">mpc52xx_spi_fsmstate_idle./a>;=6244./a>pt.6 6  .a href="+code=ma" class="sref">ms./a>->.a href="+code=sipb_fre" class="sref">irpb_fre"/a> = .a href="+code=mpc52xx_set_tbus_fre"uency class="sref">mpc52xx_set_tbus_fre"uency/a>(.a href="+code=mo" class="sref">top/a>p>.a href="+code=dev" class="sref">dev./a>,.a href="+code=nof_nde  class="sref">tof_nde /a>,;=6245./a>pt.6 6  ia href="+code=ms" class="sref">ms./a>->.a href="+code=sgpio_s"count" class="sref">mgpio_s"count"/a>,+ .a href="+code=mof_gpio_sunt" class="sref">mof_gpio_sunt"/a>(.a href="+code=mo" class="sref">top/a>p>.a href="+code=dev" class="sref">dev./a>,.a href="+code=nof_nde  class="sref">tof_nde /a>,;=62451/a>pt.6 6  pf (.a href="+code=ms" class="sref">ms./a>->.a href="+code=sgpio_s"count" class="sref">mgpio_s"count"/a>,+gt;..);{=6245./a>pt.6 6  pt.6 6  .a href="+code=soster" class="sref">master./a>->.a href="+code=dnumchipsel.et  class="sref">snumchipsel.et /a>p= .a href="+code=ms" class="sref">ms./a>->.a href="+code=sgpio_s"count" class="sref">mgpio_s"count"/a>,=6245./a>pt.6 6  pt.6 6  .a href="+code=ms" class="sref">ms./a>->.a href="+code=sgpio_s" class="sref">mgpio_s"/a>p= .a href="+code=mkmalloc class="sref">rkmalloc/a>(.a href="+code=mo" class="sref">ms./a>->.a href="+code=sgpio_s"count" class="sref">mgpio_s"count"/a>,+*.sizeof(unsigned int)=6245./a>pt.6 6  pt.6 6  .t.6 6  pt.6 6  .a href="+code=mGFP_KERNE" class="sref">SGFP_KERNE"/a>,;=6245./a>pt.6 6  }t.6 6  .f (.!a href="+code=mo" class="sref">ms./a>->.a href="+code=sgpio_s" class="sref">mgpio_s"/a>p;{=6245./a>pt.6 6          *t.6 6  .a href="+code=mr" class="sref">trc/a> = ..a href="+code=EINOMEM class="sref">rINOMEM/a> =62457/a>pt.6 6          *t.6 6  .goo wa href="+code=Err._alloc_gpio class="sref">rrr._alloc_gpio/a> =6245./a>pt.6 6          .=6245./a>=6246./a>pt.6 6  pt.6 6  .or t.a href="+code=sr class="sref">ir/a> = .0 .a href="+code=ir class="sref">ir/a> =<ia href="+code=ms" class="sref">ms./a>->.a href="+code=sgpio_s"count" class="sref">mgpio_s"count"/a>,=.a href="+code=ir class="sref">ir/a> ++;{=62461/a>pt.6 6          *t.6 6  .a href="+code=mgpio_s" class="sref">mgpio_s"/a>p= .a href="+code=mof_gt_tgpio class="sref">rof_gt_tgpio/a>(.a href="+code=mo" class="sref">top/a>p>.a href="+code=dev" class="sref">dev./a>,.a href="+code=nof_nde  class="sref">tof_nde /a>, sa href="+code=m" class="sref">mi/a> ;=6246./a>pt.6 6  pt.6 6  .t.6 6  .f (.a href="+code=mgpio_s" class="sref">mgpio_s"/a>p=<i);{=6246./a>pt.6 6  pt.6 6  .       *t.6 6  .a href="+code=mev_err" class="sref">dev_err./a>(&.a href="+code=mo" class="sref">top/a>p>.a href="+code=dev" class="sref">dev./a>, 6246./a>pt.6 6  pt.6 6  .t.6 6  pt.6 6  .t.6 6  .apau class="string">"sounld not parsethersgpio field quot;./spaue)6246./a>pt.6 6  }t.6 6  .t.6 6  pt.6 6  .t.6 6  .apau class="string">"sin oftre n"./spaue);=6246./a>pt.6 6          *       *t.6 6  .a href="+code=mr" class="sref">trc/a> = ..a href="+code=EINODEV class="sref">rINODEV/a> =62467/a>pt.6 6          *t.6 6  .........goo wa href="+code=Err._gpio class="sref">rrr._gpio/a> =6246./a>pt.6 6          .........=6246./a>=6247./a>pt.6 6  pt.6 6  .t.6 6  .a href="+code=mr" class="sref">trc/a> = .a href="+code=mgpio_re"ues" class="sref">mgpio_re"ues"/a>(.a href="+code=mgpio_s" class="sref">mgpio_s"/a>p .a href="+code=uav_eam
  class="sref">dev_eam
 /a>(&.a href="+code=mo" class="sref">top/a>p>.a href="+code=dev" class="sref">dev./a>,);=62471/a>pt.6 6          *t.6 6  .f (.a href="+code=sr" class="sref">trc/a> ;{=6247./a>pt.6 6  pt.6 6  .t.6 6  .t.6 6  .a href="+code=mev_err" class="sref">dev_err./a>(&.a href="+code=mo" class="sref">top/a>p>.a href="+code=dev" class="sref">dev./a>, 6247./a>pt.6 6  pt.6 6  .       *t.6 6  .t.6 6  .apau class="string">"soan't re"ues"tpi_ cssgpio ##37;.d quot;./spaue)6247./a>pt.6 6  pt.6 6  .t.6 6  pt.6 6  .t.6 6  .apau class="string">"sonsgpio ine"t#37;.dn"./spaue) sa href="+code=m" class="sref">mi/a>  sa href="+code=mgpio_s" class="sref">mgpio_s"/a>p;=6247./a>pt.6 6  }t.6 6  .t.6 6  pt.6 6  .goo wa href="+code=Err._gpio class="sref">rrr._gpio/a> =6247./a>pt.6 6          *       *=6247./a>=6247./a>pt.6 6          .........a href="+code=mgpio_dir7ction_ut put class="sref">mgpio_dir7ction_ut put/a>(.a href="+code=mgpio_s" class="sref">mgpio_s"/a>p .1;=6247./a>pt.6 6  pt.6 6  .........a href="+code=mo" class="sref">ms./a>->.a href="+code=sgpio_s" class="sref">mgpio_s"/a>p[a href="+code=m" class="sref">mi/a> ]= .a href="+code=mgpio_s" class="sref">dgpio_s"/a> =6248./a>pt.6 6  pt.6 6  .=62481/a>pt.6 6   =6248./a>=6243./a>pt.6 6  .a href="+code=msprn8locefrit. class="sref">rsprn8locefrit./a>(&.a href="+code=ms" class="sref">ms./a>->.a href="+code=mloce class="sref">sloce/a> ;=6248./a>pt.6 6  .a href="+code=mINIT_LIST_HEAD class="sref">sINIT_LIST_HEAD/a>(&.a href="+code=ms" class="sref">ms./a>->.a href="+code=mqueue class="sref">mqueue/a> ;=6248./a>pt.6 6  .a href="+code=sINIT_WORK class="sref">sINIT_WORK/a>(&.a href="+code=ms" class="sref">ms./a>->.a href="+code=morke class="sref">sorke/a>  sa href="+code=mpc52xx_spi_fw, class="sref">mpc52xx_spi_fw./a>,;=6194./a4pt.6 48./a>=6148./a>pt.6 6  pspau class="comment">/* IDecide.f (intrr.upts can be usedFPI_DATA.DIR/a>, .)xe);.spau class="comment">/* 8" id  L148" class="line" nam
  L148">6148./a>pt.6 6  if (.a href="+code=so" class="sref">ms./a>->.a href="+code=sirq0 class="sref">mirq0/a> +amp;.amp; .a href="+code=io" class="sref">ms./a>->.a href="+code=sirq1 class="sref">uirq1/a> ;{=6148./a>pt.6 6  pt.6 6  .a href="+code=mr" class="sref">trc/a> = .a href="+code=mre"ues"frq, class="sref">mre"ues"frq,/a>(.a href="+code=mo" class="sref">ms./a>->.a href="+code=sirq0 class="sref">mirq0/a>  sa href="+code=mpc52xx_spi_frq, class="sref">mpc52xx_spi_frq./a>,, 0 6149./a>pt.6 6  pt.6 6  .t.6 6  . pt.6 6  .apau class="string">"spc52x00-pi-mpodfquot;./spaue) sa href="+code=ms" class="sref">ms./a>,==61491/a>pt.6 6          *a href="+code=mr" class="sref">trc/a> =| .a href="+code=mre"ues"frq, class="sref">mre"ues"frq,/a>(.a href="+code=mo" class="sref">ms./a>->.a href="+code=sirq1 class="sref">uirq1/a>  sa href="+code=mpc52xx_spi_frq, class="sref">mpc52xx_spi_frq./a>,, 0 6149./a>pt.6 6  pt.6 6  .t.6 6  .t.6 6  . .apau class="string">"spc52x00-pi-mpi-fquot;./spaue) sa href="+code=ms" class="sref">ms./a>,==6149./a>pt.6 6  pt.6 6  .f (.a href="+code=sr" class="sref">trc/a> ;{=6149./a>pt.6 6  pt.6 6  .t.6 6  pa href="+code=sfreefrq, class="sref">mfreefrq,/a>(.a href="+code=mo" class="sref">ms./a>->.a href="+code=sirq0 class="sref">mirq0/a>  sa href="+code=mp" class="sref">ms./a>,==6149./a>pt.6 6  }t.6 6  .t.6 6  pa href="+code=sfreefrq, class="sref">mfreefrq,/a>(.a href="+code=mo" class="sref">ms./a>->.a href="+code=sirq1 class="sref">uirq1/a>  sa href="+code=mp" class="sref">ms./a>,==6149./a>pt.6 6          *t.6 6  .a href="+code=mo" class="sref">ms./a>->.a href="+code=sirq0 class="sref">mirq0/a> + .a href="+code=mo" class="sref">ms./a>->.a href="+code=sirq1 class="sref">uirq1/a> + .;=61497/a>pt.6 6          *=6149./a>pt.6 6  .} else{=6149./a>pt.6 6  pt.6 6  .apau class="comment">/* Ioperte mintplliedFpde mPI_DATA.DIR/a>, .)xe);.spau class="comment">/*50" id  L250" class="line" nam
  L250">6250./a>pt.6 6  pt.6 6  .a href="+code=mo" class="sref">ms./a>->.a href="+code=sirq0 class="sref">mirq0/a> + .a href="+code=mo" class="sref">ms./a>->.a href="+code=sirq1 class="sref">uirq1/a> + .;=62501/a>pt.6 6   =6250./a>=6250./a>pt.6 6  .f (.!a href="+code=mo" class="sref">ms./a>->.a href="+code=sirq0 class="sref">mirq0/a> ;6250./a>pt.6 6  pt.6 6  .a href="+code=mev_einfo class="sref">rev_einfo/a>(&.a href="+code=mo" class="sref">top/a>p>.a href="+code=dev" class="sref">dev./a>, .apau class="string">"susng tplliedFpde n"./spaue);=6250./a>p6250./a>pt.6 6   a href="+code=mev_edbg class="sref">dev_edbg/a> .amp;.a href="+code=mo" class="sref">top/a>p>.a href="+code=dev" class="sref">dev./a>, .spau class="string">"segister ng tpi_faster" truct n"./spaue);=6250./a>pt.6 6  .a href="+code=sr" class="sref">trc/a> = .a href="+code=mpi_fegister faster" class="sref">mpi_fegister faster"/a>(.a href="+code=moster" class="sref">master./a>-;=6250./a>pt.6 6  if (.a href="+code=sr" class="sref">trc/a> ;6250./a>pt.6 6  pt.6 6  .goo wa href="+code=Err._egister  class="sref">rrr._egister /a> =6251./a>p6251./a>pt.6 6  pa href="+code=sev_einfo class="sref">rev_einfo/a>(&.a href="+code=ms" class="sref">ms./a>->.a href="+code=master" class="sref">master./a>->.a href="+code=dev" class="sref">dev./a>, .spau class="string">"segister edFMPC2x00 SPIdbusn"./spaue);=6251./a>=6251./a>pt.6 6  .eturn .a href="+code=sr" class="sref">trc/a> =6251./a>=6251./a>pta href="+code=Err._egister  class="sref">rrr._egister /a> :6251./a>pt.6 6   a href="+code=mev_err" class="sref">dev_err./a>(&.a href="+code=ms" class="sref">ms./a>->.a href="+code=master" class="sref">master./a>->.a href="+code=dev" class="sref">dev./a>, .spau class="string">"snit.ialization8failedn"./spaue);=6251./a>.wa href="+code=Err._gpio class="sref">rrr._gpio/a> :6251./a>pt.6 6  iwhilet.a href="+code=sr class="sref">ir/a> --+gt;..);6251./a>pt.6 6  pt.6 6  .a href="+code=mgpio_free class="sref">dgpio_free/a>(.a href="+code=mo" class="sref">ms./a>->.a href="+code=sgpio_s" class="sref">mgpio_s"/a>p[a href="+code=m" class="sref">mi/a> ];=6252./a>p6252./a>pt.6 6  pa href="+code=skfree class="sref">dkfree/a>(.a href="+code=mo" class="sref">ms./a>->.a href="+code=sgpio_s" class="sref">mgpio_s"/a>p;=6252./a>pta href="+code=Err._alloc_gpio class="sref">rrr._alloc_gpio/a> :6252./a>pt.6 6  pa href="+code=mpi_faster._put class="sref">mpi_faster._put/a>(.a href="+code=moster" class="sref">master./a>-;=6252./a>pta href="+code=Err._alloc class="sref">rrr._alloc/a> :6252./a>pta href="+code=Err._nit. class="sref">rrr._nit./a> :6252./a>pt.6 6   a href="+code=miounma" class="sref">tiounma"/a>(.a href="+code=megs" class="sref">regs./a> ;=6252./a>pt.6 6  peturn .a href="+code=sr" class="sref">trc/a> =6252./a>p=6252./a>=6253./a>ptatic int=.a href="+code=mpc52xx_spi_fremov" class="sref">spc52xx_spi_fremov"/a>(.truct .a href="+code=mplatformfevic
  class="sref">splatformfevic
 /a>p*.a href="+code=mo" class="sref">top/a>p;62531/a>p=6253./a>pt.6 6  ptruct .a href="+code=mpi_faster" class="sref">mpi_faster"/a>p*.a href="+code=msster" class="sref">master./a>-= .a href="+code=mpi_faster._et_ class="sref">mpi_faster._et_/a>(.a href="+code=mev_egt_teriata" class="sref">dev_egt_teriata"/a> .amp;.a href="+code=mo" class="sref">top/a>p>.a href="+code=dev" class="sref">dev./a>,);=6253./a>pt.6 6  ptruct .a href="+code=mpc52xx_spi" class="sref">mpc52xx_spi./a>p*.a href="+code=ms" class="sref">ms./a>,= .a href="+code=mpi_faster._et_teviata" class="sref">dpi_faster._et_teviata"/a>(.a href="+code=moster" class="sref">master./a>-;=62534/a>pt.6 6  int=.a href="+code=m" class="sref">mi/a> =6253./a>p6256./a>pt.6 6   a href="+code=mfreefrq, class="sref">mfreefrq,/a>(.a href="+code=mo" class="sref">ms./a>->.a href="+code=sirq0 class="sref">mirq0/a>  sa href="+code=mp" class="sref">ms./a>,==6253./a>pt.6 6  .a href="+code=sfreefrq, class="sref">mfreefrq,/a>(.a href="+code=mo" class="sref">ms./a>->.a href="+code=sirq1 class="sref">uirq1/a>  sa href="+code=mp" class="sref">ms./a>,==6253./a>=6253./a>pt.6 6  .or t.a href="+code=sr class="sref">ir/a> = .0 .a href="+code=ir class="sref">ir/a> =<ia href="+code=ms" class="sref">ms./a>->.a href="+code=sgpio_s"count" class="sref">mgpio_s"count"/a>,=.a href="+code=ir class="sref">ir/a> ++;6254./a>pt.6 6  pt.6 6  .a href="+code=mgpio_free class="sref">dgpio_free/a>(.a href="+code=mo" class="sref">ms./a>->.a href="+code=sgpio_s" class="sref">mgpio_s"/a>p[a href="+code=m" class="sref">mi/a> ];=6254./a>}6254./a>pt.6 6  .a href="+code=okfree class="sref">dkfree/a>(.a href="+code=mo" class="sref">ms./a>->.a href="+code=sgpio_s" class="sref">mgpio_s"/a>p;=6254./a>pt.6 6  .a href="+code=mpi_funegister faster" class="sref">mpi_funegister faster"/a>(.a href="+code=moster" class="sref">master./a>-;=6254./a>pt.6 6  .a href="+code=miounma" class="sref">tiounma"/a>(.a href="+code=ms" class="sref">ms./a>->.a href="+code=segs" class="sref">regs./a> ;=6254./a>pt.6 6  .a href="+code=spi_faster._put class="sref">mpi_faster._put/a>(.a href="+code=moster" class="sref">master./a>-;=6254./a>=6254./a>pt.6 6  peturn .;=6254./a>p=6254./a>=6255./a>ptatic icons"tpruct .a href="+code=moffevic
 _id class="sref">toffevic
 _id/a>pta href="+code=Epc52xx_spi_fmatch class="sref">spc52xx_spi_fmatch/a>p[]= .=62551/a>pt.6 6  p{ .a href="+code=ncompticbe" class="sref">mcompticbe"/a>,= .apau class="string">"sfsl,pc52x00-pi-quot;./spaue) s} 6255./a>pt.6 6  p{=6255./a>p}=6255./a>pa href="+code=nMODULE_DEVICE_TABLE class="sref">mMODULE_DEVICE_TABLE/a>(.a href="+code=mof class="sref">tof/a>  sa href="+code=mpc52xx_spi_fmatch class="sref">spc52xx_spi_fmatch/a>p;=6255./a>p6255./a>ptatic itruct .a href="+code=mplatformfeivers class="sref">splatformfeivers/a>pta href="+code=Epc52xx_spi_foffeivers class="sref">spc52xx_spi_foffeivers/a>,= .=62557/a>pt.6 6   .a href="+code=neivers class="sref">seivers/a>,= .=6255./a>pt.6 6          ..a href="+code=nam
  class="sref">dam
 /a>(= .apau class="string">"spc52xx.-pi-quot;./spaue) 6255./a>pt.6 6  pt.6 6  ..a href="+code=nownrs class="sref">sownrs/a>,= .a href="+code=mTHI__MODULE class="sref">mTHI__MODULE/a>  6256./a>pt.6 6  pt.6 6  ..a href="+code=nof_match_tabe" class="sref">mof_match_tabe"/a>,= .a href="+code=mpc52xx_spi_fmatch class="sref">spc52xx_spi_fmatch/a>p 62561/a>pt.6 6   } 6256./a>pt.6 6  p.a href="+code=nprob  class="sref">sprob /a>,= .a href="+code=mpc52xx_spi_fprob  class="sref">spc52xx_spi_fprob /a>p 6256./a>pt.6 6  p.a href="+code=nremov" class="sref">sremov"/a>(= .a href="+code=mpc52xx_spi_fremov" class="sref">spc52xx_spi_fremov"/a>( 6256./a>p}=6256./a>pa href="+code=mpodule_platformfeivers class="sref">spodule_platformfeivers/a>(.a href="+code=moc52xx_spi_foffeivers class="sref">spc52xx_spi_foffeivers/a>,;=6256./a>p


The origiralFLXR software bythersa href="dhttp://sourceforge.net/projects/lx" >LXR ommeunity/a> stis mexperient"alFers/ion8byta href="dmailto:lx"@ineux.no">lx"@ineux.no/a> .
lx".ineux.no kindly hostd tbyta href="dhttp://www.redpill-inepro.no">Redpill Lnepro AS/a> sprovider of Lneuxiconsultingaud soperteions seric s since 1995.