linux/drivers/pwm/pwm-tiecap.c
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   1/*
   2 * ECAP PWM driver
   3 *
   4 * Copyright (C) 2012 Texas Instruments, Inc. - http://www.ti.com/
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2 of the License, or
   9 * (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software
  18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19 */
  20
  21#include <linux/module.h>
  22#include <linux/platform_device.h>
  23#include <linux/io.h>
  24#include <linux/err.h>
  25#include <linux/clk.h>
  26#include <linux/pm_runtime.h>
  27#include <linux/pwm.h>
  28#include <linux/of_device.h>
  29#include <linux/pinctrl/consumer.h>
  30
  31#include "pwm-tipwmss.h"
  32
  33/* ECAP registers and bits definitions */
  34#define CAP1                    0x08
  35#define CAP2                    0x0C
  36#define CAP3                    0x10
  37#define CAP4                    0x14
  38#define ECCTL2                  0x2A
  39#define ECCTL2_APWM_POL_LOW     BIT(10)
  40#define ECCTL2_APWM_MODE        BIT(9)
  41#define ECCTL2_SYNC_SEL_DISA    (BIT(7) | BIT(6))
  42#define ECCTL2_TSCTR_FREERUN    BIT(4)
  43
  44struct ecap_pwm_chip {
  45        struct pwm_chip chip;
  46        unsigned int    clk_rate;
  47        void __iomem    *mmio_base;
  48};
  49
  50static inline struct ecap_pwm_chip *to_ecap_pwm_chip(struct pwm_chip *chip)
  51{
  52        return container_of(chip, struct ecap_pwm_chip, chip);
  53}
  54
  55/*
  56 * period_ns = 10^9 * period_cycles / PWM_CLK_RATE
  57 * duty_ns   = 10^9 * duty_cycles / PWM_CLK_RATE
  58 */
  59static int ecap_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  60                int duty_ns, int period_ns)
  61{
  62        struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
  63        unsigned long long c;
  64        unsigned long period_cycles, duty_cycles;
  65        unsigned int reg_val;
  66
  67        if (period_ns > NSEC_PER_SEC)
  68                return -ERANGE;
  69
  70        c = pc->clk_rate;
  71        c = c * period_ns;
  72        do_div(c, NSEC_PER_SEC);
  73        period_cycles = (unsigned long)c;
  74
  75        if (period_cycles < 1) {
  76                period_cycles = 1;
  77                duty_cycles = 1;
  78        } else {
  79                c = pc->clk_rate;
  80                c = c * duty_ns;
  81                do_div(c, NSEC_PER_SEC);
  82                duty_cycles = (unsigned long)c;
  83        }
  84
  85        pm_runtime_get_sync(pc->chip.dev);
  86
  87        reg_val = readw(pc->mmio_base + ECCTL2);
  88
  89        /* Configure APWM mode & disable sync option */
  90        reg_val |= ECCTL2_APWM_MODE | ECCTL2_SYNC_SEL_DISA;
  91
  92        writew(reg_val, pc->mmio_base + ECCTL2);
  93
  94        if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
  95                /* Update active registers if not running */
  96                writel(duty_cycles, pc->mmio_base + CAP2);
  97                writel(period_cycles, pc->mmio_base + CAP1);
  98        } else {
  99                /*
 100                 * Update shadow registers to configure period and
 101                 * compare values. This helps current PWM period to
 102                 * complete on reconfiguring
 103                 */
 104                writel(duty_cycles, pc->mmio_base + CAP4);
 105                writel(period_cycles, pc->mmio_base + CAP3);
 106        }
 107
 108        if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
 109                reg_val = readw(pc->mmio_base + ECCTL2);
 110                /* Disable APWM mode to put APWM output Low */
 111                reg_val &= ~ECCTL2_APWM_MODE;
 112                writew(reg_val, pc->mmio_base + ECCTL2);
 113        }
 114
 115        pm_runtime_put_sync(pc->chip.dev);
 116        return 0;
 117}
 118
 119static int ecap_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
 120                enum pwm_polarity polarity)
 121{
 122        struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
 123        unsigned short reg_val;
 124
 125        pm_runtime_get_sync(pc->chip.dev);
 126        reg_val = readw(pc->mmio_base + ECCTL2);
 127        if (polarity == PWM_POLARITY_INVERSED)
 128                /* Duty cycle defines LOW period of PWM */
 129                reg_val |= ECCTL2_APWM_POL_LOW;
 130        else
 131                /* Duty cycle defines HIGH period of PWM */
 132                reg_val &= ~ECCTL2_APWM_POL_LOW;
 133
 134        writew(reg_val, pc->mmio_base + ECCTL2);
 135        pm_runtime_put_sync(pc->chip.dev);
 136        return 0;
 137}
 138
 139static int ecap_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 140{
 141        struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
 142        unsigned int reg_val;
 143
 144        /* Leave clock enabled on enabling PWM */
 145        pm_runtime_get_sync(pc->chip.dev);
 146
 147        /*
 148         * Enable 'Free run Time stamp counter mode' to start counter
 149         * and  'APWM mode' to enable APWM output
 150         */
 151        reg_val = readw(pc->mmio_base + ECCTL2);
 152        reg_val |= ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE;
 153        writew(reg_val, pc->mmio_base + ECCTL2);
 154        return 0;
 155}
 156
 157static void ecap_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 158{
 159        struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
 160        unsigned int reg_val;
 161
 162        /*
 163         * Disable 'Free run Time stamp counter mode' to stop counter
 164         * and 'APWM mode' to put APWM output to low
 165         */
 166        reg_val = readw(pc->mmio_base + ECCTL2);
 167        reg_val &= ~(ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE);
 168        writew(reg_val, pc->mmio_base + ECCTL2);
 169
 170        /* Disable clock on PWM disable */
 171        pm_runtime_put_sync(pc->chip.dev);
 172}
 173
 174static void ecap_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
 175{
 176        if (test_bit(PWMF_ENABLED, &pwm->flags)) {
 177                dev_warn(chip->dev, "Removing PWM device without disabling\n");
 178                pm_runtime_put_sync(chip->dev);
 179        }
 180}
 181
 182static const struct pwm_ops ecap_pwm_ops = {
 183        .free           = ecap_pwm_free,
 184        .config         = ecap_pwm_config,
 185        .set_polarity   = ecap_pwm_set_polarity,
 186        .enable         = ecap_pwm_enable,
 187        .disable        = ecap_pwm_disable,
 188        .owner          = THIS_MODULE,
 189};
 190
 191static const struct of_device_id ecap_of_match[] = {
 192        { .compatible   = "ti,am33xx-ecap" },
 193        {},
 194};
 195MODULE_DEVICE_TABLE(of, ecap_of_match);
 196
 197static int ecap_pwm_probe(struct platform_device *pdev)
 198{
 199        int ret;
 200        struct resource *r;
 201        struct clk *clk;
 202        struct ecap_pwm_chip *pc;
 203        u16 status;
 204        struct pinctrl *pinctrl;
 205
 206        pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
 207        if (IS_ERR(pinctrl))
 208                dev_warn(&pdev->dev, "unable to select pin group\n");
 209
 210        pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
 211        if (!pc) {
 212                dev_err(&pdev->dev, "failed to allocate memory\n");
 213                return -ENOMEM;
 214        }
 215
 216        clk = devm_clk_get(&pdev->dev, "fck");
 217        if (IS_ERR(clk)) {
 218                dev_err(&pdev->dev, "failed to get clock\n");
 219                return PTR_ERR(clk);
 220        }
 221
 222        pc->clk_rate = clk_get_rate(clk);
 223        if (!pc->clk_rate) {
 224                dev_err(&pdev->dev, "failed to get clock rate\n");
 225                return -EINVAL;
 226        }
 227
 228        pc->chip.dev = &pdev->dev;
 229        pc->chip.ops = &ecap_pwm_ops;
 230        pc->chip.of_xlate = of_pwm_xlate_with_flags;
 231        pc->chip.of_pwm_n_cells = 3;
 232        pc->chip.base = -1;
 233        pc->chip.npwm = 1;
 234
 235        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 236        if (!r) {
 237                dev_err(&pdev->dev, "no memory resource defined\n");
 238                return -ENODEV;
 239        }
 240
 241        pc->mmio_base = devm_request_and_ioremap(&pdev->dev, r);
 242        if (!pc->mmio_base)
 243                return -EADDRNOTAVAIL;
 244
 245        ret = pwmchip_add(&pc->chip);
 246        if (ret < 0) {
 247                dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
 248                return ret;
 249        }
 250
 251        pm_runtime_enable(&pdev->dev);
 252        pm_runtime_get_sync(&pdev->dev);
 253
 254        status = pwmss_submodule_state_change(pdev->dev.parent,
 255                        PWMSS_ECAPCLK_EN);
 256        if (!(status & PWMSS_ECAPCLK_EN_ACK)) {
 257                dev_err(&pdev->dev, "PWMSS config space clock enable failed\n");
 258                ret = -EINVAL;
 259                goto pwmss_clk_failure;
 260        }
 261
 262        pm_runtime_put_sync(&pdev->dev);
 263
 264        platform_set_drvdata(pdev, pc);
 265        return 0;
 266
 267pwmss_clk_failure:
 268        pm_runtime_put_sync(&pdev->dev);
 269        pm_runtime_disable(&pdev->dev);
 270        pwmchip_remove(&pc->chip);
 271        return ret;
 272}
 273
 274static int ecap_pwm_remove(struct platform_device *pdev)
 275{
 276        struct ecap_pwm_chip *pc = platform_get_drvdata(pdev);
 277
 278        pm_runtime_get_sync(&pdev->dev);
 279        /*
 280         * Due to hardware misbehaviour, acknowledge of the stop_req
 281         * is missing. Hence checking of the status bit skipped.
 282         */
 283        pwmss_submodule_state_change(pdev->dev.parent, PWMSS_ECAPCLK_STOP_REQ);
 284        pm_runtime_put_sync(&pdev->dev);
 285
 286        pm_runtime_put_sync(&pdev->dev);
 287        pm_runtime_disable(&pdev->dev);
 288        return pwmchip_remove(&pc->chip);
 289}
 290
 291static struct platform_driver ecap_pwm_driver = {
 292        .driver = {
 293                .name   = "ecap",
 294                .owner  = THIS_MODULE,
 295                .of_match_table = ecap_of_match,
 296        },
 297        .probe = ecap_pwm_probe,
 298        .remove = ecap_pwm_remove,
 299};
 300
 301module_platform_driver(ecap_pwm_driver);
 302
 303MODULE_DESCRIPTION("ECAP PWM driver");
 304MODULE_AUTHOR("Texas Instruments");
 305MODULE_LICENSE("GPL");
 306
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