linux/drivers/pinctrl/pinctrl-tegra.c
<<
>>
Prefs
   1/*
   2 * Driver for the NVIDIA Tegra pinmux
   3 *
   4 * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
   5 *
   6 * Derived from code:
   7 * Copyright (C) 2010 Google, Inc.
   8 * Copyright (C) 2010 NVIDIA Corporation
   9 * Copyright (C) 2009-2011 ST-Ericsson AB
  10 *
  11 * This program is free software; you can redistribute it and/or modify it
  12 * under the terms and conditions of the GNU General Public License,
  13 * version 2, as published by the Free Software Foundation.
  14 *
  15 * This program is distributed in the hope it will be useful, but WITHOUT
  16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  18 * more details.
  19 */
  20
  21#include <linux/err.h>
  22#include <linux/init.h>
  23#include <linux/io.h>
  24#include <linux/module.h>
  25#include <linux/of.h>
  26#include <linux/platform_device.h>
  27#include <linux/pinctrl/machine.h>
  28#include <linux/pinctrl/pinctrl.h>
  29#include <linux/pinctrl/pinmux.h>
  30#include <linux/pinctrl/pinconf.h>
  31#include <linux/slab.h>
  32
  33#include "core.h"
  34#include "pinctrl-tegra.h"
  35
  36struct tegra_pmx {
  37        struct device *dev;
  38        struct pinctrl_dev *pctl;
  39
  40        const struct tegra_pinctrl_soc_data *soc;
  41
  42        int nbanks;
  43        void __iomem **regs;
  44};
  45
  46static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
  47{
  48        return readl(pmx->regs[bank] + reg);
  49}
  50
  51static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
  52{
  53        writel(val, pmx->regs[bank] + reg);
  54}
  55
  56static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
  57{
  58        struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  59
  60        return pmx->soc->ngroups;
  61}
  62
  63static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
  64                                                unsigned group)
  65{
  66        struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  67
  68        return pmx->soc->groups[group].name;
  69}
  70
  71static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
  72                                        unsigned group,
  73                                        const unsigned **pins,
  74                                        unsigned *num_pins)
  75{
  76        struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  77
  78        *pins = pmx->soc->groups[group].pins;
  79        *num_pins = pmx->soc->groups[group].npins;
  80
  81        return 0;
  82}
  83
  84#ifdef CONFIG_DEBUG_FS
  85static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
  86                                       struct seq_file *s,
  87                                       unsigned offset)
  88{
  89        seq_printf(s, " %s", dev_name(pctldev->dev));
  90}
  91#endif
  92
  93static int reserve_map(struct device *dev, struct pinctrl_map **map,
  94                       unsigned *reserved_maps, unsigned *num_maps,
  95                       unsigned reserve)
  96{
  97        unsigned old_num = *reserved_maps;
  98        unsigned new_num = *num_maps + reserve;
  99        struct pinctrl_map *new_map;
 100
 101        if (old_num >= new_num)
 102                return 0;
 103
 104        new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
 105        if (!new_map) {
 106                dev_err(dev, "krealloc(map) failed\n");
 107                return -ENOMEM;
 108        }
 109
 110        memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
 111
 112        *map = new_map;
 113        *reserved_maps = new_num;
 114
 115        return 0;
 116}
 117
 118static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
 119                       unsigned *num_maps, const char *group,
 120                       const char *function)
 121{
 122        if (WARN_ON(*num_maps == *reserved_maps))
 123                return -ENOSPC;
 124
 125        (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
 126        (*map)[*num_maps].data.mux.group = group;
 127        (*map)[*num_maps].data.mux.function = function;
 128        (*num_maps)++;
 129
 130        return 0;
 131}
 132
 133static int add_map_configs(struct device *dev, struct pinctrl_map **map,
 134                           unsigned *reserved_maps, unsigned *num_maps,
 135                           const char *group, unsigned long *configs,
 136                           unsigned num_configs)
 137{
 138        unsigned long *dup_configs;
 139
 140        if (WARN_ON(*num_maps == *reserved_maps))
 141                return -ENOSPC;
 142
 143        dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
 144                              GFP_KERNEL);
 145        if (!dup_configs) {
 146                dev_err(dev, "kmemdup(configs) failed\n");
 147                return -ENOMEM;
 148        }
 149
 150        (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
 151        (*map)[*num_maps].data.configs.group_or_pin = group;
 152        (*map)[*num_maps].data.configs.configs = dup_configs;
 153        (*map)[*num_maps].data.configs.num_configs = num_configs;
 154        (*num_maps)++;
 155
 156        return 0;
 157}
 158
 159static int add_config(struct device *dev, unsigned long **configs,
 160                      unsigned *num_configs, unsigned long config)
 161{
 162        unsigned old_num = *num_configs;
 163        unsigned new_num = old_num + 1;
 164        unsigned long *new_configs;
 165
 166        new_configs = krealloc(*configs, sizeof(*new_configs) * new_num,
 167                               GFP_KERNEL);
 168        if (!new_configs) {
 169                dev_err(dev, "krealloc(configs) failed\n");
 170                return -ENOMEM;
 171        }
 172
 173        new_configs[old_num] = config;
 174
 175        *configs = new_configs;
 176        *num_configs = new_num;
 177
 178        return 0;
 179}
 180
 181static void tegra_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
 182                                      struct pinctrl_map *map,
 183                                      unsigned num_maps)
 184{
 185        int i;
 186
 187        for (i = 0; i < num_maps; i++)
 188                if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
 189                        kfree(map[i].data.configs.configs);
 190
 191        kfree(map);
 192}
 193
 194static const struct cfg_param {
 195        const char *property;
 196        enum tegra_pinconf_param param;
 197} cfg_params[] = {
 198        {"nvidia,pull",                 TEGRA_PINCONF_PARAM_PULL},
 199        {"nvidia,tristate",             TEGRA_PINCONF_PARAM_TRISTATE},
 200        {"nvidia,enable-input",         TEGRA_PINCONF_PARAM_ENABLE_INPUT},
 201        {"nvidia,open-drain",           TEGRA_PINCONF_PARAM_OPEN_DRAIN},
 202        {"nvidia,lock",                 TEGRA_PINCONF_PARAM_LOCK},
 203        {"nvidia,io-reset",             TEGRA_PINCONF_PARAM_IORESET},
 204        {"nvidia,high-speed-mode",      TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
 205        {"nvidia,schmitt",              TEGRA_PINCONF_PARAM_SCHMITT},
 206        {"nvidia,low-power-mode",       TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
 207        {"nvidia,pull-down-strength",   TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
 208        {"nvidia,pull-up-strength",     TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
 209        {"nvidia,slew-rate-falling",    TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
 210        {"nvidia,slew-rate-rising",     TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
 211};
 212
 213static int tegra_pinctrl_dt_subnode_to_map(struct device *dev,
 214                                           struct device_node *np,
 215                                           struct pinctrl_map **map,
 216                                           unsigned *reserved_maps,
 217                                           unsigned *num_maps)
 218{
 219        int ret, i;
 220        const char *function;
 221        u32 val;
 222        unsigned long config;
 223        unsigned long *configs = NULL;
 224        unsigned num_configs = 0;
 225        unsigned reserve;
 226        struct property *prop;
 227        const char *group;
 228
 229        ret = of_property_read_string(np, "nvidia,function", &function);
 230        if (ret < 0) {
 231                /* EINVAL=missing, which is fine since it's optional */
 232                if (ret != -EINVAL)
 233                        dev_err(dev,
 234                                "could not parse property nvidia,function\n");
 235                function = NULL;
 236        }
 237
 238        for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 239                ret = of_property_read_u32(np, cfg_params[i].property, &val);
 240                if (!ret) {
 241                        config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
 242                        ret = add_config(dev, &configs, &num_configs, config);
 243                        if (ret < 0)
 244                                goto exit;
 245                /* EINVAL=missing, which is fine since it's optional */
 246                } else if (ret != -EINVAL) {
 247                        dev_err(dev, "could not parse property %s\n",
 248                                cfg_params[i].property);
 249                }
 250        }
 251
 252        reserve = 0;
 253        if (function != NULL)
 254                reserve++;
 255        if (num_configs)
 256                reserve++;
 257        ret = of_property_count_strings(np, "nvidia,pins");
 258        if (ret < 0) {
 259                dev_err(dev, "could not parse property nvidia,pins\n");
 260                goto exit;
 261        }
 262        reserve *= ret;
 263
 264        ret = reserve_map(dev, map, reserved_maps, num_maps, reserve);
 265        if (ret < 0)
 266                goto exit;
 267
 268        of_property_for_each_string(np, "nvidia,pins", prop, group) {
 269                if (function) {
 270                        ret = add_map_mux(map, reserved_maps, num_maps,
 271                                          group, function);
 272                        if (ret < 0)
 273                                goto exit;
 274                }
 275
 276                if (num_configs) {
 277                        ret = add_map_configs(dev, map, reserved_maps,
 278                                              num_maps, group, configs,
 279                                              num_configs);
 280                        if (ret < 0)
 281                                goto exit;
 282                }
 283        }
 284
 285        ret = 0;
 286
 287exit:
 288        kfree(configs);
 289        return ret;
 290}
 291
 292static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
 293                                        struct device_node *np_config,
 294                                        struct pinctrl_map **map,
 295                                        unsigned *num_maps)
 296{
 297        unsigned reserved_maps;
 298        struct device_node *np;
 299        int ret;
 300
 301        reserved_maps = 0;
 302        *map = NULL;
 303        *num_maps = 0;
 304
 305        for_each_child_of_node(np_config, np) {
 306                ret = tegra_pinctrl_dt_subnode_to_map(pctldev->dev, np, map,
 307                                                      &reserved_maps, num_maps);
 308                if (ret < 0) {
 309                        tegra_pinctrl_dt_free_map(pctldev, *map, *num_maps);
 310                        return ret;
 311                }
 312        }
 313
 314        return 0;
 315}
 316
 317static struct pinctrl_ops tegra_pinctrl_ops = {
 318        .get_groups_count = tegra_pinctrl_get_groups_count,
 319        .get_group_name = tegra_pinctrl_get_group_name,
 320        .get_group_pins = tegra_pinctrl_get_group_pins,
 321#ifdef CONFIG_DEBUG_FS
 322        .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
 323#endif
 324        .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
 325        .dt_free_map = tegra_pinctrl_dt_free_map,
 326};
 327
 328static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
 329{
 330        struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 331
 332        return pmx->soc->nfunctions;
 333}
 334
 335static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
 336                                               unsigned function)
 337{
 338        struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 339
 340        return pmx->soc->functions[function].name;
 341}
 342
 343static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
 344                                         unsigned function,
 345                                         const char * const **groups,
 346                                         unsigned * const num_groups)
 347{
 348        struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 349
 350        *groups = pmx->soc->functions[function].groups;
 351        *num_groups = pmx->soc->functions[function].ngroups;
 352
 353        return 0;
 354}
 355
 356static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
 357                               unsigned group)
 358{
 359        struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 360        const struct tegra_pingroup *g;
 361        int i;
 362        u32 val;
 363
 364        g = &pmx->soc->groups[group];
 365
 366        if (WARN_ON(g->mux_reg < 0))
 367                return -EINVAL;
 368
 369        for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
 370                if (g->funcs[i] == function)
 371                        break;
 372        }
 373        if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
 374                return -EINVAL;
 375
 376        val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
 377        val &= ~(0x3 << g->mux_bit);
 378        val |= i << g->mux_bit;
 379        pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
 380
 381        return 0;
 382}
 383
 384static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
 385                                  unsigned function, unsigned group)
 386{
 387        struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 388        const struct tegra_pingroup *g;
 389        u32 val;
 390
 391        g = &pmx->soc->groups[group];
 392
 393        if (WARN_ON(g->mux_reg < 0))
 394                return;
 395
 396        val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
 397        val &= ~(0x3 << g->mux_bit);
 398        val |= g->func_safe << g->mux_bit;
 399        pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
 400}
 401
 402static struct pinmux_ops tegra_pinmux_ops = {
 403        .get_functions_count = tegra_pinctrl_get_funcs_count,
 404        .get_function_name = tegra_pinctrl_get_func_name,
 405        .get_function_groups = tegra_pinctrl_get_func_groups,
 406        .enable = tegra_pinctrl_enable,
 407        .disable = tegra_pinctrl_disable,
 408};
 409
 410static int tegra_pinconf_reg(struct tegra_pmx *pmx,
 411                             const struct tegra_pingroup *g,
 412                             enum tegra_pinconf_param param,
 413                             bool report_err,
 414                             s8 *bank, s16 *reg, s8 *bit, s8 *width)
 415{
 416        switch (param) {
 417        case TEGRA_PINCONF_PARAM_PULL:
 418                *bank = g->pupd_bank;
 419                *reg = g->pupd_reg;
 420                *bit = g->pupd_bit;
 421                *width = 2;
 422                break;
 423        case TEGRA_PINCONF_PARAM_TRISTATE:
 424                *bank = g->tri_bank;
 425                *reg = g->tri_reg;
 426                *bit = g->tri_bit;
 427                *width = 1;
 428                break;
 429        case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
 430                *bank = g->einput_bank;
 431                *reg = g->einput_reg;
 432                *bit = g->einput_bit;
 433                *width = 1;
 434                break;
 435        case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
 436                *bank = g->odrain_bank;
 437                *reg = g->odrain_reg;
 438                *bit = g->odrain_bit;
 439                *width = 1;
 440                break;
 441        case TEGRA_PINCONF_PARAM_LOCK:
 442                *bank = g->lock_bank;
 443                *reg = g->lock_reg;
 444                *bit = g->lock_bit;
 445                *width = 1;
 446                break;
 447        case TEGRA_PINCONF_PARAM_IORESET:
 448                *bank = g->ioreset_bank;
 449                *reg = g->ioreset_reg;
 450                *bit = g->ioreset_bit;
 451                *width = 1;
 452                break;
 453        case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
 454                *bank = g->drv_bank;
 455                *reg = g->drv_reg;
 456                *bit = g->hsm_bit;
 457                *width = 1;
 458                break;
 459        case TEGRA_PINCONF_PARAM_SCHMITT:
 460                *bank = g->drv_bank;
 461                *reg = g->drv_reg;
 462                *bit = g->schmitt_bit;
 463                *width = 1;
 464                break;
 465        case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
 466                *bank = g->drv_bank;
 467                *reg = g->drv_reg;
 468                *bit = g->lpmd_bit;
 469                *width = 2;
 470                break;
 471        case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
 472                *bank = g->drv_bank;
 473                *reg = g->drv_reg;
 474                *bit = g->drvdn_bit;
 475                *width = g->drvdn_width;
 476                break;
 477        case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
 478                *bank = g->drv_bank;
 479                *reg = g->drv_reg;
 480                *bit = g->drvup_bit;
 481                *width = g->drvup_width;
 482                break;
 483        case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
 484                *bank = g->drv_bank;
 485                *reg = g->drv_reg;
 486                *bit = g->slwf_bit;
 487                *width = g->slwf_width;
 488                break;
 489        case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
 490                *bank = g->drv_bank;
 491                *reg = g->drv_reg;
 492                *bit = g->slwr_bit;
 493                *width = g->slwr_width;
 494                break;
 495        default:
 496                dev_err(pmx->dev, "Invalid config param %04x\n", param);
 497                return -ENOTSUPP;
 498        }
 499
 500        if (*reg < 0) {
 501                if (report_err)
 502                        dev_err(pmx->dev,
 503                                "Config param %04x not supported on group %s\n",
 504                                param, g->name);
 505                return -ENOTSUPP;
 506        }
 507
 508        return 0;
 509}
 510
 511static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
 512                             unsigned pin, unsigned long *config)
 513{
 514        dev_err(pctldev->dev, "pin_config_get op not supported\n");
 515        return -ENOTSUPP;
 516}
 517
 518static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
 519                             unsigned pin, unsigned long config)
 520{
 521        dev_err(pctldev->dev, "pin_config_set op not supported\n");
 522        return -ENOTSUPP;
 523}
 524
 525static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
 526                                   unsigned group, unsigned long *config)
 527{
 528        struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 529        enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
 530        u16 arg;
 531        const struct tegra_pingroup *g;
 532        int ret;
 533        s8 bank, bit, width;
 534        s16 reg;
 535        u32 val, mask;
 536
 537        g = &pmx->soc->groups[group];
 538
 539        ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
 540                                &width);
 541        if (ret < 0)
 542                return ret;
 543
 544        val = pmx_readl(pmx, bank, reg);
 545        mask = (1 << width) - 1;
 546        arg = (val >> bit) & mask;
 547
 548        *config = TEGRA_PINCONF_PACK(param, arg);
 549
 550        return 0;
 551}
 552
 553static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
 554                                   unsigned group, unsigned long config)
 555{
 556        struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 557        enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
 558        u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
 559        const struct tegra_pingroup *g;
 560        int ret;
 561        s8 bank, bit, width;
 562        s16 reg;
 563        u32 val, mask;
 564
 565        g = &pmx->soc->groups[group];
 566
 567        ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
 568                                &width);
 569        if (ret < 0)
 570                return ret;
 571
 572        val = pmx_readl(pmx, bank, reg);
 573
 574        /* LOCK can't be cleared */
 575        if (param == TEGRA_PINCONF_PARAM_LOCK) {
 576                if ((val & BIT(bit)) && !arg) {
 577                        dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
 578                        return -EINVAL;
 579                }
 580        }
 581
 582        /* Special-case Boolean values; allow any non-zero as true */
 583        if (width == 1)
 584                arg = !!arg;
 585
 586        /* Range-check user-supplied value */
 587        mask = (1 << width) - 1;
 588        if (arg & ~mask) {
 589                dev_err(pctldev->dev,
 590                        "config %lx: %x too big for %d bit register\n",
 591                        config, arg, width);
 592                return -EINVAL;
 593        }
 594
 595        /* Update register */
 596        val &= ~(mask << bit);
 597        val |= arg << bit;
 598        pmx_writel(pmx, val, bank, reg);
 599
 600        return 0;
 601}
 602
 603#ifdef CONFIG_DEBUG_FS
 604static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 605                                   struct seq_file *s, unsigned offset)
 606{
 607}
 608
 609static const char *strip_prefix(const char *s)
 610{
 611        const char *comma = strchr(s, ',');
 612        if (!comma)
 613                return s;
 614
 615        return comma + 1;
 616}
 617
 618static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 619                                         struct seq_file *s, unsigned group)
 620{
 621        struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 622        const struct tegra_pingroup *g;
 623        int i, ret;
 624        s8 bank, bit, width;
 625        s16 reg;
 626        u32 val;
 627
 628        g = &pmx->soc->groups[group];
 629
 630        for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 631                ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
 632                                        &bank, &reg, &bit, &width);
 633                if (ret < 0)
 634                        continue;
 635
 636                val = pmx_readl(pmx, bank, reg);
 637                val >>= bit;
 638                val &= (1 << width) - 1;
 639
 640                seq_printf(s, "\n\t%s=%u",
 641                           strip_prefix(cfg_params[i].property), val);
 642        }
 643}
 644
 645static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
 646                                          struct seq_file *s,
 647                                          unsigned long config)
 648{
 649        enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
 650        u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
 651        const char *pname = "unknown";
 652        int i;
 653
 654        for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 655                if (cfg_params[i].param == param) {
 656                        pname = cfg_params[i].property;
 657                        break;
 658                }
 659        }
 660
 661        seq_printf(s, "%s=%d", strip_prefix(pname), arg);
 662}
 663#endif
 664
 665static struct pinconf_ops tegra_pinconf_ops = {
 666        .pin_config_get = tegra_pinconf_get,
 667        .pin_config_set = tegra_pinconf_set,
 668        .pin_config_group_get = tegra_pinconf_group_get,
 669        .pin_config_group_set = tegra_pinconf_group_set,
 670#ifdef CONFIG_DEBUG_FS
 671        .pin_config_dbg_show = tegra_pinconf_dbg_show,
 672        .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
 673        .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
 674#endif
 675};
 676
 677static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
 678        .name = "Tegra GPIOs",
 679        .id = 0,
 680        .base = 0,
 681};
 682
 683static struct pinctrl_desc tegra_pinctrl_desc = {
 684        .pctlops = &tegra_pinctrl_ops,
 685        .pmxops = &tegra_pinmux_ops,
 686        .confops = &tegra_pinconf_ops,
 687        .owner = THIS_MODULE,
 688};
 689
 690int tegra_pinctrl_probe(struct platform_device *pdev,
 691                        const struct tegra_pinctrl_soc_data *soc_data)
 692{
 693        struct tegra_pmx *pmx;
 694        struct resource *res;
 695        int i;
 696
 697        pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
 698        if (!pmx) {
 699                dev_err(&pdev->dev, "Can't alloc tegra_pmx\n");
 700                return -ENOMEM;
 701        }
 702        pmx->dev = &pdev->dev;
 703        pmx->soc = soc_data;
 704
 705        tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
 706        tegra_pinctrl_desc.name = dev_name(&pdev->dev);
 707        tegra_pinctrl_desc.pins = pmx->soc->pins;
 708        tegra_pinctrl_desc.npins = pmx->soc->npins;
 709
 710        for (i = 0; ; i++) {
 711                res = platform_get_resource(pdev, IORESOURCE_MEM, i);
 712                if (!res)
 713                        break;
 714        }
 715        pmx->nbanks = i;
 716
 717        pmx->regs = devm_kzalloc(&pdev->dev, pmx->nbanks * sizeof(*pmx->regs),
 718                                 GFP_KERNEL);
 719        if (!pmx->regs) {
 720                dev_err(&pdev->dev, "Can't alloc regs pointer\n");
 721                return -ENODEV;
 722        }
 723
 724        for (i = 0; i < pmx->nbanks; i++) {
 725                res = platform_get_resource(pdev, IORESOURCE_MEM, i);
 726                if (!res) {
 727                        dev_err(&pdev->dev, "Missing MEM resource\n");
 728                        return -ENODEV;
 729                }
 730
 731                if (!devm_request_mem_region(&pdev->dev, res->start,
 732                                            resource_size(res),
 733                                            dev_name(&pdev->dev))) {
 734                        dev_err(&pdev->dev,
 735                                "Couldn't request MEM resource %d\n", i);
 736                        return -ENODEV;
 737                }
 738
 739                pmx->regs[i] = devm_ioremap(&pdev->dev, res->start,
 740                                            resource_size(res));
 741                if (!pmx->regs[i]) {
 742                        dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i);
 743                        return -ENODEV;
 744                }
 745        }
 746
 747        pmx->pctl = pinctrl_register(&tegra_pinctrl_desc, &pdev->dev, pmx);
 748        if (!pmx->pctl) {
 749                dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 750                return -ENODEV;
 751        }
 752
 753        pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
 754
 755        platform_set_drvdata(pdev, pmx);
 756
 757        dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
 758
 759        return 0;
 760}
 761EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);
 762
 763int tegra_pinctrl_remove(struct platform_device *pdev)
 764{
 765        struct tegra_pmx *pmx = platform_get_drvdata(pdev);
 766
 767        pinctrl_unregister(pmx->pctl);
 768
 769        return 0;
 770}
 771EXPORT_SYMBOL_GPL(tegra_pinctrl_remove);
 772
lxr.linux.no kindly hosted by Redpill Linpro AS, provider of Linux consulting and operations services since 1995.