linux/drivers/pinctrl/pinctrl-samsung.h
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   1/*
   2 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
   3 *
   4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5 *              http://www.samsung.com
   6 * Copyright (c) 2012 Linaro Ltd
   7 *              http://www.linaro.org
   8 *
   9 * Author: Thomas Abraham <thomas.ab@samsung.com>
  10 *
  11 * This program is free software; you can redistribute it and/or modify
  12 * it under the terms of the GNU General Public License as published by
  13 * the Free Software Foundation; either version 2 of the License, or
  14 * (at your option) any later version.
  15 */
  16
  17#ifndef __PINCTRL_SAMSUNG_H
  18#define __PINCTRL_SAMSUNG_H
  19
  20#include <linux/pinctrl/pinctrl.h>
  21#include <linux/pinctrl/pinmux.h>
  22#include <linux/pinctrl/pinconf.h>
  23#include <linux/pinctrl/consumer.h>
  24#include <linux/pinctrl/machine.h>
  25
  26#include <linux/gpio.h>
  27
  28/* register offsets within a pin bank */
  29#define DAT_REG         0x4
  30#define PUD_REG         0x8
  31#define DRV_REG         0xC
  32#define CONPDN_REG      0x10
  33#define PUDPDN_REG      0x14
  34
  35/* pinmux function number for pin as gpio output line */
  36#define FUNC_OUTPUT     0x1
  37
  38/**
  39 * enum pincfg_type - possible pin configuration types supported.
  40 * @PINCFG_TYPE_PUD: Pull up/down configuration.
  41 * @PINCFG_TYPE_DRV: Drive strength configuration.
  42 * @PINCFG_TYPE_CON_PDN: Pin function in power down mode.
  43 * @PINCFG_TYPE_PUD_PDN: Pull up/down configuration in power down mode.
  44 */
  45enum pincfg_type {
  46        PINCFG_TYPE_PUD,
  47        PINCFG_TYPE_DRV,
  48        PINCFG_TYPE_CON_PDN,
  49        PINCFG_TYPE_PUD_PDN,
  50};
  51
  52/*
  53 * pin configuration (pull up/down and drive strength) type and its value are
  54 * packed together into a 16-bits. The upper 8-bits represent the configuration
  55 * type and the lower 8-bits hold the value of the configuration type.
  56 */
  57#define PINCFG_TYPE_MASK                0xFF
  58#define PINCFG_VALUE_SHIFT              8
  59#define PINCFG_VALUE_MASK               (0xFF << PINCFG_VALUE_SHIFT)
  60#define PINCFG_PACK(type, value)        (((value) << PINCFG_VALUE_SHIFT) | type)
  61#define PINCFG_UNPACK_TYPE(cfg)         ((cfg) & PINCFG_TYPE_MASK)
  62#define PINCFG_UNPACK_VALUE(cfg)        (((cfg) & PINCFG_VALUE_MASK) >> \
  63                                                PINCFG_VALUE_SHIFT)
  64/**
  65 * enum eint_type - possible external interrupt types.
  66 * @EINT_TYPE_NONE: bank does not support external interrupts
  67 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
  68 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
  69 * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
  70 *
  71 * Samsung GPIO controller groups all the available pins into banks. The pins
  72 * in a pin bank can support external gpio interrupts or external wakeup
  73 * interrupts or no interrupts at all. From a software perspective, the only
  74 * difference between external gpio and external wakeup interrupts is that
  75 * the wakeup interrupts can additionally wakeup the system if it is in
  76 * suspended state.
  77 */
  78enum eint_type {
  79        EINT_TYPE_NONE,
  80        EINT_TYPE_GPIO,
  81        EINT_TYPE_WKUP,
  82        EINT_TYPE_WKUP_MUX,
  83};
  84
  85/* maximum length of a pin in pin descriptor (example: "gpa0-0") */
  86#define PIN_NAME_LENGTH 10
  87
  88#define PIN_GROUP(n, p, f)                              \
  89        {                                               \
  90                .name           = n,                    \
  91                .pins           = p,                    \
  92                .num_pins       = ARRAY_SIZE(p),        \
  93                .func           = f                     \
  94        }
  95
  96#define PMX_FUNC(n, g)                                  \
  97        {                                               \
  98                .name           = n,                    \
  99                .groups         = g,                    \
 100                .num_groups     = ARRAY_SIZE(g),        \
 101        }
 102
 103struct samsung_pinctrl_drv_data;
 104
 105/**
 106 * struct samsung_pin_bank: represent a controller pin-bank.
 107 * @pctl_offset: starting offset of the pin-bank registers.
 108 * @pin_base: starting pin number of the bank.
 109 * @nr_pins: number of pins included in this bank.
 110 * @func_width: width of the function selector bit field.
 111 * @pud_width: width of the pin pull up/down selector bit field.
 112 * @drv_width: width of the pin driver strength selector bit field.
 113 * @conpdn_width: width of the sleep mode function selector bin field.
 114 * @pudpdn_width: width of the sleep mode pull up/down selector bit field.
 115 * @eint_type: type of the external interrupt supported by the bank.
 116 * @name: name to be prefixed for each pin in this pin bank.
 117 * @of_node: OF node of the bank.
 118 * @drvdata: link to controller driver data
 119 * @irq_domain: IRQ domain of the bank.
 120 * @gpio_chip: GPIO chip of the bank.
 121 * @grange: linux gpio pin range supported by this bank.
 122 */
 123struct samsung_pin_bank {
 124        u32             pctl_offset;
 125        u32             pin_base;
 126        u8              nr_pins;
 127        u8              func_width;
 128        u8              pud_width;
 129        u8              drv_width;
 130        u8              conpdn_width;
 131        u8              pudpdn_width;
 132        enum eint_type  eint_type;
 133        u32             eint_offset;
 134        char            *name;
 135        struct device_node *of_node;
 136        struct samsung_pinctrl_drv_data *drvdata;
 137        struct irq_domain *irq_domain;
 138        struct gpio_chip gpio_chip;
 139        struct pinctrl_gpio_range grange;
 140};
 141
 142/**
 143 * struct samsung_pin_ctrl: represent a pin controller.
 144 * @pin_banks: list of pin banks included in this controller.
 145 * @nr_banks: number of pin banks.
 146 * @base: starting system wide pin number.
 147 * @nr_pins: number of pins supported by the controller.
 148 * @geint_con: offset of the ext-gpio controller registers.
 149 * @geint_mask: offset of the ext-gpio interrupt mask registers.
 150 * @geint_pend: offset of the ext-gpio interrupt pending registers.
 151 * @weint_con: offset of the ext-wakeup controller registers.
 152 * @weint_mask: offset of the ext-wakeup interrupt mask registers.
 153 * @weint_pend: offset of the ext-wakeup interrupt pending registers.
 154 * @svc: offset of the interrupt service register.
 155 * @eint_gpio_init: platform specific callback to setup the external gpio
 156 *      interrupts for the controller.
 157 * @eint_wkup_init: platform specific callback to setup the external wakeup
 158 *      interrupts for the controller.
 159 * @label: for debug information.
 160 */
 161struct samsung_pin_ctrl {
 162        struct samsung_pin_bank *pin_banks;
 163        u32             nr_banks;
 164
 165        u32             base;
 166        u32             nr_pins;
 167
 168        u32             geint_con;
 169        u32             geint_mask;
 170        u32             geint_pend;
 171
 172        u32             weint_con;
 173        u32             weint_mask;
 174        u32             weint_pend;
 175
 176        u32             svc;
 177
 178        int             (*eint_gpio_init)(struct samsung_pinctrl_drv_data *);
 179        int             (*eint_wkup_init)(struct samsung_pinctrl_drv_data *);
 180        char            *label;
 181};
 182
 183/**
 184 * struct samsung_pinctrl_drv_data: wrapper for holding driver data together.
 185 * @virt_base: register base address of the controller.
 186 * @dev: device instance representing the controller.
 187 * @irq: interrpt number used by the controller to notify gpio interrupts.
 188 * @ctrl: pin controller instance managed by the driver.
 189 * @pctl: pin controller descriptor registered with the pinctrl subsystem.
 190 * @pctl_dev: cookie representing pinctrl device instance.
 191 * @pin_groups: list of pin groups available to the driver.
 192 * @nr_groups: number of such pin groups.
 193 * @pmx_functions: list of pin functions available to the driver.
 194 * @nr_function: number of such pin functions.
 195 */
 196struct samsung_pinctrl_drv_data {
 197        void __iomem                    *virt_base;
 198        struct device                   *dev;
 199        int                             irq;
 200
 201        struct samsung_pin_ctrl         *ctrl;
 202        struct pinctrl_desc             pctl;
 203        struct pinctrl_dev              *pctl_dev;
 204
 205        const struct samsung_pin_group  *pin_groups;
 206        unsigned int                    nr_groups;
 207        const struct samsung_pmx_func   *pmx_functions;
 208        unsigned int                    nr_functions;
 209};
 210
 211/**
 212 * struct samsung_pin_group: represent group of pins of a pinmux function.
 213 * @name: name of the pin group, used to lookup the group.
 214 * @pins: the pins included in this group.
 215 * @num_pins: number of pins included in this group.
 216 * @func: the function number to be programmed when selected.
 217 */
 218struct samsung_pin_group {
 219        const char              *name;
 220        const unsigned int      *pins;
 221        u8                      num_pins;
 222        u8                      func;
 223};
 224
 225/**
 226 * struct samsung_pmx_func: represent a pin function.
 227 * @name: name of the pin function, used to lookup the function.
 228 * @groups: one or more names of pin groups that provide this function.
 229 * @num_groups: number of groups included in @groups.
 230 */
 231struct samsung_pmx_func {
 232        const char              *name;
 233        const char              **groups;
 234        u8                      num_groups;
 235};
 236
 237/* list of all exported SoC specific data */
 238extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];
 239extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
 240
 241#endif /* __PINCTRL_SAMSUNG_H */
 242
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