linux/drivers/pci/msi.c
<<
>>
Prefs
   1/*
   2 * File:        msi.c
   3 * Purpose:     PCI Message Signaled Interrupt (MSI)
   4 *
   5 * Copyright (C) 2003-2004 Intel
   6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
   7 */
   8
   9#include <linux/err.h>
  10#include <linux/mm.h>
  11#include <linux/irq.h>
  12#include <linux/interrupt.h>
  13#include <linux/init.h>
  14#include <linux/export.h>
  15#include <linux/ioport.h>
  16#include <linux/pci.h>
  17#include <linux/proc_fs.h>
  18#include <linux/msi.h>
  19#include <linux/smp.h>
  20#include <linux/errno.h>
  21#include <linux/io.h>
  22#include <linux/slab.h>
  23
  24#include "pci.h"
  25#include "msi.h"
  26
  27static int pci_msi_enable = 1;
  28
  29/* Arch hooks */
  30
  31#ifndef arch_msi_check_device
  32int arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
  33{
  34        return 0;
  35}
  36#endif
  37
  38#ifndef arch_setup_msi_irqs
  39# define arch_setup_msi_irqs default_setup_msi_irqs
  40# define HAVE_DEFAULT_MSI_SETUP_IRQS
  41#endif
  42
  43#ifdef HAVE_DEFAULT_MSI_SETUP_IRQS
  44int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
  45{
  46        struct msi_desc *entry;
  47        int ret;
  48
  49        /*
  50         * If an architecture wants to support multiple MSI, it needs to
  51         * override arch_setup_msi_irqs()
  52         */
  53        if (type == PCI_CAP_ID_MSI && nvec > 1)
  54                return 1;
  55
  56        list_for_each_entry(entry, &dev->msi_list, list) {
  57                ret = arch_setup_msi_irq(dev, entry);
  58                if (ret < 0)
  59                        return ret;
  60                if (ret > 0)
  61                        return -ENOSPC;
  62        }
  63
  64        return 0;
  65}
  66#endif
  67
  68#ifndef arch_teardown_msi_irqs
  69# define arch_teardown_msi_irqs default_teardown_msi_irqs
  70# define HAVE_DEFAULT_MSI_TEARDOWN_IRQS
  71#endif
  72
  73#ifdef HAVE_DEFAULT_MSI_TEARDOWN_IRQS
  74void default_teardown_msi_irqs(struct pci_dev *dev)
  75{
  76        struct msi_desc *entry;
  77
  78        list_for_each_entry(entry, &dev->msi_list, list) {
  79                int i, nvec;
  80                if (entry->irq == 0)
  81                        continue;
  82                nvec = 1 << entry->msi_attrib.multiple;
  83                for (i = 0; i < nvec; i++)
  84                        arch_teardown_msi_irq(entry->irq + i);
  85        }
  86}
  87#endif
  88
  89#ifndef arch_restore_msi_irqs
  90# define arch_restore_msi_irqs default_restore_msi_irqs
  91# define HAVE_DEFAULT_MSI_RESTORE_IRQS
  92#endif
  93
  94#ifdef HAVE_DEFAULT_MSI_RESTORE_IRQS
  95void default_restore_msi_irqs(struct pci_dev *dev, int irq)
  96{
  97        struct msi_desc *entry;
  98
  99        entry = NULL;
 100        if (dev->msix_enabled) {
 101                list_for_each_entry(entry, &dev->msi_list, list) {
 102                        if (irq == entry->irq)
 103                                break;
 104                }
 105        } else if (dev->msi_enabled)  {
 106                entry = irq_get_msi_desc(irq);
 107        }
 108
 109        if (entry)
 110                write_msi_msg(irq, &entry->msg);
 111}
 112#endif
 113
 114static void msi_set_enable(struct pci_dev *dev, int pos, int enable)
 115{
 116        u16 control;
 117
 118        BUG_ON(!pos);
 119
 120        pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
 121        control &= ~PCI_MSI_FLAGS_ENABLE;
 122        if (enable)
 123                control |= PCI_MSI_FLAGS_ENABLE;
 124        pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
 125}
 126
 127static void msix_set_enable(struct pci_dev *dev, int enable)
 128{
 129        int pos;
 130        u16 control;
 131
 132        pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 133        if (pos) {
 134                pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
 135                control &= ~PCI_MSIX_FLAGS_ENABLE;
 136                if (enable)
 137                        control |= PCI_MSIX_FLAGS_ENABLE;
 138                pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
 139        }
 140}
 141
 142static inline __attribute_const__ u32 msi_mask(unsigned x)
 143{
 144        /* Don't shift by >= width of type */
 145        if (x >= 5)
 146                return 0xffffffff;
 147        return (1 << (1 << x)) - 1;
 148}
 149
 150static inline __attribute_const__ u32 msi_capable_mask(u16 control)
 151{
 152        return msi_mask((control >> 1) & 7);
 153}
 154
 155static inline __attribute_const__ u32 msi_enabled_mask(u16 control)
 156{
 157        return msi_mask((control >> 4) & 7);
 158}
 159
 160/*
 161 * PCI 2.3 does not specify mask bits for each MSI interrupt.  Attempting to
 162 * mask all MSI interrupts by clearing the MSI enable bit does not work
 163 * reliably as devices without an INTx disable bit will then generate a
 164 * level IRQ which will never be cleared.
 165 */
 166static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
 167{
 168        u32 mask_bits = desc->masked;
 169
 170        if (!desc->msi_attrib.maskbit)
 171                return 0;
 172
 173        mask_bits &= ~mask;
 174        mask_bits |= flag;
 175        pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits);
 176
 177        return mask_bits;
 178}
 179
 180static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
 181{
 182        desc->masked = __msi_mask_irq(desc, mask, flag);
 183}
 184
 185/*
 186 * This internal function does not flush PCI writes to the device.
 187 * All users must ensure that they read from the device before either
 188 * assuming that the device state is up to date, or returning out of this
 189 * file.  This saves a few milliseconds when initialising devices with lots
 190 * of MSI-X interrupts.
 191 */
 192static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag)
 193{
 194        u32 mask_bits = desc->masked;
 195        unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
 196                                                PCI_MSIX_ENTRY_VECTOR_CTRL;
 197        mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
 198        if (flag)
 199                mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
 200        writel(mask_bits, desc->mask_base + offset);
 201
 202        return mask_bits;
 203}
 204
 205static void msix_mask_irq(struct msi_desc *desc, u32 flag)
 206{
 207        desc->masked = __msix_mask_irq(desc, flag);
 208}
 209
 210#ifdef CONFIG_GENERIC_HARDIRQS
 211
 212static void msi_set_mask_bit(struct irq_data *data, u32 flag)
 213{
 214        struct msi_desc *desc = irq_data_get_msi(data);
 215
 216        if (desc->msi_attrib.is_msix) {
 217                msix_mask_irq(desc, flag);
 218                readl(desc->mask_base);         /* Flush write to device */
 219        } else {
 220                unsigned offset = data->irq - desc->dev->irq;
 221                msi_mask_irq(desc, 1 << offset, flag << offset);
 222        }
 223}
 224
 225void mask_msi_irq(struct irq_data *data)
 226{
 227        msi_set_mask_bit(data, 1);
 228}
 229
 230void unmask_msi_irq(struct irq_data *data)
 231{
 232        msi_set_mask_bit(data, 0);
 233}
 234
 235#endif /* CONFIG_GENERIC_HARDIRQS */
 236
 237void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
 238{
 239        BUG_ON(entry->dev->current_state != PCI_D0);
 240
 241        if (entry->msi_attrib.is_msix) {
 242                void __iomem *base = entry->mask_base +
 243                        entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
 244
 245                msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
 246                msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
 247                msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
 248        } else {
 249                struct pci_dev *dev = entry->dev;
 250                int pos = entry->msi_attrib.pos;
 251                u16 data;
 252
 253                pci_read_config_dword(dev, msi_lower_address_reg(pos),
 254                                        &msg->address_lo);
 255                if (entry->msi_attrib.is_64) {
 256                        pci_read_config_dword(dev, msi_upper_address_reg(pos),
 257                                                &msg->address_hi);
 258                        pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
 259                } else {
 260                        msg->address_hi = 0;
 261                        pci_read_config_word(dev, msi_data_reg(pos, 0), &data);
 262                }
 263                msg->data = data;
 264        }
 265}
 266
 267void read_msi_msg(unsigned int irq, struct msi_msg *msg)
 268{
 269        struct msi_desc *entry = irq_get_msi_desc(irq);
 270
 271        __read_msi_msg(entry, msg);
 272}
 273
 274void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
 275{
 276        /* Assert that the cache is valid, assuming that
 277         * valid messages are not all-zeroes. */
 278        BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo |
 279                 entry->msg.data));
 280
 281        *msg = entry->msg;
 282}
 283
 284void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
 285{
 286        struct msi_desc *entry = irq_get_msi_desc(irq);
 287
 288        __get_cached_msi_msg(entry, msg);
 289}
 290
 291void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
 292{
 293        if (entry->dev->current_state != PCI_D0) {
 294                /* Don't touch the hardware now */
 295        } else if (entry->msi_attrib.is_msix) {
 296                void __iomem *base;
 297                base = entry->mask_base +
 298                        entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
 299
 300                writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
 301                writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
 302                writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
 303        } else {
 304                struct pci_dev *dev = entry->dev;
 305                int pos = entry->msi_attrib.pos;
 306                u16 msgctl;
 307
 308                pci_read_config_word(dev, msi_control_reg(pos), &msgctl);
 309                msgctl &= ~PCI_MSI_FLAGS_QSIZE;
 310                msgctl |= entry->msi_attrib.multiple << 4;
 311                pci_write_config_word(dev, msi_control_reg(pos), msgctl);
 312
 313                pci_write_config_dword(dev, msi_lower_address_reg(pos),
 314                                        msg->address_lo);
 315                if (entry->msi_attrib.is_64) {
 316                        pci_write_config_dword(dev, msi_upper_address_reg(pos),
 317                                                msg->address_hi);
 318                        pci_write_config_word(dev, msi_data_reg(pos, 1),
 319                                                msg->data);
 320                } else {
 321                        pci_write_config_word(dev, msi_data_reg(pos, 0),
 322                                                msg->data);
 323                }
 324        }
 325        entry->msg = *msg;
 326}
 327
 328void write_msi_msg(unsigned int irq, struct msi_msg *msg)
 329{
 330        struct msi_desc *entry = irq_get_msi_desc(irq);
 331
 332        __write_msi_msg(entry, msg);
 333}
 334
 335static void free_msi_irqs(struct pci_dev *dev)
 336{
 337        struct msi_desc *entry, *tmp;
 338
 339        list_for_each_entry(entry, &dev->msi_list, list) {
 340                int i, nvec;
 341                if (!entry->irq)
 342                        continue;
 343                nvec = 1 << entry->msi_attrib.multiple;
 344#ifdef CONFIG_GENERIC_HARDIRQS
 345                for (i = 0; i < nvec; i++)
 346                        BUG_ON(irq_has_action(entry->irq + i));
 347#endif
 348        }
 349
 350        arch_teardown_msi_irqs(dev);
 351
 352        list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) {
 353                if (entry->msi_attrib.is_msix) {
 354                        if (list_is_last(&entry->list, &dev->msi_list))
 355                                iounmap(entry->mask_base);
 356                }
 357
 358                /*
 359                 * Its possible that we get into this path
 360                 * When populate_msi_sysfs fails, which means the entries
 361                 * were not registered with sysfs.  In that case don't
 362                 * unregister them.
 363                 */
 364                if (entry->kobj.parent) {
 365                        kobject_del(&entry->kobj);
 366                        kobject_put(&entry->kobj);
 367                }
 368
 369                list_del(&entry->list);
 370                kfree(entry);
 371        }
 372}
 373
 374static struct msi_desc *alloc_msi_entry(struct pci_dev *dev)
 375{
 376        struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL);
 377        if (!desc)
 378                return NULL;
 379
 380        INIT_LIST_HEAD(&desc->list);
 381        desc->dev = dev;
 382
 383        return desc;
 384}
 385
 386static void pci_intx_for_msi(struct pci_dev *dev, int enable)
 387{
 388        if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
 389                pci_intx(dev, enable);
 390}
 391
 392static void __pci_restore_msi_state(struct pci_dev *dev)
 393{
 394        int pos;
 395        u16 control;
 396        struct msi_desc *entry;
 397
 398        if (!dev->msi_enabled)
 399                return;
 400
 401        entry = irq_get_msi_desc(dev->irq);
 402        pos = entry->msi_attrib.pos;
 403
 404        pci_intx_for_msi(dev, 0);
 405        msi_set_enable(dev, pos, 0);
 406        arch_restore_msi_irqs(dev, dev->irq);
 407
 408        pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
 409        msi_mask_irq(entry, msi_capable_mask(control), entry->masked);
 410        control &= ~PCI_MSI_FLAGS_QSIZE;
 411        control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
 412        pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
 413}
 414
 415static void __pci_restore_msix_state(struct pci_dev *dev)
 416{
 417        int pos;
 418        struct msi_desc *entry;
 419        u16 control;
 420
 421        if (!dev->msix_enabled)
 422                return;
 423        BUG_ON(list_empty(&dev->msi_list));
 424        entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
 425        pos = entry->msi_attrib.pos;
 426        pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
 427
 428        /* route the table */
 429        pci_intx_for_msi(dev, 0);
 430        control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL;
 431        pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
 432
 433        list_for_each_entry(entry, &dev->msi_list, list) {
 434                arch_restore_msi_irqs(dev, entry->irq);
 435                msix_mask_irq(entry, entry->masked);
 436        }
 437
 438        control &= ~PCI_MSIX_FLAGS_MASKALL;
 439        pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
 440}
 441
 442void pci_restore_msi_state(struct pci_dev *dev)
 443{
 444        __pci_restore_msi_state(dev);
 445        __pci_restore_msix_state(dev);
 446}
 447EXPORT_SYMBOL_GPL(pci_restore_msi_state);
 448
 449
 450#define to_msi_attr(obj) container_of(obj, struct msi_attribute, attr)
 451#define to_msi_desc(obj) container_of(obj, struct msi_desc, kobj)
 452
 453struct msi_attribute {
 454        struct attribute        attr;
 455        ssize_t (*show)(struct msi_desc *entry, struct msi_attribute *attr,
 456                        char *buf);
 457        ssize_t (*store)(struct msi_desc *entry, struct msi_attribute *attr,
 458                         const char *buf, size_t count);
 459};
 460
 461static ssize_t show_msi_mode(struct msi_desc *entry, struct msi_attribute *atr,
 462                             char *buf)
 463{
 464        return sprintf(buf, "%s\n", entry->msi_attrib.is_msix ? "msix" : "msi");
 465}
 466
 467static ssize_t msi_irq_attr_show(struct kobject *kobj,
 468                                 struct attribute *attr, char *buf)
 469{
 470        struct msi_attribute *attribute = to_msi_attr(attr);
 471        struct msi_desc *entry = to_msi_desc(kobj);
 472
 473        if (!attribute->show)
 474                return -EIO;
 475
 476        return attribute->show(entry, attribute, buf);
 477}
 478
 479static const struct sysfs_ops msi_irq_sysfs_ops = {
 480        .show = msi_irq_attr_show,
 481};
 482
 483static struct msi_attribute mode_attribute =
 484        __ATTR(mode, S_IRUGO, show_msi_mode, NULL);
 485
 486
 487struct attribute *msi_irq_default_attrs[] = {
 488        &mode_attribute.attr,
 489        NULL
 490};
 491
 492void msi_kobj_release(struct kobject *kobj)
 493{
 494        struct msi_desc *entry = to_msi_desc(kobj);
 495
 496        pci_dev_put(entry->dev);
 497}
 498
 499static struct kobj_type msi_irq_ktype = {
 500        .release = msi_kobj_release,
 501        .sysfs_ops = &msi_irq_sysfs_ops,
 502        .default_attrs = msi_irq_default_attrs,
 503};
 504
 505static int populate_msi_sysfs(struct pci_dev *pdev)
 506{
 507        struct msi_desc *entry;
 508        struct kobject *kobj;
 509        int ret;
 510        int count = 0;
 511
 512        pdev->msi_kset = kset_create_and_add("msi_irqs", NULL, &pdev->dev.kobj);
 513        if (!pdev->msi_kset)
 514                return -ENOMEM;
 515
 516        list_for_each_entry(entry, &pdev->msi_list, list) {
 517                kobj = &entry->kobj;
 518                kobj->kset = pdev->msi_kset;
 519                pci_dev_get(pdev);
 520                ret = kobject_init_and_add(kobj, &msi_irq_ktype, NULL,
 521                                     "%u", entry->irq);
 522                if (ret)
 523                        goto out_unroll;
 524
 525                count++;
 526        }
 527
 528        return 0;
 529
 530out_unroll:
 531        list_for_each_entry(entry, &pdev->msi_list, list) {
 532                if (!count)
 533                        break;
 534                kobject_del(&entry->kobj);
 535                kobject_put(&entry->kobj);
 536                count--;
 537        }
 538        return ret;
 539}
 540
 541/**
 542 * msi_capability_init - configure device's MSI capability structure
 543 * @dev: pointer to the pci_dev data structure of MSI device function
 544 * @nvec: number of interrupts to allocate
 545 *
 546 * Setup the MSI capability structure of the device with the requested
 547 * number of interrupts.  A return value of zero indicates the successful
 548 * setup of an entry with the new MSI irq.  A negative return value indicates
 549 * an error, and a positive return value indicates the number of interrupts
 550 * which could have been allocated.
 551 */
 552static int msi_capability_init(struct pci_dev *dev, int nvec)
 553{
 554        struct msi_desc *entry;
 555        int pos, ret;
 556        u16 control;
 557        unsigned mask;
 558
 559        pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
 560        msi_set_enable(dev, pos, 0);    /* Disable MSI during set up */
 561
 562        pci_read_config_word(dev, msi_control_reg(pos), &control);
 563        /* MSI Entry Initialization */
 564        entry = alloc_msi_entry(dev);
 565        if (!entry)
 566                return -ENOMEM;
 567
 568        entry->msi_attrib.is_msix       = 0;
 569        entry->msi_attrib.is_64         = is_64bit_address(control);
 570        entry->msi_attrib.entry_nr      = 0;
 571        entry->msi_attrib.maskbit       = is_mask_bit_support(control);
 572        entry->msi_attrib.default_irq   = dev->irq;     /* Save IOAPIC IRQ */
 573        entry->msi_attrib.pos           = pos;
 574
 575        entry->mask_pos = msi_mask_reg(pos, entry->msi_attrib.is_64);
 576        /* All MSIs are unmasked by default, Mask them all */
 577        if (entry->msi_attrib.maskbit)
 578                pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
 579        mask = msi_capable_mask(control);
 580        msi_mask_irq(entry, mask, mask);
 581
 582        list_add_tail(&entry->list, &dev->msi_list);
 583
 584        /* Configure MSI capability structure */
 585        ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
 586        if (ret) {
 587                msi_mask_irq(entry, mask, ~mask);
 588                free_msi_irqs(dev);
 589                return ret;
 590        }
 591
 592        ret = populate_msi_sysfs(dev);
 593        if (ret) {
 594                msi_mask_irq(entry, mask, ~mask);
 595                free_msi_irqs(dev);
 596                return ret;
 597        }
 598
 599        /* Set MSI enabled bits  */
 600        pci_intx_for_msi(dev, 0);
 601        msi_set_enable(dev, pos, 1);
 602        dev->msi_enabled = 1;
 603
 604        dev->irq = entry->irq;
 605        return 0;
 606}
 607
 608static void __iomem *msix_map_region(struct pci_dev *dev, unsigned pos,
 609                                                        unsigned nr_entries)
 610{
 611        resource_size_t phys_addr;
 612        u32 table_offset;
 613        u8 bir;
 614
 615        pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset);
 616        bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
 617        table_offset &= ~PCI_MSIX_FLAGS_BIRMASK;
 618        phys_addr = pci_resource_start(dev, bir) + table_offset;
 619
 620        return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
 621}
 622
 623static int msix_setup_entries(struct pci_dev *dev, unsigned pos,
 624                                void __iomem *base, struct msix_entry *entries,
 625                                int nvec)
 626{
 627        struct msi_desc *entry;
 628        int i;
 629
 630        for (i = 0; i < nvec; i++) {
 631                entry = alloc_msi_entry(dev);
 632                if (!entry) {
 633                        if (!i)
 634                                iounmap(base);
 635                        else
 636                                free_msi_irqs(dev);
 637                        /* No enough memory. Don't try again */
 638                        return -ENOMEM;
 639                }
 640
 641                entry->msi_attrib.is_msix       = 1;
 642                entry->msi_attrib.is_64         = 1;
 643                entry->msi_attrib.entry_nr      = entries[i].entry;
 644                entry->msi_attrib.default_irq   = dev->irq;
 645                entry->msi_attrib.pos           = pos;
 646                entry->mask_base                = base;
 647
 648                list_add_tail(&entry->list, &dev->msi_list);
 649        }
 650
 651        return 0;
 652}
 653
 654static void msix_program_entries(struct pci_dev *dev,
 655                                        struct msix_entry *entries)
 656{
 657        struct msi_desc *entry;
 658        int i = 0;
 659
 660        list_for_each_entry(entry, &dev->msi_list, list) {
 661                int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE +
 662                                                PCI_MSIX_ENTRY_VECTOR_CTRL;
 663
 664                entries[i].vector = entry->irq;
 665                irq_set_msi_desc(entry->irq, entry);
 666                entry->masked = readl(entry->mask_base + offset);
 667                msix_mask_irq(entry, 1);
 668                i++;
 669        }
 670}
 671
 672/**
 673 * msix_capability_init - configure device's MSI-X capability
 674 * @dev: pointer to the pci_dev data structure of MSI-X device function
 675 * @entries: pointer to an array of struct msix_entry entries
 676 * @nvec: number of @entries
 677 *
 678 * Setup the MSI-X capability structure of device function with a
 679 * single MSI-X irq. A return of zero indicates the successful setup of
 680 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
 681 **/
 682static int msix_capability_init(struct pci_dev *dev,
 683                                struct msix_entry *entries, int nvec)
 684{
 685        int pos, ret;
 686        u16 control;
 687        void __iomem *base;
 688
 689        pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 690        pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
 691
 692        /* Ensure MSI-X is disabled while it is set up */
 693        control &= ~PCI_MSIX_FLAGS_ENABLE;
 694        pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
 695
 696        /* Request & Map MSI-X table region */
 697        base = msix_map_region(dev, pos, multi_msix_capable(control));
 698        if (!base)
 699                return -ENOMEM;
 700
 701        ret = msix_setup_entries(dev, pos, base, entries, nvec);
 702        if (ret)
 703                return ret;
 704
 705        ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
 706        if (ret)
 707                goto error;
 708
 709        /*
 710         * Some devices require MSI-X to be enabled before we can touch the
 711         * MSI-X registers.  We need to mask all the vectors to prevent
 712         * interrupts coming in before they're fully set up.
 713         */
 714        control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE;
 715        pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
 716
 717        msix_program_entries(dev, entries);
 718
 719        ret = populate_msi_sysfs(dev);
 720        if (ret) {
 721                ret = 0;
 722                goto error;
 723        }
 724
 725        /* Set MSI-X enabled bits and unmask the function */
 726        pci_intx_for_msi(dev, 0);
 727        dev->msix_enabled = 1;
 728
 729        control &= ~PCI_MSIX_FLAGS_MASKALL;
 730        pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
 731
 732        return 0;
 733
 734error:
 735        if (ret < 0) {
 736                /*
 737                 * If we had some success, report the number of irqs
 738                 * we succeeded in setting up.
 739                 */
 740                struct msi_desc *entry;
 741                int avail = 0;
 742
 743                list_for_each_entry(entry, &dev->msi_list, list) {
 744                        if (entry->irq != 0)
 745                                avail++;
 746                }
 747                if (avail != 0)
 748                        ret = avail;
 749        }
 750
 751        free_msi_irqs(dev);
 752
 753        return ret;
 754}
 755
 756/**
 757 * pci_msi_check_device - check whether MSI may be enabled on a device
 758 * @dev: pointer to the pci_dev data structure of MSI device function
 759 * @nvec: how many MSIs have been requested ?
 760 * @type: are we checking for MSI or MSI-X ?
 761 *
 762 * Look at global flags, the device itself, and its parent busses
 763 * to determine if MSI/-X are supported for the device. If MSI/-X is
 764 * supported return 0, else return an error code.
 765 **/
 766static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type)
 767{
 768        struct pci_bus *bus;
 769        int ret;
 770
 771        /* MSI must be globally enabled and supported by the device */
 772        if (!pci_msi_enable || !dev || dev->no_msi)
 773                return -EINVAL;
 774
 775        /*
 776         * You can't ask to have 0 or less MSIs configured.
 777         *  a) it's stupid ..
 778         *  b) the list manipulation code assumes nvec >= 1.
 779         */
 780        if (nvec < 1)
 781                return -ERANGE;
 782
 783        /*
 784         * Any bridge which does NOT route MSI transactions from its
 785         * secondary bus to its primary bus must set NO_MSI flag on
 786         * the secondary pci_bus.
 787         * We expect only arch-specific PCI host bus controller driver
 788         * or quirks for specific PCI bridges to be setting NO_MSI.
 789         */
 790        for (bus = dev->bus; bus; bus = bus->parent)
 791                if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
 792                        return -EINVAL;
 793
 794        ret = arch_msi_check_device(dev, nvec, type);
 795        if (ret)
 796                return ret;
 797
 798        if (!pci_find_capability(dev, type))
 799                return -EINVAL;
 800
 801        return 0;
 802}
 803
 804/**
 805 * pci_enable_msi_block - configure device's MSI capability structure
 806 * @dev: device to configure
 807 * @nvec: number of interrupts to configure
 808 *
 809 * Allocate IRQs for a device with the MSI capability.
 810 * This function returns a negative errno if an error occurs.  If it
 811 * is unable to allocate the number of interrupts requested, it returns
 812 * the number of interrupts it might be able to allocate.  If it successfully
 813 * allocates at least the number of interrupts requested, it returns 0 and
 814 * updates the @dev's irq member to the lowest new interrupt number; the
 815 * other interrupt numbers allocated to this device are consecutive.
 816 */
 817int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
 818{
 819        int status, pos, maxvec;
 820        u16 msgctl;
 821
 822        pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
 823        if (!pos)
 824                return -EINVAL;
 825        pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
 826        maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
 827        if (nvec > maxvec)
 828                return maxvec;
 829
 830        status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI);
 831        if (status)
 832                return status;
 833
 834        WARN_ON(!!dev->msi_enabled);
 835
 836        /* Check whether driver already requested MSI-X irqs */
 837        if (dev->msix_enabled) {
 838                dev_info(&dev->dev, "can't enable MSI "
 839                         "(MSI-X already enabled)\n");
 840                return -EINVAL;
 841        }
 842
 843        status = msi_capability_init(dev, nvec);
 844        return status;
 845}
 846EXPORT_SYMBOL(pci_enable_msi_block);
 847
 848void pci_msi_shutdown(struct pci_dev *dev)
 849{
 850        struct msi_desc *desc;
 851        u32 mask;
 852        u16 ctrl;
 853        unsigned pos;
 854
 855        if (!pci_msi_enable || !dev || !dev->msi_enabled)
 856                return;
 857
 858        BUG_ON(list_empty(&dev->msi_list));
 859        desc = list_first_entry(&dev->msi_list, struct msi_desc, list);
 860        pos = desc->msi_attrib.pos;
 861
 862        msi_set_enable(dev, pos, 0);
 863        pci_intx_for_msi(dev, 1);
 864        dev->msi_enabled = 0;
 865
 866        /* Return the device with MSI unmasked as initial states */
 867        pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &ctrl);
 868        mask = msi_capable_mask(ctrl);
 869        /* Keep cached state to be restored */
 870        __msi_mask_irq(desc, mask, ~mask);
 871
 872        /* Restore dev->irq to its default pin-assertion irq */
 873        dev->irq = desc->msi_attrib.default_irq;
 874}
 875
 876void pci_disable_msi(struct pci_dev *dev)
 877{
 878        if (!pci_msi_enable || !dev || !dev->msi_enabled)
 879                return;
 880
 881        pci_msi_shutdown(dev);
 882        free_msi_irqs(dev);
 883        kset_unregister(dev->msi_kset);
 884        dev->msi_kset = NULL;
 885}
 886EXPORT_SYMBOL(pci_disable_msi);
 887
 888/**
 889 * pci_msix_table_size - return the number of device's MSI-X table entries
 890 * @dev: pointer to the pci_dev data structure of MSI-X device function
 891 */
 892int pci_msix_table_size(struct pci_dev *dev)
 893{
 894        int pos;
 895        u16 control;
 896
 897        pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 898        if (!pos)
 899                return 0;
 900
 901        pci_read_config_word(dev, msi_control_reg(pos), &control);
 902        return multi_msix_capable(control);
 903}
 904
 905/**
 906 * pci_enable_msix - configure device's MSI-X capability structure
 907 * @dev: pointer to the pci_dev data structure of MSI-X device function
 908 * @entries: pointer to an array of MSI-X entries
 909 * @nvec: number of MSI-X irqs requested for allocation by device driver
 910 *
 911 * Setup the MSI-X capability structure of device function with the number
 912 * of requested irqs upon its software driver call to request for
 913 * MSI-X mode enabled on its hardware device function. A return of zero
 914 * indicates the successful configuration of MSI-X capability structure
 915 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
 916 * Or a return of > 0 indicates that driver request is exceeding the number
 917 * of irqs or MSI-X vectors available. Driver should use the returned value to
 918 * re-send its request.
 919 **/
 920int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
 921{
 922        int status, nr_entries;
 923        int i, j;
 924
 925        if (!entries)
 926                return -EINVAL;
 927
 928        status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX);
 929        if (status)
 930                return status;
 931
 932        nr_entries = pci_msix_table_size(dev);
 933        if (nvec > nr_entries)
 934                return nr_entries;
 935
 936        /* Check for any invalid entries */
 937        for (i = 0; i < nvec; i++) {
 938                if (entries[i].entry >= nr_entries)
 939                        return -EINVAL;         /* invalid entry */
 940                for (j = i + 1; j < nvec; j++) {
 941                        if (entries[i].entry == entries[j].entry)
 942                                return -EINVAL; /* duplicate entry */
 943                }
 944        }
 945        WARN_ON(!!dev->msix_enabled);
 946
 947        /* Check whether driver already requested for MSI irq */
 948        if (dev->msi_enabled) {
 949                dev_info(&dev->dev, "can't enable MSI-X "
 950                       "(MSI IRQ already assigned)\n");
 951                return -EINVAL;
 952        }
 953        status = msix_capability_init(dev, entries, nvec);
 954        return status;
 955}
 956EXPORT_SYMBOL(pci_enable_msix);
 957
 958void pci_msix_shutdown(struct pci_dev *dev)
 959{
 960        struct msi_desc *entry;
 961
 962        if (!pci_msi_enable || !dev || !dev->msix_enabled)
 963                return;
 964
 965        /* Return the device with MSI-X masked as initial states */
 966        list_for_each_entry(entry, &dev->msi_list, list) {
 967                /* Keep cached states to be restored */
 968                __msix_mask_irq(entry, 1);
 969        }
 970
 971        msix_set_enable(dev, 0);
 972        pci_intx_for_msi(dev, 1);
 973        dev->msix_enabled = 0;
 974}
 975
 976void pci_disable_msix(struct pci_dev *dev)
 977{
 978        if (!pci_msi_enable || !dev || !dev->msix_enabled)
 979                return;
 980
 981        pci_msix_shutdown(dev);
 982        free_msi_irqs(dev);
 983        kset_unregister(dev->msi_kset);
 984        dev->msi_kset = NULL;
 985}
 986EXPORT_SYMBOL(pci_disable_msix);
 987
 988/**
 989 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
 990 * @dev: pointer to the pci_dev data structure of MSI(X) device function
 991 *
 992 * Being called during hotplug remove, from which the device function
 993 * is hot-removed. All previous assigned MSI/MSI-X irqs, if
 994 * allocated for this device function, are reclaimed to unused state,
 995 * which may be used later on.
 996 **/
 997void msi_remove_pci_irq_vectors(struct pci_dev *dev)
 998{
 999        if (!pci_msi_enable || !dev)
1000                return;
1001
1002        if (dev->msi_enabled || dev->msix_enabled)
1003                free_msi_irqs(dev);
1004}
1005
1006void pci_no_msi(void)
1007{
1008        pci_msi_enable = 0;
1009}
1010
1011/**
1012 * pci_msi_enabled - is MSI enabled?
1013 *
1014 * Returns true if MSI has not been disabled by the command-line option
1015 * pci=nomsi.
1016 **/
1017int pci_msi_enabled(void)
1018{
1019        return pci_msi_enable;
1020}
1021EXPORT_SYMBOL(pci_msi_enabled);
1022
1023void pci_msi_init_pci_dev(struct pci_dev *dev)
1024{
1025        int pos;
1026        INIT_LIST_HEAD(&dev->msi_list);
1027
1028        /* Disable the msi hardware to avoid screaming interrupts
1029         * during boot.  This is the power on reset default so
1030         * usually this should be a noop.
1031         */
1032        pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
1033        if (pos)
1034                msi_set_enable(dev, pos, 0);
1035        msix_set_enable(dev, 0);
1036}
1037
lxr.linux.no kindly hosted by Redpill Linpro AS, provider of Linux consulting and operations services since 1995.