linux/drivers/ide/pdc202xx_new.c
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ptiov3./spa > v3./form > v3.a ptiov3 href="../linux+v3.8.6/drivers/ide/pdc202xx_new.c">ptiov3.img src="../.static/gfx/right.png" alt=">>">pt./spa >pt.spa class="lxr_search">ptioptiov3.input typon>hidden" namon>navtarget" option>">ptiov3.input typon>text" namon>search" idn>search">ptiov3.butt2submit">Search v3./form > ./spa >pt.spa class="lxr_prefs" > v3.a href="+prefs?return=drivers/ide/pdc202xx_new.c"ptiov3 onclick="return ajax_prefs();">ptiov3Prefs> v3./a>pt./spa >iov3 3./div >iov3 3.form ac" ="ajax+*" method="post" onsubmit="return false;">pt.input typon>hidden" namon>ajax_lookup" idn>ajax_lookup" option>">piov3 3./form >piov3 3.div class="headingbott2m">
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bf/e6/97923faf9d5b902d48766b5ee31ac3427fd1_3/0" L1" class="line" namon>L1">3 31./a>.spa  class="comment">/*./spa  >L2" class="line" namon>L2">3 32./a>.spa  class="comment"> *v3Promise TX2/TX4/TX2000/133 IDE driver./spa  >L3" class="line" namon>L3">3 33./a>.spa  class="comment"> *./spa  >L4" class="line" namon>L4">3 34./a>.spa  class="comment"> *v3This program is free software; you ca  redistribute it and/or./spa  >L5" class="line" namon>L5">3 35./a>.spa  class="comment"> *v3modify it under the terms of the GNU General Public License./spa  >L6" class="line" namon>L6">3 36./a>.spa  class="comment"> *v3as published by the Free Software Founda"
	 ; either vers
	 ./spa  >L7" class="line" namon>L7">3 37./a>.spa  class="comment"> *v32 of the License, or (at your 12"
	 ) any later vers
	 ../spa  >L8" class="line" namon>L8">3 38./a>.spa  class="comment"> *./spa  >L9" class="line" namon>L9">3 39./a>.spa  class="comment"> *v3Split from:./spa  >L10" class="line" namon>L10">3 .18.a>.spa  class="comment"> *v3linux/drivers/ide/pdc202xx.c        Vers
	  0"v4    Mar. 30, 2002./spa  >L11" class="line" namon>L11">3 11./a>.spa  class="comment"> *v3Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>./spa  >L12" class="line" namon>L12">3 12./a>.spa  class="comment"> *v3Copyright (C) 2005-2007             MontaVista Software, Inc../spa  >L13" class="line" namon>L13">3 13./a>.spa  class="comment"> *v3Por"
	 s3Copyright (C) 19993Promise Technology, Inc../spa  >L14" class="line" namon>L14">3 14./a>.spa  class="comment"> *v3Author: Frank Tierna  (frankt@promise.com)./spa  >L15" class="line" namon>L15">3 15./a>.spa  class="comment"> *v3Released under terms of General Public License./spa  >L16" class="line" namon>L16">3 16./a>.spa  class="comment"> */./spa  >L17" class="line" namon>L17">3 17./a>>L18" class="line" namon>L18">3 18./a>#include <linux/module.h./a>>>L19" class="line" namon>L19">3 19./a>#include <linux/typos.h./a>>>L20" class="line" namon>L20">3 20./a>#include <linux/kernel.h./a>>>L21" class="line" namon>L21">3 21./a>#include <linux/delay.h./a>>>L22" class="line" namon>L22">3 22./a>#include <linux/pci.h./a>>>L23" class="line" namon>L23">3 23./a>#include <linux/init.h./a>>>L24" class="line" namon>L24">3 24./a>#include <linux/ide.h./a>>>L25" class="line" namon>L25">3 25./a>>L26" class="line" namon>L26">3 26./a>#include <asm/io.h./a>>>L27" class="line" namon>L27">3 27./a>>L28" class="line" namon>L28">3 28./a>#ifdef3.a href="+code=CONFIG_PPC_PMAC" class="sref">CONFIG_PPC_PMAC./a>>L29" class="line" namon>L29">3 29./a>#include <asm/prom.h./a>>>L30" class="line" namon>L30">3 30./a>#include <asm/pci-bridge.h./a>>>L31" class="line" namon>L31">3 31./a>#endif>L32" class="line" namon>L32">3 32./a>>L33" class="line" namon>L33">3 33./a>#define3.a href="+code=DRV_NAME" class="sref">DRV_NAME./a> .spa  class="string">"pdc202xx_new"./spa  >L34" class="line" namon>L34">3 34./a>>L35" class="line" namon>L35">3 35./a>#undef3.a href="+code=DEBUG" class="sref">DEBUG./a>>L36" class="line" namon>L36">3 36./a>>L37" class="line" namon>L37">3 37./a>#ifdef3.a href="+code=DEBUG" class="sref">DEBUG./a>>L38" class="line" namon>L38">3 38./a>#define3.a href="+code=DBG" class="sref">DBG./a>(.a href="+code=fmt" class="sref">fmt./a>,3.a href="+code=args" class="sref">args./a>...)3.a href="+code=printk" class="sref">printk./a>(.spa  class="string">"%s: "./spa  3.a href="+code=fmt" class="sref">fmt./a>,3.a href="+code=__func__" class="sref">__func__./a>,3##3.a href="+code=args" class="sref">args./a>)>L39" class="line" namon>L39">3 39./a>#else>L40" class="line" namon>L40">3 40./a>#define3.a href="+code=DBG" class="sref">DBG./a>(.a href="+code=fmt" class="sref">fmt./a>,3.a href="+code=args" class="sref">args./a>...)>L41" class="line" namon>L41">3 41./a>#endif>L42" class="line" namon>L42">3 42./a>>L43" class="line" namon>L43">3 43./a>static3.a href="+code=u8" class="sref">u8./a> .a href="+code=max_dma_rate" class="sref">max_dma_rate./a>(struct3.a href="+code=pci_dev" class="sref">pci_dev./a> *.a href="+code=pdev" class="sref">pdev./a>)>L44" class="line" namon>L44">3 44./a>{>L45" class="line" namon>L45">3 45./a>        .a href="+code=u8" class="sref">u8./a> .a href="+code=mode" class="sref">mode./a>;>L46" class="line" namon>L46">3 46./a>>L47" class="line" namon>L47">3 47./a>        switch(.a href="+code=pdev" class="sref">pdev./a>->.a href="+code=device" class="sref">device./a>) {>L48" class="line" namon>L48">3 48./a>                case3.a href="+code=PCI_DEVICE_ID_PROMISE_20277" class="sref">PCI_DEVICE_ID_PROMISE_20277./a>:>L49" class="line" namon>L49">3 49./a>                case3.a href="+code=PCI_DEVICE_ID_PROMISE_20276" class="sref">PCI_DEVICE_ID_PROMISE_20276./a>:>L50" class="line" namon>L50">3 50./a>                case3.a href="+code=PCI_DEVICE_ID_PROMISE_20275" class="sref">PCI_DEVICE_ID_PROMISE_20275./a>:>L51" class="line" namon>L51">3 51./a>                case3.a href="+code=PCI_DEVICE_ID_PROMISE_20271" class="sref">PCI_DEVICE_ID_PROMISE_20271./a>:>L52" class="line" namon>L52">3 52./a>                case3.a href="+code=PCI_DEVICE_ID_PROMISE_20269" class="sref">PCI_DEVICE_ID_PROMISE_20269./a>:>L53" class="line" namon>L53">3 53./a>                        .a href="+code=mode" class="sref">mode./a> = 4;>L54" class="line" namon>L54">3 54./a>                        break;>L55" class="line" namon>L55">3 55./a>                case3.a href="+code=PCI_DEVICE_ID_PROMISE_20270" class="sref">PCI_DEVICE_ID_PROMISE_20270./a>:>L56" class="line" namon>L56">3 56./a>                case3.a href="+code=PCI_DEVICE_ID_PROMISE_20268" class="sref">PCI_DEVICE_ID_PROMISE_20268./a>:>L57" class="line" namon>L57">3 57./a>                        .a href="+code=mode" class="sref">mode./a> = 3;>L58" class="line" namon>L58">3 58./a>                        break;>L59" class="line" namon>L59">3 59./a>                default:>L60" class="line" namon>L60">3 60./a>                        return 0;>L61" class="line" namon>L61">3 61./a>        }>L62" class="line" namon>L62">3 62./a>>L63" class="line" namon>L63">3 63./a>        return .a href="+code=mode" class="sref">mode./a>;>L64" class="line" namon>L64">3 64./a>}>L65" class="line" namon>L65">3 65./a>>L66" class="line" namon>L66">3 66./a>.spa  class="comment">/**./spa  >L67" class="line" namon>L67">3 67./a>.spa  class="comment"> *vget_indexed_reg - Get indexed register./spa  >L68" class="line" namon>L68">3 68./a>.spa  class="comment"> * @hwif: for the port address./spa  >L69" class="line" namon>L69">3 69./a>.spa  class="comment"> *v@index: index of the indexed register./spa  >L70" class="line" namon>L70">3 718.a>.spa  class="comment"> */./spa  >L71" class="line" namon>L71">3 71./a>static3.a href="+code=u8" class="sref">u8./a> .a href="+code=get_indexed_reg" class="sref">get_indexed_reg./a>(.a href="+code=ide_hwif_t" class="sref">ide_hwif_t./a> *.a href="+code=hwif" class="sref">hwif./a>,3.a href="+code=u8" class="sref">u8./a> .a href="+code=index" class="sref">index./a>)>L72" class="line" namon>L72">3 72./a>{>L73" class="line" namon>L73">3 73./a>        .a href="+code=u8" class="sref">u8./a> .a href="+code=optio" class="sref">optio./a>;>L74" class="line" namon>L74">3 74./a>>L75" class="line" namon>L75">3 75./a>        .a href="+code=outb" class="sref">outb./a>(.a href="+code=index" class="sref">index./a>,3.a href="+code=hwif" class="sref">hwif./a>->.a href="+code=dma_base" class="sref">dma_base./a> + 1);>L76" class="line" namon>L76">3 76./a>        .a href="+code=optio" class="sref">optio./a> = .a href="+code=inb" class="sref">inb./a>(.a href="+code=hwif" class="sref">hwif./a>->.a href="+code=dma_base" class="sref">dma_base./a> + 3);>L77" class="line" namon>L77">3 77./a>>L78" class="line" namon>L78">3 78./a>        .a href="+code=DBG" class="sref">DBG./a>(.spa  class="string">"index[%02X] optio[%02X]\n"./spa  ,3.a href="+code=index" class="sref">index./a>,3.a href="+code=optio" class="sref">optio./a>);>L79" class="line" namon>L79">3 79./a>        return .a href="+code=optio" class="sref">optio./a>;>L80" class="line" namon>L80">3 80./a>}>L81" class="line" namon>L81">3 81./a>>L82" class="line" namon>L82">3 82./a>.spa  class="comment">/**./spa  >L83" class="line" namon>L83">3 83./a>.spa  class="comment"> *vset_indexed_reg - Set indexed register./spa  >L84" class="line" namon>L84">3 84./a>.spa  class="comment"> *v@hwif: for the port address./spa  >L85" class="line" namon>L85">3 85./a>.spa  class="comment"> *v@index: index of the indexed register./spa  >L86" class="line" namon>L86">3 86./a>.spa  class="comment"> */./spa  >L87" class="line" namon>L87">3 87./a>static3void .a href="+code=set_indexed_reg" class="sref">set_indexed_reg./a>(.a href="+code=ide_hwif_t" class="sref">ide_hwif_t./a> *.a href="+code=hwif" class="sref">hwif./a>,3.a href="+code=u8" class="sref">u8./a> .a href="+code=index" class="sref">index./a>,3.a href="+code=u8" class="sref">u8./a> .a href="+code=optio" class="sref">optio./a>)>L88" class="line" namon>L88">3 88./a>{>L89" class="line" namon>L89">3 89./a>        .a href="+code=outb" class="sref">outb./a>(.a href="+code=index" class="sref">index./a>,3.a href="+code=hwif" class="sref">hwif./a>->.a href="+code=dma_base" class="sref">dma_base./a> + 1);>L90" class="line" namon>L90">3 90./a>        .a href="+code=outb" class="sref">outb./a>(.a href="+code=optio" class="sref">optio./a>,3.a href="+code=hwif" class="sref">hwif./a>->.a href="+code=dma_base" class="sref">dma_base./a> + 3);>L91" class="line" namon>L91">3 91./a>        .a href="+code=DBG" class="sref">DBG./a>(.spa  class="string">"index[%02X] optio[%02X]\n"./spa  ,3.a href="+code=index" class="sref">index./a>,3.a href="+code=optio" class="sref">optio./a>);>L92" class="line" namon>L92">3 92./a>}>L93" class="line" namon>L93">3 93./a>>L94" class="line" namon>L94">3 94./a>.spa  class="comment">/*./spa  >L95" class="line" namon>L95">3 95./a>.spa  class="comment"> *vATA Timing Tables based on 133 MHz PLL output clock../spa  >L96" class="line" namon>L96">3 96./a>.spa  class="comment"> *./spa  >L97" class="line" namon>L97">3 97./a>.spa  class="comment"> *vIf the PLL outputs 100 MHz clock, the ASIC hardware willvset./spa  >L98" class="line" namon>L98">3 98./a>.spa  class="comment"> * the timing registers automatically when "set features" command is./spa  >L99" class="line" namon>L99">3 99./a>.spa  class="comment"> *vissued to the device. However, if the PLL output clock is 133 MHz,./spa  >L100" class="line" namon>L100">3100./a>.spa  class="comment"> * the following tables must be used../spa  >L101" class="line" namon>L101">3101./a>.spa  class="comment"> */./spa  >L102" class="line" namon>L102">3102./a>static3struct3.a href="+code=pio_timing" class="sref">pio_timing./a> {>L103" class="line" namon>L103">3103./a>        .a href="+code=u8" class="sref">u8./a> .a href="+code=reg0c" class="sref">reg0c./a>,3.a href="+code=reg0d" class="sref">reg0d./a>,3.a href="+code=reg13" class="sref">reg13./a>;>L104" class="line" namon>L104">3104./a>}3.a href="+code=pio_timings" class="sref">pio_timings./a> [] = {>L105" class="line" namon>L105">3105./a>        { 0xfb, 0x2b, 0xac },   .spa  class="comment">/* PIO3mode 0, IORDY off,3Prefetch off */./spa  >L106" class="line" namon>L106">3106./a>        { 0x46, 0x29, 0xa4 },   .spa  class="comment">/* PIO3mode 1, IORDY off,3Prefetch off */./spa  >L107" class="line" namon>L107">3107./a>        { 0x23, 0x26, 0x64 },   .spa  class="comment">/* PIO3mode 2, IORDY off,3Prefetch off */./spa  >L108" class="line" namon>L108">3108./a>        { 0x27, 0x0d, 0x35 },   .spa  class="comment">/* PIO3mode 3, IORDY on, 3Prefetch off */./spa  >L109" class="line" namon>L109">3109./a>        { 0x23, 0x09, 0x25 },   .spa  class="comment">/* PIO3mode 4, IORDY on, 3Prefetch off */./spa  >L110" class="line" namon>L110">31.18.a>};>L111" class="line" namon>L111">3111./a>>L112" class="line" namon>L112">3112./a>static3struct3.a href="+code=mwdma_timing" class="sref">mwdma_timing./a> {>L113" class="line" namon>L113">3113./a>        .a href="+code=u8" class="sref">u8./a> .a href="+code=reg0o" class="sref">reg0o./a>,3.a href="+code=reg0f" class="sref">reg0f./a>;>L114" class="line" namon>L114">3114./a>}3.a href="+code=mwdma_timings" class="sref">mwdma_timings./a> [] = {>L115" class="line" namon>L115">3115./a>        { 0xdf, 0x5f },         .spa  class="comment">/* MWDMA3mode 0 */./spa  >L116" class="line" namon>L116">3116./a>        { 0x6b, 0x27 },         .spa  class="comment">/* MWDMA3mode 1 */./spa  >L117" class="line" namon>L117">3117./a>        { 0x69, 0x25 },         .spa  class="comment">/* MWDMA3mode 2 */./spa  >L118" class="line" namon>L118">3118./a>};>L119" class="line" namon>L119">3119./a>>L120" class="line" namon>L120">3120./a>static3struct3.a href="+code=udma_timing" class="sref">udma_timing./a> {>L121" class="line" namon>L121">3121./a>        .a href="+code=u8" class="sref">u8./a> .a href="+code=reg10" class="sref">reg10./a>,3.a href="+code=reg11" class="sref">reg11./a>,3.a href="+code=reg12" class="sref">reg12./a>;>L122" class="line" namon>L122">3122./a>}3.a href="+code=udma_timings" class="sref">udma_timings./a> [] = {>L123" class="line" namon>L123">3123./a>        { 0x4a, 0x0f, 0xd5 },   .spa  class="comment">/* UDMA3mode 0 */./spa  >L124" class="line" namon>L124">3124./a>        { 0x3a, 0x0a, 0xd0 },   .spa  class="comment">/* UDMA3mode 1 */./spa  >L125" class="line" namon>L125">3125./a>        { 0x2a, 0x07, 0xcd },   .spa  class="comment">/* UDMA3mode 2 */./spa  >L126" class="line" namon>L126">3126./a>        { 0x1a, 0x05, 0xcd },   .spa  class="comment">/* UDMA3mode 3 */./spa  >L127" class="line" namon>L127">3127./a>        { 0x1a, 0x03, 0xcd },   .spa  class="comment">/* UDMA3mode 4 */./spa  >L128" class="line" namon>L128">3128./a>        { 0x1a, 0x02, 0xcb },   .spa  class="comment">/* UDMA3mode 5 */./spa  >L129" class="line" namon>L129">3129./a>        { 0x1a, 0x01, 0xcb },   .spa  class="comment">/* UDMA3mode 6 */./spa  >L130" class="line" namon>L130">31318.a>};>L131" class="line" namon>L131">3131./a>>L132" class="line" namon>L132">3132./a>static3void .a href="+code=pdcnew_set_dma_mode" class="sref">pdcnew_set_dma_mode./a>(.a href="+code=ide_hwif_t" class="sref">ide_hwif_t./a> *.a href="+code=hwif" class="sref">hwif./a>,3.a href="+code=ide_drive_t" class="sref">ide_drive_t./a> *.a href="+code=drive" class="sref">drive./a>)>L133" class="line" namon>L133">3133./a>{>L134" class="line" namon>L134">3134./a>        struct3.a href="+code=pci_dev" class="sref">pci_dev./a> *.a href="+code=dev" class="sref">dev./a>     = .a href="+code=to_pci_dev" class="sref">to_pci_dev./a>(.a href="+code=hwif" class="sref">hwif./a>->.a href="+code=dev" class="sref">dev./a>);>L135" class="line" namon>L135">3135./a>        .a href="+code=u8" class="sref">u8./a> .a href="+code=adj" class="sref">adj./a>                  = (.a href="+code=drive" class="sref">drive./a>->.a href="+code=dn" class="sref">dn./a> & 1) ? 0x08 : 0x00;>L136" class="line" namon>L136">3136./a>        const3.a href="+code=u8" class="sref">u8./a> .a href="+code=speed" class="sref">speed./a>          = .a href="+code=drive" class="sref">drive./a>->.a href="+code=dma_mode" class="sref">dma_mode./a>;>L137" class="line" namon>L137">3137./a>>L138" class="line" namon>L138">3138./a>        .spa  class="comment">/*./spa  >L139" class="line" namon>L139">3139./a>.spa  class="comment">         * IDE corevissues SETFEATURES_XFER to the drive first3(thanks to./spa  >L140" class="line" namon>L140">3140./a>.spa  class="comment">         * IDE_HFLAG_POST_SET_MODE in ->host_flags).  PDC202xx hardware will./spa  >L141" class="line" namon>L141">3141./a>.spa  class="comment">         * automatically set the timing registers based on 100 MHz PLL output../spa  >L142" class="line" namon>L142">3142./a>.spa  class="comment">         *./spa  >L143" class="line" namon>L143">3143./a>.spa  class="comment">         * As we set up the PLL to output 133 MHz for UltraDMA/133 capable./spa  >L144" class="line" namon>L144">3144./a>.spa  class="comment">         * chips, we must override the default register settings..../spa  >L145" class="line" namon>L145">3145./a>.spa  class="comment">         */./spa  >L146" class="line" namon>L146">3146./a>        if (.a href="+code=max_dma_rate" class="sref">max_dma_rate./a>(.a href="+code=dev" class="sref">dev./a>) == 4) {>L147" class="line" namon>L147">3147./a>                .a href="+code=u8" class="sref">u8./a> .a href="+code=mode" class="sref">mode./a> = .a href="+code=speed" class="sref">speed./a> & 0x07;>L148" class="line" namon>L148">3148./a>>L149" class="line" namon>L149">3149./a>                if (.a href="+code=speed" class="sref">speed./a> >= .a href="+code=XFER_UDMA_0" class="sref">XFER_UDMA_0./a>) {>L150" class="line" namon>L150">3150./a>                        .a href="+code=set_indexed_reg" class="sref">set_indexed_reg./a>(.a href="+code=hwif" class="sref">hwif./a>,30x10 + .a href="+code=adj" class="sref">adj./a>,>L151" class="line" namon>L151">3151./a>                                        .a href="+code=udma_timings" class="sref">udma_timings./a>[.a href="+code=mode" class="sref">mode./a>]..a href="+code=reg10" class="sref">reg10./a>);>L152" class="line" namon>L152">3152./a>                        .a href="+code=set_indexed_reg" class="sref">set_indexed_reg./a>(.a href="+code=hwif" class="sref">hwif./a>,30x11 + .a href="+code=adj" class="sref">adj./a>,>L153" class="line" namon>L153">3153./a>                                        .a href="+code=udma_timings" class="sref">udma_timings./a>[.a href="+code=mode" class="sref">mode./a>]..a href="+code=reg11" class="sref">reg11./a>);>L154" class="line" namon>L154">3154./a>                        .a href="+code=set_indexed_reg" class="sref">set_indexed_reg./a>(.a href="+code=hwif" class="sref">hwif./a>,30x12 + .a href="+code=adj" class="sref">adj./a>,>L155" class="line" namon>L155">3155./a>                                        .a href="+code=udma_timings" class="sref">udma_timings./a>[.a href="+code=mode" class="sref">mode./a>]..a href="+code=reg12" class="sref">reg12./a>);>L156" class="line" namon>L156">3156./a>                } else {>L157" class="line" namon>L157">3157./a>                        .a href="+code=set_indexed_reg" class="sref">set_indexed_reg./a>(.a href="+code=hwif" class="sref">hwif./a>,30x0e + .a href="+code=adj" class="sref">adj./a>,>L158" class="line" namon>L158">3158./a>                                        .a href="+code=mwdma_timings" class="sref">mwdma_timings./a>[.a href="+code=mode" class="sref">mode./a>]..a href="+code=reg0o" class="sref">reg0o./a>);>L159" class="line" namon>L159">3159./a>                        .a href="+code=set_indexed_reg" class="sref">set_indexed_reg./a>(.a href="+code=hwif" class="sref">hwif./a>,30x0f + .a href="+code=adj" class="sref">adj./a>,>L160" class="line" namon>L160">3160./a>                                        .a href="+code=mwdma_timings" class="sref">mwdma_timings./a>[.a href="+code=mode" class="sref">mode./a>]..a href="+code=reg0f" class="sref">reg0f./a>);>L161" class="line" namon>L161">3161./a>                }>L162" class="line" namon>L162">3162./a>        } else if (.a href="+code=speed" class="sref">speed./a> == .a href="+code=XFER_UDMA_2" class="sref">XFER_UDMA_2./a>) {>L163" class="line" namon>L163">3163./a>                .spa  class="comment">/* Set tHOLD bit to 0 if using UDMA3mode 2 */./spa  >L164" class="line" namon>L164">3164./a>                .a href="+code=u8" class="sref">u8./a> .a href="+code=tmp" class="sref">tmp./a> = .a href="+code=get_indexed_reg" class="sref">get_indexed_reg./a>(.a href="+code=hwif" class="sref">hwif./a>,30x10 + .a href="+code=adj" class="sref">adj./a>);>L165" class="line" namon>L165">3165./a>>L166" class="line" namon>L166">3166./a>                .a href="+code=set_indexed_reg" class="sref">set_indexed_reg./a>(.a href="+code=hwif" class="sref">hwif./a>,30x10 + .a href="+code=adj" class="sref">adj./a>, .a href="+code=tmp" class="sref">tmp./a> & 0x7f);>L167" class="line" namon>L167">3167./a>        }>L168" class="line" namon>L168">3168./a>}>L169" class="line" namon>L169">3169./a>>L170" class="line" namon>L170">3170./a>static3void .a href="+code=pdcnew_set_pio_mode" class="sref">pdcnew_set_pio_mode./a>(.a href="+code=ide_hwif_t" class="sref">ide_hwif_t./a> *.a href="+code=hwif" class="sref">hwif./a>,3.a href="+code=ide_drive_t" class="sref">ide_drive_t./a> *.a href="+code=drive" class="sref">drive./a>)>L171" class="line" namon>L171">3171./a>{>L172" class="line" namon>L172">3172./a>        struct3.a href="+code=pci_dev" class="sref">pci_dev./a> *.a href="+code=dev" class="sref">dev./a> = .a href="+code=to_pci_dev" class="sref">to_pci_dev./a>(.a href="+code=hwif" class="sref">hwif./a>->.a href="+code=dev" class="sref">dev./a>);>L173" class="line" namon>L173">3173./a>        .a href="+code=u8" class="sref">u8./a> .a href="+code=adj" class="sref">adj./a> = (.a href="+code=drive" class="sref">drive./a>->.a href="+code=dn" class="sref">dn./a> & 1) ? 0x08 : 0x00;>L174" class="line" namon>L174">3174./a>        const3.a href="+code=u8" class="sref">u8./a> .a href="+code=pio" class="sref">pio./a> = .a href="+code=drive" class="sref">drive./a>->.a href="+code=pio_mode" class="sref">pio_mode./a> - .a href="+code=XFER_PIO_0" class="sref">XFER_PIO_0./a>;>L175" class="line" namon>L175">3175./a>>L176" class="line" namon>L176">3176./a>        if (.a href="+code=max_dma_rate" class="sref">max_dma_rate./a>(.a href="+code=dev" class="sref">dev./a>) == 4) {>L177" class="line" namon>L177">3177./a>                .a href="+code=set_indexed_reg" class="sref">set_indexed_reg./a>(.a href="+code=hwif" class="sref">hwif./a>,30x0c + .a href="+code=adj" class="sref">adj./a>, .a href="+code=pio_timings" class="sref">pio_timings./a>[.a href="+code=pio" class="sref">pio./a>]..a href="+code=reg0c" class="sref">reg0c./a>);>L178" class="line" namon>L178">3178./a>                .a href="+code=set_indexed_reg" class="sref">set_indexed_reg./a>(.a href="+code=hwif" class="sref">hwif./a>,30x0d + .a href="+code=adj" class="sref">adj./a>, .a href="+code=pio_timings" class="sref">pio_timings./a>[.a href="+code=pio" class="sref">pio./a>]..a href="+code=reg0d" class="sref">reg0d./a>);>L179" class="line" namon>L179">3179./a>                .a href="+code=set_indexed_reg" class="sref">set_indexed_reg./a>(.a href="+code=hwif" class="sref">hwif./a>,30x13 + .a href="+code=adj" class="sref">adj./a>, .a href="+code=pio_timings" class="sref">pio_timings./a>[.a href="+code=pio" class="sref">pio./a>]..a href="+code=reg13" class="sref">reg13./a>);>L180" class="line" namon>L180">3180./a>        }>L181" class="line" namon>L181">3181./a>}>L182" class="line" namon>L182">3182./a>>L183" class="line" namon>L183">3183./a>static3.a href="+code=u8" class="sref">u8./a> .a href="+code=pdcnew_cable_detect" class="sref">pdcnew_cable_detect./a>(.a href="+code=ide_hwif_t" class="sref">ide_hwif_t./a> *.a href="+code=hwif" class="sref">hwif./a>)>L184" class="line" namon>L184">3184./a>{>L185" class="line" namon>L185">3185./a>        if (.a href="+code=get_indexed_reg" class="sref">get_indexed_reg./a>(.a href="+code=hwif" class="sref">hwif./a>,30x0b) & 0x04)>L186" class="line" namon>L186">3186./a>                return .a href="+code=ATA_CBL_PATA40" class="sref">ATA_CBL_PATA40./a>;>L187" class="line" namon>L187">3187./a>        else>L188" class="line" namon>L188">3188./a>                return .a href="+code=ATA_CBL_PATA80" class="sref">ATA_CBL_PATA80./a>;>L189" class="line" namon>L189">3189./a>}>L190" class="line" namon>L190">3190./a>>L191" class="line" namon>L191">3191./a>static3void .a href="+code=pdcnew_reset" class="sref">pdcnew_reset./a>(.a href="+code=ide_drive_t" class="sref">ide_drive_t./a> *.a href="+code=drive" class="sref">drive./a>)>L192" class="line" namon>L192">3192./a>{>L193" class="line" namon>L193">3193./a>        .spa  class="comment">/*./spa  >L194" class="line" namon>L194">3194./a>.spa  class="comment">         * Deleted this because it is redundant from the caller../spa  >L195" class="line" namon>L195">3195./a>.spa  class="comment">         */./spa  >L196" class="line" namon>L196">3196./a>        .a href="+code=printk" class="sref">printk./a>(.a href="+code=KERN_WARNING" class="sref">KERN_WARNING./a> .spa  class="string">"pdc202xx_new: %s channel reset.\n"./spa  ,>L197" class="line" namon>L197">3197./a>                .a href="+code=drive" class="sref">drive./a>->.a href="+code=hwif" class="sref">hwif./a>->.a href="+code=channel" class="sref">channel./a> ? .spa  class="string">"Secondary"./spa  3: .spa  class="string">"Primary"./spa  );>L198" class="line" namon>L198">3198./a>}>L199" class="line" namon>L199">3199./a>>L200" class="line" namon>L200">3200./a>.spa  class="comment">/**./spa  >L201" class="line" namon>L201">3201./a>.spa  class="comment"> * read_counter - Read the byte count registers./spa  >L202" class="line" namon>L202">3202./a>.spa  class="comment"> * @dma_base: for the port address./spa  >L203" class="line" namon>L203">3203./a>.spa  class="comment"> */./spa  >L204" class="line" namon>L204">3204./a>static3long3.a href="+code=read_counter" class="sref">read_counter./a>(.a href="+code=u32" class="sref">u32./a> .a href="+code=dma_base" class="sref">dma_base./a>)>L205" class="line" namon>L205">3205./a>{>L206" class="line" namon>L206">3206./a>        .a href="+code=u32" class="sref">u32./a>  .a href="+code=pri_dma_base" class="sref">pri_dma_base./a> = .a href="+code=dma_base" class="sref">dma_base./a>, .a href="+code=sec_dma_base" class="sref">sec_dma_base./a> = .a href="+code=dma_base" class="sref">dma_base./a> + 0x08;>L207" class="line" namon>L207">3207./a>        .a href="+code=u8" class="sref">u8./a>   .a href="+code=cnt0" class="sref">cnt0./a>, .a href="+code=cnt1" class="sref">cnt1./a>, .a href="+code=cnt2" class="sref">cnt2./a>, .a href="+code=cnt3" class="sref">cnt3./a>;>L208" class="line" namon>L208">3208./a>        long3.a href="+code=count" class="sref">count./a> = 0, .a href="+code=last" class="sref">last./a>;>L209" class="line" namon>L209">3209./a>        int  .a href="+code=retry" class="sref">retry./a> = 3;>L210" class="line" namon>L210">3210./a>>L211" class="line" namon>L211">3211./a>        do {>L212" class="line" namon>L212">3212./a>                .a href="+code=last" class="sref">last./a> = .a href="+code=count" class="sref">count./a>;>L213" class="line" namon>L213">3213./a>>L214" class="line" namon>L214">3214./a>                .spa  class="comment">/* Read the current count */./spa  >L215" class="line" namon>L215">3215./a>                .a href="+code=outb" class="sref">outb./a>(0x20, .a href="+code=pri_dma_base" class="sref">pri_dma_base./a> + 0x01);>L216" class="line" namon>L216">3216./a>                .a href="+code=cnt0" class="sref">cnt0./a> = .a href="+code=inb" class="sref">inb./a>(.a href="+code=pri_dma_base" class="sref">pri_dma_base./a> + 0x03);>L217" class="line" namon>L217">3217./a>                .a href="+code=outb" class="sref">outb./a>(0x21, .a href="+code=pri_dma_base" class="sref">pri_dma_base./a> + 0x01);>L218" class="line" namon>L218">3218./a>                .a href="+code=cnt1" class="sref">cnt1./a> = .a href="+code=inb" class="sref">inb./a>(.a href="+code=pri_dma_base" class="sref">pri_dma_base./a> + 0x03);>L219" class="line" namon>L219">3219./a>                .a href="+code=outb" class="sref">outb./a>(0x20, .a href="+code=sec_dma_base" class="sref">sec_dma_base./a> + 0x01);>L220" class="line" namon>L220">3220./a>                .a href="+code=cnt2" class="sref">cnt2./a> = .a href="+code=inb" class="sref">inb./a>(.a href="+code=sec_dma_base" class="sref">sec_dma_base./a> + 0x03);>L221" class="line" namon>L221">3221./a>                .a href="+code=outb" class="sref">outb./a>(0x21, .a href="+code=sec_dma_base" class="sref">sec_dma_base./a> + 0x01);>L222" class="line" namon>L222">3222./a>                .a href="+code=cnt3" class="sref">cnt3./a> = .a href="+code=inb" class="sref">inb./a>(.a href="+code=sec_dma_base" class="sref">sec_dma_base./a> + 0x03);>L223" class="line" namon>L223">3223./a>>L224" class="line" namon>L224">3224./a>                .a href="+code=count" class="sref">count./a> = (.a href="+code=cnt3" class="sref">cnt3./a> << 23) | (.a href="+code=cnt2" class="sref">cnt2./a> << 15) | (.a href="+code=cnt1" class="sref">cnt1./a> << 8) | .a href="+code=cnt0" class="sref">cnt0./a>;>L225" class="line" namon>L225">3225./a>>L226" class="line" namon>L226">3226./a>                .spa  class="comment">/*./spa  >L227" class="line" namon>L227">3227./a>.spa  class="comment">                 * The 30-bit decrementing counter is read in 4 pieces../spa  >L228" class="line" namon>L228">3228./a>.spa  class="comment">                 * Incorrect optio may be read when the most significant bytes./spa  >L229" class="line" namon>L229">3229./a>.spa  class="comment">                 * are changing..../spa  >L230" class="line" namon>L230">3230./a>.spa  class="comment">                 */./spa  >L231" class="line" namon>L231">3231./a>        } while (.a href="+code=retry" class="sref">retry./a>-- && (((.a href="+code=last" class="sref">last./a> ^ .a href="+code=count" class="sref">count./a>) & 0x3fff8000) || .a href="+code=last" class="sref">last./a> < .a href="+code=count" class="sref">count./a>));>L232" class="line" namon>L232">3232./a>>L233" class="line" namon>L233">3233./a>        .a href="+code=DBG" class="sref">DBG./a>(.spa  class="string">"cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n"./spa  ,>L234" class="line" namon>L234">3234./a>                  .a href="+code=cnt0" class="sref">cnt0./a>, .a href="+code=cnt1" class="sref">cnt1./a>, .a href="+code=cnt2" class="sref">cnt2./a>, .a href="+code=cnt3" class="sref">cnt3./a>);>L235" class="line" namon>L235">3235./a>>L236" class="line" namon>L236">3236./a>        return .a href="+code=count" class="sref">count./a>;>L237" class="line" namon>L237">3237./a>}>L238" class="line" namon>L238">3238./a>>L239" class="line" namon>L239">3239./a>.spa  class="comment">/**./spa  >L240" class="line" namon>L240">3240./a>.spa  class="comment"> * detect_pll_input_clock - Detect the PLL input clock in Hz../spa  >L241" class="line" namon>L241">3241./a>.spa  class="comment"> * @dma_base: for the port address./spa  >L242" class="line" namon>L242">3242./a>.spa  class="comment"> * E.g.316949000 on 33 MHz PCI bus, i.e. half of the PCI clock../spa  >L243" class="line" namon>L243">3243./a>.spa  class="comment"> */./spa  >L244" class="line" namon>L244">3244./a>static3long3.a href="+code=detect_pll_input_clock" class="sref">detect_pll_input_clock./a>(unsigned3long3.a href="+code=dma_base" class="sref">dma_base./a>)>L245" class="line" namon>L245">3245./a>{>L246" class="line" namon>L246">3246./a>        struct3.a href="+code=timeopt" class="sref">timeopt./a> .a href="+code=start_time" class="sref">start_time./a>, .a href="+code=end_time" class="sref">end_time./a>;>L247" class="line" namon>L247">3247./a>        long3.a href="+code=start_count" class="sref">start_count./a>, .a href="+code=end_count" class="sref">end_count./a>;>L248" class="line" namon>L248">3248./a>        long3.a href="+code=pll_input" class="sref">pll_input./a>, .a href="+code=usec_elapsed" class="sref">usec_elapsed./a>;>L249" class="line" namon>L249">3249./a>        .a href="+code=u8" class="sref">u8./a> .a href="+code=scr1" class="sref">scr1./a>;>L250" class="line" namon>L250">3250./a>>L251" class="line" namon>L251">3251./a>        .a href="+code=start_count" class="sref">start_count./a> = .a href="+code=read_counter" class="sref">read_counter./a>(.a href="+code=dma_base" class="sref">dma_base./a>);>L252" class="line" namon>L252">3252./a>        .a href="+code=do_gettimeofday" class="sref">do_gettimeofday./a>(&.a href="+code=start_time" class="sref">start_time./a>);>L253" class="line" namon>L253">3253./a>>L254" class="line" namon>L254">3254./a>        .spa  class="comment">/* Start the test3mode */./spa  >L255" class="line" namon>L255">3255./a>        .a href="+code=outb" class="sref">outb./a>(0x01, .a href="+code=dma_base" class="sref">dma_base./a> + 0x01);>L256" class="line" namon>L256">3256./a>        .a href="+code=scr1" class="sref">scr1./a> = .a href="+code=inb" class="sref">inb./a>(.a href="+code=dma_base" class="sref">dma_base./a> + 0x03);>L257" class="line" namon>L257">3257./a>        .a href="+code=DBG" class="sref">DBG./a>(.spa  class="string">"scr1[%02X]\n"./spa  ,3.a href="+code=scr1" class="sref">scr1./a>);>L258" class="line" namon>L258">3258./a>        .a href="+code=outb" class="sref">outb./a>(.a href="+code=scr1" class="sref">scr1./a> | 0x40, .a href="+code=dma_base" class="sref">dma_base./a> + 0x03);>L259" class="line" namon>L259">3259./a>>L260" class="line" namon>L260">3260./a>        .spa  class="comment">/* Let the counter run for 10 ms. */./spa  >L261" class="line" namon>L261">3261./a>        .a href="+code=mdelay" class="sref">mdelay./a>(10);>L262" class="line" namon>L262">3262./a>>L263" class="line" namon>L263">3263./a>        .a href="+code=end_count" class="sref">end_count./a> = .a href="+code=read_counter" class="sref">read_counter./a>(.a href="+code=dma_base" class="sref">dma_base./a>);>L264" class="line" namon>L264">3264./a>        .a href="+code=do_gettimeofday" class="sref">do_gettimeofday./a>(&.a href="+code=end_time" class="sref">end_time./a>);>L265" class="line" namon>L265">3265./a>>L266" class="line" namon>L266">3266./a>        .spa  class="comment">/* Stop the test3mode */./spa  >L267" class="line" namon>L267">3267./a>        .a href="+code=outb" class="sref">outb./a>(0x01, .a href="+code=dma_base" class="sref">dma_base./a> + 0x01);>L268" class="line" namon>L268">3268./a>        .a href="+code=scr1" class="sref">scr1./a> = .a href="+code=inb" class="sref">inb./a>(.a href="+code=dma_base" class="sref">dma_base./a> + 0x03);>L269" class="line" namon>L269">3269./a>        .a href="+code=DBG" class="sref">DBG./a>(.spa  class="string">"scr1[%02X]\n"./spa  ,3.a href="+code=scr1" class="sref">scr1./a>);>L270" class="line" namon>L270">3270./a>        .a href="+code=outb" class="sref">outb./a>(.a href="+code=scr1" class="sref">scr1./a> & ~0x40, .a href="+code=dma_base" class="sref">dma_base./a> + 0x03);>L271" class="line" namon>L271">3271./a>>L272" class="line" namon>L272">3272./a>        .spa  class="comment">/*./spa  >L273" class="line" namon>L273">3273./a>.spa  class="comment">         * Calculate the input clock in Hz./spa  >L274" class="line" namon>L274">3274./a>.spa  class="comment">         * (the clock counter is 30 bit wide and counts down)./spa  >L275" class="line" namon>L275">3275./a>.spa  class="comment">         */./spa  >L276" class="line" namon>L276">3276./a>        .a href="+code=usec_elapsed" class="sref">usec_elapsed./a> = (.a href="+code=end_time" class="sref">end_time./a>..a href="+code=tv_sec" class="sref">tv_sec./a> - .a href="+code=start_time" class="sref">start_time./a>..a href="+code=tv_sec" class="sref">tv_sec./a>) * 1000000 +>L277" class="line" namon>L277">3277./a>                (.a href="+code=end_time" class="sref">end_time./a>..a href="+code=tv_usec" class="sref">tv_usec./a> - .a href="+code=start_time" class="sref">start_time./a>..a href="+code=tv_usec" class="sref">tv_usec./a>);>L278" class="line" namon>L278">3278./a>        .a href="+code=pll_input" class="sref">pll_input./a> = ((.a href="+code=start_count" class="sref">start_count./a> - .a href="+code=end_count" class="sref">end_count./a>) & 0x3fffffff) / 10 *>L279" class="line" namon>L279">3279./a>                (10000000 / .a href="+code=usec_elapsed" class="sref">usec_elapsed./a>);>L280" class="line" namon>L280">3280./a>>L281" class="line" namon>L281">3281./a>        .a href="+code=DBG" class="sref">DBG./a>(.spa  class="string">"start[%ld] end[%ld]\n"./spa  ,3.a href="+code=start_count" class="sref">start_count./a>, .a href="+code=end_count" class="sref">end_count./a>);>L282" class="line" namon>L282">3282./a>>L283" class="line" namon>L283">3283./a>        return .a href="+code=pll_input" class="sref">pll_input./a>;>L284" class="line" namon>L284">3284./a>}>L285" class="line" namon>L285">3285./a>>L286" class="line" namon>L286">3286./a>#ifdef .a href="+code=CONFIG_PPC_PMAC" class="sref">CONFIG_PPC_PMAC./a>>L287" class="line" namon>L287">3287./a>static3void .a href="+code=apple_kiwi_init" class="sref">apple_kiwi_init./a>(struct3.a href="+code=pci_dev" class="sref">pci_dev./a> *.a href="+code=pdev" class="sref">pdev./a>)>L288" class="line" namon>L288">3288./a>{>L289" class="line" namon>L289">3289./a>        struct3.a href="+code=device_node" class="sref">device_node./a> *.a href="+code=np" class="sref">np./a> = .a href="+code=pci_device_to_OF_node" class="sref">pci_device_to_OF_node./a>(.a href="+code=pdev" class="sref">pdev./a>);>L290" class="line" namon>L290">3290./a>        .a href="+code=u8" class="sref">u8./a> .a href="+code=conf" class="sref">conf./a>;>L291" class="line" namon>L291">3291./a>>L292" class="line" namon>L292">3292./a>        if (.a href="+code=np" class="sref">np./a> == .a href="+code=NULL" class="sref">NULL./a> || !.a href="+code=of_device_is_compatible" class="sref">of_device_is_compatible./a>(.a href="+code=np" class="sref">np./a>, .spa  class="string">"kiwi-root"./spa  ))>L293" class="line" namon>L293">3293./a>                return;>L294" class="line" namon>L294">3294./a>>L295" class="line" namon>L295">3295./a>        if (.a href="+code=pdev" class="sref">pdev./a>->.a href="+code=revision" class="sref">revision./a> >= 0x03) {>L296" class="line" namon>L296">3296./a>                .spa  class="comment">/* Setup chip magic3config stuff (from darwin) */./spa  >L297" class="line" namon>L297">3297./a>                .a href="+code=pci_read_config_byte" class="sref">pci_read_config_byte./a> (.a href="+code=pdev" class="sref">pdev./a>, 0x40, &.a href="+code=conf" class="sref">conf./a>);>L298" class="line" namon>L298">3298./a>                .a href="+code=pci_write_config_byte" class="sref">pci_write_config_byte./a>(.a href="+code=pdev" class="sref">pdev./a>, 0x40, (.a href="+code=conf" class="sref">conf./a> | 0x01));>L299" class="line" namon>L299">3299./a>        }>L300" class="line" namon>L300">3300./a>}>L301" class="line" namon>L301">3301./a>#endif .spa  class="comment">/* CONFIG_PPC_PMAC */./spa  >L302" class="line" namon>L302">3302./a>>L303" class="line" namon>L303">3303./a>static3int .a href="+code=init_chipset_pdcnew" class="sref">init_chipset_pdcnew./a>(struct3.a href="+code=pci_dev" class="sref">pci_dev./a> *.a href="+code=dev" class="sref">dev./a>)>L304" class="line" namon>L304">3304./a>{>L305" class="line" namon>L305">3305./a>        const3char *.a href="+code=name" class="sref">name./a> = .a href="+code=DRV_NAME" class="sref">DRV_NAME./a>;>L306" class="line" namon>L306">3306./a>        unsigned3long3.a href="+code=dma_base" class="sref">dma_base./a> = .a href="+code=pci_resource_start" class="sref">pci_resource_start./a>(.a href="+code=dev" class="sref">dev./a>, 4);>L307" class="line" namon>L307">3307./a>        unsigned3long3.a href="+code=sec_dma_base" class="sref">sec_dma_base./a> = .a href="+code=dma_base" class="sref">dma_base./a> + 0x08;>L308" class="line" namon>L308">3308./a>        long3.a href="+code=pll_input" class="sref">pll_input./a>, .a href="+code=pll_output" class="sref">pll_output./a>, .a href="+code=ratio" class="sref">ratio./a>;>L309" class="line" namon>L309">3309./a>        int .a href="+code=f" class="sref">f./a>,3.a href="+code=r" class="sref">r./a>;>L310" class="line" namon>L310">3310./a>        .a href="+code=u8" class="sref">u8./a> .a href="+code=pll_ctl0" class="sref">pll_ctl0./a>, .a href="+code=pll_ctl1" class="sref">pll_ctl1./a>;>L311" class="line" namon>L311">3311./a>>L312" class="line" namon>L312">3312./a>        if (.a href="+code=dma_base" class="sref">dma_base./a> == 0)>L313" class="line" namon>L313">3313./a>                return -.a href="+code=EFAULT" class="sref">EFAULT./a>;>L314" class="line" namon>L314">3314./a>>L315" class="line" namon>L315">3315./a>#ifdef .a href="+code=CONFIG_PPC_PMAC" class="sref">CONFIG_PPC_PMAC./a>>L316" class="line" namon>L316">3316./a>        .a href="+code=apple_kiwi_init" class="sref">apple_kiwi_init./a>(.a href="+code=dev" class="sref">dev./a>);>L317" class="line" namon>L317">3317./a>#endif>L318" class="line" namon>L318">3318./a>>L319" class="line" namon>L319">3319./a>        .spa  class="comment">/* Calculate the required3PLL output frequency */./spa  >L320" class="line" namon>L320">3320./a>        switch(.a href="+code=max_dma_rate" class="sref">max_dma_rate./a>(.a href="+code=dev" class="sref">dev./a>)) {>L321" class="line" namon>L321">3321./a>                case 4: .spa  class="comment">/* it's 133 MHz for Ultra133 chips */./spa  >L322" class="line" namon>L322">3322./a>                        .a href="+code=pll_output" class="sref">pll_output./a> = 133333333;>L323" class="line" namon>L323">3323./a>                        break;>L324" class="line" namon>L324">3324./a>                case 3: .spa  class="comment">/* and  100 MHz for Ultra100 chips */./spa  >L325" class="line" namon>L325">3325./a>                default:>L326" class="line" namon>L326">3326./a>                        .a href="+code=pll_output" class="sref">pll_output./a> = 100000000;>L327" class="line" namon>L327">3327./a>                        break;>L328" class="line" namon>L328">3328./a>        }>L329" class="line" namon>L329">3329./a>>L330" class="line" namon>L330">3330./a>        .spa  class="comment">/*./spa  >L331" class="line" namon>L331">3331./a>.spa  class="comment">         * Detect PLL input clock../spa  >L332" class="line" namon>L332">3332./a>.spa  class="comment">         * On some systems, where PCI bus is running at non-standard clock rate./spa  >L333" class="line" namon>L333">3333./a>.spa  class="comment">         * (e.g.325 or 40 MHz), we have to adjust the cycle time../spa  >L334" class="line" namon>L334">3334./a>.spa  class="comment">         * PDC20268 and newer chips employ PLL circuit to help correct timing./spa  >L335" class="line" namon>L335">3335./a>.spa  class="comment">         * registers setting../spa  >L336" class="line" namon>L336">3336./a>.spa  class="comment">         */./spa  >L337" class="line" namon>L337">3337./a>        .a href="+code=pll_input" class="sref">pll_input./a> = .a href="+code=detect_pll_input_clock" class="sref">detect_pll_input_clock./a>(.a href="+code=dma_base" class="sref">dma_base./a>);>L338" class="line" namon>L338">3338./a>        .a href="+code=printk" class="sref">printk./a>(.a href="+code=KERN_INFO" class="sref">KERN_INFO./a> .spa  class="string">"%s %s: PLL input clock is %ld kHz\n"./spa  ,>L339" class="line" namon>L339">3339./a>                .a href="+code=name" class="sref">name./a>, .a href="+code=pci_name" class="sref">pci_name./a>(.a href="+code=dev" class="sref">dev./a>), .a href="+code=pll_input" class="sref">pll_input./a> / 1000);>L340" class="line" namon>L340">3340./a>>L341" class="line" namon>L341">3341./a>        .spa  class="comment">/* Sanity check */./spa  >L342" class="line" namon>L342">3342./a>        if (.a href="+code=unlikely" class="sref">unlikely./a>(.a href="+code=pll_input" class="sref">pll_input./a> < 5000000L || .a href="+code=pll_input" class="sref">pll_input./a> > 70000000L)) {>L343" class="line" namon>L343">3343./a>                .a href="+code=printk" class="sref">printk./a>(.a href="+code=KERN_ERR" class="sref">KERN_ERR./a> .spa  class="string">"%s %s: Bad PLL input clock %ld Hz, giving up!"./spa  >L344" class="line" namon>L344">3344./a>                        .spa  class="string">"\n"./spa  ,3.a href="+code=name" class="sref">name./a>, .a href="+code=pci_name" class="sref">pci_name./a>(.a href="+code=dev" class="sref">dev./a>), .a href="+code=pll_input" class="sref">pll_input./a>);>L345" class="line" namon>L345">3345./a>                goto .a href="+code=out" class="sref">out./a>;>L346" class="line" namon>L346">3346./a>        }>L347" class="line" namon>L347">3347./a>>L348" class="line" namon>L348">3348./a>#ifdef .a href="+code=DEBUG" class="sref">DEBUG./a>>L349" class="line" namon>L349">3349./a>        .a href="+code=DBG" class="sref">DBG./a>(.spa  class="string">"pll_output is %ld Hz\n"./spa  , .a href="+code=pll_output" class="sref">pll_output./a>);>L350" class="line" namon>L350">3350./a>>L351" class="line" namon>L351">3351./a>        .spa  class="comment">/* Show the current clock optio of PLL control register./spa  >L352" class="line" namon>L352">3352./a>.spa  class="comment">         * (maybe already3configured3by the BIOS)./spa  >L353" class="line" namon>L353">3353./a>.spa  class="comment">         */./spa  >L354" class="line" namon>L354">3354./a>        .a href="+code=outb" class="sref">outb./a>(0x02, .a href="+code=sec_dma_base" class="sref">sec_dma_base./a> + 0x01);>L355" class="line" namon>L355">3355./a>        .a href="+code=pll_ctl0" class="sref">pll_ctl0./a> = .a href="+code=inb" class="sref">inb./a>(.a href="+code=sec_dma_base" class="sref">sec_dma_base./a> + 0x03);>L356" class="line" namon>L356">3356./a>        .a href="+code=outb" class="sref">outb./a>(0x03, .a href="+code=sec_dma_base" class="sref">sec_dma_base./a> + 0x01);>L357" class="line" namon>L357">3357./a>        .a href="+code=pll_ctl1" class="sref">pll_ctl1./a> = .a href="+code=inb" class="sref">inb./a>(.a href="+code=sec_dma_base" class="sref">sec_dma_base./a> + 0x03);>L358" class="line" namon>L358">3358./a>>L359" class="line" namon>L359">3359./a>        .a href="+code=DBG" class="sref">DBG./a>(.spa  class="string">"pll_ctl[%02X][%02X]\n"./spa  ,3.a href="+code=pll_ctl0" class="sref">pll_ctl0./a>, .a href="+code=pll_ctl1" class="sref">pll_ctl1./a>);>L360" class="line" namon>L360">3360./a>#endif>L361" class="line" namon>L361">3361./a>>L362" class="line" namon>L362">3362./a>        .spa  class="comment">/*./spa  >L363" class="line" namon>L363">3363./a>.spa  class="comment">         * Calculate the ratio of F, R and NO./spa  >L364" class="line" namon>L364">3364./a>.spa  class="comment">         * POUT = (F + 2) / (( R + 2) * NO)./spa  >L365" class="line" namon>L365">3365./a>.spa  class="comment">         */./spa  >L366" class="line" namon>L366">3366./a>        .a href="+code=ratio" class="sref">ratio./a> = .a href="+code=pll_output" class="sref">pll_output./a> / (.a href="+code=pll_input" class="sref">pll_input./a> / 1000);>L367" class="line" namon>L367">3367./a>        if (.a href="+code=ratio" class="sref">ratio./a> < 8600L) { .spa  class="comment">/* 8.6x */./spa  >L368" class="line" namon>L368">3368./a>                .spa  class="comment">/* Using NO = 0x01, R = 0x0d */./spa  >L369" class="line" namon>L369">3369./a>                .a href="+code=r" class="sref">r./a> = 0x0d;>L370" class="line" namon>L370">3370./a>        } else if (.a href="+code=ratio" class="sref">ratio./a> < 12900L) { .spa  class="comment">/* 12.9x */./spa  >L371" class="line" namon>L371">3371./a>                .spa  class="comment">/* Using NO = 0x01, R = 0x08 */./spa  >L372" class="line" namon>L372">3372./a>                .a href="+code=r" class="sref">r./a> = 0x08;>L373" class="line" namon>L373">3373./a>        } else if (.a href="+code=ratio" class="sref">ratio./a> < 16100L) { .spa  class="comment">/* 16.1x */./spa  >L374" class="line" namon>L374">3374./a>                .spa  class="comment">/* Using NO = 0x01, R = 0x06 */./spa  >L375" class="line" namon>L375">3375./a>                .a href="+code=r" class="sref">r./a> = 0x06;>L376" class="line" namon>L376">3376./a>        } else if (.a href="+code=ratio" class="sref">ratio./a> < 64000L) { .spa  class="comment">/* 64x */./spa  >L377" class="line" namon>L377">3377./a>                .a href="+code=r" class="sref">r./a> = 0x00;>L378" class="line" namon>L378">3378./a>        } else {>L379" class="line" namon>L379">3379./a>                .spa  class="comment">/* Invalid ratio */./spa  >L380" class="line" namon>L380">3380./a>                .a href="+code=printk" class="sref">printk./a>(.a href="+code=KERN_ERR" class="sref">KERN_ERR./a> .spa  class="string">"%s %s: Bad ratio %ld, giving up!\n"./spa  ,>L381" class="line" namon>L381">3381./a>                        .a href="+code=name" class="sref">name./a>, .a href="+code=pci_name" class="sref">pci_name./a>(.a href="+code=dev" class="sref">dev./a>), .a href="+code=ratio" class="sref">ratio./a>);>L382" class="line" namon>L382">3382./a>                goto .a href="+code=out" class="sref">out./a>;>L383" class="line" namon>L383">3383./a>        }>L384" class="line" namon>L384">3384./a>>L385" class="line" namon>L385">3385./a>        .a href="+code=f" class="sref">f./a> = (.a href="+code=ratio" class="sref">ratio./a> * (.a href="+code=r" class="sref">r./a> + 2)) / 1000 - 2;>L386" class="line" namon>L386">3386./a>>L387" class="line" namon>L387">3387./a>        .a href="+code=DBG" class="sref">DBG./a>(.spa  class="string">"F[%d] R[%d] ratio*1000[%ld]\n"./spa  ,3.a href="+code=f" class="sref">f./a>,3.a href="+code=r" class="sref">r./a>, .a href="+code=ratio" class="sref">ratio./a>);>L388" class="line" namon>L388">3388./a>>L389" class="line" namon>L389">3389./a>        if (.a href="+code=unlikely" class="sref">unlikely./a>(.a href="+code=f" class="sref">f./a> < 0 || .a href="+code=f" class="sref">f./a> > 127)) {>L390" class="line" namon>L390">3390./a>                .spa  class="comment">/* Invalid F */./spa  >L391" class="line" namon>L391">3391./a>                .a href="+code=printk" class="sref">printk./a>(.a href="+code=KERN_ERR" class="sref">KERN_ERR./a> .spa  class="string">"%s %s: F[%d] invalid!\n"./spa  ,>L392" class="line" namon>L392">3392./a>                        .a href="+code=name" class="sref">name./a>, .a href="+code=pci_name" class="sref">pci_name./a>(.a href="+code=dev" class="sref">dev./a>), .a href="+code=f" class="sref">f./a>);>L393" class="line" namon>L393">3393./a>                goto .a href="+code=out" class="sref">out./a>;>L394" class="line" namon>L394">3394./a>        }>L395" class="line" namon>L395">3395./a>>L396" class="line" namon>L396">3396./a>        .a href="+code=pll_ctl0" class="sref">pll_ctl0./a> = (.a href="+code=u8" class="sref">u8./a>) .a href="+code=f" class="sref">f./a>;>L397" class="line" namon>L397">3397./a>        .a href="+code=pll_ctl1" class="sref">pll_ctl1./a> = (.a href="+code=u8" class="sref">u8./a>) .a href="+code=r" class="sref">r./a>;>L398" class="line" namon>L398">3398./a>>L399" class="line" namon>L399">3399./a>        .a href="+code=DBG" class="sref">DBG./a>(.spa  class="string">"Writing pll_ctl[%02X][%02X]\n"./spa  ,3.a href="+code=pll_ctl0" class="sref">pll_ctl0./a>, .a href="+code=pll_ctl1" class="sref">pll_ctl1./a>);>L400" class="line" namon>L400">3400./a>>L401" class="line" namon>L401">3401./a>        .a href="+code=outb" class="sref">outb./a>(0x02,     .a href="+code=sec_dma_base" class="sref">sec_dma_base./a> + 0x01);>L402" class="line" namon>L402">3402./a>        .a href="+code=outb" class="sref">outb./a>(.a href="+code=pll_ctl0" class="sref">pll_ctl0./a>, .a href="+code=sec_dma_base" class="sref">sec_dma_base./a> + 0x03);>L403" class="line" namon>L403">3403./a>        .a href="+code=outb" class="sref">outb./a>(0x03,     .a href="+code=sec_dma_base" class="sref">sec_dma_base./a> + 0x01);>L404" class="line" namon>L404">3404./a>        .a href="+code=outb" class="sref">outb./a>(.a href="+code=pll_ctl1" class="sref">pll_ctl1./a>, .a href="+code=sec_dma_base" class="sref">sec_dma_base./a> + 0x03);>L405" class="line" namon>L405">3405./a>>L406" class="line" namon>L406">3406./a>        .spa  class="comment">/* Wait the PLL circuit to be stable */./spa  >L407" class="line" namon>L407">3407./a>        .a href="+code=mdelay" class="sref">mdelay./a>(30);>L408" class="line" namon>L408">3408./a>>L409" class="line" namon>L409">3409./a>#ifdef .a href="+code=DEBUG" class="sref">DEBUG./a>>L410" class="line" namon>L410">3410./a>        .spa  class="comment">/*./spa  >L411" class="line" namon>L411">3411./a>.spa  class="comment">         *  Show the current clock optio of PLL control register./spa  >L412" class="line" namon>L412">3412./a>.spa  class="comment">         */./spa  >L413" class="line" namon>L413">3413./a>        .a href="+code=outb" class="sref">outb./a>(0x02, .a href="+code=sec_dma_base" class="sref">sec_dma_base./a> + 0x01);>L414" class="line" namon>L414">3414./a>        .a href="+code=pll_ctl0" class="sref">pll_ctl0./a> = .a href="+code=inb" class="sref">inb./a>(.a href="+code=sec_dma_base" class="sref">sec_dma_base./a> + 0x03);>L415" class="line" namon>L415">3415./a>        .a href="+code=outb" class="sref">outb./a>(0x03, .a href="+code=sec_dma_base" class="sref">sec_dma_base./a> + 0x01);>L416" class="line" namon>L416">3416./a>        .a href="+code=pll_ctl1" class="sref">pll_ctl1./a> = .a href="+code=inb" class="sref">inb./a>(.a href="+code=sec_dma_base" class="sref">sec_dma_base./a> + 0x03);>L417" class="line" namon>L417">3417./a>>L418" class="line" namon>L418">3418./a>        .a href="+code=DBG" class="sref">DBG./a>(.spa  class="string">"pll_ctl[%02X][%02X]\n"./spa  ,3.a href="+code=pll_ctl0" class="sref">pll_ctl0./a>, .a href="+code=pll_ctl1" class="sref">pll_ctl1./a>);>L419" class="line" namon>L419">3419./a>#endif>L420" class="line" namon>L420">3420./a>>L421" class="line" namon>L421">3421./a> .a href="+code=out" class="sref">out./a>:>L422" class="line" namon>L422">3422./a>        return 0;>L423" class="line" namon>L423">3423./a>}>L424" class="line" namon>L424">3424./a>>L425" class="line" namon>L425">3425./a>static3struct3.a href="+code=pci_dev" class="sref">pci_dev./a> *.a href="+code=pdc20270_get_dev2" class="sref">pdc20270_get_dev2./a>(struct3.a href="+code=pci_dev" class="sref">pci_dev./a> *.a href="+code=dev" class="sref">dev./a>)>L426" class="line" namon>L426">3426./a>{>L427" class="line" namon>L427">3427./a>        struct3.a href="+code=pci_dev" class="sref">pci_dev./a> *.a href="+code=dev2" class="sref">dev2./a>;>L428" class="line" namon>L428">3428./a>>L429" class="line" namon>L429">3429./a>        .a href="+code=dev2" class="sref">dev2./a> = .a href="+code=pci_get_slot" class="sref">pci_get_slot./a>(.a href="+code=dev" class="sref">dev./a>->.a href="+code=bus" class="sref">bus./a>, .a href="+code=PCI_DEVFN" class="sref">PCI_DEVFN./a>(.a href="+code=PCI_SLOT" class="sref">PCI_SLOT./a>(.a href="+code=dev" class="sref">dev./a>->.a href="+code=devfn" class="sref">devfn./a>) + 1,>L430" class="line" namon>L430">3430./a>                                                .a href="+code=PCI_FUNC" class="sref">PCI_FUNC./a>(.a href="+code=dev" class="sref">dev./a>->.a href="+code=devfn" class="sref">devfn./a>)));>L431" class="line" namon>L431">3431./a>>L432" class="line" namon>L432">3432./a>        if (.a href="+code=dev2" class="sref">dev2./a> &&>L433" class="line" namon>L433">3433./a>            .a href="+code=dev2" class="sref">dev2./a>->.a href="+code=vendor" class="sref">vendor./a> == .a href="+code=dev" class="sref">dev./a>->.a href="+code=vendor" class="sref">vendor./a> &&>L434" class="line" namon>L434">3434./a>            .a href="+code=dev2" class="sref">dev2./a>->.a href="+code=device" class="sref">device./a> == .a href="+code=dev" class="sref">dev./a>->.a href="+code=device" class="sref">device./a>) {>L435" class="line" namon>L435">3435./a>>L436" class="line" namon>L436">3436./a>                if (.a href="+code=dev2" class="sref">dev2./a>->.a href="+code=irq" class="sref">irq./a> != .a href="+code=dev" class="sref">dev./a>->.a href="+code=irq" class="sref">irq./a>) {>L437" class="line" namon>L437">3437./a>                        .a href="+code=dev2" class="sref">dev2./a>->.a href="+code=irq" class="sref">irq./a> = .a href="+code=dev" class="sref">dev./a>->.a href="+code=irq" class="sref">irq./a>;>L438" class="line" namon>L438">3438./a>                        .a href="+code=printk" class="sref">printk./a>(.a href="+code=KERN_INFO" class="sref">KERN_INFO./a> .a href="+code=DRV_NAME" class="sref">DRV_NAME./a> .spa  class="string">" %s: PCI3config space "./spa  >L439" class="line" namon>L439">3439./a>                                .spa  class="string">"interrupt fixed\n"./spa  ,3.a href="+code=pci_name" class="sref">pci_name./a>(.a href="+code=dev" class="sref">dev./a>));>L440" class="line" namon>L440">3440./a>                }>L441" class="line" namon>L441">3441./a>>L442" class="line" namon>L442">3442./a>                return .a href="+code=dev2" class="sref">dev2./a>;>L443" class="line" namon>L443">3443./a>        }>L444" class="line" namon>L444">3444./a>>L445" class="line" namon>L445">3445./a>        return .a href="+code=NULL" class="sref">NULL./a>;>L446" class="line" namon>L446">3446./a>}>L447" class="line" namon>L447">3447./a>>L448" class="line" namon>L448">3448./a>static3const3struct3.a href="+code=ide_port_ops" class="sref">ide_port_ops./a> .a href="+code=pdcnew_port_ops" class="sref">pdcnew_port_ops./a> = {>L449" class="line" namon>L449">3449./a>        ..a href="+code=set_pio_mode" class="sref">set_pio_mode./a>           = .a href="+code=pdcnew_set_pio_mode" class="sref">pdcnew_set_pio_mode./a>,>L450" class="line" namon>L450">3450./a>        ..a href="+code=set_dma_mode" class="sref">set_dma_mode./a>           = .a href="+code=pdcnew_set_dma_mode" class="sref">pdcnew_set_dma_mode./a>,>L451" class="line" namon>L451">3451./a>        ..a href="+code=resetproc" class="sref">resetproc./a>              = .a href="+code=pdcnew_reset" class="sref">pdcnew_reset./a>,>L452" class="line" namon>L452">3452./a>        ..a href="+code=cable_detect" class="sref">cable_detect./a>           = .a href="+code=pdcnew_cable_detect" class="sref">pdcnew_cable_detect./a>,>L453" class="line" namon>L453">3453./a>};>L454" class="line" namon>L454">3454./a>>L455" class="line" namon>L455">3455./a>#define .a href="+code=DECLARE_PDCNEW_DEV" class="sref">DECLARE_PDCNEW_DEV./a>(.a href="+code=udma" class="sref">udma./a>) \>L456" class="line" namon>L456">3456./a>        { \>L457" class="line" namon>L457">3457./a>                ..a href="+code=name" class="sref">name./a>           = .a href="+code=DRV_NAME" class="sref">DRV_NAME./a>, \>L458" class="line" namon>L458">3458./a>                ..a href="+code=init_chipset" class="sref">init_chipset./a>   = .a href="+code=init_chipset_pdcnew" class="sref">init_chipset_pdcnew./a>, \>L459" class="line" namon>L459">3459./a>                ..a href="+code=port_ops" class="sref">port_ops./a>       = &.a href="+code=pdcnew_port_ops" class="sref">pdcnew_port_ops./a>, \>L460" class="line" namon>L460">3460./a>                ..a href="+code=host_flags" class="sref">host_flags./a>     = .a href="+code=IDE_HFLAG_POST_SET_MODE" class="sref">IDE_HFLAG_POST_SET_MODE./a> | \>L461" class="line" namon>L461">3461./a>                                  .a href="+code=IDE_HFLAG_ERROR_STOPS_FIFO" class="sref">IDE_HFLAG_ERROR_STOPS_FIFO./a> | \>L462" class="line" namon>L462">3462./a>                                  .a href="+code=IDE_HFLAG_OFF_BOARD" class="sref">IDE_HFLAG_OFF_BOARD./a>, \>L463" class="line" namon>L463">3463./a>                ..a href="+code=pio_mask" class="sref">pio_mask./a>       = .a href="+code=ATA_PIO4" class="sref">ATA_PIO4./a>, \>L464" class="line" namon>L464">3464./a>                ..a href="+code=mwdma_mask" class="sref">mwdma_mask./a>     = .a href="+code=ATA_MWDMA2" class="sref">ATA_MWDMA2./a>, \>L465" class="line" namon>L465">3465./a>                ..a href="+code=udma_mask" class="sref">udma_mask./a>      = .a href="+code=udma" class="sref">udma./a>, \>L466" class="line" namon>L466">3466./a>        }>L467" class="line" namon>L467">3467./a>>L468" class="line" namon>L468">3468./a>static3const3struct3.a href="+code=ide_port_info" class="sref">ide_port_info./a> .a href="+code=pdcnew_chipsets" class="sref">pdcnew_chipsets./a>[] = {>L469" class="line" namon>L469">3469./a>        .spa  class="comment">/* 0: PDC202{68,70} */./spa            .a href="+code=DECLARE_PDCNEW_DEV" class="sref">DECLARE_PDCNEW_DEV./a>(.a href="+code=ATA_UDMA5" class="sref">ATA_UDMA5./a>),>L470" class="line" namon>L470">3470./a>        .spa  class="comment">/* 1: PDC202{69,71,75,76,77} */./spa   .a href="+code=DECLARE_PDCNEW_DEV" class="sref">DECLARE_PDCNEW_DEV./a>(.a href="+code=ATA_UDMA6" class="sref">ATA_UDMA6./a>),>L471" class="line" namon>L471">3471./a>};>L472" class="line" namon>L472">3472./a>>L473" class="line" namon>L473">3473./a>.spa  class="comment">/**./spa  >L474" class="line" namon>L474">3474./a>.spa  class="comment"> *      pdc202new_init_one      -       called when a pdc202xx is found./spa  >L475" class="line" namon>L475">3475./a>.spa  class="comment"> *      @dev: the pdc202new device./spa  >L476" class="line" namon>L476">3476./a>.spa  class="comment"> *      @id: the matching pci id./spa  >L477" class="line" namon>L477">3477./a>.spa  class="comment"> *./spa  >L478" class="line" namon>L478">3478./a>.spa  class="comment"> *      Called when the PCI registration layer (or the IDE initialization)./spa  >L479" class="line" namon>L479">3479./a>.spa  class="comment"> *      finds a device matching our IDE device tables../spa  >L480" class="line" namon>L480">3480./a>.spa  class="comment"> */./spa  >L481" class="line" namon>L481">3481./a> >L482" class="line" namon>L482">3482./a>static3int .a href="+code=pdc202new_init_one" class="sref">pdc202new_init_one./a>(struct3.a href="+code=pci_dev" class="sref">pci_dev./a> *.a href="+code=dev" class="sref">dev./a>,3const3struct3.a href="+code=pci_device_id" class="sref">pci_device_id./a> *.a href="+code=id" class="sref">id./a>)>L483" class="line" namon>L483">3483./a>{>L484" class="line" namon>L484">3484./a>        const3struct3.a href="+code=ide_port_info" class="sref">ide_port_info./a> *.a href="+code=d" class="sref">d./a> = &.a href="+code=pdcnew_chipsets" class="sref">pdcnew_chipsets./a>[.a href="+code=id" class="sref">id./a>->.a href="+code=driver_data" class="sref">driver_data./a>];>L485" class="line" namon>L485">3485./a>        struct3.a href="+code=pci_dev" class="sref">pci_dev./a> *.a href="+code=bridge" class="sref">bridge./a> = .a href="+code=dev" class="sref">dev./a>->.a href="+code=bus" class="sref">bus./a>->.a href="+code=self" class="sref">self./a>;>L486" class="line" namon>L486">3486./a>>L487" class="line" namon>L487">3487./a>        if (.a href="+code=dev" class="sref">dev./a>->.a href="+code=device" class="sref">device./a> == .a href="+code=PCI_DEVICE_ID_PROMISE_20270" class="sref">PCI_DEVICE_ID_PROMISE_20270./a> && .a href="+code=bridge" class="sref">bridge./a> &&>L488" class="line" namon>L488">3488./a>            .a href="+code=bridge" class="sref">bridge./a>->.a href="+code=vendor" class="sref">vendor./a> == .a href="+code=PCI_VENDOR_ID_DEC" class="sref">PCI_VENDOR_ID_DEC./a> &&>L489" class="line" namon>L489">3489./a>            .a href="+code=bridge" class="sref">bridge./a>->.a href="+code=device" class="sref">device./a> == .a href="+code=PCI_DEVICE_ID_DEC_21150" class="sref">PCI_DEVICE_ID_DEC_21150./a>) {>L490" class="line" namon>L490">3490./a>                struct3.a href="+code=pci_dev" class="sref">pci_dev./a> *.a href="+code=dev2" class="sref">dev2./a>;>L491" class="line" namon>L491">3491./a>>L492" class="line" namon>L492">3492./a>                if (.a href="+code=PCI_SLOT" class="sref">PCI_SLOT./a>(.a href="+code=dev" class="sref">dev./a>->.a href="+code=devfn" class="sref">devfn./a>) & 2)>L493" class="line" namon>L493">3493./a>                        return -.a href="+code=ENODEV" class="sref">ENODEV./a>;>L494" class="line" namon>L494">3494./a>>L495" class="line" namon>L495">3495./a>                .a href="+code=dev2" class="sref">dev2./a> = .a href="+code=pdc20270_get_dev2" class="sref">pdc20270_get_dev2./a>(.a href="+code=dev" class="sref">dev./a>);>L496" class="line" namon>L496">3496./a>>L497" class="line" namon>L497">3497./a>                if (.a href="+code=dev2" class="sref">dev2./a>) {>L498" class="line" namon>L498">3498./a>                        int .a href="+code=ret" class="sref">ret./a> = .a href="+code=ide_pci_init_two" class="sref">ide_pci_init_two./a>(.a href="+code=dev" class="sref">dev./a>,3.a href="+code=dev2" class="sref">dev2./a>,3.a href="+code=d" class="sref">d./a>,3.a href="+code=NULL" class="sref">NULL./a>);>L499" class="line" namon>L499">3499./a>                        if (.a href="+code=ret" class="sref">ret./a> < 0)>L500" class="line" namon>L500">3500./a>                                .a href="+code=pci_dev_put" class="sref">pci_dev_put./a>(.a href="+code=dev2" class="sref">dev2./a>);>L501" class="line" namon>L501">3501./a>                        return .a href="+code=ret" class="sref">ret./a>;>L502" class="line" namon>L502">3502./a>                }>L503" class="line" namon>L503">3503./a>        }>L504" class="line" namon>L504">3504./a>>L505" class="line" namon>L505">3505./a>        if (.a href="+code=dev" class="sref">dev./a>->.a href="+code=device" class="sref">device./a> == .a href="+code=PCI_DEVICE_ID_PROMISE_20276" class="sref">PCI_DEVICE_ID_PROMISE_20276./a> && .a href="+code=bridge" class="sref">bridge./a> &&>L506" class="line" namon>L506">3506./a>            .a href="+code=bridge" class="sref">bridge./a>->.a href="+code=vendor" class="sref">vendor./a> == .a href="+code=PCI_VENDOR_ID_INTEL" class="sref">PCI_VENDOR_ID_INTEL./a> &&>L507" class="line" namon>L507">3507./a>            (.a href="+code=bridge" class="sref">bridge./a>->.a href="+code=device" class="sref">device./a> == .a href="+code=PCI_DEVICE_ID_INTEL_I960" class="sref">PCI_DEVICE_ID_INTEL_I960./a> ||>L508" class="line" namon>L508">3508./a>             .a href="+code=bridge" class="sref">bridge./a>->.a href="+code=device" class="sref">device./a> == .a href="+code=PCI_DEVICE_ID_INTEL_I960RM" class="sref">PCI_DEVICE_ID_INTEL_I960RM./a>)) {>L509" class="line" namon>L509">3509./a>                .a href="+code=printk" class="sref">printk./a>(.a href="+code=KERN_INFO" class="sref">KERN_INFO./a> .a href="+code=DRV_NAME" class="sref">DRV_NAME./a> .spa  class="string">" %s: attached to I2O RAID controller,"./spa  >L510" class="line" namon>L510">3510./a>                        .spa  class="string">" skipping\n"./spa  ,3.a href="+code=pci_name" class="sref">pci_name./a>(.a href="+code=dev" class="sref">dev./a>));>L511" class="line" namon>L511">3511./a>                return -.a href="+code=ENODEV" class="sref">ENODEV./a>;>L512" class="line" namon>L512">3512./a>        }>L513" class="line" namon>L513">3513./a>>L514" class="line" namon>L514">3514./a>        return .a href="+code=ide_pci_init_one" class="sref">ide_pci_init_one./a>(.a href="+code=dev" class="sref">dev./a>,3.a href="+code=d" class="sref">d./a>,3.a href="+code=NULL" class="sref">NULL./a>);>L515" class="line" namon>L515">3515./a>}>L516" class="line" namon>L516">3516./a>>L517" class="line" namon>L517">3517./a>static3void .a href="+code=pdc202new_remove" class="sref">pdc202new_remove./a>(struct3.a href="+code=pci_dev" class="sref">pci_dev./a> *.a href="+code=dev" class="sref">dev./a>)>L518" class="line" namon>L518">3518./a>{>L519" class="line" namon>L519">3519./a>        struct3.a href="+code=ide_host" class="sref">ide_host./a> *.a href="+code=host" class="sref">host./a> = .a href="+code=pci_get_drvdata" class="sref">pci_get_drvdata./a>(.a href="+code=dev" class="sref">dev./a>);>L520" class="line" namon>L520">3520./a>        struct3.a href="+code=pci_dev" class="sref">pci_dev./a> *.a href="+code=dev2" class="sref">dev2./a> = .a href="+code=host" class="sref">host./a>->.a href="+code=dev" class="sref">dev./a>[1] ? .a href="+code=to_pci_dev" class="sref">to_pci_dev./a>(.a href="+code=host" class="sref">host./a>->.a href="+code=dev" class="sref">dev./a>[1]) : .a href="+code=NULL" class="sref">NULL./a>;>L521" class="line" namon>L521">3521./a>>L522" class="line" namon>L522">3522./a>        .a href="+code=ide_pci_remove" class="sref">ide_pci_remove./a>(.a href="+code=dev" class="sref">dev./a>);>L523" class="line" namon>L523">3523./a>        .a href="+code=pci_dev_put" class="sref">pci_dev_put./a>(.a href="+code=dev2" class="sref">dev2./a>);>L524" class="line" namon>L524">3524./a>}>L525" class="line" namon>L525">3525./a>>L526" class="line" namon>L526">3526./a>static3const3struct3.a href="+code=pci_device_id" class="sref">pci_device_id./a> .a href="+code=pdc202new_pci_tbl" class="sref">pdc202new_pci_tbl./a>[] = {>L527" class="line" namon>L527">3527./a>        { .a href="+code=PCI_VDEVICE" class="sref">PCI_VDEVICE./a>(.a href="+code=PROMISE" class="sref">PROMISE./a>,3.a href="+code=PCI_DEVICE_ID_PROMISE_20268" class="sref">PCI_DEVICE_ID_PROMISE_20268./a>), 0 },>L528" class="line" namon>L528">3528./a>        { .a href="+code=PCI_VDEVICE" class="sref">PCI_VDEVICE./a>(.a href="+code=PROMISE" class="sref">PROMISE./a>,3.a href="+code=PCI_DEVICE_ID_PROMISE_20269" class="sref">PCI_DEVICE_ID_PROMISE_20269./a>), 1 },>L529" class="line" namon>L529">3529./a>        { .a href="+code=PCI_VDEVICE" class="sref">PCI_VDEVICE./a>(.a href="+code=PROMISE" class="sref">PROMISE./a>,3.a href="+code=PCI_DEVICE_ID_PROMISE_20270" class="sref">PCI_DEVICE_ID_PROMISE_20270./a>), 0 },>L530" class="line" namon>L530">3530./a>        { .a href="+code=PCI_VDEVICE" class="sref">PCI_VDEVICE./a>(.a href="+code=PROMISE" class="sref">PROMISE./a>,3.a href="+code=PCI_DEVICE_ID_PROMISE_20271" class="sref">PCI_DEVICE_ID_PROMISE_20271./a>), 1 },>L531" class="line" namon>L531">3531./a>        { .a href="+code=PCI_VDEVICE" class="sref">PCI_VDEVICE./a>(.a href="+code=PROMISE" class="sref">PROMISE./a>,3.a href="+code=PCI_DEVICE_ID_PROMISE_20275" class="sref">PCI_DEVICE_ID_PROMISE_20275./a>), 1 },>L532" class="line" namon>L532">3532./a>        { .a href="+code=PCI_VDEVICE" class="sref">PCI_VDEVICE./a>(.a href="+code=PROMISE" class="sref">PROMISE./a>,3.a href="+code=PCI_DEVICE_ID_PROMISE_20276" class="sref">PCI_DEVICE_ID_PROMISE_20276./a>), 1 },>L533" class="line" namon>L533">3533./a>        { .a href="+code=PCI_VDEVICE" class="sref">PCI_VDEVICE./a>(.a href="+code=PROMISE" class="sref">PROMISE./a>,3.a href="+code=PCI_DEVICE_ID_PROMISE_20277" class="sref">PCI_DEVICE_ID_PROMISE_20277./a>), 1 },>L534" class="line" namon>L534">3534./a>        { 0, },>L535" class="line" namon>L535">3535./a>};>L536" class="line" namon>L536">3536./a>.a href="+code=MODULE_DEVICE_TABLE" class="sref">MODULE_DEVICE_TABLE./a>(.a href="+code=pci" class="sref">pci./a>,3.a href="+code=pdc202new_pci_tbl" class="sref">pdc202new_pci_tbl./a>);>L537" class="line" namon>L537">3537./a>>L538" class="line" namon>L538">3538./a>static3struct3.a href="+code=pci_driver" class="sref">pci_driver./a> .a href="+code=pdc202new_pci_driver" class="sref">pdc202new_pci_driver./a> = {>L539" class="line" namon>L539">3539./a>        ..a href="+code=name" class="sref">name./a>           = .spa  class="string">"Promise_IDE"./spa  ,>L540" class="line" namon>L540">3540./a>        ..a href="+code=id_table" class="sref">id_table./a>       = .a href="+code=pdc202new_pci_tbl" class="sref">pdc202new_pci_tbl./a>,>L541" class="line" namon>L541">3541./a>        ..a href="+code=probe" class="sref">probe./a>          = .a href="+code=pdc202new_init_one" class="sref">pdc202new_init_one./a>,>L542" class="line" namon>L542">3542./a>        ..a href="+code=remove" class="sref">remove./a>         = .a href="+code=pdc202new_remove" class="sref">pdc202new_remove./a>,>L543" class="line" namon>L543">3543./a>        ..a href="+code=suspend" class="sref">suspend./a>        = .a href="+code=ide_pci_suspend" class="sref">ide_pci_suspend./a>,>L544" class="line" namon>L544">3544./a>        ..a href="+code=resume" class="sref">resume./a>         = .a href="+code=ide_pci_resume" class="sref">ide_pci_resume./a>,>L545" class="line" namon>L545">3545./a>};>L546" class="line" namon>L546">3546./a>>L547" class="line" namon>L547">3547./a>static3int .a href="+code=__init" class="sref">__init./a> .a href="+code=pdc202new_ide_init" class="sref">pdc202new_ide_init./a>(void)>L548" class="line" namon>L548">3548./a>{>L549" class="line" namon>L549">3549./a>        return .a href="+code=ide_pci_register_driver" class="sref">ide_pci_register_driver./a>(&.a href="+code=pdc202new_pci_driver" class="sref">pdc202new_pci_driver./a>);>L550" class="line" namon>L550">3550./a>}>L551" class="line" namon>L551">3551./a>>L552" class="line" namon>L552">3552./a>static3void .a href="+code=__exit" class="sref">__exit./a> .a href="+code=pdc202new_ide_exit" class="sref">pdc202new_ide_exit./a>(void)>L553" class="line" namon>L553">3553./a>{>L554" class="line" namon>L554">3554./a>        .a href="+code=pci_unregister_driver" class="sref">pci_unregister_driver./a>(&.a href="+code=pdc202new_pci_driver" class="sref">pdc202new_pci_driver./a>);>L555" class="line" namon>L555">3555./a>}>L556" class="line" namon>L556">3556./a>>L557" class="line" namon>L557">3557./a>.a href="+code=module_init" class="sref">module_init./a>(.a href="+code=pdc202new_ide_init" class="sref">pdc202new_ide_init./a>);>L558" class="line" namon>L558">3558./a>.a href="+code=module_exit" class="sref">module_exit./a>(.a href="+code=pdc202new_ide_exit" class="sref">pdc202new_ide_exit./a>);>L559" class="line" namon>L559">3559./a>>L560" class="line" namon>L560">3560./a>.a href="+code=MODULE_AUTHOR" class="sref">MODULE_AUTHOR./a>(.spa  class="string">"Andre Hedrick, Frank Tiernan"./spa  );>L561" class="line" namon>L561">3561./a>.a href="+code=MODULE_DESCRIPTION" class="sref">MODULE_DESCRIPTION./a>(.spa  class="string">"PCI driver module for Promise PDC20268 and higher"./spa  );>L562" class="line" namon>L562">3562./a>.a href="+code=MODULE_LICENSE" class="sref">MODULE_LICENSE./a>(.spa  class="string">"GPL"./spa  );>L563" class="line" namon>L563">3563./a>
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