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22#include <linux/slab.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/init.h>
27#include <linux/firmware.h>
28
29#include "dvb_frontend.h"
30#include "ds3000.h"
31
32static int debug;
33
34#define dprintk(args...) \
35 do { \
36 if (debug) \
37 printk(args); \
38 } while (0)
39
40
41
42#define DS3000_DEFAULT_FIRMWARE "dvb-fe-ds3000.fw"
43
44#define DS3000_SAMPLE_RATE 96000
45#define DS3000_XTAL_FREQ 27000
46
47
48static u8 ds3000_dvbs_init_tab[] = {
49 0x23, 0x05,
50 0x08, 0x03,
51 0x0c, 0x00,
52 0x21, 0x54,
53 0x25, 0x82,
54 0x27, 0x31,
55 0x30, 0x08,
56 0x31, 0x40,
57 0x32, 0x32,
58 0x33, 0x35,
59 0x35, 0xff,
60 0x3a, 0x00,
61 0x37, 0x10,
62 0x38, 0x10,
63 0x39, 0x02,
64 0x42, 0x60,
65 0x4a, 0x40,
66 0x4b, 0x04,
67 0x4d, 0x91,
68 0x5d, 0xc8,
69 0x50, 0x77,
70 0x51, 0x77,
71 0x52, 0x36,
72 0x53, 0x36,
73 0x56, 0x01,
74 0x63, 0x43,
75 0x64, 0x30,
76 0x65, 0x40,
77 0x68, 0x26,
78 0x69, 0x4c,
79 0x70, 0x20,
80 0x71, 0x70,
81 0x72, 0x04,
82 0x73, 0x00,
83 0x70, 0x40,
84 0x71, 0x70,
85 0x72, 0x04,
86 0x73, 0x00,
87 0x70, 0x60,
88 0x71, 0x70,
89 0x72, 0x04,
90 0x73, 0x00,
91 0x70, 0x80,
92 0x71, 0x70,
93 0x72, 0x04,
94 0x73, 0x00,
95 0x70, 0xa0,
96 0x71, 0x70,
97 0x72, 0x04,
98 0x73, 0x00,
99 0x70, 0x1f,
100 0x76, 0x00,
101 0x77, 0xd1,
102 0x78, 0x0c,
103 0x79, 0x80,
104 0x7f, 0x04,
105 0x7c, 0x00,
106 0x80, 0x86,
107 0x81, 0xa6,
108 0x85, 0x04,
109 0xcd, 0xf4,
110 0x90, 0x33,
111 0xa0, 0x44,
112 0xc0, 0x18,
113 0xc3, 0x10,
114 0xc4, 0x08,
115 0xc5, 0x80,
116 0xc6, 0x80,
117 0xc7, 0x0a,
118 0xc8, 0x1a,
119 0xc9, 0x80,
120 0xfe, 0x92,
121 0xe0, 0xf8,
122 0xe6, 0x8b,
123 0xd0, 0x40,
124 0xf8, 0x20,
125 0xfa, 0x0f,
126 0xfd, 0x20,
127 0xad, 0x20,
128 0xae, 0x07,
129 0xb8, 0x00,
130};
131
132
133static u8 ds3000_dvbs2_init_tab[] = {
134 0x23, 0x0f,
135 0x08, 0x07,
136 0x0c, 0x00,
137 0x21, 0x54,
138 0x25, 0x82,
139 0x27, 0x31,
140 0x30, 0x08,
141 0x31, 0x32,
142 0x32, 0x32,
143 0x33, 0x35,
144 0x35, 0xff,
145 0x3a, 0x00,
146 0x37, 0x10,
147 0x38, 0x10,
148 0x39, 0x02,
149 0x42, 0x60,
150 0x4a, 0x80,
151 0x4b, 0x04,
152 0x4d, 0x81,
153 0x5d, 0x88,
154 0x50, 0x36,
155 0x51, 0x36,
156 0x52, 0x36,
157 0x53, 0x36,
158 0x63, 0x60,
159 0x64, 0x10,
160 0x65, 0x10,
161 0x68, 0x04,
162 0x69, 0x29,
163 0x70, 0x20,
164 0x71, 0x70,
165 0x72, 0x04,
166 0x73, 0x00,
167 0x70, 0x40,
168 0x71, 0x70,
169 0x72, 0x04,
170 0x73, 0x00,
171 0x70, 0x60,
172 0x71, 0x70,
173 0x72, 0x04,
174 0x73, 0x00,
175 0x70, 0x80,
176 0x71, 0x70,
177 0x72, 0x04,
178 0x73, 0x00,
179 0x70, 0xa0,
180 0x71, 0x70,
181 0x72, 0x04,
182 0x73, 0x00,
183 0x70, 0x1f,
184 0xa0, 0x44,
185 0xc0, 0x08,
186 0xc1, 0x10,
187 0xc2, 0x08,
188 0xc3, 0x10,
189 0xc4, 0x08,
190 0xc5, 0xf0,
191 0xc6, 0xf0,
192 0xc7, 0x0a,
193 0xc8, 0x1a,
194 0xc9, 0x80,
195 0xca, 0x23,
196 0xcb, 0x24,
197 0xce, 0x74,
198 0x90, 0x03,
199 0x76, 0x80,
200 0x77, 0x42,
201 0x78, 0x0a,
202 0x79, 0x80,
203 0xad, 0x40,
204 0xae, 0x07,
205 0x7f, 0xd4,
206 0x7c, 0x00,
207 0x80, 0xa8,
208 0x81, 0xda,
209 0x7c, 0x01,
210 0x80, 0xda,
211 0x81, 0xec,
212 0x7c, 0x02,
213 0x80, 0xca,
214 0x81, 0xeb,
215 0x7c, 0x03,
216 0x80, 0xba,
217 0x81, 0xdb,
218 0x85, 0x08,
219 0x86, 0x00,
220 0x87, 0x02,
221 0x89, 0x80,
222 0x8b, 0x44,
223 0x8c, 0xaa,
224 0x8a, 0x10,
225 0xba, 0x00,
226 0xf5, 0x04,
227 0xfe, 0x44,
228 0xd2, 0x32,
229 0xb8, 0x00,
230};
231
232struct ds3000_state {
233 struct i2c_adapter *i2c;
234 const struct ds3000_config *config;
235 struct dvb_frontend frontend;
236
237 u16 prevUCBS2;
238};
239
240static int ds3000_writereg(struct ds3000_state *state, int reg, int data)
241{
242 u8 buf[] = { reg, data };
243 struct i2c_msg msg = { .addr = state->config->demod_address,
244 .flags = 0, .buf = buf, .len = 2 };
245 int err;
246
247 dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data);
248
249 err = i2c_transfer(state->i2c, &msg, 1);
250 if (err != 1) {
251 printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x,"
252 " value == 0x%02x)\n", __func__, err, reg, data);
253 return -EREMOTEIO;
254 }
255
256 return 0;
257}
258
259static int ds3000_tuner_writereg(struct ds3000_state *state, int reg, int data)
260{
261 u8 buf[] = { reg, data };
262 struct i2c_msg msg = { .addr = 0x60,
263 .flags = 0, .buf = buf, .len = 2 };
264 int err;
265
266 dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data);
267
268 ds3000_writereg(state, 0x03, 0x11);
269 err = i2c_transfer(state->i2c, &msg, 1);
270 if (err != 1) {
271 printk("%s: writereg error(err == %i, reg == 0x%02x,"
272 " value == 0x%02x)\n", __func__, err, reg, data);
273 return -EREMOTEIO;
274 }
275
276 return 0;
277}
278
279
280static int ds3000_writeFW(struct ds3000_state *state, int reg,
281 const u8 *data, u16 len)
282{
283 int i, ret = -EREMOTEIO;
284 struct i2c_msg msg;
285 u8 *buf;
286
287 buf = kmalloc(33, GFP_KERNEL);
288 if (buf == NULL) {
289 printk(KERN_ERR "Unable to kmalloc\n");
290 ret = -ENOMEM;
291 goto error;
292 }
293
294 *(buf) = reg;
295
296 msg.addr = state->config->demod_address;
297 msg.flags = 0;
298 msg.buf = buf;
299 msg.len = 33;
300
301 for (i = 0; i < len; i += 32) {
302 memcpy(buf + 1, data + i, 32);
303
304 dprintk("%s: write reg 0x%02x, len = %d\n", __func__, reg, len);
305
306 ret = i2c_transfer(state->i2c, &msg, 1);
307 if (ret != 1) {
308 printk(KERN_ERR "%s: write error(err == %i, "
309 "reg == 0x%02x\n", __func__, ret, reg);
310 ret = -EREMOTEIO;
311 }
312 }
313
314error:
315 kfree(buf);
316
317 return ret;
318}
319
320static int ds3000_readreg(struct ds3000_state *state, u8 reg)
321{
322 int ret;
323 u8 b0[] = { reg };
324 u8 b1[] = { 0 };
325 struct i2c_msg msg[] = {
326 {
327 .addr = state->config->demod_address,
328 .flags = 0,
329 .buf = b0,
330 .len = 1
331 }, {
332 .addr = state->config->demod_address,
333 .flags = I2C_M_RD,
334 .buf = b1,
335 .len = 1
336 }
337 };
338
339 ret = i2c_transfer(state->i2c, msg, 2);
340
341 if (ret != 2) {
342 printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret);
343 return ret;
344 }
345
346 dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]);
347
348 return b1[0];
349}
350
351static int ds3000_tuner_readreg(struct ds3000_state *state, u8 reg)
352{
353 int ret;
354 u8 b0[] = { reg };
355 u8 b1[] = { 0 };
356 struct i2c_msg msg[] = {
357 {
358 .addr = 0x60,
359 .flags = 0,
360 .buf = b0,
361 .len = 1
362 }, {
363 .addr = 0x60,
364 .flags = I2C_M_RD,
365 .buf = b1,
366 .len = 1
367 }
368 };
369
370 ds3000_writereg(state, 0x03, 0x12);
371 ret = i2c_transfer(state->i2c, msg, 2);
372
373 if (ret != 2) {
374 printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret);
375 return ret;
376 }
377
378 dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]);
379
380 return b1[0];
381}
382
383static int ds3000_load_firmware(struct dvb_frontend *fe,
384 const struct firmware *fw);
385
386static int ds3000_firmware_ondemand(struct dvb_frontend *fe)
387{
388 struct ds3000_state *state = fe->demodulator_priv;
389 const struct firmware *fw;
390 int ret = 0;
391
392 dprintk("%s()\n", __func__);
393
394 ret = ds3000_readreg(state, 0xb2);
395 if (ret < 0)
396 return ret;
397
398
399
400 printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n", __func__,
401 DS3000_DEFAULT_FIRMWARE);
402 ret = request_firmware(&fw, DS3000_DEFAULT_FIRMWARE,
403 state->i2c->dev.parent);
404 printk(KERN_INFO "%s: Waiting for firmware upload(2)...\n", __func__);
405 if (ret) {
406 printk(KERN_ERR "%s: No firmware uploaded (timeout or file not "
407 "found?)\n", __func__);
408 return ret;
409 }
410
411 ret = ds3000_load_firmware(fe, fw);
412 if (ret)
413 printk("%s: Writing firmware to device failed\n", __func__);
414
415 release_firmware(fw);
416
417 dprintk("%s: Firmware upload %s\n", __func__,
418 ret == 0 ? "complete" : "failed");
419
420 return ret;
421}
422
423static int ds3000_load_firmware(struct dvb_frontend *fe,
424 const struct firmware *fw)
425{
426 struct ds3000_state *state = fe->demodulator_priv;
427
428 dprintk("%s\n", __func__);
429 dprintk("Firmware is %zu bytes (%02x %02x .. %02x %02x)\n",
430 fw->size,
431 fw->data[0],
432 fw->data[1],
433 fw->data[fw->size - 2],
434 fw->data[fw->size - 1]);
435
436
437 ds3000_writereg(state, 0xb2, 0x01);
438
439 ds3000_writeFW(state, 0xb0, fw->data, fw->size);
440 ds3000_writereg(state, 0xb2, 0x00);
441
442 return 0;
443}
444
445static int ds3000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
446{
447 struct ds3000_state *state = fe->demodulator_priv;
448 u8 data;
449
450 dprintk("%s(%d)\n", __func__, voltage);
451
452 data = ds3000_readreg(state, 0xa2);
453 data |= 0x03;
454
455 switch (voltage) {
456 case SEC_VOLTAGE_18:
457 data &= ~0x03;
458 break;
459 case SEC_VOLTAGE_13:
460 data &= ~0x03;
461 data |= 0x01;
462 break;
463 case SEC_VOLTAGE_OFF:
464 break;
465 }
466
467 ds3000_writereg(state, 0xa2, data);
468
469 return 0;
470}
471
472static int ds3000_read_status(struct dvb_frontend *fe, fe_status_t* status)
473{
474 struct ds3000_state *state = fe->demodulator_priv;
475 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
476 int lock;
477
478 *status = 0;
479
480 switch (c->delivery_system) {
481 case SYS_DVBS:
482 lock = ds3000_readreg(state, 0xd1);
483 if ((lock & 0x07) == 0x07)
484 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
485 FE_HAS_VITERBI | FE_HAS_SYNC |
486 FE_HAS_LOCK;
487
488 break;
489 case SYS_DVBS2:
490 lock = ds3000_readreg(state, 0x0d);
491 if ((lock & 0x8f) == 0x8f)
492 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
493 FE_HAS_VITERBI | FE_HAS_SYNC |
494 FE_HAS_LOCK;
495
496 break;
497 default:
498 return 1;
499 }
500
501 dprintk("%s: status = 0x%02x\n", __func__, lock);
502
503 return 0;
504}
505
506
507static int ds3000_read_ber(struct dvb_frontend *fe, u32* ber)
508{
509 struct ds3000_state *state = fe->demodulator_priv;
510 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
511 u8 data;
512 u32 ber_reading, lpdc_frames;
513
514 dprintk("%s()\n", __func__);
515
516 switch (c->delivery_system) {
517 case SYS_DVBS:
518
519
520 ds3000_writereg(state, 0xf9, 0x04);
521
522 data = ds3000_readreg(state, 0xf8);
523
524 if ((data & 0x10) == 0) {
525
526
527
528 *ber = (ds3000_readreg(state, 0xf7) << 8) |
529 ds3000_readreg(state, 0xf6);
530
531
532
533 data |= 0x10;
534 ds3000_writereg(state, 0xf8, data);
535 ds3000_writereg(state, 0xf8, data);
536 } else
537
538
539 *ber = 0xffffffff;
540 break;
541 case SYS_DVBS2:
542
543 lpdc_frames = (ds3000_readreg(state, 0xd7) << 16) |
544 (ds3000_readreg(state, 0xd6) << 8) |
545 ds3000_readreg(state, 0xd5);
546
547 ber_reading = (ds3000_readreg(state, 0xf8) << 8) |
548 ds3000_readreg(state, 0xf7);
549 if (lpdc_frames > 750) {
550
551 ds3000_writereg(state, 0xd1, 0x01);
552
553 ds3000_writereg(state, 0xf9, 0x01);
554
555 ds3000_writereg(state, 0xf9, 0x00);
556
557 ds3000_writereg(state, 0xd1, 0x00);
558 *ber = ber_reading;
559 } else
560
561
562 *ber = 0xffffffff;
563 break;
564 default:
565 return 1;
566 }
567
568 return 0;
569}
570
571
572static int ds3000_read_signal_strength(struct dvb_frontend *fe,
573 u16 *signal_strength)
574{
575 struct ds3000_state *state = fe->demodulator_priv;
576 u16 sig_reading, sig_strength;
577 u8 rfgain, bbgain;
578
579 dprintk("%s()\n", __func__);
580
581 rfgain = ds3000_tuner_readreg(state, 0x3d) & 0x1f;
582 bbgain = ds3000_tuner_readreg(state, 0x21) & 0x1f;
583
584 if (rfgain > 15)
585 rfgain = 15;
586 if (bbgain > 13)
587 bbgain = 13;
588
589 sig_reading = rfgain * 2 + bbgain * 3;
590
591 sig_strength = 40 + (64 - sig_reading) * 50 / 64 ;
592
593
594 *signal_strength = sig_strength * 1000;
595
596 dprintk("%s: raw / cooked = 0x%04x / 0x%04x\n", __func__,
597 sig_reading, *signal_strength);
598
599 return 0;
600}
601
602
603static int ds3000_read_snr(struct dvb_frontend *fe, u16 *snr)
604{
605 struct ds3000_state *state = fe->demodulator_priv;
606 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
607 u8 snr_reading, snr_value;
608 u32 dvbs2_signal_reading, dvbs2_noise_reading, tmp;
609 static const u16 dvbs_snr_tab[] = {
610 0x0000, 0x1b13, 0x2aea, 0x3627, 0x3ede, 0x45fe, 0x4c03,
611 0x513a, 0x55d4, 0x59f2, 0x5dab, 0x6111, 0x6431, 0x6717,
612 0x69c9, 0x6c4e, 0x6eac, 0x70e8, 0x7304, 0x7505
613 };
614 static const u16 dvbs2_snr_tab[] = {
615 0x0000, 0x0bc2, 0x12a3, 0x1785, 0x1b4e, 0x1e65, 0x2103,
616 0x2347, 0x2546, 0x2710, 0x28ae, 0x2a28, 0x2b83, 0x2cc5,
617 0x2df1, 0x2f09, 0x3010, 0x3109, 0x31f4, 0x32d2, 0x33a6,
618 0x3470, 0x3531, 0x35ea, 0x369b, 0x3746, 0x37ea, 0x3888,
619 0x3920, 0x39b3, 0x3a42, 0x3acc, 0x3b51, 0x3bd3, 0x3c51,
620 0x3ccb, 0x3d42, 0x3db6, 0x3e27, 0x3e95, 0x3f00, 0x3f68,
621 0x3fcf, 0x4033, 0x4094, 0x40f4, 0x4151, 0x41ac, 0x4206,
622 0x425e, 0x42b4, 0x4308, 0x435b, 0x43ac, 0x43fc, 0x444a,
623 0x4497, 0x44e2, 0x452d, 0x4576, 0x45bd, 0x4604, 0x4649,
624 0x468e, 0x46d1, 0x4713, 0x4755, 0x4795, 0x47d4, 0x4813,
625 0x4851, 0x488d, 0x48c9, 0x4904, 0x493f, 0x4978, 0x49b1,
626 0x49e9, 0x4a20, 0x4a57
627 };
628
629 dprintk("%s()\n", __func__);
630
631 switch (c->delivery_system) {
632 case SYS_DVBS:
633 snr_reading = ds3000_readreg(state, 0xff);
634 snr_reading /= 8;
635 if (snr_reading == 0)
636 *snr = 0x0000;
637 else {
638 if (snr_reading > 20)
639 snr_reading = 20;
640 snr_value = dvbs_snr_tab[snr_reading - 1] * 10 / 23026;
641
642
643 *snr = snr_value * 8 * 655;
644 }
645 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
646 snr_reading, *snr);
647 break;
648 case SYS_DVBS2:
649 dvbs2_noise_reading = (ds3000_readreg(state, 0x8c) & 0x3f) +
650 (ds3000_readreg(state, 0x8d) << 4);
651 dvbs2_signal_reading = ds3000_readreg(state, 0x8e);
652 tmp = dvbs2_signal_reading * dvbs2_signal_reading >> 1;
653 if (tmp == 0) {
654 *snr = 0x0000;
655 return 0;
656 }
657 if (dvbs2_noise_reading == 0) {
658 snr_value = 0x0013;
659
660
661 *snr = 0xffff;
662 return 0;
663 }
664 if (tmp > dvbs2_noise_reading) {
665 snr_reading = tmp / dvbs2_noise_reading;
666 if (snr_reading > 80)
667 snr_reading = 80;
668 snr_value = dvbs2_snr_tab[snr_reading - 1] / 1000;
669
670
671 *snr = snr_value * 5 * 655;
672 } else {
673 snr_reading = dvbs2_noise_reading / tmp;
674 if (snr_reading > 80)
675 snr_reading = 80;
676 *snr = -(dvbs2_snr_tab[snr_reading] / 1000);
677 }
678 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
679 snr_reading, *snr);
680 break;
681 default:
682 return 1;
683 }
684
685 return 0;
686}
687
688
689static int ds3000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
690{
691 struct ds3000_state *state = fe->demodulator_priv;
692 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
693 u8 data;
694 u16 _ucblocks;
695
696 dprintk("%s()\n", __func__);
697
698 switch (c->delivery_system) {
699 case SYS_DVBS:
700 *ucblocks = (ds3000_readreg(state, 0xf5) << 8) |
701 ds3000_readreg(state, 0xf4);
702 data = ds3000_readreg(state, 0xf8);
703
704 data &= ~0x20;
705 ds3000_writereg(state, 0xf8, data);
706
707 data |= 0x20;
708 ds3000_writereg(state, 0xf8, data);
709 break;
710 case SYS_DVBS2:
711 _ucblocks = (ds3000_readreg(state, 0xe2) << 8) |
712 ds3000_readreg(state, 0xe1);
713 if (_ucblocks > state->prevUCBS2)
714 *ucblocks = _ucblocks - state->prevUCBS2;
715 else
716 *ucblocks = state->prevUCBS2 - _ucblocks;
717 state->prevUCBS2 = _ucblocks;
718 break;
719 default:
720 return 1;
721 }
722
723 return 0;
724}
725
726static int ds3000_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
727{
728 struct ds3000_state *state = fe->demodulator_priv;
729 u8 data;
730
731 dprintk("%s(%d)\n", __func__, tone);
732 if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) {
733 printk(KERN_ERR "%s: Invalid, tone=%d\n", __func__, tone);
734 return -EINVAL;
735 }
736
737 data = ds3000_readreg(state, 0xa2);
738 data &= ~0xc0;
739 ds3000_writereg(state, 0xa2, data);
740
741 switch (tone) {
742 case SEC_TONE_ON:
743 dprintk("%s: setting tone on\n", __func__);
744 data = ds3000_readreg(state, 0xa1);
745 data &= ~0x43;
746 data |= 0x04;
747 ds3000_writereg(state, 0xa1, data);
748 break;
749 case SEC_TONE_OFF:
750 dprintk("%s: setting tone off\n", __func__);
751 data = ds3000_readreg(state, 0xa2);
752 data |= 0x80;
753 ds3000_writereg(state, 0xa2, data);
754 break;
755 }
756
757 return 0;
758}
759
760static int ds3000_send_diseqc_msg(struct dvb_frontend *fe,
761 struct dvb_diseqc_master_cmd *d)
762{
763 struct ds3000_state *state = fe->demodulator_priv;
764 int i;
765 u8 data;
766
767
768 dprintk("%s(", __func__);
769 for (i = 0 ; i < d->msg_len;) {
770 dprintk("0x%02x", d->msg[i]);
771 if (++i < d->msg_len)
772 dprintk(", ");
773 }
774
775
776 data = ds3000_readreg(state, 0xa2);
777 data &= ~0xc0;
778 ds3000_writereg(state, 0xa2, data);
779
780
781 for (i = 0; i < d->msg_len; i++)
782 ds3000_writereg(state, 0xa3 + i, d->msg[i]);
783
784 data = ds3000_readreg(state, 0xa1);
785
786
787 data &= ~0xf8;
788
789
790 data |= ((d->msg_len - 1) << 3) | 0x07;
791 ds3000_writereg(state, 0xa1, data);
792
793
794 for (i = 0; i < 15; i++) {
795 data = ds3000_readreg(state, 0xa1);
796 if ((data & 0x40) == 0)
797 break;
798 msleep(10);
799 }
800
801
802 if (i == 15) {
803 data = ds3000_readreg(state, 0xa1);
804 data &= ~0x80;
805 data |= 0x40;
806 ds3000_writereg(state, 0xa1, data);
807
808 data = ds3000_readreg(state, 0xa2);
809 data &= ~0xc0;
810 data |= 0x80;
811 ds3000_writereg(state, 0xa2, data);
812
813 return 1;
814 }
815
816 data = ds3000_readreg(state, 0xa2);
817 data &= ~0xc0;
818 data |= 0x80;
819 ds3000_writereg(state, 0xa2, data);
820
821 return 0;
822}
823
824
825static int ds3000_diseqc_send_burst(struct dvb_frontend *fe,
826 fe_sec_mini_cmd_t burst)
827{
828 struct ds3000_state *state = fe->demodulator_priv;
829 int i;
830 u8 data;
831
832 dprintk("%s()\n", __func__);
833
834 data = ds3000_readreg(state, 0xa2);
835 data &= ~0xc0;
836 ds3000_writereg(state, 0xa2, data);
837
838
839 if (burst == SEC_MINI_A)
840
841 ds3000_writereg(state, 0xa1, 0x02);
842 else if (burst == SEC_MINI_B)
843
844 ds3000_writereg(state, 0xa1, 0x01);
845 else
846 return -EINVAL;
847
848 msleep(13);
849 for (i = 0; i < 5; i++) {
850 data = ds3000_readreg(state, 0xa1);
851 if ((data & 0x40) == 0)
852 break;
853 msleep(1);
854 }
855
856 if (i == 5) {
857 data = ds3000_readreg(state, 0xa1);
858 data &= ~0x80;
859 data |= 0x40;
860 ds3000_writereg(state, 0xa1, data);
861
862 data = ds3000_readreg(state, 0xa2);
863 data &= ~0xc0;
864 data |= 0x80;
865 ds3000_writereg(state, 0xa2, data);
866
867 return 1;
868 }
869
870 data = ds3000_readreg(state, 0xa2);
871 data &= ~0xc0;
872 data |= 0x80;
873 ds3000_writereg(state, 0xa2, data);
874
875 return 0;
876}
877
878static void ds3000_release(struct dvb_frontend *fe)
879{
880 struct ds3000_state *state = fe->demodulator_priv;
881 dprintk("%s\n", __func__);
882 kfree(state);
883}
884
885static struct dvb_frontend_ops ds3000_ops;
886
887struct dvb_frontend *ds3000_attach(const struct ds3000_config *config,
888 struct i2c_adapter *i2c)
889{
890 struct ds3000_state *state = NULL;
891 int ret;
892
893 dprintk("%s\n", __func__);
894
895
896 state = kzalloc(sizeof(struct ds3000_state), GFP_KERNEL);
897 if (state == NULL) {
898 printk(KERN_ERR "Unable to kmalloc\n");
899 goto error2;
900 }
901
902 state->config = config;
903 state->i2c = i2c;
904 state->prevUCBS2 = 0;
905
906
907 ret = ds3000_readreg(state, 0x00) & 0xfe;
908 if (ret != 0xe0) {
909 printk(KERN_ERR "Invalid probe, probably not a DS3000\n");
910 goto error3;
911 }
912
913 printk(KERN_INFO "DS3000 chip version: %d.%d attached.\n",
914 ds3000_readreg(state, 0x02),
915 ds3000_readreg(state, 0x01));
916
917 memcpy(&state->frontend.ops, &ds3000_ops,
918 sizeof(struct dvb_frontend_ops));
919 state->frontend.demodulator_priv = state;
920 return &state->frontend;
921
922error3:
923 kfree(state);
924error2:
925 return NULL;
926}
927EXPORT_SYMBOL(ds3000_attach);
928
929static int ds3000_set_carrier_offset(struct dvb_frontend *fe,
930 s32 carrier_offset_khz)
931{
932 struct ds3000_state *state = fe->demodulator_priv;
933 s32 tmp;
934
935 tmp = carrier_offset_khz;
936 tmp *= 65536;
937 tmp = (2 * tmp + DS3000_SAMPLE_RATE) / (2 * DS3000_SAMPLE_RATE);
938
939 if (tmp < 0)
940 tmp += 65536;
941
942 ds3000_writereg(state, 0x5f, tmp >> 8);
943 ds3000_writereg(state, 0x5e, tmp & 0xff);
944
945 return 0;
946}
947
948static int ds3000_set_frontend(struct dvb_frontend *fe)
949{
950 struct ds3000_state *state = fe->demodulator_priv;
951 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
952
953 int i;
954 fe_status_t status;
955 u8 mlpf, mlpf_new, mlpf_max, mlpf_min, nlpf, div4;
956 s32 offset_khz;
957 u16 value, ndiv;
958 u32 f3db;
959
960 dprintk("%s() ", __func__);
961
962 if (state->config->set_ts_params)
963 state->config->set_ts_params(fe, 0);
964
965
966 ds3000_tuner_writereg(state, 0x07, 0x02);
967 ds3000_tuner_writereg(state, 0x10, 0x00);
968 ds3000_tuner_writereg(state, 0x60, 0x79);
969 ds3000_tuner_writereg(state, 0x08, 0x01);
970 ds3000_tuner_writereg(state, 0x00, 0x01);
971 div4 = 0;
972
973
974 if (c->frequency < 1146000) {
975 ds3000_tuner_writereg(state, 0x10, 0x11);
976 div4 = 1;
977 ndiv = ((c->frequency * (6 + 8) * 4) +
978 (DS3000_XTAL_FREQ / 2)) /
979 DS3000_XTAL_FREQ - 1024;
980 } else {
981 ds3000_tuner_writereg(state, 0x10, 0x01);
982 ndiv = ((c->frequency * (6 + 8) * 2) +
983 (DS3000_XTAL_FREQ / 2)) /
984 DS3000_XTAL_FREQ - 1024;
985 }
986
987 ds3000_tuner_writereg(state, 0x01, (ndiv & 0x0f00) >> 8);
988 ds3000_tuner_writereg(state, 0x02, ndiv & 0x00ff);
989
990
991 ds3000_tuner_writereg(state, 0x03, 0x06);
992 ds3000_tuner_writereg(state, 0x51, 0x0f);
993 ds3000_tuner_writereg(state, 0x51, 0x1f);
994 ds3000_tuner_writereg(state, 0x50, 0x10);
995 ds3000_tuner_writereg(state, 0x50, 0x00);
996 msleep(5);
997
998
999 ds3000_tuner_writereg(state, 0x51, 0x17);
1000 ds3000_tuner_writereg(state, 0x51, 0x1f);
1001 ds3000_tuner_writereg(state, 0x50, 0x08);
1002 ds3000_tuner_writereg(state, 0x50, 0x00);
1003 msleep(5);
1004
1005 value = ds3000_tuner_readreg(state, 0x3d);
1006 value &= 0x0f;
1007 if ((value > 4) && (value < 15)) {
1008 value -= 3;
1009 if (value < 4)
1010 value = 4;
1011 value = ((value << 3) | 0x01) & 0x79;
1012 }
1013
1014 ds3000_tuner_writereg(state, 0x60, value);
1015 ds3000_tuner_writereg(state, 0x51, 0x17);
1016 ds3000_tuner_writereg(state, 0x51, 0x1f);
1017 ds3000_tuner_writereg(state, 0x50, 0x08);
1018 ds3000_tuner_writereg(state, 0x50, 0x00);
1019
1020
1021 ds3000_tuner_writereg(state, 0x04, 0x2e);
1022 ds3000_tuner_writereg(state, 0x51, 0x1b);
1023 ds3000_tuner_writereg(state, 0x51, 0x1f);
1024 ds3000_tuner_writereg(state, 0x50, 0x04);
1025 ds3000_tuner_writereg(state, 0x50, 0x00);
1026 msleep(5);
1027
1028 f3db = ((c->symbol_rate / 1000) << 2) / 5 + 2000;
1029 if ((c->symbol_rate / 1000) < 5000)
1030 f3db += 3000;
1031 if (f3db < 7000)
1032 f3db = 7000;
1033 if (f3db > 40000)
1034 f3db = 40000;
1035
1036
1037 value = ds3000_tuner_readreg(state, 0x26);
1038 mlpf = 0x2e * 207 / ((value << 1) + 151);
1039 mlpf_max = mlpf * 135 / 100;
1040 mlpf_min = mlpf * 78 / 100;
1041 if (mlpf_max > 63)
1042 mlpf_max = 63;
1043
1044
1045 nlpf = ((mlpf * f3db * 1000) + (2766 * DS3000_XTAL_FREQ / 2))
1046 / (2766 * DS3000_XTAL_FREQ);
1047 if (nlpf > 23)
1048 nlpf = 23;
1049 if (nlpf < 1)
1050 nlpf = 1;
1051
1052
1053 mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
1054 (1000 * f3db / 2)) / (1000 * f3db);
1055
1056 if (mlpf_new < mlpf_min) {
1057 nlpf++;
1058 mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
1059 (1000 * f3db / 2)) / (1000 * f3db);
1060 }
1061
1062 if (mlpf_new > mlpf_max)
1063 mlpf_new = mlpf_max;
1064
1065 ds3000_tuner_writereg(state, 0x04, mlpf_new);
1066 ds3000_tuner_writereg(state, 0x06, nlpf);
1067 ds3000_tuner_writereg(state, 0x51, 0x1b);
1068 ds3000_tuner_writereg(state, 0x51, 0x1f);
1069 ds3000_tuner_writereg(state, 0x50, 0x04);
1070 ds3000_tuner_writereg(state, 0x50, 0x00);
1071 msleep(5);
1072
1073
1074 ds3000_tuner_writereg(state, 0x51, 0x1e);
1075 ds3000_tuner_writereg(state, 0x51, 0x1f);
1076 ds3000_tuner_writereg(state, 0x50, 0x01);
1077 ds3000_tuner_writereg(state, 0x50, 0x00);
1078 msleep(60);
1079
1080 offset_khz = (ndiv - ndiv % 2 + 1024) * DS3000_XTAL_FREQ
1081 / (6 + 8) / (div4 + 1) / 2 - c->frequency;
1082
1083
1084 ds3000_writereg(state, 0x07, 0x80);
1085 ds3000_writereg(state, 0x07, 0x00);
1086
1087 ds3000_writereg(state, 0xb2, 0x01);
1088
1089 ds3000_writereg(state, 0x00, 0x01);
1090
1091 switch (c->delivery_system) {
1092 case SYS_DVBS:
1093
1094 for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2)
1095 ds3000_writereg(state,
1096 ds3000_dvbs_init_tab[i],
1097 ds3000_dvbs_init_tab[i + 1]);
1098 value = ds3000_readreg(state, 0xfe);
1099 value &= 0xc0;
1100 value |= 0x1b;
1101 ds3000_writereg(state, 0xfe, value);
1102 break;
1103 case SYS_DVBS2:
1104
1105 for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2)
1106 ds3000_writereg(state,
1107 ds3000_dvbs2_init_tab[i],
1108 ds3000_dvbs2_init_tab[i + 1]);
1109 if (c->symbol_rate >= 30000000)
1110 ds3000_writereg(state, 0xfe, 0x54);
1111 else
1112 ds3000_writereg(state, 0xfe, 0x98);
1113 break;
1114 default:
1115 return 1;
1116 }
1117
1118
1119 ds3000_writereg(state, 0x29, 0x80);
1120
1121 ds3000_writereg(state, 0x25, 0x8a);
1122
1123
1124 if ((c->symbol_rate / 1000) <= 5000) {
1125 value = 29777 / (c->symbol_rate / 1000) + 1;
1126 if (value % 2 != 0)
1127 value++;
1128 ds3000_writereg(state, 0xc3, 0x0d);
1129 ds3000_writereg(state, 0xc8, value);
1130 ds3000_writereg(state, 0xc4, 0x10);
1131 ds3000_writereg(state, 0xc7, 0x0e);
1132 } else if ((c->symbol_rate / 1000) <= 10000) {
1133 value = 92166 / (c->symbol_rate / 1000) + 1;
1134 if (value % 2 != 0)
1135 value++;
1136 ds3000_writereg(state, 0xc3, 0x07);
1137 ds3000_writereg(state, 0xc8, value);
1138 ds3000_writereg(state, 0xc4, 0x09);
1139 ds3000_writereg(state, 0xc7, 0x12);
1140 } else if ((c->symbol_rate / 1000) <= 20000) {
1141 value = 64516 / (c->symbol_rate / 1000) + 1;
1142 ds3000_writereg(state, 0xc3, value);
1143 ds3000_writereg(state, 0xc8, 0x0e);
1144 ds3000_writereg(state, 0xc4, 0x07);
1145 ds3000_writereg(state, 0xc7, 0x18);
1146 } else {
1147 value = 129032 / (c->symbol_rate / 1000) + 1;
1148 ds3000_writereg(state, 0xc3, value);
1149 ds3000_writereg(state, 0xc8, 0x0a);
1150 ds3000_writereg(state, 0xc4, 0x05);
1151 ds3000_writereg(state, 0xc7, 0x24);
1152 }
1153
1154
1155 value = (((c->symbol_rate / 1000) << 16) +
1156 (DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
1157 ds3000_writereg(state, 0x61, value & 0x00ff);
1158 ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);
1159
1160
1161 ds3000_writereg(state, 0x56, 0x00);
1162
1163
1164 ds3000_writereg(state, 0x76, 0x00);
1165
1166
1167
1168
1169
1170
1171
1172 if (state->config->ci_mode) {
1173 switch (c->delivery_system) {
1174 case SYS_DVBS:
1175 default:
1176 ds3000_writereg(state, 0xfd, 0x80);
1177 break;
1178 case SYS_DVBS2:
1179 ds3000_writereg(state, 0xfd, 0x01);
1180 break;
1181 }
1182 }
1183
1184
1185 ds3000_writereg(state, 0x00, 0x00);
1186
1187 ds3000_writereg(state, 0xb2, 0x00);
1188
1189 ds3000_set_carrier_offset(fe, offset_khz);
1190
1191 for (i = 0; i < 30 ; i++) {
1192 ds3000_read_status(fe, &status);
1193 if (status & FE_HAS_LOCK)
1194 break;
1195
1196 msleep(10);
1197 }
1198
1199 return 0;
1200}
1201
1202static int ds3000_tune(struct dvb_frontend *fe,
1203 bool re_tune,
1204 unsigned int mode_flags,
1205 unsigned int *delay,
1206 fe_status_t *status)
1207{
1208 if (re_tune) {
1209 int ret = ds3000_set_frontend(fe);
1210 if (ret)
1211 return ret;
1212 }
1213
1214 *delay = HZ / 5;
1215
1216 return ds3000_read_status(fe, status);
1217}
1218
1219static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe)
1220{
1221 dprintk("%s()\n", __func__);
1222 return DVBFE_ALGO_HW;
1223}
1224
1225
1226
1227
1228
1229
1230static int ds3000_initfe(struct dvb_frontend *fe)
1231{
1232 struct ds3000_state *state = fe->demodulator_priv;
1233 int ret;
1234
1235 dprintk("%s()\n", __func__);
1236
1237 ds3000_writereg(state, 0x08, 0x01 | ds3000_readreg(state, 0x08));
1238 msleep(1);
1239
1240
1241 ds3000_tuner_writereg(state, 0x42, 0x73);
1242 ds3000_tuner_writereg(state, 0x05, 0x01);
1243 ds3000_tuner_writereg(state, 0x62, 0xf5);
1244
1245 ret = ds3000_firmware_ondemand(fe);
1246 if (ret != 0) {
1247 printk(KERN_ERR "%s: Unable initialize firmware\n", __func__);
1248 return ret;
1249 }
1250
1251 return 0;
1252}
1253
1254
1255static int ds3000_sleep(struct dvb_frontend *fe)
1256{
1257 dprintk("%s()\n", __func__);
1258 return 0;
1259}
1260
1261static struct dvb_frontend_ops ds3000_ops = {
1262 .delsys = { SYS_DVBS, SYS_DVBS2},
1263 .info = {
1264 .name = "Montage Technology DS3000/TS2020",
1265 .frequency_min = 950000,
1266 .frequency_max = 2150000,
1267 .frequency_stepsize = 1011,
1268 .frequency_tolerance = 5000,
1269 .symbol_rate_min = 1000000,
1270 .symbol_rate_max = 45000000,
1271 .caps = FE_CAN_INVERSION_AUTO |
1272 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1273 FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
1274 FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1275 FE_CAN_2G_MODULATION |
1276 FE_CAN_QPSK | FE_CAN_RECOVER
1277 },
1278
1279 .release = ds3000_release,
1280
1281 .init = ds3000_initfe,
1282 .sleep = ds3000_sleep,
1283 .read_status = ds3000_read_status,
1284 .read_ber = ds3000_read_ber,
1285 .read_signal_strength = ds3000_read_signal_strength,
1286 .read_snr = ds3000_read_snr,
1287 .read_ucblocks = ds3000_read_ucblocks,
1288 .set_voltage = ds3000_set_voltage,
1289 .set_tone = ds3000_set_tone,
1290 .diseqc_send_master_cmd = ds3000_send_diseqc_msg,
1291 .diseqc_send_burst = ds3000_diseqc_send_burst,
1292 .get_frontend_algo = ds3000_get_algo,
1293
1294 .set_frontend = ds3000_set_frontend,
1295 .tune = ds3000_tune,
1296};
1297
1298module_param(debug, int, 0644);
1299MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
1300
1301MODULE_DESCRIPTION("DVB Frontend module for Montage Technology "
1302 "DS3000/TS2020 hardware");
1303MODULE_AUTHOR("Konstantin Dimitrov");
1304MODULE_LICENSE("GPL");
1305MODULE_FIRMWARE(DS3000_DEFAULT_FIRMWARE);
1306
