linux/drivers/watchdog/of_xilinx_wdt.c
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   1/*
   2*   of_xilinx_wdt.c  1.01  A Watchdog Device Driver for Xilinx xps_timebase_wdt
   3*
   4*   (C) Copyright 2011 (Alejandro Cabrera <aldaya@gmail.com>)
   5*
   6*       -----------------------
   7*
   8*   This program is free software; you can redistribute it and/or
   9*   modify it under the terms of the GNU General Public License
  10*   as published by the Free Software Foundation; either version
  11*   2 of the License, or (at your option) any later version.
  12*
  13*       -----------------------
  14*       30-May-2011 Alejandro Cabrera <aldaya@gmail.com>
  15*               - If "xlnx,wdt-enable-once" wasn't found on device tree the
  16*                 module will use CONFIG_WATCHDOG_NOWAYOUT
  17*               - If the device tree parameters ("clock-frequency" and
  18*                 "xlnx,wdt-interval") wasn't found the driver won't
  19*                 know the wdt reset interval
  20*/
  21
  22#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  23
  24#include <linux/module.h>
  25#include <linux/types.h>
  26#include <linux/kernel.h>
  27#include <linux/fs.h>
  28#include <linux/miscdevice.h>
  29#include <linux/init.h>
  30#include <linux/ioport.h>
  31#include <linux/watchdog.h>
  32#include <linux/io.h>
  33#include <linux/uaccess.h>
  34#include <linux/of.h>
  35#include <linux/of_device.h>
  36#include <linux/of_address.h>
  37
  38/* Register offsets for the Wdt device */
  39#define XWT_TWCSR0_OFFSET   0x0 /* Control/Status Register0 */
  40#define XWT_TWCSR1_OFFSET   0x4 /* Control/Status Register1 */
  41#define XWT_TBR_OFFSET      0x8 /* Timebase Register Offset */
  42
  43/* Control/Status Register Masks  */
  44#define XWT_CSR0_WRS_MASK   0x00000008 /* Reset status */
  45#define XWT_CSR0_WDS_MASK   0x00000004 /* Timer state  */
  46#define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 */
  47
  48/* Control/Status Register 0/1 bits  */
  49#define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 */
  50
  51/* SelfTest constants */
  52#define XWT_MAX_SELFTEST_LOOP_COUNT 0x00010000
  53#define XWT_TIMER_FAILED            0xFFFFFFFF
  54
  55#define WATCHDOG_NAME     "Xilinx Watchdog"
  56#define PFX WATCHDOG_NAME ": "
  57
  58struct xwdt_device {
  59        struct resource  res;
  60        void __iomem *base;
  61        u32 nowayout;
  62        u32 wdt_interval;
  63        u32 boot_status;
  64};
  65
  66static struct xwdt_device xdev;
  67
  68static  u32 timeout;
  69static  u32 control_status_reg;
  70static  u8  expect_close;
  71static  u8  no_timeout;
  72static unsigned long driver_open;
  73
  74static  DEFINE_SPINLOCK(spinlock);
  75
  76static void xwdt_start(void)
  77{
  78        spin_lock(&spinlock);
  79
  80        /* Clean previous status and enable the watchdog timer */
  81        control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET);
  82        control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);
  83
  84        iowrite32((control_status_reg | XWT_CSR0_EWDT1_MASK),
  85                                xdev.base + XWT_TWCSR0_OFFSET);
  86
  87        iowrite32(XWT_CSRX_EWDT2_MASK, xdev.base + XWT_TWCSR1_OFFSET);
  88
  89        spin_unlock(&spinlock);
  90}
  91
  92static void xwdt_stop(void)
  93{
  94        spin_lock(&spinlock);
  95
  96        control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET);
  97
  98        iowrite32((control_status_reg & ~XWT_CSR0_EWDT1_MASK),
  99                                xdev.base + XWT_TWCSR0_OFFSET);
 100
 101        iowrite32(0, xdev.base + XWT_TWCSR1_OFFSET);
 102
 103        spin_unlock(&spinlock);
 104        pr_info("Stopped!\n");
 105}
 106
 107static void xwdt_keepalive(void)
 108{
 109        spin_lock(&spinlock);
 110
 111        control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET);
 112        control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);
 113        iowrite32(control_status_reg, xdev.base + XWT_TWCSR0_OFFSET);
 114
 115        spin_unlock(&spinlock);
 116}
 117
 118static void xwdt_get_status(int *status)
 119{
 120        int new_status;
 121
 122        spin_lock(&spinlock);
 123
 124        control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET);
 125        new_status = ((control_status_reg &
 126                        (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK)) != 0);
 127        spin_unlock(&spinlock);
 128
 129        *status = 0;
 130        if (new_status & 1)
 131                *status |= WDIOF_CARDRESET;
 132}
 133
 134static u32 xwdt_selftest(void)
 135{
 136        int i;
 137        u32 timer_value1;
 138        u32 timer_value2;
 139
 140        spin_lock(&spinlock);
 141
 142        timer_value1 = ioread32(xdev.base + XWT_TBR_OFFSET);
 143        timer_value2 = ioread32(xdev.base + XWT_TBR_OFFSET);
 144
 145        for (i = 0;
 146                ((i <= XWT_MAX_SELFTEST_LOOP_COUNT) &&
 147                        (timer_value2 == timer_value1)); i++) {
 148                timer_value2 = ioread32(xdev.base + XWT_TBR_OFFSET);
 149        }
 150
 151        spin_unlock(&spinlock);
 152
 153        if (timer_value2 != timer_value1)
 154                return ~XWT_TIMER_FAILED;
 155        else
 156                return XWT_TIMER_FAILED;
 157}
 158
 159static int xwdt_open(struct inode *inode, struct file *file)
 160{
 161        /* Only one process can handle the wdt at a time */
 162        if (test_and_set_bit(0, &driver_open))
 163                return -EBUSY;
 164
 165        /* Make sure that the module are always loaded...*/
 166        if (xdev.nowayout)
 167                __module_get(THIS_MODULE);
 168
 169        xwdt_start();
 170        pr_info("Started...\n");
 171
 172        return nonseekable_open(inode, file);
 173}
 174
 175static int xwdt_release(struct inode *inode, struct file *file)
 176{
 177        if (expect_close == 42) {
 178                xwdt_stop();
 179        } else {
 180                pr_crit("Unexpected close, not stopping watchdog!\n");
 181                xwdt_keepalive();
 182        }
 183
 184        clear_bit(0, &driver_open);
 185        expect_close = 0;
 186        return 0;
 187}
 188
 189/*
 190 *      xwdt_write:
 191 *      @file: file handle to the watchdog
 192 *      @buf: buffer to write (unused as data does not matter here
 193 *      @count: count of bytes
 194 *      @ppos: pointer to the position to write. No seeks allowed
 195 *
 196 *      A write to a watchdog device is defined as a keepalive signal. Any
 197 *      write of data will do, as we don't define content meaning.
 198 */
 199static ssize_t xwdt_write(struct file *file, const char __user *buf,
 200                                                size_t len, loff_t *ppos)
 201{
 202        if (len) {
 203                if (!xdev.nowayout) {
 204                        size_t i;
 205
 206                        /* In case it was set long ago */
 207                        expect_close = 0;
 208
 209                        for (i = 0; i != len; i++) {
 210                                char c;
 211
 212                                if (get_user(c, buf + i))
 213                                        return -EFAULT;
 214                                if (c == 'V')
 215                                        expect_close = 42;
 216                        }
 217                }
 218                xwdt_keepalive();
 219        }
 220        return len;
 221}
 222
 223static const struct watchdog_info ident = {
 224        .options =  WDIOF_MAGICCLOSE |
 225                    WDIOF_KEEPALIVEPING,
 226        .firmware_version =     1,
 227        .identity =     WATCHDOG_NAME,
 228};
 229
 230/*
 231 *      xwdt_ioctl:
 232 *      @file: file handle to the device
 233 *      @cmd: watchdog command
 234 *      @arg: argument pointer
 235 *
 236 *      The watchdog API defines a common set of functions for all watchdogs
 237 *      according to their available features.
 238 */
 239static long xwdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
 240{
 241        int status;
 242
 243        union {
 244                struct watchdog_info __user *ident;
 245                int __user *i;
 246        } uarg;
 247
 248        uarg.i = (int __user *)arg;
 249
 250        switch (cmd) {
 251        case WDIOC_GETSUPPORT:
 252                return copy_to_user(uarg.ident, &ident,
 253                                        sizeof(ident)) ? -EFAULT : 0;
 254
 255        case WDIOC_GETBOOTSTATUS:
 256                return put_user(xdev.boot_status, uarg.i);
 257
 258        case WDIOC_GETSTATUS:
 259                xwdt_get_status(&status);
 260                return put_user(status, uarg.i);
 261
 262        case WDIOC_KEEPALIVE:
 263                xwdt_keepalive();
 264                return 0;
 265
 266        case WDIOC_GETTIMEOUT:
 267                if (no_timeout)
 268                        return -ENOTTY;
 269                else
 270                        return put_user(timeout, uarg.i);
 271
 272        default:
 273                return -ENOTTY;
 274        }
 275}
 276
 277static const struct file_operations xwdt_fops = {
 278        .owner      = THIS_MODULE,
 279        .llseek     = no_llseek,
 280        .write      = xwdt_write,
 281        .open       = xwdt_open,
 282        .release    = xwdt_release,
 283        .unlocked_ioctl = xwdt_ioctl,
 284};
 285
 286static struct miscdevice xwdt_miscdev = {
 287        .minor      = WATCHDOG_MINOR,
 288        .name       = "watchdog",
 289        .fops       = &xwdt_fops,
 290};
 291
 292static int xwdt_probe(struct platform_device *pdev)
 293{
 294        int rc;
 295        u32 *tmptr;
 296        u32 *pfreq;
 297
 298        no_timeout = 0;
 299
 300        pfreq = (u32 *)of_get_property(pdev->dev.of_node,
 301                                        "clock-frequency", NULL);
 302
 303        if (pfreq == NULL) {
 304                pr_warn("The watchdog clock frequency cannot be obtained!\n");
 305                no_timeout = 1;
 306        }
 307
 308        rc = of_address_to_resource(pdev->dev.of_node, 0, &xdev.res);
 309        if (rc) {
 310                pr_warn("invalid address!\n");
 311                return rc;
 312        }
 313
 314        tmptr = (u32 *)of_get_property(pdev->dev.of_node,
 315                                        "xlnx,wdt-interval", NULL);
 316        if (tmptr == NULL) {
 317                pr_warn("Parameter \"xlnx,wdt-interval\" not found in device tree!\n");
 318                no_timeout = 1;
 319        } else {
 320                xdev.wdt_interval = *tmptr;
 321        }
 322
 323        tmptr = (u32 *)of_get_property(pdev->dev.of_node,
 324                                        "xlnx,wdt-enable-once", NULL);
 325        if (tmptr == NULL) {
 326                pr_warn("Parameter \"xlnx,wdt-enable-once\" not found in device tree!\n");
 327                xdev.nowayout = WATCHDOG_NOWAYOUT;
 328        }
 329
 330/*
 331 *  Twice of the 2^wdt_interval / freq  because the first wdt overflow is
 332 *  ignored (interrupt), reset is only generated at second wdt overflow
 333 */
 334        if (!no_timeout)
 335                timeout = 2 * ((1<<xdev.wdt_interval) / *pfreq);
 336
 337        if (!request_mem_region(xdev.res.start,
 338                        xdev.res.end - xdev.res.start + 1, WATCHDOG_NAME)) {
 339                rc = -ENXIO;
 340                pr_err("memory request failure!\n");
 341                goto err_out;
 342        }
 343
 344        xdev.base = ioremap(xdev.res.start, xdev.res.end - xdev.res.start + 1);
 345        if (xdev.base == NULL) {
 346                rc = -ENOMEM;
 347                pr_err("ioremap failure!\n");
 348                goto release_mem;
 349        }
 350
 351        rc = xwdt_selftest();
 352        if (rc == XWT_TIMER_FAILED) {
 353                pr_err("SelfTest routine error!\n");
 354                goto unmap_io;
 355        }
 356
 357        xwdt_get_status(&xdev.boot_status);
 358
 359        rc = misc_register(&xwdt_miscdev);
 360        if (rc) {
 361                pr_err("cannot register miscdev on minor=%d (err=%d)\n",
 362                       xwdt_miscdev.minor, rc);
 363                goto unmap_io;
 364        }
 365
 366        if (no_timeout)
 367                pr_info("driver loaded (timeout=? sec, nowayout=%d)\n",
 368                        xdev.nowayout);
 369        else
 370                pr_info("driver loaded (timeout=%d sec, nowayout=%d)\n",
 371                        timeout, xdev.nowayout);
 372
 373        expect_close = 0;
 374        clear_bit(0, &driver_open);
 375
 376        return 0;
 377
 378unmap_io:
 379        iounmap(xdev.base);
 380release_mem:
 381        release_mem_region(xdev.res.start, resource_size(&xdev.res));
 382err_out:
 383        return rc;
 384}
 385
 386static int xwdt_remove(struct platform_device *dev)
 387{
 388        misc_deregister(&xwdt_miscdev);
 389        iounmap(xdev.base);
 390        release_mem_region(xdev.res.start, resource_size(&xdev.res));
 391
 392        return 0;
 393}
 394
 395/* Match table for of_platform binding */
 396static struct of_device_id xwdt_of_match[] = {
 397        { .compatible = "xlnx,xps-timebase-wdt-1.01.a", },
 398        {},
 399};
 400MODULE_DEVICE_TABLE(of, xwdt_of_match);
 401
 402static struct platform_driver xwdt_driver = {
 403        .probe       = xwdt_probe,
 404        .remove      = xwdt_remove,
 405        .driver = {
 406                .owner = THIS_MODULE,
 407                .name  = WATCHDOG_NAME,
 408                .of_match_table = xwdt_of_match,
 409        },
 410};
 411
 412module_platform_driver(xwdt_driver);
 413
 414MODULE_AUTHOR("Alejandro Cabrera <aldaya@gmail.com>");
 415MODULE_DESCRIPTION("Xilinx Watchdog driver");
 416MODULE_LICENSE("GPL");
 417MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
 418
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