linux/drivers/mfd/rtsx_pcr.c
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   1/* Driver for Realtek PCI-Express card reader
   2 *
   3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of the GNU General Public License as published by the
   7 * Free Software Foundation; either version 2, or (at your option) any
   8 * later version.
   9 *
  10 * This program is distributed in the hope that it will be useful, but
  11 * WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13 * General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License along
  16 * with this program; if not, see <http://www.gnu.org/licenses/>.
  17 *
  18 * Author:
  19 *   Wei WANG <wei_wang@realsil.com.cn>
  20 *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  21 */
  22
  23#include <linux/pci.h>
  24#include <linux/module.h>
  25#include <linux/slab.h>
  26#include <linux/dma-mapping.h>
  27#include <linux/highmem.h>
  28#include <linux/interrupt.h>
  29#include <linux/delay.h>
  30#include <linux/idr.h>
  31#include <linux/platform_device.h>
  32#include <linux/mfd/core.h>
  33#include <linux/mfd/rtsx_pci.h>
  34#include <asm/unaligned.h>
  35
  36#include "rtsx_pcr.h"
  37
  38static bool msi_en = true;
  39module_param(msi_en, bool, S_IRUGO | S_IWUSR);
  40MODULE_PARM_DESC(msi_en, "Enable MSI");
  41
  42static DEFINE_IDR(rtsx_pci_idr);
  43static DEFINE_SPINLOCK(rtsx_pci_lock);
  44
  45static struct mfd_cell rtsx_pcr_cells[] = {
  46        [RTSX_SD_CARD] = {
  47                .name = DRV_NAME_RTSX_PCI_SDMMC,
  48        },
  49        [RTSX_MS_CARD] = {
  50                .name = DRV_NAME_RTSX_PCI_MS,
  51        },
  52};
  53
  54static DEFINE_PCI_DEVICE_TABLE(rtsx_pci_ids) = {
  55        { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  56        { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  57        { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  58        { 0, }
  59};
  60
  61MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
  62
  63void rtsx_pci_start_run(struct rtsx_pcr *pcr)
  64{
  65        /* If pci device removed, don't queue idle work any more */
  66        if (pcr->remove_pci)
  67                return;
  68
  69        if (pcr->state != PDEV_STAT_RUN) {
  70                pcr->state = PDEV_STAT_RUN;
  71                if (pcr->ops->enable_auto_blink)
  72                        pcr->ops->enable_auto_blink(pcr);
  73        }
  74
  75        mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200));
  76}
  77EXPORT_SYMBOL_GPL(rtsx_pci_start_run);
  78
  79int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
  80{
  81        int i;
  82        u32 val = HAIMR_WRITE_START;
  83
  84        val |= (u32)(addr & 0x3FFF) << 16;
  85        val |= (u32)mask << 8;
  86        val |= (u32)data;
  87
  88        rtsx_pci_writel(pcr, RTSX_HAIMR, val);
  89
  90        for (i = 0; i < MAX_RW_REG_CNT; i++) {
  91                val = rtsx_pci_readl(pcr, RTSX_HAIMR);
  92                if ((val & HAIMR_TRANS_END) == 0) {
  93                        if (data != (u8)val)
  94                                return -EIO;
  95                        return 0;
  96                }
  97        }
  98
  99        return -ETIMEDOUT;
 100}
 101EXPORT_SYMBOL_GPL(rtsx_pci_write_register);
 102
 103int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
 104{
 105        u32 val = HAIMR_READ_START;
 106        int i;
 107
 108        val |= (u32)(addr & 0x3FFF) << 16;
 109        rtsx_pci_writel(pcr, RTSX_HAIMR, val);
 110
 111        for (i = 0; i < MAX_RW_REG_CNT; i++) {
 112                val = rtsx_pci_readl(pcr, RTSX_HAIMR);
 113                if ((val & HAIMR_TRANS_END) == 0)
 114                        break;
 115        }
 116
 117        if (i >= MAX_RW_REG_CNT)
 118                return -ETIMEDOUT;
 119
 120        if (data)
 121                *data = (u8)(val & 0xFF);
 122
 123        return 0;
 124}
 125EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
 126
 127int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
 128{
 129        int err, i, finished = 0;
 130        u8 tmp;
 131
 132        rtsx_pci_init_cmd(pcr);
 133
 134        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val);
 135        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8));
 136        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
 137        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81);
 138
 139        err = rtsx_pci_send_cmd(pcr, 100);
 140        if (err < 0)
 141                return err;
 142
 143        for (i = 0; i < 100000; i++) {
 144                err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
 145                if (err < 0)
 146                        return err;
 147
 148                if (!(tmp & 0x80)) {
 149                        finished = 1;
 150                        break;
 151                }
 152        }
 153
 154        if (!finished)
 155                return -ETIMEDOUT;
 156
 157        return 0;
 158}
 159EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
 160
 161int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
 162{
 163        int err, i, finished = 0;
 164        u16 data;
 165        u8 *ptr, tmp;
 166
 167        rtsx_pci_init_cmd(pcr);
 168
 169        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
 170        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80);
 171
 172        err = rtsx_pci_send_cmd(pcr, 100);
 173        if (err < 0)
 174                return err;
 175
 176        for (i = 0; i < 100000; i++) {
 177                err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
 178                if (err < 0)
 179                        return err;
 180
 181                if (!(tmp & 0x80)) {
 182                        finished = 1;
 183                        break;
 184                }
 185        }
 186
 187        if (!finished)
 188                return -ETIMEDOUT;
 189
 190        rtsx_pci_init_cmd(pcr);
 191
 192        rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0);
 193        rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0);
 194
 195        err = rtsx_pci_send_cmd(pcr, 100);
 196        if (err < 0)
 197                return err;
 198
 199        ptr = rtsx_pci_get_cmd_data(pcr);
 200        data = ((u16)ptr[1] << 8) | ptr[0];
 201
 202        if (val)
 203                *val = data;
 204
 205        return 0;
 206}
 207EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
 208
 209void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
 210{
 211        rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
 212        rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
 213
 214        rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
 215        rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
 216}
 217EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd);
 218
 219void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
 220                u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
 221{
 222        unsigned long flags;
 223        u32 val = 0;
 224        u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
 225
 226        val |= (u32)(cmd_type & 0x03) << 30;
 227        val |= (u32)(reg_addr & 0x3FFF) << 16;
 228        val |= (u32)mask << 8;
 229        val |= (u32)data;
 230
 231        spin_lock_irqsave(&pcr->lock, flags);
 232        ptr += pcr->ci;
 233        if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
 234                put_unaligned_le32(val, ptr);
 235                ptr++;
 236                pcr->ci++;
 237        }
 238        spin_unlock_irqrestore(&pcr->lock, flags);
 239}
 240EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
 241
 242void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
 243{
 244        u32 val = 1 << 31;
 245
 246        rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
 247
 248        val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
 249        /* Hardware Auto Response */
 250        val |= 0x40000000;
 251        rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
 252}
 253EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait);
 254
 255int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
 256{
 257        struct completion trans_done;
 258        u32 val = 1 << 31;
 259        long timeleft;
 260        unsigned long flags;
 261        int err = 0;
 262
 263        spin_lock_irqsave(&pcr->lock, flags);
 264
 265        /* set up data structures for the wakeup system */
 266        pcr->done = &trans_done;
 267        pcr->trans_result = TRANS_NOT_READY;
 268        init_completion(&trans_done);
 269
 270        rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
 271
 272        val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
 273        /* Hardware Auto Response */
 274        val |= 0x40000000;
 275        rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
 276
 277        spin_unlock_irqrestore(&pcr->lock, flags);
 278
 279        /* Wait for TRANS_OK_INT */
 280        timeleft = wait_for_completion_interruptible_timeout(
 281                        &trans_done, msecs_to_jiffies(timeout));
 282        if (timeleft <= 0) {
 283                dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
 284                                __func__, __LINE__);
 285                err = -ETIMEDOUT;
 286                goto finish_send_cmd;
 287        }
 288
 289        spin_lock_irqsave(&pcr->lock, flags);
 290        if (pcr->trans_result == TRANS_RESULT_FAIL)
 291                err = -EINVAL;
 292        else if (pcr->trans_result == TRANS_RESULT_OK)
 293                err = 0;
 294        else if (pcr->trans_result == TRANS_NO_DEVICE)
 295                err = -ENODEV;
 296        spin_unlock_irqrestore(&pcr->lock, flags);
 297
 298finish_send_cmd:
 299        spin_lock_irqsave(&pcr->lock, flags);
 300        pcr->done = NULL;
 301        spin_unlock_irqrestore(&pcr->lock, flags);
 302
 303        if ((err < 0) && (err != -ENODEV))
 304                rtsx_pci_stop_cmd(pcr);
 305
 306        if (pcr->finish_me)
 307                complete(pcr->finish_me);
 308
 309        return err;
 310}
 311EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd);
 312
 313static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
 314                dma_addr_t addr, unsigned int len, int end)
 315{
 316        u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
 317        u64 val;
 318        u8 option = SG_VALID | SG_TRANS_DATA;
 319
 320        dev_dbg(&(pcr->pci->dev), "DMA addr: 0x%x, Len: 0x%x\n",
 321                        (unsigned int)addr, len);
 322
 323        if (end)
 324                option |= SG_END;
 325        val = ((u64)addr << 32) | ((u64)len << 12) | option;
 326
 327        put_unaligned_le64(val, ptr);
 328        ptr++;
 329        pcr->sgi++;
 330}
 331
 332int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
 333                int num_sg, bool read, int timeout)
 334{
 335        struct completion trans_done;
 336        u8 dir;
 337        int err = 0, i, count;
 338        long timeleft;
 339        unsigned long flags;
 340        struct scatterlist *sg;
 341        enum dma_data_direction dma_dir;
 342        u32 val;
 343        dma_addr_t addr;
 344        unsigned int len;
 345
 346        dev_dbg(&(pcr->pci->dev), "--> %s: num_sg = %d\n", __func__, num_sg);
 347
 348        /* don't transfer data during abort processing */
 349        if (pcr->remove_pci)
 350                return -EINVAL;
 351
 352        if ((sglist == NULL) || (num_sg <= 0))
 353                return -EINVAL;
 354
 355        if (read) {
 356                dir = DEVICE_TO_HOST;
 357                dma_dir = DMA_FROM_DEVICE;
 358        } else {
 359                dir = HOST_TO_DEVICE;
 360                dma_dir = DMA_TO_DEVICE;
 361        }
 362
 363        count = dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dma_dir);
 364        if (count < 1) {
 365                dev_err(&(pcr->pci->dev), "scatterlist map failed\n");
 366                return -EINVAL;
 367        }
 368        dev_dbg(&(pcr->pci->dev), "DMA mapping count: %d\n", count);
 369
 370        val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE;
 371        pcr->sgi = 0;
 372        for_each_sg(sglist, sg, count, i) {
 373                addr = sg_dma_address(sg);
 374                len = sg_dma_len(sg);
 375                rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1);
 376        }
 377
 378        spin_lock_irqsave(&pcr->lock, flags);
 379
 380        pcr->done = &trans_done;
 381        pcr->trans_result = TRANS_NOT_READY;
 382        init_completion(&trans_done);
 383        rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
 384        rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
 385
 386        spin_unlock_irqrestore(&pcr->lock, flags);
 387
 388        timeleft = wait_for_completion_interruptible_timeout(
 389                        &trans_done, msecs_to_jiffies(timeout));
 390        if (timeleft <= 0) {
 391                dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
 392                                __func__, __LINE__);
 393                err = -ETIMEDOUT;
 394                goto out;
 395        }
 396
 397        spin_lock_irqsave(&pcr->lock, flags);
 398
 399        if (pcr->trans_result == TRANS_RESULT_FAIL)
 400                err = -EINVAL;
 401        else if (pcr->trans_result == TRANS_NO_DEVICE)
 402                err = -ENODEV;
 403
 404        spin_unlock_irqrestore(&pcr->lock, flags);
 405
 406out:
 407        spin_lock_irqsave(&pcr->lock, flags);
 408        pcr->done = NULL;
 409        spin_unlock_irqrestore(&pcr->lock, flags);
 410
 411        dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dma_dir);
 412
 413        if ((err < 0) && (err != -ENODEV))
 414                rtsx_pci_stop_cmd(pcr);
 415
 416        if (pcr->finish_me)
 417                complete(pcr->finish_me);
 418
 419        return err;
 420}
 421EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data);
 422
 423int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
 424{
 425        int err;
 426        int i, j;
 427        u16 reg;
 428        u8 *ptr;
 429
 430        if (buf_len > 512)
 431                buf_len = 512;
 432
 433        ptr = buf;
 434        reg = PPBUF_BASE2;
 435        for (i = 0; i < buf_len / 256; i++) {
 436                rtsx_pci_init_cmd(pcr);
 437
 438                for (j = 0; j < 256; j++)
 439                        rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
 440
 441                err = rtsx_pci_send_cmd(pcr, 250);
 442                if (err < 0)
 443                        return err;
 444
 445                memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
 446                ptr += 256;
 447        }
 448
 449        if (buf_len % 256) {
 450                rtsx_pci_init_cmd(pcr);
 451
 452                for (j = 0; j < buf_len % 256; j++)
 453                        rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
 454
 455                err = rtsx_pci_send_cmd(pcr, 250);
 456                if (err < 0)
 457                        return err;
 458        }
 459
 460        memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
 461
 462        return 0;
 463}
 464EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf);
 465
 466int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
 467{
 468        int err;
 469        int i, j;
 470        u16 reg;
 471        u8 *ptr;
 472
 473        if (buf_len > 512)
 474                buf_len = 512;
 475
 476        ptr = buf;
 477        reg = PPBUF_BASE2;
 478        for (i = 0; i < buf_len / 256; i++) {
 479                rtsx_pci_init_cmd(pcr);
 480
 481                for (j = 0; j < 256; j++) {
 482                        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 483                                        reg++, 0xFF, *ptr);
 484                        ptr++;
 485                }
 486
 487                err = rtsx_pci_send_cmd(pcr, 250);
 488                if (err < 0)
 489                        return err;
 490        }
 491
 492        if (buf_len % 256) {
 493                rtsx_pci_init_cmd(pcr);
 494
 495                for (j = 0; j < buf_len % 256; j++) {
 496                        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 497                                        reg++, 0xFF, *ptr);
 498                        ptr++;
 499                }
 500
 501                err = rtsx_pci_send_cmd(pcr, 250);
 502                if (err < 0)
 503                        return err;
 504        }
 505
 506        return 0;
 507}
 508EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf);
 509
 510static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
 511{
 512        int err;
 513
 514        rtsx_pci_init_cmd(pcr);
 515
 516        while (*tbl & 0xFFFF0000) {
 517                rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 518                                (u16)(*tbl >> 16), 0xFF, (u8)(*tbl));
 519                tbl++;
 520        }
 521
 522        err = rtsx_pci_send_cmd(pcr, 100);
 523        if (err < 0)
 524                return err;
 525
 526        return 0;
 527}
 528
 529int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
 530{
 531        const u32 *tbl;
 532
 533        if (card == RTSX_SD_CARD)
 534                tbl = pcr->sd_pull_ctl_enable_tbl;
 535        else if (card == RTSX_MS_CARD)
 536                tbl = pcr->ms_pull_ctl_enable_tbl;
 537        else
 538                return -EINVAL;
 539
 540        return rtsx_pci_set_pull_ctl(pcr, tbl);
 541}
 542EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable);
 543
 544int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
 545{
 546        const u32 *tbl;
 547
 548        if (card == RTSX_SD_CARD)
 549                tbl = pcr->sd_pull_ctl_disable_tbl;
 550        else if (card == RTSX_MS_CARD)
 551                tbl = pcr->ms_pull_ctl_disable_tbl;
 552        else
 553                return -EINVAL;
 554
 555
 556        return rtsx_pci_set_pull_ctl(pcr, tbl);
 557}
 558EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
 559
 560static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
 561{
 562        pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN;
 563
 564        if (pcr->num_slots > 1)
 565                pcr->bier |= MS_INT_EN;
 566
 567        /* Enable Bus Interrupt */
 568        rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
 569
 570        dev_dbg(&(pcr->pci->dev), "RTSX_BIER: 0x%08x\n", pcr->bier);
 571}
 572
 573static inline u8 double_ssc_depth(u8 depth)
 574{
 575        return ((depth > 1) ? (depth - 1) : depth);
 576}
 577
 578static u8 revise_ssc_depth(u8 ssc_depth, u8 div)
 579{
 580        if (div > CLK_DIV_1) {
 581                if (ssc_depth > (div - 1))
 582                        ssc_depth -= (div - 1);
 583                else
 584                        ssc_depth = SSC_DEPTH_4M;
 585        }
 586
 587        return ssc_depth;
 588}
 589
 590int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
 591                u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
 592{
 593        int err, clk;
 594        u8 N, min_N, max_N, clk_divider;
 595        u8 mcu_cnt, div, max_div;
 596        u8 depth[] = {
 597                [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M,
 598                [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M,
 599                [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
 600                [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
 601                [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
 602        };
 603
 604        if (initial_mode) {
 605                /* We use 250k(around) here, in initial stage */
 606                clk_divider = SD_CLK_DIVIDE_128;
 607                card_clock = 30000000;
 608        } else {
 609                clk_divider = SD_CLK_DIVIDE_0;
 610        }
 611        err = rtsx_pci_write_register(pcr, SD_CFG1,
 612                        SD_CLK_DIVIDE_MASK, clk_divider);
 613        if (err < 0)
 614                return err;
 615
 616        card_clock /= 1000000;
 617        dev_dbg(&(pcr->pci->dev), "Switch card clock to %dMHz\n", card_clock);
 618
 619        min_N = 80;
 620        max_N = 208;
 621        max_div = CLK_DIV_8;
 622
 623        clk = card_clock;
 624        if (!initial_mode && double_clk)
 625                clk = card_clock * 2;
 626        dev_dbg(&(pcr->pci->dev),
 627                        "Internal SSC clock: %dMHz (cur_clock = %d)\n",
 628                        clk, pcr->cur_clock);
 629
 630        if (clk == pcr->cur_clock)
 631                return 0;
 632
 633        if (pcr->ops->conv_clk_and_div_n)
 634                N = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
 635        else
 636                N = (u8)(clk - 2);
 637        if ((clk <= 2) || (N > max_N))
 638                return -EINVAL;
 639
 640        mcu_cnt = (u8)(125/clk + 3);
 641        if (mcu_cnt > 15)
 642                mcu_cnt = 15;
 643
 644        /* Make sure that the SSC clock div_n is equal or greater than min_N */
 645        div = CLK_DIV_1;
 646        while ((N < min_N) && (div < max_div)) {
 647                if (pcr->ops->conv_clk_and_div_n) {
 648                        int dbl_clk = pcr->ops->conv_clk_and_div_n(N,
 649                                        DIV_N_TO_CLK) * 2;
 650                        N = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk,
 651                                        CLK_TO_DIV_N);
 652                } else {
 653                        N = (N + 2) * 2 - 2;
 654                }
 655                div++;
 656        }
 657        dev_dbg(&(pcr->pci->dev), "N = %d, div = %d\n", N, div);
 658
 659        ssc_depth = depth[ssc_depth];
 660        if (double_clk)
 661                ssc_depth = double_ssc_depth(ssc_depth);
 662
 663        ssc_depth = revise_ssc_depth(ssc_depth, div);
 664        dev_dbg(&(pcr->pci->dev), "ssc_depth = %d\n", ssc_depth);
 665
 666        rtsx_pci_init_cmd(pcr);
 667        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
 668                        CLK_LOW_FREQ, CLK_LOW_FREQ);
 669        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
 670                        0xFF, (div << 4) | mcu_cnt);
 671        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
 672        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
 673                        SSC_DEPTH_MASK, ssc_depth);
 674        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, N);
 675        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
 676        if (vpclk) {
 677                rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
 678                                PHASE_NOT_RESET, 0);
 679                rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
 680                                PHASE_NOT_RESET, PHASE_NOT_RESET);
 681        }
 682
 683        err = rtsx_pci_send_cmd(pcr, 2000);
 684        if (err < 0)
 685                return err;
 686
 687        /* Wait SSC clock stable */
 688        udelay(10);
 689        err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
 690        if (err < 0)
 691                return err;
 692
 693        pcr->cur_clock = clk;
 694        return 0;
 695}
 696EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock);
 697
 698int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
 699{
 700        if (pcr->ops->card_power_on)
 701                return pcr->ops->card_power_on(pcr, card);
 702
 703        return 0;
 704}
 705EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on);
 706
 707int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
 708{
 709        if (pcr->ops->card_power_off)
 710                return pcr->ops->card_power_off(pcr, card);
 711
 712        return 0;
 713}
 714EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off);
 715
 716int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card)
 717{
 718        unsigned int cd_mask[] = {
 719                [RTSX_SD_CARD] = SD_EXIST,
 720                [RTSX_MS_CARD] = MS_EXIST
 721        };
 722
 723        if (!pcr->ms_pmos) {
 724                /* When using single PMOS, accessing card is not permitted
 725                 * if the existing card is not the designated one.
 726                 */
 727                if (pcr->card_exist & (~cd_mask[card]))
 728                        return -EIO;
 729        }
 730
 731        return 0;
 732}
 733EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check);
 734
 735int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 736{
 737        if (pcr->ops->switch_output_voltage)
 738                return pcr->ops->switch_output_voltage(pcr, voltage);
 739
 740        return 0;
 741}
 742EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage);
 743
 744unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
 745{
 746        unsigned int val;
 747
 748        val = rtsx_pci_readl(pcr, RTSX_BIPR);
 749        if (pcr->ops->cd_deglitch)
 750                val = pcr->ops->cd_deglitch(pcr);
 751
 752        return val;
 753}
 754EXPORT_SYMBOL_GPL(rtsx_pci_card_exist);
 755
 756void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
 757{
 758        struct completion finish;
 759
 760        pcr->finish_me = &finish;
 761        init_completion(&finish);
 762
 763        if (pcr->done)
 764                complete(pcr->done);
 765
 766        if (!pcr->remove_pci)
 767                rtsx_pci_stop_cmd(pcr);
 768
 769        wait_for_completion_interruptible_timeout(&finish,
 770                        msecs_to_jiffies(2));
 771        pcr->finish_me = NULL;
 772}
 773EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer);
 774
 775static void rtsx_pci_card_detect(struct work_struct *work)
 776{
 777        struct delayed_work *dwork;
 778        struct rtsx_pcr *pcr;
 779        unsigned long flags;
 780        unsigned int card_detect = 0, card_inserted, card_removed;
 781        u32 irq_status;
 782
 783        dwork = to_delayed_work(work);
 784        pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
 785
 786        dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
 787
 788        mutex_lock(&pcr->pcr_mutex);
 789        spin_lock_irqsave(&pcr->lock, flags);
 790
 791        irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
 792        dev_dbg(&(pcr->pci->dev), "irq_status: 0x%08x\n", irq_status);
 793
 794        irq_status &= CARD_EXIST;
 795        card_inserted = pcr->card_inserted & irq_status;
 796        card_removed = pcr->card_removed;
 797        pcr->card_inserted = 0;
 798        pcr->card_removed = 0;
 799
 800        spin_unlock_irqrestore(&pcr->lock, flags);
 801
 802        if (card_inserted || card_removed) {
 803                dev_dbg(&(pcr->pci->dev),
 804                                "card_inserted: 0x%x, card_removed: 0x%x\n",
 805                                card_inserted, card_removed);
 806
 807                if (pcr->ops->cd_deglitch)
 808                        card_inserted = pcr->ops->cd_deglitch(pcr);
 809
 810                card_detect = card_inserted | card_removed;
 811
 812                pcr->card_exist |= card_inserted;
 813                pcr->card_exist &= ~card_removed;
 814        }
 815
 816        mutex_unlock(&pcr->pcr_mutex);
 817
 818        if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event)
 819                pcr->slots[RTSX_SD_CARD].card_event(
 820                                pcr->slots[RTSX_SD_CARD].p_dev);
 821        if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event)
 822                pcr->slots[RTSX_MS_CARD].card_event(
 823                                pcr->slots[RTSX_MS_CARD].p_dev);
 824}
 825
 826static irqreturn_t rtsx_pci_isr(int irq, void *dev_id)
 827{
 828        struct rtsx_pcr *pcr = dev_id;
 829        u32 int_reg;
 830
 831        if (!pcr)
 832                return IRQ_NONE;
 833
 834        spin_lock(&pcr->lock);
 835
 836        int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
 837        /* Clear interrupt flag */
 838        rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
 839        if ((int_reg & pcr->bier) == 0) {
 840                spin_unlock(&pcr->lock);
 841                return IRQ_NONE;
 842        }
 843        if (int_reg == 0xFFFFFFFF) {
 844                spin_unlock(&pcr->lock);
 845                return IRQ_HANDLED;
 846        }
 847
 848        int_reg &= (pcr->bier | 0x7FFFFF);
 849
 850        if (int_reg & SD_INT) {
 851                if (int_reg & SD_EXIST) {
 852                        pcr->card_inserted |= SD_EXIST;
 853                } else {
 854                        pcr->card_removed |= SD_EXIST;
 855                        pcr->card_inserted &= ~SD_EXIST;
 856                }
 857        }
 858
 859        if (int_reg & MS_INT) {
 860                if (int_reg & MS_EXIST) {
 861                        pcr->card_inserted |= MS_EXIST;
 862                } else {
 863                        pcr->card_removed |= MS_EXIST;
 864                        pcr->card_inserted &= ~MS_EXIST;
 865                }
 866        }
 867
 868        if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) {
 869                if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) {
 870                        pcr->trans_result = TRANS_RESULT_FAIL;
 871                        if (pcr->done)
 872                                complete(pcr->done);
 873                } else if (int_reg & TRANS_OK_INT) {
 874                        pcr->trans_result = TRANS_RESULT_OK;
 875                        if (pcr->done)
 876                                complete(pcr->done);
 877                }
 878        }
 879
 880        if (pcr->card_inserted || pcr->card_removed)
 881                schedule_delayed_work(&pcr->carddet_work,
 882                                msecs_to_jiffies(200));
 883
 884        spin_unlock(&pcr->lock);
 885        return IRQ_HANDLED;
 886}
 887
 888static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
 889{
 890        dev_info(&(pcr->pci->dev), "%s: pcr->msi_en = %d, pci->irq = %d\n",
 891                        __func__, pcr->msi_en, pcr->pci->irq);
 892
 893        if (request_irq(pcr->pci->irq, rtsx_pci_isr,
 894                        pcr->msi_en ? 0 : IRQF_SHARED,
 895                        DRV_NAME_RTSX_PCI, pcr)) {
 896                dev_err(&(pcr->pci->dev),
 897                        "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
 898                        pcr->pci->irq);
 899                return -1;
 900        }
 901
 902        pcr->irq = pcr->pci->irq;
 903        pci_intx(pcr->pci, !pcr->msi_en);
 904
 905        return 0;
 906}
 907
 908static void rtsx_pci_idle_work(struct work_struct *work)
 909{
 910        struct delayed_work *dwork = to_delayed_work(work);
 911        struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work);
 912
 913        dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
 914
 915        mutex_lock(&pcr->pcr_mutex);
 916
 917        pcr->state = PDEV_STAT_IDLE;
 918
 919        if (pcr->ops->disable_auto_blink)
 920                pcr->ops->disable_auto_blink(pcr);
 921        if (pcr->ops->turn_off_led)
 922                pcr->ops->turn_off_led(pcr);
 923
 924        mutex_unlock(&pcr->pcr_mutex);
 925}
 926
 927static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
 928{
 929        int err;
 930
 931        rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
 932
 933        rtsx_pci_enable_bus_int(pcr);
 934
 935        /* Power on SSC */
 936        err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
 937        if (err < 0)
 938                return err;
 939
 940        /* Wait SSC power stable */
 941        udelay(200);
 942
 943        if (pcr->ops->optimize_phy) {
 944                err = pcr->ops->optimize_phy(pcr);
 945                if (err < 0)
 946                        return err;
 947        }
 948
 949        rtsx_pci_init_cmd(pcr);
 950
 951        /* Set mcu_cnt to 7 to ensure data can be sampled properly */
 952        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
 953
 954        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
 955        /* Disable card clock */
 956        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
 957        /* Reset ASPM state to default value */
 958        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
 959        /* Reset delink mode */
 960        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
 961        /* Card driving select */
 962        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
 963                        0x07, DRIVER_TYPE_D);
 964        /* Enable SSC Clock */
 965        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
 966                        0xFF, SSC_8X_EN | SSC_SEL_4M);
 967        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
 968        /* Disable cd_pwr_save */
 969        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
 970        /* Clear Link Ready Interrupt */
 971        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
 972                        LINK_RDY_INT, LINK_RDY_INT);
 973        /* Enlarge the estimation window of PERST# glitch
 974         * to reduce the chance of invalid card interrupt
 975         */
 976        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
 977        /* Update RC oscillator to 400k
 978         * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
 979         *                1: 2M  0: 400k
 980         */
 981        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
 982        /* Set interrupt write clear
 983         * bit 1: U_elbi_if_rd_clr_en
 984         *      1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
 985         *      0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
 986         */
 987        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
 988        /* Force CLKREQ# PIN to drive 0 to request clock */
 989        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08);
 990
 991        err = rtsx_pci_send_cmd(pcr, 100);
 992        if (err < 0)
 993                return err;
 994
 995        /* Enable clk_request_n to enable clock power management */
 996        rtsx_pci_write_config_byte(pcr, 0x81, 1);
 997        /* Enter L1 when host tx idle */
 998        rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B);
 999
1000        if (pcr->ops->extra_init_hw) {
1001                err = pcr->ops->extra_init_hw(pcr);
1002                if (err < 0)
1003                        return err;
1004        }
1005
1006        /* No CD interrupt if probing driver with card inserted.
1007         * So we need to initialize pcr->card_exist here.
1008         */
1009        if (pcr->ops->cd_deglitch)
1010                pcr->card_exist = pcr->ops->cd_deglitch(pcr);
1011        else
1012                pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST;
1013
1014        return 0;
1015}
1016
1017static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
1018{
1019        int err;
1020
1021        spin_lock_init(&pcr->lock);
1022        mutex_init(&pcr->pcr_mutex);
1023
1024        switch (PCI_PID(pcr)) {
1025        default:
1026        case 0x5209:
1027                rts5209_init_params(pcr);
1028                break;
1029
1030        case 0x5229:
1031                rts5229_init_params(pcr);
1032                break;
1033
1034        case 0x5289:
1035                rtl8411_init_params(pcr);
1036                break;
1037        }
1038
1039        dev_dbg(&(pcr->pci->dev), "PID: 0x%04x, IC version: 0x%02x\n",
1040                        PCI_PID(pcr), pcr->ic_version);
1041
1042        pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
1043                        GFP_KERNEL);
1044        if (!pcr->slots)
1045                return -ENOMEM;
1046
1047        pcr->state = PDEV_STAT_IDLE;
1048        err = rtsx_pci_init_hw(pcr);
1049        if (err < 0) {
1050                kfree(pcr->slots);
1051                return err;
1052        }
1053
1054        return 0;
1055}
1056
1057static int rtsx_pci_probe(struct pci_dev *pcidev,
1058                          const struct pci_device_id *id)
1059{
1060        struct rtsx_pcr *pcr;
1061        struct pcr_handle *handle;
1062        u32 base, len;
1063        int ret, i;
1064
1065        dev_dbg(&(pcidev->dev),
1066                ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
1067                pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1068                (int)pcidev->revision);
1069
1070        ret = pci_enable_device(pcidev);
1071        if (ret)
1072                return ret;
1073
1074        ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI);
1075        if (ret)
1076                goto disable;
1077
1078        pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
1079        if (!pcr) {
1080                ret = -ENOMEM;
1081                goto release_pci;
1082        }
1083
1084        handle = kzalloc(sizeof(*handle), GFP_KERNEL);
1085        if (!handle) {
1086                ret = -ENOMEM;
1087                goto free_pcr;
1088        }
1089        handle->pcr = pcr;
1090
1091        if (!idr_pre_get(&rtsx_pci_idr, GFP_KERNEL)) {
1092                ret = -ENOMEM;
1093                goto free_handle;
1094        }
1095
1096        spin_lock(&rtsx_pci_lock);
1097        ret = idr_get_new(&rtsx_pci_idr, pcr, &pcr->id);
1098        spin_unlock(&rtsx_pci_lock);
1099        if (ret)
1100                goto free_handle;
1101
1102        pcr->pci = pcidev;
1103        dev_set_drvdata(&pcidev->dev, handle);
1104
1105        len = pci_resource_len(pcidev, 0);
1106        base = pci_resource_start(pcidev, 0);
1107        pcr->remap_addr = ioremap_nocache(base, len);
1108        if (!pcr->remap_addr) {
1109                ret = -ENOMEM;
1110                goto free_host;
1111        }
1112
1113        pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
1114                        RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
1115                        GFP_KERNEL);
1116        if (pcr->rtsx_resv_buf == NULL) {
1117                ret = -ENXIO;
1118                goto unmap;
1119        }
1120        pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
1121        pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
1122        pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
1123        pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
1124
1125        pcr->card_inserted = 0;
1126        pcr->card_removed = 0;
1127        INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
1128        INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work);
1129
1130        pcr->msi_en = msi_en;
1131        if (pcr->msi_en) {
1132                ret = pci_enable_msi(pcidev);
1133                if (ret < 0)
1134                        pcr->msi_en = false;
1135        }
1136
1137        ret = rtsx_pci_acquire_irq(pcr);
1138        if (ret < 0)
1139                goto free_dma;
1140
1141        pci_set_master(pcidev);
1142        synchronize_irq(pcr->irq);
1143
1144        ret = rtsx_pci_init_chip(pcr);
1145        if (ret < 0)
1146                goto disable_irq;
1147
1148        for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) {
1149                rtsx_pcr_cells[i].platform_data = handle;
1150                rtsx_pcr_cells[i].pdata_size = sizeof(*handle);
1151        }
1152        ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
1153                        ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL);
1154        if (ret < 0)
1155                goto disable_irq;
1156
1157        schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1158
1159        return 0;
1160
1161disable_irq:
1162        free_irq(pcr->irq, (void *)pcr);
1163free_dma:
1164        dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1165                        pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1166unmap:
1167        iounmap(pcr->remap_addr);
1168free_host:
1169        dev_set_drvdata(&pcidev->dev, NULL);
1170free_handle:
1171        kfree(handle);
1172free_pcr:
1173        kfree(pcr);
1174release_pci:
1175        pci_release_regions(pcidev);
1176disable:
1177        pci_disable_device(pcidev);
1178
1179        return ret;
1180}
1181
1182static void rtsx_pci_remove(struct pci_dev *pcidev)
1183{
1184        struct pcr_handle *handle = pci_get_drvdata(pcidev);
1185        struct rtsx_pcr *pcr = handle->pcr;
1186
1187        pcr->remove_pci = true;
1188
1189        cancel_delayed_work(&pcr->carddet_work);
1190        cancel_delayed_work(&pcr->idle_work);
1191
1192        mfd_remove_devices(&pcidev->dev);
1193
1194        dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1195                        pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1196        free_irq(pcr->irq, (void *)pcr);
1197        if (pcr->msi_en)
1198                pci_disable_msi(pcr->pci);
1199        iounmap(pcr->remap_addr);
1200
1201        dev_set_drvdata(&pcidev->dev, NULL);
1202        pci_release_regions(pcidev);
1203        pci_disable_device(pcidev);
1204
1205        spin_lock(&rtsx_pci_lock);
1206        idr_remove(&rtsx_pci_idr, pcr->id);
1207        spin_unlock(&rtsx_pci_lock);
1208
1209        kfree(pcr->slots);
1210        kfree(pcr);
1211        kfree(handle);
1212
1213        dev_dbg(&(pcidev->dev),
1214                ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
1215                pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1216}
1217
1218#ifdef CONFIG_PM
1219
1220static int rtsx_pci_suspend(struct pci_dev *pcidev, pm_message_t state)
1221{
1222        struct pcr_handle *handle;
1223        struct rtsx_pcr *pcr;
1224        int ret = 0;
1225
1226        dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1227
1228        handle = pci_get_drvdata(pcidev);
1229        pcr = handle->pcr;
1230
1231        cancel_delayed_work(&pcr->carddet_work);
1232        cancel_delayed_work(&pcr->idle_work);
1233
1234        mutex_lock(&pcr->pcr_mutex);
1235
1236        if (pcr->ops->turn_off_led)
1237                pcr->ops->turn_off_led(pcr);
1238
1239        rtsx_pci_writel(pcr, RTSX_BIER, 0);
1240        pcr->bier = 0;
1241
1242        rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
1243        rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x02);
1244
1245        pci_save_state(pcidev);
1246        pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1247        pci_disable_device(pcidev);
1248        pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1249
1250        mutex_unlock(&pcr->pcr_mutex);
1251        return ret;
1252}
1253
1254static int rtsx_pci_resume(struct pci_dev *pcidev)
1255{
1256        struct pcr_handle *handle;
1257        struct rtsx_pcr *pcr;
1258        int ret = 0;
1259
1260        dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1261
1262        handle = pci_get_drvdata(pcidev);
1263        pcr = handle->pcr;
1264
1265        mutex_lock(&pcr->pcr_mutex);
1266
1267        pci_set_power_state(pcidev, PCI_D0);
1268        pci_restore_state(pcidev);
1269        ret = pci_enable_device(pcidev);
1270        if (ret)
1271                goto out;
1272        pci_set_master(pcidev);
1273
1274        ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1275        if (ret)
1276                goto out;
1277
1278        ret = rtsx_pci_init_hw(pcr);
1279        if (ret)
1280                goto out;
1281
1282        schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1283
1284out:
1285        mutex_unlock(&pcr->pcr_mutex);
1286        return ret;
1287}
1288
1289#else /* CONFIG_PM */
1290
1291#define rtsx_pci_suspend NULL
1292#define rtsx_pci_resume NULL
1293
1294#endif /* CONFIG_PM */
1295
1296static struct pci_driver rtsx_pci_driver = {
1297        .name = DRV_NAME_RTSX_PCI,
1298        .id_table = rtsx_pci_ids,
1299        .probe = rtsx_pci_probe,
1300        .remove = rtsx_pci_remove,
1301        .suspend = rtsx_pci_suspend,
1302        .resume = rtsx_pci_resume,
1303};
1304module_pci_driver(rtsx_pci_driver);
1305
1306MODULE_LICENSE("GPL");
1307MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1308MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");
1309
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