linux/drivers/edac/i82975x_edac.c
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   1/*
   2 * Intel 82975X Memory Controller kernel module
   3 * (C) 2007 aCarLab (India) Pvt. Ltd. (http://acarlab.com)
   4 * (C) 2007 jetzbroadband (http://jetzbroadband.com)
   5 * This file may be distributed under the terms of the
   6 * GNU General Public License.
   7 *
   8 * Written by Arvind R.
   9 *   Copied from i82875p_edac.c source:
  10 */
  11
  12#include <linux/module.h>
  13#include <linux/init.h>
  14#include <linux/pci.h>
  15#include <linux/pci_ids.h>
  16#include <linux/edac.h>
  17#include "edac_core.h"
  18
  19#define I82975X_REVISION        " Ver: 1.0.0"
  20#define EDAC_MOD_STR            "i82975x_edac"
  21
  22#define i82975x_printk(level, fmt, arg...) \
  23        edac_printk(level, "i82975x", fmt, ##arg)
  24
  25#define i82975x_mc_printk(mci, level, fmt, arg...) \
  26        edac_mc_chipset_printk(mci, level, "i82975x", fmt, ##arg)
  27
  28#ifndef PCI_DEVICE_ID_INTEL_82975_0
  29#define PCI_DEVICE_ID_INTEL_82975_0     0x277c
  30#endif                          /* PCI_DEVICE_ID_INTEL_82975_0 */
  31
  32#define I82975X_NR_DIMMS                8
  33#define I82975X_NR_CSROWS(nr_chans)     (I82975X_NR_DIMMS / (nr_chans))
  34
  35/* Intel 82975X register addresses - device 0 function 0 - DRAM Controller */
  36#define I82975X_EAP             0x58    /* Dram Error Address Pointer (32b)
  37                                         *
  38                                         * 31:7  128 byte cache-line address
  39                                         * 6:1   reserved
  40                                         * 0     0: CH0; 1: CH1
  41                                         */
  42
  43#define I82975X_DERRSYN         0x5c    /* Dram Error SYNdrome (8b)
  44                                         *
  45                                         *  7:0  DRAM ECC Syndrome
  46                                         */
  47
  48#define I82975X_DES             0x5d    /* Dram ERRor DeSTination (8b)
  49                                         * 0h:    Processor Memory Reads
  50                                         * 1h:7h  reserved
  51                                         * More - See Page 65 of Intel DocSheet.
  52                                         */
  53
  54#define I82975X_ERRSTS          0xc8    /* Error Status Register (16b)
  55                                         *
  56                                         * 15:12 reserved
  57                                         * 11    Thermal Sensor Event
  58                                         * 10    reserved
  59                                         *  9    non-DRAM lock error (ndlock)
  60                                         *  8    Refresh Timeout
  61                                         *  7:2  reserved
  62                                         *  1    ECC UE (multibit DRAM error)
  63                                         *  0    ECC CE (singlebit DRAM error)
  64                                         */
  65
  66/* Error Reporting is supported by 3 mechanisms:
  67  1. DMI SERR generation  ( ERRCMD )
  68  2. SMI DMI  generation  ( SMICMD )
  69  3. SCI DMI  generation  ( SCICMD )
  70NOTE: Only ONE of the three must be enabled
  71*/
  72#define I82975X_ERRCMD          0xca    /* Error Command (16b)
  73                                         *
  74                                         * 15:12 reserved
  75                                         * 11    Thermal Sensor Event
  76                                         * 10    reserved
  77                                         *  9    non-DRAM lock error (ndlock)
  78                                         *  8    Refresh Timeout
  79                                         *  7:2  reserved
  80                                         *  1    ECC UE (multibit DRAM error)
  81                                         *  0    ECC CE (singlebit DRAM error)
  82                                         */
  83
  84#define I82975X_SMICMD          0xcc    /* Error Command (16b)
  85                                         *
  86                                         * 15:2  reserved
  87                                         *  1    ECC UE (multibit DRAM error)
  88                                         *  0    ECC CE (singlebit DRAM error)
  89                                         */
  90
  91#define I82975X_SCICMD          0xce    /* Error Command (16b)
  92                                         *
  93                                         * 15:2  reserved
  94                                         *  1    ECC UE (multibit DRAM error)
  95                                         *  0    ECC CE (singlebit DRAM error)
  96                                         */
  97
  98#define I82975X_XEAP    0xfc    /* Extended Dram Error Address Pointer (8b)
  99                                         *
 100                                         * 7:1   reserved
 101                                         * 0     Bit32 of the Dram Error Address
 102                                         */
 103
 104#define I82975X_MCHBAR          0x44    /*
 105                                         *
 106                                         * 31:14 Base Addr of 16K memory-mapped
 107                                         *      configuration space
 108                                         * 13:1  reserverd
 109                                         *  0    mem-mapped config space enable
 110                                         */
 111
 112/* NOTE: Following addresses have to indexed using MCHBAR offset (44h, 32b) */
 113/* Intel 82975x memory mapped register space */
 114
 115#define I82975X_DRB_SHIFT 25    /* fixed 32MiB grain */
 116
 117#define I82975X_DRB             0x100   /* DRAM Row Boundary (8b x 8)
 118                                         *
 119                                         * 7   set to 1 in highest DRB of
 120                                         *      channel if 4GB in ch.
 121                                         * 6:2 upper boundary of rank in
 122                                         *      32MB grains
 123                                         * 1:0 set to 0
 124                                         */
 125#define I82975X_DRB_CH0R0               0x100
 126#define I82975X_DRB_CH0R1               0x101
 127#define I82975X_DRB_CH0R2               0x102
 128#define I82975X_DRB_CH0R3               0x103
 129#define I82975X_DRB_CH1R0               0x180
 130#define I82975X_DRB_CH1R1               0x181
 131#define I82975X_DRB_CH1R2               0x182
 132#define I82975X_DRB_CH1R3               0x183
 133
 134
 135#define I82975X_DRA             0x108   /* DRAM Row Attribute (4b x 8)
 136                                         *  defines the PAGE SIZE to be used
 137                                         *      for the rank
 138                                         *  7    reserved
 139                                         *  6:4  row attr of odd rank, i.e. 1
 140                                         *  3    reserved
 141                                         *  2:0  row attr of even rank, i.e. 0
 142                                         *
 143                                         * 000 = unpopulated
 144                                         * 001 = reserved
 145                                         * 010 = 4KiB
 146                                         * 011 = 8KiB
 147                                         * 100 = 16KiB
 148                                         * others = reserved
 149                                         */
 150#define I82975X_DRA_CH0R01              0x108
 151#define I82975X_DRA_CH0R23              0x109
 152#define I82975X_DRA_CH1R01              0x188
 153#define I82975X_DRA_CH1R23              0x189
 154
 155
 156#define I82975X_BNKARC  0x10e /* Type of device in each rank - Bank Arch (16b)
 157                                         *
 158                                         * 15:8  reserved
 159                                         * 7:6  Rank 3 architecture
 160                                         * 5:4  Rank 2 architecture
 161                                         * 3:2  Rank 1 architecture
 162                                         * 1:0  Rank 0 architecture
 163                                         *
 164                                         * 00 => 4 banks
 165                                         * 01 => 8 banks
 166                                         */
 167#define I82975X_C0BNKARC        0x10e
 168#define I82975X_C1BNKARC        0x18e
 169
 170
 171
 172#define I82975X_DRC             0x120 /* DRAM Controller Mode0 (32b)
 173                                         *
 174                                         * 31:30 reserved
 175                                         * 29    init complete
 176                                         * 28:11 reserved, according to Intel
 177                                         *    22:21 number of channels
 178                                         *              00=1 01=2 in 82875
 179                                         *              seems to be ECC mode
 180                                         *              bits in 82975 in Asus
 181                                         *              P5W
 182                                         *       19:18 Data Integ Mode
 183                                         *              00=none 01=ECC in 82875
 184                                         * 10:8  refresh mode
 185                                         *  7    reserved
 186                                         *  6:4  mode select
 187                                         *  3:2  reserved
 188                                         *  1:0  DRAM type 10=Second Revision
 189                                         *              DDR2 SDRAM
 190                                         *         00, 01, 11 reserved
 191                                         */
 192#define I82975X_DRC_CH0M0               0x120
 193#define I82975X_DRC_CH1M0               0x1A0
 194
 195
 196#define I82975X_DRC_M1  0x124 /* DRAM Controller Mode1 (32b)
 197                                         * 31   0=Standard Address Map
 198                                         *      1=Enhanced Address Map
 199                                         * 30:0 reserved
 200                                         */
 201
 202#define I82975X_DRC_CH0M1               0x124
 203#define I82975X_DRC_CH1M1               0x1A4
 204
 205enum i82975x_chips {
 206        I82975X = 0,
 207};
 208
 209struct i82975x_pvt {
 210        void __iomem *mch_window;
 211};
 212
 213struct i82975x_dev_info {
 214        const char *ctl_name;
 215};
 216
 217struct i82975x_error_info {
 218        u16 errsts;
 219        u32 eap;
 220        u8 des;
 221        u8 derrsyn;
 222        u16 errsts2;
 223        u8 chan;                /* the channel is bit 0 of EAP */
 224        u8 xeap;                /* extended eap bit */
 225};
 226
 227static const struct i82975x_dev_info i82975x_devs[] = {
 228        [I82975X] = {
 229                .ctl_name = "i82975x"
 230        },
 231};
 232
 233static struct pci_dev *mci_pdev;        /* init dev: in case that AGP code has
 234                                         * already registered driver
 235                                         */
 236
 237static int i82975x_registered = 1;
 238
 239static void i82975x_get_error_info(struct mem_ctl_info *mci,
 240                struct i82975x_error_info *info)
 241{
 242        struct pci_dev *pdev;
 243
 244        pdev = to_pci_dev(mci->pdev);
 245
 246        /*
 247         * This is a mess because there is no atomic way to read all the
 248         * registers at once and the registers can transition from CE being
 249         * overwritten by UE.
 250         */
 251        pci_read_config_word(pdev, I82975X_ERRSTS, &info->errsts);
 252        pci_read_config_dword(pdev, I82975X_EAP, &info->eap);
 253        pci_read_config_byte(pdev, I82975X_XEAP, &info->xeap);
 254        pci_read_config_byte(pdev, I82975X_DES, &info->des);
 255        pci_read_config_byte(pdev, I82975X_DERRSYN, &info->derrsyn);
 256        pci_read_config_word(pdev, I82975X_ERRSTS, &info->errsts2);
 257
 258        pci_write_bits16(pdev, I82975X_ERRSTS, 0x0003, 0x0003);
 259
 260        /*
 261         * If the error is the same then we can for both reads then
 262         * the first set of reads is valid.  If there is a change then
 263         * there is a CE no info and the second set of reads is valid
 264         * and should be UE info.
 265         */
 266        if (!(info->errsts2 & 0x0003))
 267                return;
 268
 269        if ((info->errsts ^ info->errsts2) & 0x0003) {
 270                pci_read_config_dword(pdev, I82975X_EAP, &info->eap);
 271                pci_read_config_byte(pdev, I82975X_XEAP, &info->xeap);
 272                pci_read_config_byte(pdev, I82975X_DES, &info->des);
 273                pci_read_config_byte(pdev, I82975X_DERRSYN,
 274                                &info->derrsyn);
 275        }
 276}
 277
 278static int i82975x_process_error_info(struct mem_ctl_info *mci,
 279                struct i82975x_error_info *info, int handle_errors)
 280{
 281        int row, chan;
 282        unsigned long offst, page;
 283
 284        if (!(info->errsts2 & 0x0003))
 285                return 0;
 286
 287        if (!handle_errors)
 288                return 1;
 289
 290        if ((info->errsts ^ info->errsts2) & 0x0003) {
 291                edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
 292                                     -1, -1, -1, "UE overwrote CE", "");
 293                info->errsts = info->errsts2;
 294        }
 295
 296        page = (unsigned long) info->eap;
 297        page >>= 1;
 298        if (info->xeap & 1)
 299                page |= 0x80000000;
 300        page >>= (PAGE_SHIFT - 1);
 301        row = edac_mc_find_csrow_by_page(mci, page);
 302
 303        if (row == -1)  {
 304                i82975x_mc_printk(mci, KERN_ERR, "error processing EAP:\n"
 305                        "\tXEAP=%u\n"
 306                        "\t EAP=0x%08x\n"
 307                        "\tPAGE=0x%08x\n",
 308                        (info->xeap & 1) ? 1 : 0, info->eap, (unsigned int) page);
 309                return 0;
 310        }
 311        chan = (mci->csrows[row]->nr_channels == 1) ? 0 : info->eap & 1;
 312        offst = info->eap
 313                        & ((1 << PAGE_SHIFT) -
 314                           (1 << mci->csrows[row]->channels[chan]->dimm->grain));
 315
 316        if (info->errsts & 0x0002)
 317                edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
 318                                     page, offst, 0,
 319                                     row, -1, -1,
 320                                     "i82975x UE", "");
 321        else
 322                edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
 323                                     page, offst, info->derrsyn,
 324                                     row, chan ? chan : 0, -1,
 325                                     "i82975x CE", "");
 326
 327        return 1;
 328}
 329
 330static void i82975x_check(struct mem_ctl_info *mci)
 331{
 332        struct i82975x_error_info info;
 333
 334        edac_dbg(1, "MC%d\n", mci->mc_idx);
 335        i82975x_get_error_info(mci, &info);
 336        i82975x_process_error_info(mci, &info, 1);
 337}
 338
 339/* Return 1 if dual channel mode is active.  Else return 0. */
 340static int dual_channel_active(void __iomem *mch_window)
 341{
 342        /*
 343         * We treat interleaved-symmetric configuration as dual-channel - EAP's
 344         * bit-0 giving the channel of the error location.
 345         *
 346         * All other configurations are treated as single channel - the EAP's
 347         * bit-0 will resolve ok in symmetric area of mixed
 348         * (symmetric/asymmetric) configurations
 349         */
 350        u8      drb[4][2];
 351        int     row;
 352        int    dualch;
 353
 354        for (dualch = 1, row = 0; dualch && (row < 4); row++) {
 355                drb[row][0] = readb(mch_window + I82975X_DRB + row);
 356                drb[row][1] = readb(mch_window + I82975X_DRB + row + 0x80);
 357                dualch = dualch && (drb[row][0] == drb[row][1]);
 358        }
 359        return dualch;
 360}
 361
 362static enum dev_type i82975x_dram_type(void __iomem *mch_window, int rank)
 363{
 364        /*
 365         * ECC is possible on i92975x ONLY with DEV_X8
 366         */
 367        return DEV_X8;
 368}
 369
 370static void i82975x_init_csrows(struct mem_ctl_info *mci,
 371                struct pci_dev *pdev, void __iomem *mch_window)
 372{
 373        struct csrow_info *csrow;
 374        unsigned long last_cumul_size;
 375        u8 value;
 376        u32 cumul_size, nr_pages;
 377        int index, chan;
 378        struct dimm_info *dimm;
 379        enum dev_type dtype;
 380
 381        last_cumul_size = 0;
 382
 383        /*
 384         * 82875 comment:
 385         * The dram row boundary (DRB) reg values are boundary address
 386         * for each DRAM row with a granularity of 32 or 64MB (single/dual
 387         * channel operation).  DRB regs are cumulative; therefore DRB7 will
 388         * contain the total memory contained in all rows.
 389         *
 390         */
 391
 392        for (index = 0; index < mci->nr_csrows; index++) {
 393                csrow = mci->csrows[index];
 394
 395                value = readb(mch_window + I82975X_DRB + index +
 396                                        ((index >= 4) ? 0x80 : 0));
 397                cumul_size = value;
 398                cumul_size <<= (I82975X_DRB_SHIFT - PAGE_SHIFT);
 399                /*
 400                 * Adjust cumul_size w.r.t number of channels
 401                 *
 402                 */
 403                if (csrow->nr_channels > 1)
 404                        cumul_size <<= 1;
 405                edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size);
 406
 407                nr_pages = cumul_size - last_cumul_size;
 408                if (!nr_pages)
 409                        continue;
 410
 411                /*
 412                 * Initialise dram labels
 413                 * index values:
 414                 *   [0-7] for single-channel; i.e. csrow->nr_channels = 1
 415                 *   [0-3] for dual-channel; i.e. csrow->nr_channels = 2
 416                 */
 417                dtype = i82975x_dram_type(mch_window, index);
 418                for (chan = 0; chan < csrow->nr_channels; chan++) {
 419                        dimm = mci->csrows[index]->channels[chan]->dimm;
 420
 421                        dimm->nr_pages = nr_pages / csrow->nr_channels;
 422
 423                        snprintf(csrow->channels[chan]->dimm->label, EDAC_MC_LABEL_LEN, "DIMM %c%d",
 424                                 (chan == 0) ? 'A' : 'B',
 425                                 index);
 426                        dimm->grain = 1 << 7;   /* 128Byte cache-line resolution */
 427                        dimm->dtype = i82975x_dram_type(mch_window, index);
 428                        dimm->mtype = MEM_DDR2; /* I82975x supports only DDR2 */
 429                        dimm->edac_mode = EDAC_SECDED; /* only supported */
 430                }
 431
 432                csrow->first_page = last_cumul_size;
 433                csrow->last_page = cumul_size - 1;
 434                last_cumul_size = cumul_size;
 435        }
 436}
 437
 438/* #define  i82975x_DEBUG_IOMEM */
 439
 440#ifdef i82975x_DEBUG_IOMEM
 441static void i82975x_print_dram_timings(void __iomem *mch_window)
 442{
 443        /*
 444         * The register meanings are from Intel specs;
 445         * (shows 13-5-5-5 for 800-DDR2)
 446         * Asus P5W Bios reports 15-5-4-4
 447         * What's your religion?
 448         */
 449        static const int caslats[4] = { 5, 4, 3, 6 };
 450        u32     dtreg[2];
 451
 452        dtreg[0] = readl(mch_window + 0x114);
 453        dtreg[1] = readl(mch_window + 0x194);
 454        i82975x_printk(KERN_INFO, "DRAM Timings :     Ch0    Ch1\n"
 455                "                RAS Active Min = %d     %d\n"
 456                "                CAS latency    =  %d      %d\n"
 457                "                RAS to CAS     =  %d      %d\n"
 458                "                RAS precharge  =  %d      %d\n",
 459                (dtreg[0] >> 19 ) & 0x0f,
 460                        (dtreg[1] >> 19) & 0x0f,
 461                caslats[(dtreg[0] >> 8) & 0x03],
 462                        caslats[(dtreg[1] >> 8) & 0x03],
 463                ((dtreg[0] >> 4) & 0x07) + 2,
 464                        ((dtreg[1] >> 4) & 0x07) + 2,
 465                (dtreg[0] & 0x07) + 2,
 466                        (dtreg[1] & 0x07) + 2
 467        );
 468
 469}
 470#endif
 471
 472static int i82975x_probe1(struct pci_dev *pdev, int dev_idx)
 473{
 474        int rc = -ENODEV;
 475        struct mem_ctl_info *mci;
 476        struct edac_mc_layer layers[2];
 477        struct i82975x_pvt *pvt;
 478        void __iomem *mch_window;
 479        u32 mchbar;
 480        u32 drc[2];
 481        struct i82975x_error_info discard;
 482        int     chans;
 483#ifdef i82975x_DEBUG_IOMEM
 484        u8 c0drb[4];
 485        u8 c1drb[4];
 486#endif
 487
 488        edac_dbg(0, "\n");
 489
 490        pci_read_config_dword(pdev, I82975X_MCHBAR, &mchbar);
 491        if (!(mchbar & 1)) {
 492                edac_dbg(3, "failed, MCHBAR disabled!\n");
 493                goto fail0;
 494        }
 495        mchbar &= 0xffffc000;   /* bits 31:14 used for 16K window */
 496        mch_window = ioremap_nocache(mchbar, 0x1000);
 497
 498#ifdef i82975x_DEBUG_IOMEM
 499        i82975x_printk(KERN_INFO, "MCHBAR real = %0x, remapped = %p\n",
 500                                        mchbar, mch_window);
 501
 502        c0drb[0] = readb(mch_window + I82975X_DRB_CH0R0);
 503        c0drb[1] = readb(mch_window + I82975X_DRB_CH0R1);
 504        c0drb[2] = readb(mch_window + I82975X_DRB_CH0R2);
 505        c0drb[3] = readb(mch_window + I82975X_DRB_CH0R3);
 506        c1drb[0] = readb(mch_window + I82975X_DRB_CH1R0);
 507        c1drb[1] = readb(mch_window + I82975X_DRB_CH1R1);
 508        c1drb[2] = readb(mch_window + I82975X_DRB_CH1R2);
 509        c1drb[3] = readb(mch_window + I82975X_DRB_CH1R3);
 510        i82975x_printk(KERN_INFO, "DRBCH0R0 = 0x%02x\n", c0drb[0]);
 511        i82975x_printk(KERN_INFO, "DRBCH0R1 = 0x%02x\n", c0drb[1]);
 512        i82975x_printk(KERN_INFO, "DRBCH0R2 = 0x%02x\n", c0drb[2]);
 513        i82975x_printk(KERN_INFO, "DRBCH0R3 = 0x%02x\n", c0drb[3]);
 514        i82975x_printk(KERN_INFO, "DRBCH1R0 = 0x%02x\n", c1drb[0]);
 515        i82975x_printk(KERN_INFO, "DRBCH1R1 = 0x%02x\n", c1drb[1]);
 516        i82975x_printk(KERN_INFO, "DRBCH1R2 = 0x%02x\n", c1drb[2]);
 517        i82975x_printk(KERN_INFO, "DRBCH1R3 = 0x%02x\n", c1drb[3]);
 518#endif
 519
 520        drc[0] = readl(mch_window + I82975X_DRC_CH0M0);
 521        drc[1] = readl(mch_window + I82975X_DRC_CH1M0);
 522#ifdef i82975x_DEBUG_IOMEM
 523        i82975x_printk(KERN_INFO, "DRC_CH0 = %0x, %s\n", drc[0],
 524                        ((drc[0] >> 21) & 3) == 1 ?
 525                                "ECC enabled" : "ECC disabled");
 526        i82975x_printk(KERN_INFO, "DRC_CH1 = %0x, %s\n", drc[1],
 527                        ((drc[1] >> 21) & 3) == 1 ?
 528                                "ECC enabled" : "ECC disabled");
 529
 530        i82975x_printk(KERN_INFO, "C0 BNKARC = %0x\n",
 531                readw(mch_window + I82975X_C0BNKARC));
 532        i82975x_printk(KERN_INFO, "C1 BNKARC = %0x\n",
 533                readw(mch_window + I82975X_C1BNKARC));
 534        i82975x_print_dram_timings(mch_window);
 535        goto fail1;
 536#endif
 537        if (!(((drc[0] >> 21) & 3) == 1 || ((drc[1] >> 21) & 3) == 1)) {
 538                i82975x_printk(KERN_INFO, "ECC disabled on both channels.\n");
 539                goto fail1;
 540        }
 541
 542        chans = dual_channel_active(mch_window) + 1;
 543
 544        /* assuming only one controller, index thus is 0 */
 545        layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
 546        layers[0].size = I82975X_NR_DIMMS;
 547        layers[0].is_virt_csrow = true;
 548        layers[1].type = EDAC_MC_LAYER_CHANNEL;
 549        layers[1].size = I82975X_NR_CSROWS(chans);
 550        layers[1].is_virt_csrow = false;
 551        mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
 552        if (!mci) {
 553                rc = -ENOMEM;
 554                goto fail1;
 555        }
 556
 557        edac_dbg(3, "init mci\n");
 558        mci->pdev = &pdev->dev;
 559        mci->mtype_cap = MEM_FLAG_DDR2;
 560        mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
 561        mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
 562        mci->mod_name = EDAC_MOD_STR;
 563        mci->mod_ver = I82975X_REVISION;
 564        mci->ctl_name = i82975x_devs[dev_idx].ctl_name;
 565        mci->dev_name = pci_name(pdev);
 566        mci->edac_check = i82975x_check;
 567        mci->ctl_page_to_phys = NULL;
 568        edac_dbg(3, "init pvt\n");
 569        pvt = (struct i82975x_pvt *) mci->pvt_info;
 570        pvt->mch_window = mch_window;
 571        i82975x_init_csrows(mci, pdev, mch_window);
 572        mci->scrub_mode = SCRUB_HW_SRC;
 573        i82975x_get_error_info(mci, &discard);  /* clear counters */
 574
 575        /* finalize this instance of memory controller with edac core */
 576        if (edac_mc_add_mc(mci)) {
 577                edac_dbg(3, "failed edac_mc_add_mc()\n");
 578                goto fail2;
 579        }
 580
 581        /* get this far and it's successful */
 582        edac_dbg(3, "success\n");
 583        return 0;
 584
 585fail2:
 586        edac_mc_free(mci);
 587
 588fail1:
 589        iounmap(mch_window);
 590fail0:
 591        return rc;
 592}
 593
 594/* returns count (>= 0), or negative on error */
 595static int i82975x_init_one(struct pci_dev *pdev,
 596                            const struct pci_device_id *ent)
 597{
 598        int rc;
 599
 600        edac_dbg(0, "\n");
 601
 602        if (pci_enable_device(pdev) < 0)
 603                return -EIO;
 604
 605        rc = i82975x_probe1(pdev, ent->driver_data);
 606
 607        if (mci_pdev == NULL)
 608                mci_pdev = pci_dev_get(pdev);
 609
 610        return rc;
 611}
 612
 613static void i82975x_remove_one(struct pci_dev *pdev)
 614{
 615        struct mem_ctl_info *mci;
 616        struct i82975x_pvt *pvt;
 617
 618        edac_dbg(0, "\n");
 619
 620        mci = edac_mc_del_mc(&pdev->dev);
 621        if (mci  == NULL)
 622                return;
 623
 624        pvt = mci->pvt_info;
 625        if (pvt->mch_window)
 626                iounmap( pvt->mch_window );
 627
 628        edac_mc_free(mci);
 629}
 630
 631static DEFINE_PCI_DEVICE_TABLE(i82975x_pci_tbl) = {
 632        {
 633                PCI_VEND_DEV(INTEL, 82975_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 634                I82975X
 635        },
 636        {
 637                0,
 638        }       /* 0 terminated list. */
 639};
 640
 641MODULE_DEVICE_TABLE(pci, i82975x_pci_tbl);
 642
 643static struct pci_driver i82975x_driver = {
 644        .name = EDAC_MOD_STR,
 645        .probe = i82975x_init_one,
 646        .remove = i82975x_remove_one,
 647        .id_table = i82975x_pci_tbl,
 648};
 649
 650static int __init i82975x_init(void)
 651{
 652        int pci_rc;
 653
 654        edac_dbg(3, "\n");
 655
 656       /* Ensure that the OPSTATE is set correctly for POLL or NMI */
 657       opstate_init();
 658
 659        pci_rc = pci_register_driver(&i82975x_driver);
 660        if (pci_rc < 0)
 661                goto fail0;
 662
 663        if (mci_pdev == NULL) {
 664                mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
 665                                PCI_DEVICE_ID_INTEL_82975_0, NULL);
 666
 667                if (!mci_pdev) {
 668                        edac_dbg(0, "i82975x pci_get_device fail\n");
 669                        pci_rc = -ENODEV;
 670                        goto fail1;
 671                }
 672
 673                pci_rc = i82975x_init_one(mci_pdev, i82975x_pci_tbl);
 674
 675                if (pci_rc < 0) {
 676                        edac_dbg(0, "i82975x init fail\n");
 677                        pci_rc = -ENODEV;
 678                        goto fail1;
 679                }
 680        }
 681
 682        return 0;
 683
 684fail1:
 685        pci_unregister_driver(&i82975x_driver);
 686
 687fail0:
 688        if (mci_pdev != NULL)
 689                pci_dev_put(mci_pdev);
 690
 691        return pci_rc;
 692}
 693
 694static void __exit i82975x_exit(void)
 695{
 696        edac_dbg(3, "\n");
 697
 698        pci_unregister_driver(&i82975x_driver);
 699
 700        if (!i82975x_registered) {
 701                i82975x_remove_one(mci_pdev);
 702                pci_dev_put(mci_pdev);
 703        }
 704}
 705
 706module_init(i82975x_init);
 707module_exit(i82975x_exit);
 708
 709MODULE_LICENSE("GPL");
 710MODULE_AUTHOR("Arvind R. <arvino55@gmail.com>");
 711MODULE_DESCRIPTION("MC support for Intel 82975 memory hub controllers");
 712
 713module_param(edac_op_state, int, 0444);
 714MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
 715
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