linux/drivers/edac/i82443bxgx_edac.c
<<
> > p/spa pspa class="lxr_search"> > ="+search" method="post" onsubmit="return do_search(this);"> > > > Search > p/spa > ="ajax+*" method="post" onsubmit="return false;"> pinput typ"v2hidden" nam"v2ajax_lookup" idv2ajax_lookup" lue="v2"> >
pdiv idv2file_contents"
o o1p/a>pspa
 class="comment">/*p/spa
  o o2p/a>pspa
 class="comment"> * Intel 82443BX/GX (440BX/GX chipset) Memory Controller EDAC kernelp/spa
  o o3p/a>pspa
 class="comment"> * module (C) 2006 Tim Smallp/spa
  o o4p/a>pspa
 class="comment"> *p/spa
  o o5p/a>pspa
 class="comment"> * This file may be distributed under the terms of the GNU Generalp/spa
  o o6p/a>pspa
 class="comment"> * Public License.p/spa
  o o7p/a>pspa
 class="comment"> *p/spa
  o o8p/a>pspa
 class="comment"> * Written by Tim Small <tim@buttersideup.com>, based  vawork by Linuxp/spa
  o o9p/a>pspa
 class="comment"> * Networx, Thayne Harbaugh, Da
 Hollis <goemon at anime dot net> andp/spa
  o on>
a>pspa
 class="comment"> * others.p/spa
  o 11p/a>pspa
 class="comment"> *p/spa
  o 12p/a>pspa
 class="comment"> * 440GX fix by Jason Uhlenkott <juhlenko@akamai.com>.p/spa
  o 13p/a>pspa
 class="comment"> *p/spa
  o 14p/a>pspa
 class="comment"> * Written with reference to 82443BX Host Bridge Datasheet:p/spa
  o 15p/a>pspa
 class="comment"> * http://download.intel.com/design/chipsets/datashts/29063301.pdfp/spa
  o 16p/a>pspa
 class="comment"> * references to this document given in [].p/spa
  o 17p/a>pspa
 class="comment"> *p/spa
  o 18p/a>pspa
 class="comment"> * This module doesn't support the 440LX, but it may be possible top/spa
  o 19p/a>pspa
 class="comment"> * make it do so (the 440LX's register definion>
s are different, butp/spa
  o 2n>
a>pspa
 class="comment"> * not completely so - I haven't studied them in enough detail to knowp/spa
  o 21p/a>pspa
 class="comment"> * how easy this would be).p/spa
  o 22p/a>pspa
 class="comment"> */p/spa
  o 23p/a> o 24p/a>#include <linux/module.hp/a>> o 25p/a>#include <linux/inio.hp/a>> o 26p/a> o 27p/a>#include <linux/pci.hp/a>> o 28p/a>#include <linux/pci_ids.hp/a>> o 29p/a> o 30p/a> o 31p/a>#include <linux/edac.hp/a>> o 32p/a>#include "edac_core.hp/a>" o 33p/a> o 34p/a>#defineopa href="+code=I82443_REVISION" class="sref">I82443_REVISIONp/a> pspa
 class="string">"0.1"o 35p/a> o 36p/a>#defineopa href="+code=EDAC_MOD_STR" class="sref">EDAC_MOD_STRp/a> o opspa
 class="string">"i82443bxgx_edac"o 37p/a> o 38p/a>pspa
 class="comment">/* The 82443BX supports SDRAM, or EDO (EDO for mobile only), "Memoryo 39p/a>pspa
 class="comment"> * Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memoryo 4n>
a>pspa
 class="comment"> * rows" "The 82443BX supports multiple-bit error detecon>
 andp/spa
  o 41p/a>pspa
 class="comment"> * single-bit error correcon>
 when ECC mode is enabled andp/spa
  o 42p/a>pspa
 class="comment"> * single/multi-bit error detecon>
 when correcon>
 is disabled.p/spa
  o 43p/a>pspa
 class="comment"> * During writes to the DRAM, the 82443BX generates ECC for the datap/spa
  o 44p/a>pspa
 class="comment"> * >
 a QWord basis. Partial QWord writes require a read-modify-writep/spa
  o 45p/a>pspa
 class="comment"> * cycle when ECC is enabled."o 46p/a>pspa
 class="comment">*/p/spa
  o 47p/a> o 48p/a>pspa
 class="comment">/* "Addion>
ally, the 82443BX ensures that the data is correcoed inp/spa
  o 49p/a>pspa
 class="comment"> * main memory so that accumulaon>
 of errors is prevented. Anotherp/spa
  o 5n>
a>pspa
 class="comment"> * error within the sam" QWord would result in a double-bit errorp/spa
  o 51p/a>pspa
 class="comment"> * which is unrecoverable. This is known as hardware scrubbing sincep/spa
  o 52p/a>pspa
 class="comment"> * it requires no software interventn>
 to correco the data in memory."o 53p/a>pspa
 class="comment"> */p/spa
  o 54p/a> o 55p/a>pspa
 class="comment">/* [Also see page 100 (secon>
 4.3), "DRAM Interface"]p/spa
  o 56p/a>pspa
 class="comment"> * [Also see page 112 (secon>
 4.6.1.4), ECC]p/spa
  o 57p/a>pspa
 class="comment"> */p/spa
  o 58p/a> o 59p/a>#defineopa href="+code=I82443BXGX_NR_CSROWS" class="sref">I82443BXGX_NR_CSROWSp/a> 8 o 60p/a>#defineopa href="+code=I82443BXGX_NR_CHANS" class="sref">I82443BXGX_NR_CHANSp/a> o1 o 61p/a>#defineopa href="+code=I82443BXGX_NR_DIMMS" class="sref">I82443BXGX_NR_DIMMSp/a> o4 o 62p/a> o 63p/a>pspa
 class="comment">/* 82443 PCI Device 0 */p/spa
  o 64p/a>#defineopa href="+code=I82443BXGX_NBXCFG" class="sref">I82443BXGX_NBXCFGp/a> 0x50 opspa
 class="comment">/* 32bit register starting at this PCIp/spa
  o 65p/a>pspa
 class="comment">                                 * config space offset */p/spa
  o 66p/a>#defineopa href="+code=I82443BXGX_NBXCFG_OFFSET_NON_ECCROW" class="sref">I82443BXGX_NBXCFG_OFFSET_NON_ECCROWp/a> 24 opspa
 class="comment">/* Array of bits, zero ifp/spa
  o 67p/a>pspa
 class="comment">                                                 * row is non-ECC */p/spa
  o 68p/a>#defineopa href="+code=I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ" class="sref">I82443BXGX_NBXCFG_OFFSET_DRAM_FREQp/a> 12  opspa
 class="comment">/* 2 bits,00=100MHz,10=66 MHz */p/spa
  o 69p/a> o 70p/a>#defineopa href="+code=I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY" class="sref">I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITYp/a> 7       pspa
 class="comment">/* 2 bits:       */p/spa
  o 71p/a>#defineopa href="+code=I82443BXGX_NBXCFG_INTEGRITY_NONE" class="sref">I82443BXGX_NBXCFG_INTEGRITY_NONEp/a> o 0x0 opspa
 class="comment">/* 00 = Non-ECC */p/spa
  o 72p/a>#defineopa href="+code=I82443BXGX_NBXCFG_INTEGRITY_EC" class="sref">I82443BXGX_NBXCFG_INTEGRITY_ECp/a> o o 0x1 opspa
 class="comment">/* 01 = EC (only) */p/spa
  o 73p/a>#defineopa href="+code=I82443BXGX_NBXCFG_INTEGRITY_ECC" class="sref">I82443BXGX_NBXCFG_INTEGRITY_ECCp/a> o o0x2 opspa
 class="comment">/* 10 = ECC */p/spa
  o 74p/a>#defineopa href="+code=I82443BXGX_NBXCFG_INTEGRITY_SCRUB" class="sref">I82443BXGX_NBXCFG_INTEGRITY_SCRUBp/a> o0x3 opspa
 class="comment">/* 11 = ECC + HW Scrub */p/spa
  o 75p/a> o 76p/a>#defineopa href="+code=I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE" class="sref">I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLEp/a> o6 o 77p/a> o 78p/a>pspa
 class="comment">/* 82443 PCI Device 0 */p/spa
  o 79p/a>#defineopa href="+code=I82443BXGX_EAP" class="sref">I82443BXGX_EAPp/a> o 0x80   pspa
 class="comment">/* 32bit register starting at this PCIp/spa
  o 8n>
a>pspa
 class="comment">                                 * config space offset, Error Addressp/spa
  o 81p/a>pspa
 class="comment">                                 * Pointer Register */p/spa
  o 82p/a>#defineopa href="+code=I82443BXGX_EAP_OFFSET_EAP" class="sref">I82443BXGX_EAP_OFFSET_EAPp/a> o12  opspa
 class="comment">/* High 20 bits of error address */p/spa
  o 83p/a>#defineopa href="+code=I82443BXGX_EAP_OFFSET_MBE" class="sref">I82443BXGX_EAP_OFFSET_MBEp/a> opa href="+code=BIT" class="sref">BITp/a>(1)       pspa
 class="comment">/* Err at EAP was multi-bit (W1TC) */p/spa
  o 84p/a>#defineopa href="+code=I82443BXGX_EAP_OFFSET_SBE" class="sref">I82443BXGX_EAP_OFFSET_SBEp/a> opa href="+code=BIT" class="sref">BITp/a>(0)       pspa
 class="comment">/* Err at EAP was single-bit (W1TC) */p/spa
  o 85p/a> o 86p/a>#defineopa href="+code=I82443BXGX_ERRCMD" class="sref">I82443BXGX_ERRCMDp/a> o0x90 pspa
 class="comment">/* 8bit register starting at this PCIp/spa
  o 87p/a>pspa
 class="comment">                                 * config space offset. */p/spa
  o 88p/a>#defineopa href="+code=I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE" class="sref">I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBEp/a> pa href="+code=BIT" class="sref">BITp/a>(1)     pspa
 class="comment">/* 1 = enable */p/spa
  o 89p/a>#defineopa href="+code=I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE" class="sref">I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBEp/a> pa href="+code=BIT" class="sref">BITp/a>(0)     pspa
 class="comment">/* 1 = enable */p/spa
  o 90p/a> o 91p/a>#defineopa href="+code=I82443BXGX_ERRSTS" class="sref">I82443BXGX_ERRSTSp/a> o0x91 pspa
 class="comment">/* 16bit register starting at this PCIp/spa
  o 92p/a>pspa
 class="comment">                                 * config space offset. */p/spa
  o 93p/a>#defineopa href="+code=I82443BXGX_ERRSTS_OFFSET_MBFRE" class="sref">I82443BXGX_ERRSTS_OFFSET_MBFREp/a> 5        pspa
 class="comment">/* 3 bits - first err row multibit */p/spa
  o 94p/a>#defineopa href="+code=I82443BXGX_ERRSTS_OFFSET_MEF" class="sref">I82443BXGX_ERRSTS_OFFSET_MEFp/a> o pa href="+code=BIT" class="sref">BITp/a>(4)   pspa
 class="comment">/* 1 = MBE occurred */p/spa
  o 95p/a>#defineopa href="+code=I82443BXGX_ERRSTS_OFFSET_SBFRE" class="sref">I82443BXGX_ERRSTS_OFFSET_SBFREp/a> 1        pspa
 class="comment">/* 3 bits - first err row singlebit */p/spa
  o 96p/a>#defineopa href="+code=I82443BXGX_ERRSTS_OFFSET_SEF" class="sref">I82443BXGX_ERRSTS_OFFSET_SEFp/a> o pa href="+code=BIT" class="sref">BITp/a>(0)   pspa
 class="comment">/* 1 = SBE occurred */p/spa
  o 97p/a> o 98p/a>#defineopa href="+code=I82443BXGX_DRAMC" class="sref">I82443BXGX_DRAMCp/a> 0x57   pspa
 class="comment">/* 8bit register starting at this PCIp/spa
  o 99p/a>pspa
 class="comment">                                 * config space offset. */p/spa
  o100p/a>#defineopa href="+code=I82443BXGX_DRAMC_OFFSET_DT" class="sref">I82443BXGX_DRAMC_OFFSET_DTp/a> 3    pspa
 class="comment">/* 2 bits, DRAM Type */p/spa
  o101p/a>#defineopa href="+code=I82443BXGX_DRAMC_DRAM_IS_EDO" class="sref">I82443BXGX_DRAMC_DRAM_IS_EDOp/a> 0 opspa
 class="comment">/* 00 = EDO */p/spa
  o102p/a>#defineopa href="+code=I82443BXGX_DRAMC_DRAM_IS_SDRAM" class="sref">I82443BXGX_DRAMC_DRAM_IS_SDRAMp/a> 1        pspa
 class="comment">/* 01 = SDRAM */p/spa
  o103p/a>#defineopa href="+code=I82443BXGX_DRAMC_DRAM_IS_RSDRAM" class="sref">I82443BXGX_DRAMC_DRAM_IS_RSDRAMp/a> 2       pspa
 class="comment">/* 10 = Registered SDRAM */p/spa
  o104p/a> o105p/a>#defineopa href="+code=I82443BXGX_DRB" class="sref">I82443BXGX_DRBp/a> 0x60     pspa
 class="comment">/* 8x 8bit registers starting at this PCIp/spa
  o106p/a>pspa
 class="comment">                                 * config space offset. */p/spa
  o107p/a> o108p/a>pspa
 class="comment">/* FIXME - don't poll when ECC disabled? */p/spa
  o109p/a> o1on>
a>structopa href="+code=i82443bxgx_edacmc_error_info" class="sref">i82443bxgx_edacmc_error_infop/a> { o111p/a>        pa href="+code=u32" class="sref">u32p/a> pa href="+code=eap" class="sref">eapp/a>; o112p/a>}; o113p/a> o114p/a>static structopa href="+code=edac_pci_ctl_info" class="sref">edac_pci_ctl_infop/a> *pa href="+code=i82443bxgx_pci" class="sref">i82443bxgx_pcip/a>; o115p/a> o116p/a>static structopa href="+code=pci_dev" class="sref">pci_devp/a> *pa href="+code=mci_pdev" class="sref">mci_pdevp/a>;        pspa
 class="comment">/* inio dev: in case that AGP code hasp/spa
  o117p/a>pspa
 class="comment">                                         * already registered driverp/spa
  o118p/a>pspa
 class="comment">                                         */p/spa
  o119p/a> o120p/a>static intopa href="+code=i82443bxgx_registered" class="sref">i82443bxgx_registeredp/a> = 1; o121p/a> o122p/a>static voidopa href="+code=i82443bxgx_edacmc_get_error_info" class="sref">i82443bxgx_edacmc_get_error_infop/a>(structopa href="+code=mem_ctl_info" class="sref">mem_ctl_infop/a> *pa href="+code=mci" class="sref">mcip/a>, o123p/a>                                structopa href="+code=i82443bxgx_edacmc_error_info" class="sref">i82443bxgx_edacmc_error_infop/a> o124p/a>                                *pa href="+code=info" class="sref">infop/a>) o125p/a>{ o126p/a>        structopa href="+code=pci_dev" class="sref">pci_devp/a> *pa href="+code=pdev" class="sref">pdevp/a>; o127p/a>        pa href="+code=pdev" class="sref">pdevp/a> = pa href="+code=to_pci_dev" class="sref">to_pci_devp/a>(pa href="+code=mci" class="sref">mcip/a>->pa href="+code=pdev" class="sref">pdevp/a>); o128p/a>        pa href="+code=pci_read_config_dword" class="sref">pci_read_config_dwordp/a>(pa href="+code=pdev" class="sref">pdevp/a>,opa href="+code=I82443BXGX_EAP" class="sref">I82443BXGX_EAPp/a>, &pa href="+code=info" class="sref">infop/a>->pa href="+code=eap" class="sref">eapp/a>); o129p/a>        if (pa href="+code=info" class="sref">infop/a>->pa href="+code=eap" class="sref">eapp/a> &opa href="+code=I82443BXGX_EAP_OFFSET_SBE" class="sref">I82443BXGX_EAP_OFFSET_SBEp/a>) o130p/a>                pspa
 class="comment">/* Clear error to allow next error to be reported [p.61] */p/spa
  o131p/a>                pa href="+code=pci_write_bits32" class="sref">pci_write_bits32p/a>(pa href="+code=pdev" class="sref">pdevp/a>,opa href="+code=I82443BXGX_EAP" class="sref">I82443BXGX_EAPp/a>, o132p/a>                                 pa href="+code=I82443BXGX_EAP_OFFSET_SBE" class="sref">I82443BXGX_EAP_OFFSET_SBEp/a>, o133p/a>                                opa href="+code=I82443BXGX_EAP_OFFSET_SBE" class="sref">I82443BXGX_EAP_OFFSET_SBEp/a>); o134p/a> o135p/a>        if (pa href="+code=info" class="sref">infop/a>->pa href="+code=eap" class="sref">eapp/a> &opa href="+code=I82443BXGX_EAP_OFFSET_MBE" class="sref">I82443BXGX_EAP_OFFSET_MBEp/a>) o136p/a>                pspa
 class="comment">/* Clear error to allow next error to be reported [p.61] */p/spa
  o137p/a>                pa href="+code=pci_write_bits32" class="sref">pci_write_bits32p/a>(pa href="+code=pdev" class="sref">pdevp/a>,opa href="+code=I82443BXGX_EAP" class="sref">I82443BXGX_EAPp/a>, o138p/a>                                opa href="+code=I82443BXGX_EAP_OFFSET_MBE" class="sref">I82443BXGX_EAP_OFFSET_MBEp/a>, o139p/a>                                opa href="+code=I82443BXGX_EAP_OFFSET_MBE" class="sref">I82443BXGX_EAP_OFFSET_MBEp/a>); o14n>
a>} o141p/a> o142p/a>static intopa href="+code=i82443bxgx_edacmc_process_error_info" class="sref">i82443bxgx_edacmc_process_error_infop/a>(structopa href="+code=mem_ctl_info" class="sref">mem_ctl_infop/a> *pa href="+code=mci" class="sref">mcip/a>, o143p/a>                                oooooooooooooooostruct o144p/a>                                               opa href="+code=i82443bxgx_edacmc_error_info" class="sref">i82443bxgx_edacmc_error_infop/a> o145p/a>                                               o*pa href="+code=info" class="sref">infop/a>, intopa href="+code=handle_errors" class="sref">handle_errorsp/a>) o146p/a>{ o147p/a>        intopa href="+code=error_found" class="sref">error_foundp/a> = 0; o148p/a>        pa href="+code=u32" class="sref">u32p/a> pa href="+code=eapaddr" class="sref">eapaddrp/a>,opa href="+code=page" class="sref">pagep/a>,opa href="+code=pageoffset" class="sref">pageoffsetp/a>; o149p/a> o150p/a>        pspa
 class="comment">/* bits 30:12 hold the 4kb block in which the error occurredp/spa
  o151p/a>pspa
 class="comment">        o* [p.61] */p/spa
  o152p/a>        pa href="+code=eapaddr" class="sref">eapaddrp/a> = (pa href="+code=info" class="sref">infop/a>->pa href="+code=eap" class="sref">eapp/a> &o0xfffff000); o153p/a>        pa href="+code=page" class="sref">pagep/a> = pa href="+code=eapaddr" class="sref">eapaddrp/a> >> pa href="+code=PAGE_SHIFT" class="sref">PAGE_SHIFTp/a>; o154p/a>        pa href="+code=pageoffset" class="sref">pageoffsetp/a> = pa href="+code=eapaddr" class="sref">eapaddrp/a> - (pa href="+code=page" class="sref">pagep/a> << pa href="+code=PAGE_SHIFT" class="sref">PAGE_SHIFTp/a>); o155p/a> o156p/a>        if (pa href="+code=info" class="sref">infop/a>->pa href="+code=eap" class="sref">eapp/a> &opa href="+code=I82443BXGX_EAP_OFFSET_SBE" class="sref">I82443BXGX_EAP_OFFSET_SBEp/a>) { o157p/a>                pa href="+code=error_found" class="sref">error_foundp/a> = 1; o158p/a>                if (pa href="+code=handle_errors" class="sref">handle_errorsp/a>) o159p/a>                        pa href="+code=edac_mc_handle_error" class="sref">edac_mc_handle_errorp/a>(pa href="+code=HW_EVENT_ERR_CORRECTED" class="sref">HW_EVENT_ERR_CORRECTEDp/a>,opa href="+code=mci" class="sref">mcip/a>, 1, o160p/a>                                             pa href="+code=page" class="sref">pagep/a>,opa href="+code=pageoffset" class="sref">pageoffsetp/a>, 0, o161p/a>                                             pa href="+code=edac_mc_find_csrow_by_page" class="sref">edac_mc_find_csrow_by_pagep/a>(pa href="+code=mci" class="sref">mcip/a>,opa href="+code=page" class="sref">pagep/a>), o162p/a>                                             0, -1,opa href="+code=mci" class="sref">mcip/a>->pa href="+code=ctl_nam"" class="sref">ctl_nam"p/a>,opspa
 class="string">""o163p/a>        } o164p/a> o165p/a>        if (pa href="+code=info" class="sref">infop/a>->pa href="+code=eap" class="sref">eapp/a> &opa href="+code=I82443BXGX_EAP_OFFSET_MBE" class="sref">I82443BXGX_EAP_OFFSET_MBEp/a>) { o166p/a>                pa href="+code=error_found" class="sref">error_foundp/a> = 1; o167p/a>                if (pa href="+code=handle_errors" class="sref">handle_errorsp/a>) o168p/a>                        pa href="+code=edac_mc_handle_error" class="sref">edac_mc_handle_errorp/a>(pa href="+code=HW_EVENT_ERR_UNCORRECTED" class="sref">HW_EVENT_ERR_UNCORRECTEDp/a>,opa href="+code=mci" class="sref">mcip/a>, 1, o169p/a>                                o            pa href="+code=page" class="sref">pagep/a>,opa href="+code=pageoffset" class="sref">pageoffsetp/a>, 0, o170p/a>                                             pa href="+code=edac_mc_find_csrow_by_page" class="sref">edac_mc_find_csrow_by_pagep/a>(pa href="+code=mci" class="sref">mcip/a>,opa href="+code=page" class="sref">pagep/a>), o171p/a>                                             0, -1,opa href="+code=mci" class="sref">mcip/a>->pa href="+code=ctl_nam"" class="sref">ctl_nam"p/a>,opspa
 class="string">""o172p/a>        } o173p/a> o174p/a>        return pa href="+code=error_found" class="sref">error_foundp/a>; o175p/a>} o176p/a> o177p/a>static voidopa href="+code=i82443bxgx_edacmc_check" class="sref">i82443bxgx_edacmc_checkp/a>(structopa href="+code=mem_ctl_info" class="sref">mem_ctl_infop/a> *pa href="+code=mci" class="sref">mcip/a>) o178p/a>{ o179p/a>        structopa href="+code=i82443bxgx_edacmc_error_info" class="sref">i82443bxgx_edacmc_error_infop/a> pa href="+code=info" class="sref">infop/a>; o180p/a> o181p/a>        pa href="+code=edac_dbg" class="sref">edac_dbgp/a>(1,opspa
 class="string">"MC%d\n"mcip/a>->pa href="+code=mc_idx" class="sref">mc_idxp/a>); o182p/a>        pa href="+code=i82443bxgx_edacmc_get_error_info" class="sref">i82443bxgx_edacmc_get_error_infop/a>(pa href="+code=mci" class="sref">mcip/a>,o&pa href="+code=info" class="sref">infop/a>); o183p/a>        pa href="+code=i82443bxgx_edacmc_process_error_info" class="sref">i82443bxgx_edacmc_process_error_infop/a>(pa href="+code=mci" class="sref">mcip/a>,o&pa href="+code=info" class="sref">infop/a>, 1); o184p/a>} o185p/a> o186p/a>static voidopa href="+code=i82443bxgx_inio_csrows" class="sref">i82443bxgx_inio_csrowsp/a>(structopa href="+code=mem_ctl_info" class="sref">mem_ctl_infop/a> *pa href="+code=mci" class="sref">mcip/a>, o187p/a>                                structopa href="+code=pci_dev" class="sref">pci_devp/a> *pa href="+code=pdev" class="sref">pdevp/a>, o188p/a>                                enum pa href="+code=edac_type" class="sref">edac_typep/a> pa href="+code=edac_mode" class="sref">edac_modep/a>, o189p/a>                                enum pa href="+code=mem_type" class="sref">mem_typep/a> pa href="+code=mtype" class="sref">mtypep/a>) o190p/a>{ o191p/a>        structopa href="+code=csrow_info" class="sref">csrow_infop/a> *pa href="+code=csrow" class="sref">csrowp/a>; o192p/a>        structopa href="+code=dimm_info" class="sref">dimm_infop/a> *pa href="+code=dimm" class="sref">dimmp/a>; o193p/a>        intopa href="+code=index" class="sref">indexp/a>; o194p/a>        pa href="+code=u8" class="sref">u8p/a> pa href="+code=drbar" class="sref">drbarp/a>,opa href="+code=dramc" class="sref">dramcp/a>; o195p/a>        pa href="+code=u32" class="sref">u32p/a> pa href="+code=row_base" class="sref">row_basep/a>,opa href="+code=row_high_limit" class="sref">row_high_limitp/a>,opa href="+code=row_high_limit_last" class="sref">row_high_limit_lastp/a>; o196p/a> o197p/a>        pa href="+code=pci_read_config_byte" class="sref">pci_read_config_bytep/a>(pa href="+code=pdev" class="sref">pdevp/a>,opa href="+code=I82443BXGX_DRAMC" class="sref">I82443BXGX_DRAMCp/a>,o&pa href="+code=dramc" class="sref">dramcp/a>); o198p/a>        pa href="+code=row_high_limit_last" class="sref">row_high_limit_lastp/a> = 0; o199p/a>        for (pa href="+code=index" class="sref">indexp/a> = 0;opa href="+code=index" class="sref">indexp/a> < pa href="+code=mci" class="sref">mcip/a>->pa href="+code=nr_csrows" class="sref">nr_csrowsp/a>;opa href="+code=index" class="sref">indexp/a>++) { o200p/a>                pa href="+code=csrow" class="sref">csrowp/a> = pa href="+code=mci" class="sref">mcip/a>->pa href="+code=csrows" class="sref">csrowsp/a>[pa href="+code=index" class="sref">indexp/a>]; o201p/a>                pa href="+code=dimm" class="sref">dimmp/a> = pa href="+code=csrow" class="sref">csrowp/a>->pa href="+code=channels" class="sref">channelsp/a>[0]->pa href="+code=dimm" class="sref">dimmp/a>; o202p/a> o203p/a>                pa href="+code=pci_read_config_byte" class="sref">pci_read_config_bytep/a>(pa href="+code=pdev" class="sref">pdevp/a>,opa href="+code=I82443BXGX_DRB" class="sref">I82443BXGX_DRBp/a> +opa href="+code=index" class="sref">indexp/a>,o&pa href="+code=drbar" class="sref">drbarp/a>); o204p/a>                pa href="+code=edac_dbg" class="sref">edac_dbgp/a>(1,opspa
 class="string">"MC%d: Row=%d DRB = %#0x\n"o205p/a>                         pa href="+code=mci" class="sref">mcip/a>->pa href="+code=mc_idx" class="sref">mc_idxp/a>,opa href="+code=index" class="sref">indexp/a>,opa href="+code=drbar" class="sref">drbarp/a>); o206p/a>                pa href="+code=row_high_limit" class="sref">row_high_limitp/a> = ((pa href="+code=u32" class="sref">u32p/a>)opa href="+code=drbar" class="sref">drbarp/a> << 23); o207p/a>                pspa
 class="comment">/* find the DRAM Chip Seleco Base address and mask */p/spa
  o208p/a>                pa href="+code=edac_dbg" class="sref">edac_dbgp/a>(1,opspa
 class="string">"MC%d: Row=%d, Boundary Address=%#0x, Last = %#0x\n"o209p/a>                         pa href="+code=mci" class="sref">mcip/a>->pa href="+code=mc_idx" class="sref">mc_idxp/a>,opa href="+code=index" class="sref">indexp/a>,opa href="+code=row_high_limit" class="sref">row_high_limitp/a>, o210p/a>                         pa href="+code=row_high_limit_last" class="sref">row_high_limit_lastp/a>); o211p/a> o212p/a>                pspa
 class="comment">/* 440GX goes to 2GB, represented with a DRB of 0. */p/spa
  o213p/a>                if (pa href="+code=row_high_limit_last" class="sref">row_high_limit_lastp/a> &&o!pa href="+code=row_high_limit" class="sref">row_high_limitp/a>) o214p/a>                        pa href="+code=row_high_limit" class="sref">row_high_limitp/a> = 1UL << 31; o215p/a> o216p/a>                pspa
 class="comment">/* This row is empty [p.49] */p/spa
  o217p/a>                if (pa href="+code=row_high_limit" class="sref">row_high_limitp/a> == pa href="+code=row_high_limit_last" class="sref">row_high_limit_lastp/a>) o218p/a>                        continue; o219p/a>                pa href="+code=row_base" class="sref">row_basep/a> = pa href="+code=row_high_limit_last" class="sref">row_high_limit_lastp/a>; o220p/a>                pa href="+code=csrow" class="sref">csrowp/a>->pa href="+code=first_page" class="sref">first_pagep/a> = pa href="+code=row_base" class="sref">row_basep/a> >> pa href="+code=PAGE_SHIFT" class="sref">PAGE_SHIFTp/a>; o221p/a>                pa href="+code=csrow" class="sref">csrowp/a>->pa href="+code=last_page" class="sref">last_pagep/a> = (pa href="+code=row_high_limit" class="sref">row_high_limitp/a> >> pa href="+code=PAGE_SHIFT" class="sref">PAGE_SHIFTp/a>) - 1; o222p/a>                pa href="+code=dimm" class="sref">dimmp/a>->pa href="+code=nr_pages" class="sref">nr_pagesp/a> = pa href="+code=csrow" class="sref">csrowp/a>->pa href="+code=last_page" class="sref">last_pagep/a> - pa href="+code=csrow" class="sref">csrowp/a>->pa href="+code=first_page" class="sref">first_pagep/a> + 1; o223p/a>                pspa
 class="comment">/* EAP reports in 4kilobyte granularity [61] */p/spa
  o224p/a>                pa href="+code=dimm" class="sref">dimmp/a>->pa href="+code=grain" class="sref">grainp/a> = 1 << 12; o225p/a>                pa href="+code=dimm" class="sref">dimmp/a>->pa href="+code=mtype" class="sref">mtypep/a> = pa href="+code=mtype" class="sref">mtypep/a>; o226p/a>                pspa
 class="comment">/* I don't think 440BX ca
 tell you device type? FIXME? */p/spa
  o227p/a>                pa href="+code=dimm" class="sref">dimmp/a>->pa href="+code=dtype" class="sref">dtypep/a> = pa href="+code=DEV_UNKNOWN" class="sref">DEV_UNKNOWNp/a>; o228p/a>                p               pspa
 claMode rowg3n>2b to all rows on 440BX */p/spa
  o229p/a>                pa href="+code=dimm" class="sref">dimmp/a>->pa href="+code=edac_mode" class="sref">edac_modep/a> = pa href="+code=edac_mode" class="sref">edac_modep/a>; o230p/a>                pa href="+code=row_high_limit_last" class="sref">row_high_limit_lastp/a> = pa href="+code=row_high_limit" class="sref">row_high_limitp/a>; o231p/a>        } o232p/a>} o233p/a> o234p/a>static intopa href="+code=i82443bxgx_edacmc_probe1" class="sref">i82443bxgx_edacmc_probe1p/a>(structopa href="+code=pci_dev" class="sref">pci_devp/a> *pa href="+code=pdev" class="sref">pdevp/a>, intopa href="+code=dev_idx" class="sref">dev_idxp/a>) o235p/a>{ o236p/a>        structopa href="+code=mem_ctl_info" class="sref">mem_ctl_infop/a> *pa href="+code=mci" class="sref">mcip/a>; o237p/a>        structopa href="+code=edac_mc_layer" class="sref">edac_mc_layerp/a> pa href="+code=layers" class="sref">layersp/a>[2]; o238p/a>        pa href="+code=u8" class="sref">u8p/a> pa href="+code=dramc" class="sref">dramcp/a>; o239p/a>        pa href="+code=u32" class="sref">u32p/a> pa href="+code=nbxcfg" class="sref">nbxcfgp/a>,opa href="+code=ecc_mode" class="sref">ecc_modep/a>; o240p/a>        enum pa href="+code=mem_type" class="sref">mem_typep/a> pa href="+code=mtype" class="sref">mtypep/a>; o241p/a>        enum pa href="+code=edac_type" class="sref">edac_typep/a> pa href="+code=edac_mode" class="sref">edac_modep/a>; o242p/a> o243p/a>        pa href="+code=edac_dbg" class="sref">edac_dbgp/a>(0,opspa
 class="string">"MC:\n"o244p/a> o245p/a>        p               pspa
 claSomething rowreally hosed if PCI config space reads fromp/spa
  o246p/a>pspa
 class="comment">         * the MC aren't working.p/spa
  o247p/a>pspa
 class="comment">         */p/spa
  o248p/a>        if (pa href="+code=pci_read_config_dword" class="sref">pci_read_config_dwordp/a>(pa href="+code=pdev" class="sref">pdevp/a>,opa href="+code=I82443BXGX_NBXCFG" class="sref">I82443BXGX_NBXCFGp/a>,o&pa href="+code=nbxcfg" class="sref">nbxcfgp/a>)) o249p/a>                return -pa href="+code=EIO" class="sref">EIOp/a>; o250p/a> o251p/a>        pa href="+code=layers" class="sref">layersp/a>[0].pa href="+code=type" class="sref">typep/a> = pa href="+code=EDAC_MC_LAYER_CHIP_SELECT" class="sref">EDAC_MC_LAYER_CHIP_SELECTp/a>; o252p/a>        pa href="+code=layers" class="sref">layersp/a>[0].pa href="+code=size" class="sref">sizep/a> = pa href="+code=I82443BXGX_NR_CSROWS" class="sref">I82443BXGX_NR_CSROWSp/a>; o253p/a>        pa href="+code=layers" class="sref">layersp/a>[0].pa href="+code=is_viro_csrow" class="sref">is_viro_csrowp/a> = pa href="+code=true" class="sref">truep/a>; o254p/a>        pa href="+code=layers" class="sref">layersp/a>[1].pa href="+code=type" class="sref">typep/a> = pa href="+code=EDAC_MC_LAYER_CHANNEL" class="sref">EDAC_MC_LAYER_CHANNELp/a>; o255p/a>        pa href="+code=layers" class="sref">layersp/a>[1].pa href="+code=size" class="sref">sizep/a> = pa href="+code=I82443BXGX_NR_CHANS" class="sref">I82443BXGX_NR_CHANSp/a>; o256p/a>        pa href="+code=layers" class="sref">layersp/a>[1].pa href="+code=is_viro_csrow" class="sref">is_viro_csrowp/a> = pa href="+code=false" class="sref">falsep/a>; o257p/a>        pa href="+code=mci" class="sref">mcip/a> = pa href="+code=edac_mc_alloc" class="sref">edac_mc_allocp/a>(0,opa href="+code=ARRAY_SIZE" class="sref">ARRAY_SIZEp/a>(pa href="+code=layers" class="sref">layersp/a>),opa href="+code=layers" class="sref">layersp/a>, 0); o258p/a>        if (pa href="+code=mci" class="sref">mcip/a> == pa href="+code=NULL" class="sref">NULLp/a>) o259p/a>                return -pa href="+code=ENOMEM" class="sref">ENOMEMp/a>; o260p/a> o261p/a>        pa href="+code=edac_dbg" class="sref">edac_dbgp/a>(0,opspa
 class="string">"MC: mci = %p\n"mcip/a>); o262p/a>        pa href="+code=mci" class="sref">mcip/a>->pa href="+code=pdev" class="sref">pdevp/a> = &pa href="+code=pdev" class="sref">pdevp/a>->pa href="+code=dev" class="sref">devp/a>; o263p/a>        pa href="+code=mci" class="sref">mcip/a>->pa href="+code=mtype_cap" class="sref">mtype_capp/a> = pa href="+code=MEM_FLAG_EDO" class="sref">MEM_FLAG_EDOp/a> | pa href="+code=MEM_FLAG_SDR" class="sref">MEM_FLAG_SDRp/a> | pa href="+code=MEM_FLAG_RDR" class="sref">MEM_FLAG_RDRp/a>; o264p/a>        pa href="+code=mci" class="sref">mcip/a>->pa href="+code=edac_ctl_cap" class="sref">edac_ctl_capp/a> = pa href="+code=EDAC_FLAG_NONE" class="sref">EDAC_FLAG_NONEp/a> | pa href="+code=EDAC_FLAG_EC" class="sref">EDAC_FLAG_ECp/a> | pa href="+code=EDAC_FLAG_SECDED" class="sref">EDAC_FLAG_SECDEDp/a>; o265p/a>        pa href="+code=pci_read_config_byte" class="sref">pci_read_config_bytep/a>(pa href="+code=pdev" class="sref">pdevp/a>,opa href="+code=I82443BXGX_DRAMC" class="sref">I82443BXGX_DRAMCp/a>,o&pa href="+code=dramc" class="sref">dramcp/a>); o266p/a>        switch ((pa href="+code=dramc" class="sref">dramcp/a> >> pa href="+code=I82443BXGX_DRAMC_OFFSET_DT" class="sref">I82443BXGX_DRAMC_OFFSET_DTp/a>) &o(pa href="+code=BIT" class="sref">BITp/a>(0) | pa href="+code=BIT" class="sref">BITp/a>(1))) { o267p/a>        case pa href="+code=I82443BXGX_DRAMC_DRAM_IS_EDO" class="sref">I82443BXGX_DRAMC_DRAM_IS_EDOp/a>: o268p/a>                pa href="+code=mtype" class="sref">mtypep/a> = pa href="+code=MEM_EDO" class="sref">MEM_EDOp/a>; o269p/a>                break; o270p/a>        case pa href="+code=I82443BXGX_DRAMC_DRAM_IS_SDRAM" class="sref">I82443BXGX_DRAMC_DRAM_IS_SDRAMp/a>: o271p/a>                pa href="+code=mtype" class="sref">mtypep/a> = pa href="+code=MEM_SDR" class="sref">MEM_SDRp/a>; o272p/a>                break; o273p/a>        case pa href="+code=I82443BXGX_DRAMC_DRAM_IS_RSDRAM" class="sref">I82443BXGX_DRAMC_DRAM_IS_RSDRAMp/a>: o274p/a>                pa href="+code=mtype" class="sref">mtypep/a> = pa href="+code=MEM_RDR" class="sref">MEM_RDRp/a>; o275p/a>                break; o276p/a>        default: o277p/a>                pa href="+code=edac_dbg" class="sref">edac_dbgp/a>(0,opspa
 class="string">"Unknown/reserved DRAM type value in DRAMC register!\n"o278p/a>                pa href="+code=mtype" class="sref">mtypep/a> = -pa href="+code=MEM_UNKNOWN" class="sref">MEM_UNKNOWNp/a>; o279p/a>        } o280p/a> o281p/a>        if ((pa href="+code=mtype" class="sref">mtypep/a> == pa href="+code=MEM_SDR" class="sref">MEM_SDRp/a>) || (pa href="+code=mtype" class="sref">mtypep/a> == pa href="+code=MEM_RDR" class="sref">MEM_RDRp/a>)) o282p/a>                pa href="+code=mci" class="sref">mcip/a>->pa href="+code=edac_cap" class="sref">edac_capp/a> = pa href="+code=mci" class="sref">mcip/a>->pa href="+code=edac_ctl_cap" class="sref">edac_ctl_capp/a>; o283p/a>        else o284p/a>                pa href="+code=mci" class="sref">mcip/a>->pa href="+code=edac_cap" class="sref">edac_capp/a> = pa href="+code=EDAC_FLAG_NONE" class="sref">EDAC_FLAG_NONEp/a>; o285p/a> o286p/a>        pa href="+code=mci" class="sref">mcip/a>->pa href="+code=scrub_cap" class="sref">scrub_capp/a> = pa href="+code=SCRUB_FLAG_HW_SRC" class="sref">SCRUB_FLAG_HW_SRCp/a>; o287p/a>        pa href="+code=pci_read_config_dword" class="sref">pci_read_config_dwordp/a>(pa href="+code=pdev" class="sref">pdevp/a>,opa href="+code=I82443BXGX_NBXCFG" class="sref">I82443BXGX_NBXCFGp/a>,o&pa href="+code=nbxcfg" class="sref">nbxcfgp/a>); o288p/a>        pa href="+code=ecc_mode" class="sref">ecc_modep/a> = ((pa href="+code=nbxcfg" class="sref">nbxcfgp/a> >> pa href="+code=I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY" class="sref">I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITYp/a>) & o289p/a>                (pa href="+code=BIT" class="sref">BITp/a>(0) | pa href="+code=BIT" class="sref">BITp/a>(1))); o290p/a> o291p/a>        pa href="+code=mci" class="sref">mcip/a>->pa href="+code=scrub_mode" class="sref">scrub_modep/a> = (pa href="+code=ecc_mode" class="sref">ecc_modep/a> == pa href="+code=I82443BXGX_NBXCFG_INTEGRITY_SCRUB" class="sref">I82443BXGX_NBXCFG_INTEGRITY_SCRUBp/a>) o292p/a>                ? pa href="+code=SCRUB_HW_SRC" class="sref">SCRUB_HW_SRCp/a> : pa href="+code=SCRUB_NONE" class="sref">SCRUB_NONEp/a>; o293p/a> o294p/a>        switch (pa href="+code=ecc_mode" class="sref">ecc_modep/a>) { o295p/a>        case pa href="+code=I82443BXGX_NBXCFG_INTEGRITY_NONE" class="sref">I82443BXGX_NBXCFG_INTEGRITY_NONEp/a>: o296p/a>                pa href="+code=edac_mode" class="sref">edac_modep/a> = pa href="+code=EDAC_NONE" class="sref">EDAC_NONEp/a>; o297p/a>                break; o298p/a>        case pa href="+code=I82443BXGX_NBXCFG_INTEGRITY_EC" class="sref">I82443BXGX_NBXCFG_INTEGRITY_ECp/a>: o299p/a>                pa href="+code=edac_mode" class="sref">edac_modep/a> = pa href="+code=EDAC_EC" class="sref">EDAC_ECp/a>; o300p/a>                break; o301p/a>        case pa href="+code=I82443BXGX_NBXCFG_INTEGRITY_ECC" class="sref">I82443BXGX_NBXCFG_INTEGRITY_ECCp/a>: o302p/a>        case pa href="+code=I82443BXGX_NBXCFG_INTEGRITY_SCRUB" class="sref">I82443BXGX_NBXCFG_INTEGRITY_SCRUBp/a>: o303p/a>                pa href="+code=edac_mode" class="sref">edac_modep/a> = pa href="+code=EDAC_SECDED" class="sref">EDAC_SECDEDp/a>; o304p/a>                break; o305p/a>        default: o306p/a>                pa href="+code=edac_dbg" class="sref">edac_dbgp/a>(0,opspa
 class="string">"Unknown/reserved ECC state in NBXCFG register!\n"o307p/a>                pa href="+code=edac_mode" class="sref">edac_modep/a> = pa href="+code=EDAC_UNKNOWN" class="sref">EDAC_UNKNOWNp/a>; o308p/a>                break; o309p/a>        } o310p/a> o311p/a>        pa href="+code=i82443bxgx_inio_csrows" class="sref">i82443bxgx_inio_csrowsp/a>(pa href="+code=mci" class="sref">mcip/a>,opa href="+code=pdev" class="sref">pdevp/a>,opa href="+code=edac_mode" class="sref">edac_modep/a>,opa href="+code=mtype" class="sref">mtypep/a>); o312p/a> o313p/a>        p               pspa
 claMany BIOSes don't clear error flags on boot, so do thisp/spa
  o314p/a>pspa
 class="comment">         * here, or we get "phantom" errors occurring at module-loadp/spa
  o315p/a>pspa
 class="comment">         * time. */p/spa
  o316p/a>        pa href="+code=pci_write_bits32" class="sref">pci_write_bits32p/a>(pa href="+code=pdev" class="sref">pdevp/a>,opa href="+code=I82443BXGX_EAP" class="sref">I82443BXGX_EAPp/a>, o317p/a>                        (pa href="+code=I82443BXGX_EAP_OFFSET_SBE" class="sref">I82443BXGX_EAP_OFFSET_SBEp/a> | o318p/a>                                pa href="+code=I82443BXGX_EAP_OFFSET_MBE" class="sref">I82443BXGX_EAP_OFFSET_MBEp/a>), o319p/a>                        (pa href="+code=I82443BXGX_EAP_OFFSET_SBE" class="sref">I82443BXGX_EAP_OFFSET_SBEp/a> | o320p/a>                                pa href="+code=I82443BXGX_EAP_OFFSET_MBE" class="sref">I82443BXGX_EAP_OFFSET_MBEp/a>)); o321p/a> o322p/a>        pa href="+code=mci" class="sref">mcip/a>->pa href="+code=mod_nam"" class="sref">mod_nam"p/a> = pa href="+code=EDAC_MOD_STR" class="sref">EDAC_MOD_STRp/a>; o323p/a>        pa href="+code=mci" class="sref">mcip/a>->pa href="+code=mod_ver" class="sref">mod_verp/a> = pa href="+code=I82443_REVISION" class="sref">I82443_REVISIONp/a>; o324p/a>        pa href="+code=mci" class="sref">mcip/a>->pa href="+code=ctl_nam"" class="sref">ctl_nam"p/a> = pspa
 class="string">"I82443BXGX"o325p/a>        pa href="+code=mci" class="sref">mcip/a>->pa href="+code=dev_nam"" class="sref">dev_nam"p/a> = pa href="+code=pci_nam"" class="sref">pci_nam"p/a>(pa href="+code=pdev" class="sref">pdevp/a>); o326p/a>        pa href="+code=mci" class="sref">mcip/a>->pa href="+code=edac_check" class="sref">edac_checkp/a> = pa href="+code=i82443bxgx_edacmc_check" class="sref">i82443bxgx_edacmc_checkp/a>; o327p/a>        pa href="+code=mci" class="sref">mcip/a>->pa href="+code=ctl_page_to_phys" class="sref">ctl_page_to_physp/a> = pa href="+code=NULL" class="sref">NULLp/a>; o328p/a> o329p/a>        if (pa href="+code=edac_mc_add_mc" class="sref">edac_mc_add_mcp/a>(pa href="+code=mci" class="sref">mcip/a>)) { o330p/a>                pa href="+code=edac_dbg" class="sref">edac_dbgp/a>(3,opspa
 class="string">"failed edac_mc_add_mc()\n"o331p/a>                goto pa href="+code=fail" class="sref">failp/a>; o332p/a>        } o333p/a> o334p/a>        p               pspa
 claallocating generic PCI control info */p/spa
  o335p/a>        pa href="+code=i82443bxgx_pci" class="sref">i82443bxgx_pcip/a> = pa href="+code=edac_pci_create_generic_ctl" class="sref">edac_pci_create_generic_ctlp/a>(&pa href="+code=pdev" class="sref">pdevp/a>->pa href="+code=dev" class="sref">devp/a>,opa href="+code=EDAC_MOD_STR" class="sref">EDAC_MOD_STRp/a>); o336p/a>        if (!pa href="+code=i82443bxgx_pci" class="sref">i82443bxgx_pcip/a>) { o337p/a>                pa href="+code=printk" class="sref">printkp/a>(pa href="+code=KERN_WARNING" class="sref">KERN_WARNINGp/a> o338p/a>                        pspa
 class="string">"%s(): Unable to create PCI control\n"o339p/a>                        pa href="+code=__func__" class="sref">__func__p/a>); o340p/a>                pa href="+code=printk" class="sref">printkp/a>(pa href="+code=KERN_WARNING" class="sref">KERN_WARNINGp/a> o341p/a>                        pspa
 class="string">"%s(): PCI error report via EDAC not setup\n"o342p/a>                        pa href="+code=__func__" class="sref">__func__p/a>); o343p/a>        } o344p/a> o345p/a>        pa href="+code=edac_dbg" class="sref">edac_dbgp/a>(3,opspa
 class="string">"MC: success\n"o346p/a>        return 0; o347p/a> o348p/a>pa href="+code=fail" class="sref">failp/a>: o349p/a>        pa href="+code=edac_mc_free" class="sref">edac_mc_freep/a>(pa href="+code=mci" class="sref">mcip/a>); o350p/a>        return -pa href="+code=ENODEV" class="sref">ENODEVp/a>; o351p/a>} o352p/a> o353p/a>pa href="+code=EXPORT_SYMBOL_GPL" class="sref">EXPORT_SYMBOL_GPLp/a>(pa href="+code=i82443bxgx_edacmc_probe1" class="sref">i82443bxgx_edacmc_probe1p/a>); o354p/a> o355p/a>pspa
 class="comment">clareturns count (>= 0), or negative on error */p/spa
  o356p/a>static intopa href="+code=i82443bxgx_edacmc_inio_one" class="sref">i82443bxgx_edacmc_inio_onep/a>(structopa href="+code=pci_dev" class="sref">pci_devp/a> *pa href="+code=pdev" class="sref">pdevp/a>, o357p/a>                                      const structopa href="+code=pci_device_id" class="sref">pci_device_idp/a> *pa href="+code=ent" class="sref">entp/a>) o358p/a>{ o359p/a>        intopa href="+code=rc" class="sref">rcp/a>; o360p/a> o361p/a>        pa href="+code=edac_dbg" class="sref">edac_dbgp/a>(0,opspa
 class="string">"MC:\n"o362p/a> o363p/a>        p               pspa
 cladon't need to call pci_enable_device() */p/spa
  o364p/a>        pa href="+code=rc" class="sref">rcp/a> = pa href="+code=i82443bxgx_edacmc_probe1" class="sref">i82443bxgx_edacmc_probe1p/a>(pa href="+code=pdev" class="sref">pdevp/a>,opa href="+code=ent" class="sref">entp/a>->pa href="+code=driver_data" class="sref">driver_datap/a>); o365p/a> o366p/a>        if (pa href="+code=mci_pdev" class="sref">mci_pdevp/a> == pa href="+code=NULL" class="sref">NULLp/a>) o367p/a>                pa href="+code=mci_pdev" class="sref">mci_pdevp/a> =opa href="+code=pci_dev_get" class="sref">pci_dev_getp/a>(pa href="+code=pdev" class="sref">pdevp/a>); o368p/a> o369p/a>        return pa href="+code=rc" class="sref">rcp/a>; o370p/a>} o371p/a> o372p/a>static void pa href="+code=i82443bxgx_edacmc_remove_one" class="sref">i82443bxgx_edacmc_remove_onep/a>(structopa href="+code=pci_dev" class="sref">pci_devp/a> *pa href="+code=pdev" class="sref">pdevp/a>) o373p/a>{ o374p/a>        structopa href="+code=mem_ctl_info" class="sref">mem_ctl_infop/a> *pa href="+code=mci" class="sref">mcip/a>; o375p/a> o376p/a>        pa href="+code=edac_dbg" class="sref">edac_dbgp/a>(0,opspa
 class="string">"\n"o377p/a> o378p/a>        if (pa href="+code=i82443bxgx_pci" class="sref">i82443bxgx_pcip/a>) o379p/a>                pa href="+code=edac_pci_release_generic_ctl" class="sref">edac_pci_release_generic_ctlp/a>(pa href="+code=i82443bxgx_pci" class="sref">i82443bxgx_pcip/a>); o380p/a> o381p/a>        if ((pa href="+code=mci" class="sref">mcip/a> = pa href="+code=edac_mc_del_mc" class="sref">edac_mc_del_mcp/a>(&pa href="+code=pdev" class="sref">pdevp/a>->pa href="+code=dev" class="sref">devp/a>)) == pa href="+code=NULL" class="sref">NULLp/a>) o382p/a>                return; o383p/a> o384p/a>        pa href="+code=edac_mc_free" class="sref">edac_mc_freep/a>(pa href="+code=mci" class="sref">mcip/a>); o385p/a>} o386p/a> o387p/a>pa href="+code=EXPORT_SYMBOL_GPL" class="sref">EXPORT_SYMBOL_GPLp/a>(pa href="+code=i82443bxgx_edacmc_remove_one" class="sref">i82443bxgx_edacmc_remove_onep/a>); o388p/a> o389p/a>static pa href="+code=DEFINE_PCI_DEVICE_TABLE" class="sref">DEFINE_PCI_DEVICE_TABLEp/a>(pa href="+code=i82443bxgx_pci_tbl" class="sref">i82443bxgx_pci_tblp/a>) = { o390p/a>        {pa href="+code=PCI_DEVICE" class="sref">PCI_DEVICEp/a>(pa href="+code=PCI_VENDOR_ID_INTEL" class="sref">PCI_VENDOR_ID_INTELp/a>,opa href="+code=PCI_DEVICE_ID_INTEL_82443BX_0" class="sref">PCI_DEVICE_ID_INTEL_82443BX_0p/a>)}, o391p/a>        {pa href="+code=PCI_DEVICE" class="sref">PCI_DEVICEp/a>(pa href="+code=PCI_VENDOR_ID_INTEL" class="sref">PCI_VENDOR_ID_INTELp/a>,opa href="+code=PCI_DEVICE_ID_INTEL_82443BX_2" class="sref">PCI_DEVICE_ID_INTEL_82443BX_2p/a>)}, o392p/a>        {pa href="+code=PCI_DEVICE" class="sref">PCI_DEVICEp/a>(pa href="+code=PCI_VENDOR_ID_INTEL" class="sref">PCI_VENDOR_ID_INTELp/a>,opa href="+code=PCI_DEVICE_ID_INTEL_82443GX_0" class="sref">PCI_DEVICE_ID_INTEL_82443GX_0p/a>)}, o393p/a>        {pa href="+code=PCI_DEVICE" class="sref">PCI_DEVICEp/a>(pa href="+code=PCI_VENDOR_ID_INTEL" class="sref">PCI_VENDOR_ID_INTELp/a>,opa href="+code=PCI_DEVICE_ID_INTEL_82443GX_2" class="sref">PCI_DEVICE_ID_INTEL_82443GX_2p/a>)}, o394p/a>        {0,}                    p               pspa
 cla0 terminated list. */p/spa
  o395p/a>}; o396p/a> o397p/a>pa href="+code=MODULE_DEVICE_TABLE" class="sref">MODULE_DEVICE_TABLEp/a>(pa href="+code=pci" class="sref">pcip/a>,opa href="+code=i82443bxgx_pci_tbl" class="sref">i82443bxgx_pci_tblp/a>); o398p/a> o399p/a>static structopa href="+code=pci_driver" class="sref">pci_driverp/a> pa href="+code=i82443bxgx_edacmc_driver" class="sref">i82443bxgx_edacmc_driverp/a> = { o400p/a>        .pa href="+code=nam"" class="sref">nam"p/a> = pa href="+code=EDAC_MOD_STR" class="sref">EDAC_MOD_STRp/a>, o401p/a>        .pa href="+code=probe" class="sref">probep/a> = pa href="+code=i82443bxgx_edacmc_inio_one" class="sref">i82443bxgx_edacmc_inio_onep/a>, o402p/a>        .pa href="+code=remove" class="sref">removep/a> = pa href="+code=i82443bxgx_edacmc_remove_one" class="sref">i82443bxgx_edacmc_remove_onep/a>, o403p/a>        .pa href="+code=id_table" class="sref">id_tablep/a> = pa href="+code=i82443bxgx_pci_tbl" class="sref">i82443bxgx_pci_tblp/a>, o404p/a>}; o405p/a> o406p/a>static intopa href="+code=__inio" class="sref">__iniop/a> pa href="+code=i82443bxgx_edacmc_inio" class="sref">i82443bxgx_edacmc_iniop/a>(void) o407p/a>{ o408p/a>        intopa href="+code=pci_rc" class="sref">pci_rcp/a>; o409p/a>       p               pspa
 claEnsure that the OPSTATE rowset correctly for POLL or NMI */p/spa
  o410p/a>       pa href="+code=opstate_inio" class="sref">opstate_iniop/a>(); o411p/a> o412p/a>        pa href="+code=pci_rc" class="sref">pci_rcp/a> =opa href="+code=pci_register_driver" class="sref">pci_register_driverp/a>(&pa href="+code=i82443bxgx_edacmc_driver" class="sref">i82443bxgx_edacmc_driverp/a>); o413p/a>        if (pa href="+code=pci_rc" class="sref">pci_rcp/a> < 0) o414p/a>                goto pa href="+code=fail0" class="sref">fail0p/a>; o415p/a> o416p/a>        if (pa href="+code=mci_pdev" class="sref">mci_pdevp/a> == pa href="+code=NULL" class="sref">NULLp/a>) { o417p/a>                const structopa href="+code=pci_device_id" class="sref">pci_device_idp/a> *pa href="+code=id" class="sref">idp/a> = &pa href="+code=i82443bxgx_pci_tbl" class="sref">i82443bxgx_pci_tblp/a>[0]; o418p/a>                intopa href="+code=i" class="sref">ip/a> = 0; o419p/a>                pa href="+code=i82443bxgx_registered" class="sref">i82443bxgx_registeredp/a> = 0; o420p/a> o421p/a>                while (pa href="+code=mci_pdev" class="sref">mci_pdevp/a> == pa href="+code=NULL" class="sref">NULLp/a> &&opa href="+code=id" class="sref">idp/a>->pa href="+code=vendor" class="sref">vendorp/a> != 0) { o422p/a>                        pa href="+code=mci_pdev" class="sref">mci_pdevp/a> =opa href="+code=pci_get_device" class="sref">pci_get_devicep/a>(pa href="+code=id" class="sref">idp/a>->pa href="+code=vendor" class="sref">vendorp/a>, o423p/a>                                        pa href="+code=id" class="sref">idp/a>->pa href="+code=device" class="sref">devicep/a>,opa href="+code=NULL" class="sref">NULLp/a>); o424p/a>                        pa href="+code=i" class="sref">ip/a>++; o425p/a>                        pa href="+code=id" class="sref">idp/a> = &pa href="+code=i82443bxgx_pci_tbl" class="sref">i82443bxgx_pci_tblp/a>[pa href="+code=i" class="sref">ip/a>]; o426p/a>                } o427p/a>                if (!pa href="+code=mci_pdev" class="sref">mci_pdevp/a>) { o428p/a>                        pa href="+code=edac_dbg" class="sref">edac_dbgp/a>(0,opspa
 class="string">"i82443bxgx pci_get_device fail\n"o429p/a>                        pa href="+code=pci_rc" class="sref">pci_rcp/a> =o-pa href="+code=ENODEV" class="sref">ENODEVp/a>; o430p/a>                        goto pa href="+code=fail1" class="sref">fail1p/a>; o431p/a>                } o432p/a> o433p/a>                pa href="+code=pci_rc" class="sref">pci_rcp/a> =opa href="+code=i82443bxgx_edacmc_inio_one" class="sref">i82443bxgx_edacmc_inio_onep/a>(pa href="+code=mci_pdev" class="sref">mci_pdevp/a>,opa href="+code=i82443bxgx_pci_tbl" class="sref">i82443bxgx_pci_tblp/a>); o434p/a> o435p/a>                if (pa href="+code=pci_rc" class="sref">pci_rcp/a> < 0) { o436p/a>                        pa href="+code=edac_dbg" class="sref">edac_dbgp/a>(0,opspa
 class="string">"i82443bxgx inio fail\n"o437p/a>                        pa href="+code=pci_rc" class="sref">pci_rcp/a> =o-pa href="+code=ENODEV" class="sref">ENODEVp/a>; o438p/a>                        goto pa href="+code=fail1" class="sref">fail1p/a>; o439p/a>                } o440p/a>        } o441p/a> o442p/a>        return 0; o443p/a> o444p/a>pa href="+code=fail1" class="sref">fail1p/a>: o445p/a>        pa href="+code=pci_unregister_driver" class="sref">pci_unregister_driverp/a>(&pa href="+code=i82443bxgx_edacmc_driver" class="sref">i82443bxgx_edacmc_driverp/a>); o446p/a> o447p/a>pa href="+code=fail0" class="sref">fail0p/a>: o448p/a>        if (pa href="+code=mci_pdev" class="sref">mci_pdevp/a> != pa href="+code=NULL" class="sref">NULLp/a>) o449p/a>                pa href="+code=pci_dev_put" class="sref">pci_dev_putp/a>(pa href="+code=mci_pdev" class="sref">mci_pdevp/a>); o450p/a> o451p/a>        return pa href="+code=pci_rc" class="sref">pci_rcp/a>; o452p/a>} o453p/a> o454p/a>static void pa href="+code=__exio" class="sref">__exiop/a> pa href="+code=i82443bxgx_edacmc_exio" class="sref">i82443bxgx_edacmc_exiop/a>(void) o455p/a>{ o456p/a>        pa href="+code=pci_unregister_driver" class="sref">pci_unregister_driverp/a>(&pa href="+code=i82443bxgx_edacmc_driver" class="sref">i82443bxgx_edacmc_driverp/a>); o457p/a> o458p/a>        if (!pa href="+code=i82443bxgx_registered" class="sref">i82443bxgx_registeredp/a>) o459p/a>                pa href="+code=i82443bxgx_edacmc_remove_one" class="sref">i82443bxgx_edacmc_remove_onep/a>(pa href="+code=mci_pdev" class="sref">mci_pdevp/a>); o460p/a> o461p/a>        if (pa href="+code=mci_pdev" class="sref">mci_pdevp/a>) o462p/a>                pa href="+code=pci_dev_put" class="sref">pci_dev_putp/a>(pa href="+code=mci_pdev" class="sref">mci_pdevp/a>); o463p/a>} o464p/a> o465p/a>pa href="+code=module_inio" class="sref">module_iniop/a>(pa href="+code=i82443bxgx_edacmc_inio" class="sref">i82443bxgx_edacmc_iniop/a>); o466p/a>pa href="+code=module_exio" class="sref">module_exiop/a>(pa href="+code=i82443bxgx_edacmc_exio" class="sref">i82443bxgx_edacmc_exiop/a>); o467p/a> o468p/a>pa href="+code=MODULE_LICENSE" class="sref">MODULE_LICENSEp/a>(pspa
 class="string">"GPL"o469p/a>pa href="+code=MODULE_AUTHOR" class="sref">MODULE_AUTHORp/a>(pspa
 class="string">"Tim Small <tim@buttersideup.com> - WPAD"o470p/a>pa href="+code=MODULE_DESCRIPTION" class="sref">MODULE_DESCRIPTIONp/a>(pspa
 class="string">"EDAC MC support for Intel 82443BX/GX memory controllers"o471p/a> o472p/a>pa href="+code=module_param" class="sref">module_paramp/a>(pa href="+code=edac_op_state" class="sref">edac_op_statep/a>,oint, 0444); o473p/a>pa href="+code=MODULE_PARM_DESC" class="sref">MODULE_PARM_DESCp/a>(pa href="+code=edac_op_state" class="sref">edac_op_statep/a>,opspa
 class="string">"EDAC Error Reporting state: 0=Poll,1=NMI"o474p/a>
lxr.linux.no kindly hosted by Redpill Linpro ASp/a>,oprovider of Linux consulting and operations services since 1995.