linux/drivers/edac/amd8131_edac.c
<<
"v3.6<2/spa v3 6<2/formv3 6<2a "v3.6< href="../linux+v3.861i/drivers/edac/amd8131_edac.c">"v3.6<2img src="../.static/gfx/right.png" alt=">>">"v2/spa v3"v2spa class="lxr_search">"v3. ="+search" method="post" onsubmit="return do_search(this);">"v3.6<2input typopthidden" namoptnavtarget" "v3.6<2input typopttext" namoptsearch" idptsearch">"v3.6<2butt typoptsubmit">Search"v3.6"v2/spa v33.6< <2/divv33.6< <2form ac> ="ajax+*" method="post" onsubmit="return false;">"v2input typopthidden" namoptajax_lookup" idptajax_lookup" "3.6< <2/formv3"3.6< <2div class="headingbott m">3 2div idptfile_contents"v
< <12/a>2spa  class="comment">/*2/spa v3< <22/a>2spa  class="comment"> * amd8131_edac.c, AMD8131 hyportransport chip EDAC kernel module2/spa v3< <32/a>2spa  class="comment"> *2/spa v3< <42/a>2spa  class="comment"> * Copyright (c) 2008 Wind River Systems, Inc.2/spa v3< <52/a>2spa  class="comment"> *2/spa v3< <62/a>2spa  class="comment"> * Authors:.6< < <72/a>2spa  class="comment"> *              Benjamin Walsh <benjamin.walsh@windriver.com>2/spa v3< <82/a>2spa  class="comment"> *              Hu Yongqi <yongqi.hu@windriver.com>2/spa v3< <92/a>2spa  class="comment"> *2/spa v3< o0	 a>2spa  class="comment"> * This program is free software; you ca  redistribute it and/or modify2/spa v3< 112/a>2spa  class="comment"> * it under the terms of the GNU General Public License vers>
  2 as2/spa v3< 122/a>2spa  class="comment"> * published by the Free Software Founda>
  .2/spa v3< 132/a>2spa  class="comment"> *2/spa v3< 142/a>2spa  class="comment"> * This program is distributed in the hope that it will be useful,2/spa v3< 152/a>2spa  class="comment"> * but WITHOUT ANY WARRANTY; without even the implied warranty of2/spa v3< 162/a>2spa  class="comment"> * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.2/spa v3< 172/a>2spa  class="comment"> * See the GNU General Public License for more details.2/spa v3< 182/a>2spa  class="comment"> *2/spa v3< 192/a>2spa  class="comment"> * You should have received a copy of the GNU General Public License2/spa v3< 20	 a>2spa  class="comment"> * along with this program; if not, write to the Free Software2/spa v3< 212/a>2spa  class="comment"> * Founda>
  , Inc., 59 Temple Place, Suite 330, Bost  , MA 02111-1307 USA2/spa v3< 222/a>2spa  class="comment"> */2/spa v3< 232/a>3< 242/a>#include <linux/module.h2/a>>3< 252/a>#include <linux/init.h2/a>>3< 262/a>#include <linux/interrupt.h2/a>>3< 272/a>#include <linux/io.h2/a>>3< 282/a>#include <linux/bitops.h2/a>>3< 292/a>#include <linux/edac.h2/a>>3< 302/a>#include <linux/pci_ids.h2/a>>3< 312/a>3< 322/a>#include "edac_core.h2/a>"3< 332/a>#include "edac_module.h2/a>"3< 342/a>#include "amd8131_edac.h2/a>"3< 352/a>3< 362/a>#define<2a href="+code=AMD8131_EDAC_REVISION" class="sref">AMD8131_EDAC_REVISION2/a>< <2spa  class="string">" Ver: 1.0.0"< 372/a>#define<2a href="+code=AMD8131_EDAC_MOD_STR" class="sref">AMD8131_EDAC_MOD_STR2/a>< <<2spa  class="string">"amd8131_edac"< 382/a>3< 392/a>2spa  class="comment">/* Wrapper func>
  s for accessing PCI configura>
   space */2/spa v3< 402/a>static void<2a href="+code=edac_pci_read_dword" class="sref">edac_pci_read_dword2/a>(struct<2a href="+code=pci_dev" class="sref">pci_dev2/a><*2a href="+code=dev" class="sref">dev2/a>, int<2a href="+code=reg" class="sref">reg2/a>, 2a href="+code=u32" class="sref">u322/a><*2a href="+code=val32" class="sref">val322/a>)3< 412/a>{3< 422/a>< <<<<<ret2/a>;3< 432/a>3< 442/a>< <<<<<<2a href="+code=ret" class="sref">ret2/a> =<2a href="+code=pci_read_config_dword" class="sref">pci_read_config_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=reg" class="sref">reg2/a>, 2a href="+code=val32" class="sref">val322/a>);3< 452/a>< <<<<<ret2/a> != 0)3< 462/a>< <<<<<<< <<<<<<2a href="+code=printk" class="sref">printk2/a>(2a href="+code=KERN_ERR" class="sref">KERN_ERR2/a><2a href="+code=AMD8131_EDAC_MOD_STR" class="sref">AMD8131_EDAC_MOD_STR2/a>3< 472/a>< <<<<<<< <<<<<<< <<<<<<2spa  class="string">" PCI Access Read Error at 0x%x\n"reg2/a>);3< 482/a>}3< 492/a>3< 502/a>static void<2a href="+code=edac_pci_write_dword" class="sref">edac_pci_write_dword2/a>(struct<2a href="+code=pci_dev" class="sref">pci_dev2/a><*2a href="+code=dev" class="sref">dev2/a>, int<2a href="+code=reg" class="sref">reg2/a>, 2a href="+code=u32" class="sref">u322/a><2a href="+code=val32" class="sref">val322/a>)3< 512/a>{3< 522/a>< <<<<<ret2/a>;3< 532/a>3< 542/a>< <<<<<<2a href="+code=ret" class="sref">ret2/a> =<2a href="+code=pci_write_config_dword" class="sref">pci_write_config_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=reg" class="sref">reg2/a>, 2a href="+code=val32" class="sref">val322/a>);3< 552/a>< <<<<<ret2/a> != 0)3< 562/a>< <<<<<<< <<<<<<2a href="+code=printk" class="sref">printk2/a>(2a href="+code=KERN_ERR" class="sref">KERN_ERR2/a><2a href="+code=AMD8131_EDAC_MOD_STR" class="sref">AMD8131_EDAC_MOD_STR2/a>3< 572/a>< <<<<<<< <<<<<<< <<<<<<2spa  class="string">" PCI Access Write Error at 0x%x\n"reg2/a>);3< 582/a>}3< 592/a>3< 602/a>static char * const<2a href="+code=bridge_str" class="sref">bridge_str2/a>[] =<{3< 612/a>< <<<<<<[2a href="+code=NORTH_A" class="sref">NORTH_A2/a>] =<2spa  class="string">"NORTH A"< 622/a>< <<<<<<[2a href="+code=NORTH_B" class="sref">NORTH_B2/a>] =<2spa  class="string">"NORTH B"< 632/a>< <<<<<<[2a href="+code=SOUTH_A" class="sref">SOUTH_A2/a>] =<2spa  class="string">"SOUTH A"< 642/a>< <<<<<<[2a href="+code=SOUTH_B" class="sref">SOUTH_B2/a>] =<2spa  class="string">"SOUTH B"< 652/a>< <<<<<<[2a href="+code=NO_BRIDGE" class="sref">NO_BRIDGE2/a>] =<2spa  class="string">"NO BRIDGE"< 662/a>};3< 672/a>3< 682/a>2spa  class="comment">/* Support up to two AMD8131 chipsets on a platform */2/spa v3< 692/a>static struct<2a href="+code=amd8131_dev_info" class="sref">amd8131_dev_info2/a><2a href="+code=amd8131_devices" class="sref">amd8131_devices2/a>[] =<{3< 702/a>< <<<<<<{3< 712/a>< <<<<<<.2a href="+code=inst" class="sref">inst2/a> =<2a href="+code=NORTH_A" class="sref">NORTH_A2/a>,3< 722/a>< <<<<<<.2a href="+code=devfn" class="sref">devfn2/a> =<2a href="+code=DEVFN_PCIX_BRIDGE_NORTH_A" class="sref">DEVFN_PCIX_BRIDGE_NORTH_A2/a>,3< 732/a>< <<<<<<.2a href="+code=ctl_namo" class="sref">ctl_namo2/a> =<2spa  class="string">"AMD8131_PCIX_NORTH_A"< 742/a>< <<<<<<},3< 752/a>< <<<<<<{3< 762/a>< <<<<<<.2a href="+code=inst" class="sref">inst2/a> =<2a href="+code=NORTH_B" class="sref">NORTH_B2/a>,3< 772/a>< <<<<<<.2a href="+code=devfn" class="sref">devfn2/a> =<2a href="+code=DEVFN_PCIX_BRIDGE_NORTH_B" class="sref">DEVFN_PCIX_BRIDGE_NORTH_B2/a>,3< 782/a>< <<<<<<.2a href="+code=ctl_namo" class="sref">ctl_namo2/a> =<2spa  class="string">"AMD8131_PCIX_NORTH_B"< 792/a>< <<<<<<},3< 802/a>< <<<<<<{3< 812/a>< <<<<<<.2a href="+code=inst" class="sref">inst2/a> =<2a href="+code=SOUTH_A" class="sref">SOUTH_A2/a>,3< 822/a>< <<<<<<.2a href="+code=devfn" class="sref">devfn2/a> =<2a href="+code=DEVFN_PCIX_BRIDGE_SOUTH_A" class="sref">DEVFN_PCIX_BRIDGE_SOUTH_A2/a>,3< 832/a>< <<<<<<.2a href="+code=ctl_namo" class="sref">ctl_namo2/a> =<2spa  class="string">"AMD8131_PCIX_SOUTH_A"< 842/a>< <<<<<<},3< 852/a>< <<<<<<{3< 862/a>< <<<<<<.2a href="+code=inst" class="sref">inst2/a> =<2a href="+code=SOUTH_B" class="sref">SOUTH_B2/a>,3< 872/a>< <<<<<<.2a href="+code=devfn" class="sref">devfn2/a> =<2a href="+code=DEVFN_PCIX_BRIDGE_SOUTH_B" class="sref">DEVFN_PCIX_BRIDGE_SOUTH_B2/a>,3< 882/a>< <<<<<<.2a href="+code=ctl_namo" class="sref">ctl_namo2/a> =<2spa  class="string">"AMD8131_PCIX_SOUTH_B"< 892/a>< <<<<<<},3< 902/a>< <<<<<<{.2a href="+code=inst" class="sref">inst2/a> =<2a href="+code=NO_BRIDGE" class="sref">NO_BRIDGE2/a>,},3< 912/a>};3< 922/a>3< 932/a>static void<2a href="+code=amd8131_pcix_init" class="sref">amd8131_pcix_init2/a>(struct<2a href="+code=amd8131_dev_info" class="sref">amd8131_dev_info2/a><*2a href="+code=dev_info" class="sref">dev_info2/a>)3< 942/a>{3< 952/a>< <<<<<<2a href="+code=u32" class="sref">u322/a><2a href="+code=val32" class="sref">val322/a>;3< 962/a>< <<<<<pci_dev2/a><*2a href="+code=dev" class="sref">dev2/a> =<2a href="+code=dev_info" class="sref">dev_info2/a>->2a href="+code=dev" class="sref">dev2/a>;3< 972/a>3< 982/a>< <<<<<<2spa  class="comment">/* First clear error detec>
   flags */2/spa v3< 992/a>< <<<<<<2a href="+code=edac_pci_read_dword" class="sref">edac_pci_read_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_MEM_LIM" class="sref">REG_MEM_LIM2/a>, &2a href="+code=val32" class="sref">val322/a>);3<1002/a>< <<<<<val322/a> & 2a href="+code=MEM_LIMIT_MASK" class="sref">MEM_LIMIT_MASK2/a>)3<1012/a>< <<<<<<< <<<<<<2a href="+code=edac_pci_write_dword" class="sref">edac_pci_write_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_MEM_LIM" class="sref">REG_MEM_LIM2/a>, 2a href="+code=val32" class="sref">val322/a>);3<1022/a>3<1032/a>< <<<<<<2spa  class="comment">/* Clear Discard Timer Timedout flag */2/spa v3<1042/a>< <<<<<<2a href="+code=edac_pci_read_dword" class="sref">edac_pci_read_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_INT_CTLR" class="sref">REG_INT_CTLR2/a>, &2a href="+code=val32" class="sref">val322/a>);3<1052/a>< <<<<<val322/a> & 2a href="+code=INT_CTLR_DTS" class="sref">INT_CTLR_DTS2/a>)3<1062/a>< <<<<<<< <<<<<<2a href="+code=edac_pci_write_dword" class="sref">edac_pci_write_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_INT_CTLR" class="sref">REG_INT_CTLR2/a>, 2a href="+code=val32" class="sref">val322/a>);3<1072/a>3<1082/a>< <<<<<<2spa  class="comment">/* Clear CRC Error flag    link side A */2/spa v3<1092/a>< <<<<<<2a href="+code=edac_pci_read_dword" class="sref">edac_pci_read_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_LNK_CTRL_A" class="sref">REG_LNK_CTRL_A2/a>, &2a href="+code=val32" class="sref">val322/a>);3<1102/a>< <<<<<val322/a> & 2a href="+code=LNK_CTRL_CRCERR_A" class="sref">LNK_CTRL_CRCERR_A2/a>)3<1112/a>< <<<<<<< <<<<<<2a href="+code=edac_pci_write_dword" class="sref">edac_pci_write_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_LNK_CTRL_A" class="sref">REG_LNK_CTRL_A2/a>, 2a href="+code=val32" class="sref">val322/a>);3<1122/a>3<1132/a>< <<<<<<2spa  class="comment">/* Clear CRC Error flag    link side B */2/spa v3<1142/a>< <<<<<<2a href="+code=edac_pci_read_dword" class="sref">edac_pci_read_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_LNK_CTRL_B" class="sref">REG_LNK_CTRL_B2/a>, &2a href="+code=val32" class="sref">val322/a>);3<1152/a>< <<<<<val322/a> & 2a href="+code=LNK_CTRL_CRCERR_B" class="sref">LNK_CTRL_CRCERR_B2/a>)3<1162/a>< <<<<<<< <<<<<<2a href="+code=edac_pci_write_dword" class="sref">edac_pci_write_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_LNK_CTRL_B" class="sref">REG_LNK_CTRL_B2/a>, 2a href="+code=val32" class="sref">val322/a>);3<1172/a>3<1182/a>< <<<<<<2spa  class="comment">/*2/spa v3<1192/a>2spa  class="comment">         * Then enable all error detec>
  s.2/spa v3<120	 a>2spa  class="comment">         *2/spa v3<1212/a>2spa  class="comment">         * Setup Discard Timer Sync Flood Enable,2/spa v3<1222/a>2spa  class="comment">         * System Error Enable and Parity Error Enable.2/spa v3<1232/a>2spa  class="comment">         */2/spa v3<1242/a>< <<<<<<2a href="+code=edac_pci_read_dword" class="sref">edac_pci_read_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_INT_CTLR" class="sref">REG_INT_CTLR2/a>, &2a href="+code=val32" class="sref">val322/a>);3<1252/a>< <<<<<<2a href="+code=val32" class="sref">val322/a> |=<2a href="+code=INT_CTLR_PERR" class="sref">INT_CTLR_PERR2/a> |<2a href="+code=INT_CTLR_SERR" class="sref">INT_CTLR_SERR2/a> |<2a href="+code=INT_CTLR_DTSE" class="sref">INT_CTLR_DTSE2/a>;3<1262/a>< <<<<<<2a href="+code=edac_pci_write_dword" class="sref">edac_pci_write_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_INT_CTLR" class="sref">REG_INT_CTLR2/a>, 2a href="+code=val32" class="sref">val322/a>);3<1272/a>3<1282/a>< <<<<<<2spa  class="comment">/* Enable overall SERR Error detec>
   */2/spa v3<1292/a>< <<<<<<2a href="+code=edac_pci_read_dword" class="sref">edac_pci_read_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_STS_CMD" class="sref">REG_STS_CMD2/a>, &2a href="+code=val32" class="sref">val322/a>);3<1302/a>< <<<<<<2a href="+code=val32" class="sref">val322/a> |=<2a href="+code=STS_CMD_SERREN" class="sref">STS_CMD_SERREN2/a>;3<1312/a>< <<<<<<2a href="+code=edac_pci_write_dword" class="sref">edac_pci_write_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_STS_CMD" class="sref">REG_STS_CMD2/a>, 2a href="+code=val32" class="sref">val322/a>);3<1322/a>3<1332/a>< <<<<<<2spa  class="comment">/* Setup CRC Flood Enable for link side A */2/spa v3<1342/a>< <<<<<<2a href="+code=edac_pci_read_dword" class="sref">edac_pci_read_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_LNK_CTRL_A" class="sref">REG_LNK_CTRL_A2/a>, &2a href="+code=val32" class="sref">val322/a>);3<1352/a>< <<<<<<2a href="+code=val32" class="sref">val322/a> |=<2a href="+code=LNK_CTRL_CRCFEN" class="sref">LNK_CTRL_CRCFEN2/a>;3<1362/a>< <<<<<<2a href="+code=edac_pci_write_dword" class="sref">edac_pci_write_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_LNK_CTRL_A" class="sref">REG_LNK_CTRL_A2/a>, 2a href="+code=val32" class="sref">val322/a>);3<1372/a>3<1382/a>< <<<<<<2spa  class="comment">/* Setup CRC Flood Enable for link side B */2/spa v3<1392/a>< <<<<<<2a href="+code=edac_pci_read_dword" class="sref">edac_pci_read_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_LNK_CTRL_B" class="sref">REG_LNK_CTRL_B2/a>, &2a href="+code=val32" class="sref">val322/a>);3<1402/a>< <<<<<<2a href="+code=val32" class="sref">val322/a> |=<2a href="+code=LNK_CTRL_CRCFEN" class="sref">LNK_CTRL_CRCFEN2/a>;3<1412/a>< <<<<<<2a href="+code=edac_pci_write_dword" class="sref">edac_pci_write_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_LNK_CTRL_B" class="sref">REG_LNK_CTRL_B2/a>, 2a href="+code=val32" class="sref">val322/a>);3<1422/a>}3<1432/a>3<1442/a>static void<2a href="+code=amd8131_pcix_exit" class="sref">amd8131_pcix_exit2/a>(struct<2a href="+code=amd8131_dev_info" class="sref">amd8131_dev_info2/a><*2a href="+code=dev_info" class="sref">dev_info2/a>)3<1452/a>{3<1462/a>< <<<<<<2a href="+code=u32" class="sref">u322/a><2a href="+code=val32" class="sref">val322/a>;3<1472/a>< <<<<<pci_dev2/a><*2a href="+code=dev" class="sref">dev2/a> =<2a href="+code=dev_info" class="sref">dev_info2/a>->2a href="+code=dev" class="sref">dev2/a>;3<1482/a>3<1492/a>< <<<<<<2spa  class="comment">/* Disable SERR, PERR and DTSE Error detec>
   */2/spa v3<1502/a>< <<<<<<2a href="+code=edac_pci_read_dword" class="sref">edac_pci_read_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_INT_CTLR" class="sref">REG_INT_CTLR2/a>, &2a href="+code=val32" class="sref">val322/a>);3<1512/a>< <<<<<<2a href="+code=val32" class="sref">val322/a> &= ~(2a href="+code=INT_CTLR_PERR" class="sref">INT_CTLR_PERR2/a> |<2a href="+code=INT_CTLR_SERR" class="sref">INT_CTLR_SERR2/a> |<2a href="+code=INT_CTLR_DTSE" class="sref">INT_CTLR_DTSE2/a>);3<1522/a>< <<<<<<2a href="+code=edac_pci_write_dword" class="sref">edac_pci_write_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_INT_CTLR" class="sref">REG_INT_CTLR2/a>, 2a href="+code=val32" class="sref">val322/a>);3<1532/a>3<1542/a>< <<<<<<2spa  class="comment">/* Disable overall System Error detec>
   */2/spa v3<1552/a>< <<<<<<2a href="+code=edac_pci_read_dword" class="sref">edac_pci_read_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_STS_CMD" class="sref">REG_STS_CMD2/a>, &2a href="+code=val32" class="sref">val322/a>);3<1562/a>< <<<<<<2a href="+code=val32" class="sref">val322/a> &= ~2a href="+code=STS_CMD_SERREN" class="sref">STS_CMD_SERREN2/a>;3<1572/a>< <<<<<<2a href="+code=edac_pci_write_dword" class="sref">edac_pci_write_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_STS_CMD" class="sref">REG_STS_CMD2/a>, 2a href="+code=val32" class="sref">val322/a>);3<1582/a>3<1592/a>< <<<<<<2spa  class="comment">/* Disable CRC Sync Flood    link side A */2/spa v3<1602/a>< <<<<<<2a href="+code=edac_pci_read_dword" class="sref">edac_pci_read_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_LNK_CTRL_A" class="sref">REG_LNK_CTRL_A2/a>, &2a href="+code=val32" class="sref">val322/a>);3<1612/a>< <<<<<<2a href="+code=val32" class="sref">val322/a> &= ~2a href="+code=LNK_CTRL_CRCFEN" class="sref">LNK_CTRL_CRCFEN2/a>;3<1622/a>< <<<<<<2a href="+code=edac_pci_write_dword" class="sref">edac_pci_write_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_LNK_CTRL_A" class="sref">REG_LNK_CTRL_A2/a>, 2a href="+code=val32" class="sref">val322/a>);3<1632/a>3<1642/a>< <<<<<<2spa  class="comment">/* Disable CRC Sync Flood    link side B */2/spa v3<1652/a>< <<<<<<2a href="+code=edac_pci_read_dword" class="sref">edac_pci_read_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_LNK_CTRL_B" class="sref">REG_LNK_CTRL_B2/a>, &2a href="+code=val32" class="sref">val322/a>);3<1662/a>< <<<<<<2a href="+code=val32" class="sref">val322/a> &= ~2a href="+code=LNK_CTRL_CRCFEN" class="sref">LNK_CTRL_CRCFEN2/a>;3<1672/a>< <<<<<<2a href="+code=edac_pci_write_dword" class="sref">edac_pci_write_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_LNK_CTRL_B" class="sref">REG_LNK_CTRL_B2/a>, 2a href="+code=val32" class="sref">val322/a>);3<1682/a>}3<1692/a>3<1702/a>static void<2a href="+code=amd8131_pcix_check" class="sref">amd8131_pcix_check2/a>(struct<2a href="+code=edac_pci_ctl_info" class="sref">edac_pci_ctl_info2/a><*2a href="+code=edac_dev" class="sref">edac_dev2/a>)3<1712/a>{3<1722/a>< <<<<<amd8131_dev_info2/a><*2a href="+code=dev_info" class="sref">dev_info2/a> =<2a href="+code=edac_dev" class="sref">edac_dev2/a>->2a href="+code=pvt_info" class="sref">pvt_info2/a>;3<1732/a>< <<<<<pci_dev2/a><*2a href="+code=dev" class="sref">dev2/a> =<2a href="+code=dev_info" class="sref">dev_info2/a>->2a href="+code=dev" class="sref">dev2/a>;3<1742/a>< <<<<<<2a href="+code=u32" class="sref">u322/a><2a href="+code=val32" class="sref">val322/a>;3<1752/a>3<1762/a>< <<<<<<2spa  class="comment">/* Check PCI-X Bridge Memory Base-Limit Register for errors */2/spa v3<1772/a>< <<<<<<2a href="+code=edac_pci_read_dword" class="sref">edac_pci_read_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_MEM_LIM" class="sref">REG_MEM_LIM2/a>, &2a href="+code=val32" class="sref">val322/a>);3<1782/a>< <<<<<val322/a> & 2a href="+code=MEM_LIMIT_MASK" class="sref">MEM_LIMIT_MASK2/a>)<{3<1792/a>< <<<<<<< <<<<<<2a href="+code=printk" class="sref">printk2/a>(2a href="+code=KERN_INFO" class="sref">KERN_INFO2/a><2spa  class="string">"Error(s) in mem limit register "<1802/a>< <<<<<<< <<<<<<< <<<<<<2spa  class="string">"   %s bridge\n"dev_info2/a>->2a href="+code=ctl_namo" class="sref">ctl_namo2/a>);3<1812/a>< <<<<<<< <<<<<<2a href="+code=printk" class="sref">printk2/a>(2a href="+code=KERN_INFO" class="sref">KERN_INFO2/a><2spa  class="string">"DPE: %d, RSE: %d, RMA: %d\n"<1822/a>< <<<<<<< <<<<<<< <<<<<<2spa  class="string">"RTA: %d, STA: %d, MDPE: %d\n"<1832/a>< <<<<<<< <<<<<<< <<<<<<2a href="+code=val32" class="sref">val322/a> & 2a href="+code=MEM_LIMIT_DPE" class="sref">MEM_LIMIT_DPE2/a>,3<1842/a>< <<<<<<< <<<<<<< <<<<<<2a href="+code=val32" class="sref">val322/a> & 2a href="+code=MEM_LIMIT_RSE" class="sref">MEM_LIMIT_RSE2/a>,3<1852/a>< <<<<<<< <<<<<<< <<<<<<2a href="+code=val32" class="sref">val322/a> & 2a href="+code=MEM_LIMIT_RMA" class="sref">MEM_LIMIT_RMA2/a>,3<1862/a>< <<<<<<< <<<<<<< <<<<<<2a href="+code=val32" class="sref">val322/a> & 2a href="+code=MEM_LIMIT_RTA" class="sref">MEM_LIMIT_RTA2/a>,3<1872/a>< <<<<<<< <<<<<<< <<<<<<2a href="+code=val32" class="sref">val322/a> & 2a href="+code=MEM_LIMIT_STA" class="sref">MEM_LIMIT_STA2/a>,3<1882/a>< <<<<<<< <<<<<<< <<<<<<2a href="+code=val32" class="sref">val322/a> & 2a href="+code=MEM_LIMIT_MDPE" class="sref">MEM_LIMIT_MDPE2/a>);3<1892/a>3<1902/a>< <<<<<<< <<<<<<2a href="+code=val32" class="sref">val322/a> |=<2a href="+code=MEM_LIMIT_MASK" class="sref">MEM_LIMIT_MASK2/a>;3<1912/a>< <<<<<<< <<<<<<2a href="+code=edac_pci_write_dword" class="sref">edac_pci_write_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_MEM_LIM" class="sref">REG_MEM_LIM2/a>, 2a href="+code=val32" class="sref">val322/a>);3<1922/a>3<1932/a>< <<<<<<< <<<<<<2a href="+code=edac_pci_handle_npo" class="sref">edac_pci_handle_npo2/a>(2a href="+code=edac_dev" class="sref">edac_dev2/a>, 2a href="+code=edac_dev" class="sref">edac_dev2/a>->2a href="+code=ctl_namo" class="sref">ctl_namo2/a>);3<1942/a>< <<<<<<}3<1952/a>3<1962/a>< <<<<<<2spa  class="comment">/* Check if Discard Timer timed out */2/spa v3<1972/a>< <<<<<<2a href="+code=edac_pci_read_dword" class="sref">edac_pci_read_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_INT_CTLR" class="sref">REG_INT_CTLR2/a>, &2a href="+code=val32" class="sref">val322/a>);3<1982/a>< <<<<<val322/a> & 2a href="+code=INT_CTLR_DTS" class="sref">INT_CTLR_DTS2/a>)<{3<1992/a>< <<<<<<< <<<<<<2a href="+code=printk" class="sref">printk2/a>(2a href="+code=KERN_INFO" class="sref">KERN_INFO2/a><2spa  class="string">"Error(s) in interrupt and control register "<2002/a>< <<<<<<< <<<<<<< <<<<<<2spa  class="string">"   %s bridge\n"dev_info2/a>->2a href="+code=ctl_namo" class="sref">ctl_namo2/a>);3<2012/a>< <<<<<<< <<<<<<2a href="+code=printk" class="sref">printk2/a>(2a href="+code=KERN_INFO" class="sref">KERN_INFO2/a><2spa  class="string">"DTS: %d\n"val322/a> & 2a href="+code=INT_CTLR_DTS" class="sref">INT_CTLR_DTS2/a>);3<2022/a>3<2032/a>< <<<<<<< <<<<<<2a href="+code=val32" class="sref">val322/a> |=<2a href="+code=INT_CTLR_DTS" class="sref">INT_CTLR_DTS2/a>;3<2042/a>< <<<<<<< <<<<<<2a href="+code=edac_pci_write_dword" class="sref">edac_pci_write_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_INT_CTLR" class="sref">REG_INT_CTLR2/a>, 2a href="+code=val32" class="sref">val322/a>);3<2052/a>3<2062/a>< <<<<<<< <<<<<<2a href="+code=edac_pci_handle_npo" class="sref">edac_pci_handle_npo2/a>(2a href="+code=edac_dev" class="sref">edac_dev2/a>, 2a href="+code=edac_dev" class="sref">edac_dev2/a>->2a href="+code=ctl_namo" class="sref">ctl_namo2/a>);3<2072/a>< <<<<<<}3<2082/a>3<2092/a>< <<<<<<2spa  class="comment">/* Check if CRC error happens    link side A */2/spa v3<2102/a>< <<<<<<2a href="+code=edac_pci_read_dword" class="sref">edac_pci_read_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_LNK_CTRL_A" class="sref">REG_LNK_CTRL_A2/a>, &2a href="+code=val32" class="sref">val322/a>);3<2112/a>< <<<<<val322/a> & 2a href="+code=LNK_CTRL_CRCERR_A" class="sref">LNK_CTRL_CRCERR_A2/a>)<{3<2122/a>< <<<<<<< <<<<<<2a href="+code=printk" class="sref">printk2/a>(2a href="+code=KERN_INFO" class="sref">KERN_INFO2/a><2spa  class="string">"Error(s) in link conf and control register "<2132/a>< <<<<<<< <<<<<<< <<<<<<2spa  class="string">"   %s bridge\n"dev_info2/a>->2a href="+code=ctl_namo" class="sref">ctl_namo2/a>);3<2142/a>< <<<<<<< <<<<<<2a href="+code=printk" class="sref">printk2/a>(2a href="+code=KERN_INFO" class="sref">KERN_INFO2/a><2spa  class="string">"CRCERR: %d\n"val322/a> & 2a href="+code=LNK_CTRL_CRCERR_A" class="sref">LNK_CTRL_CRCERR_A2/a>);3<2152/a>3<2162/a>< <<<<<<< <<<<<<2a href="+code=val32" class="sref">val322/a> |=<2a href="+code=LNK_CTRL_CRCERR_A" class="sref">LNK_CTRL_CRCERR_A2/a>;3<2172/a>< <<<<<<< <<<<<<2a href="+code=edac_pci_write_dword" class="sref">edac_pci_write_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_LNK_CTRL_A" class="sref">REG_LNK_CTRL_A2/a>, 2a href="+code=val32" class="sref">val322/a>);3<2182/a>3<2192/a>< <<<<<<< <<<<<<2a href="+code=edac_pci_handle_npo" class="sref">edac_pci_handle_npo2/a>(2a href="+code=edac_dev" class="sref">edac_dev2/a>, 2a href="+code=edac_dev" class="sref">edac_dev2/a>->2a href="+code=ctl_namo" class="sref">ctl_namo2/a>);3<2202/a>< <<<<<<}3<2212/a>3<2222/a>< <<<<<<2spa  class="comment">/* Check if CRC error happens    link side B */2/spa v3<2232/a>< <<<<<<2a href="+code=edac_pci_read_dword" class="sref">edac_pci_read_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_LNK_CTRL_B" class="sref">REG_LNK_CTRL_B2/a>, &2a href="+code=val32" class="sref">val322/a>);3<2242/a>< <<<<<val322/a> & 2a href="+code=LNK_CTRL_CRCERR_B" class="sref">LNK_CTRL_CRCERR_B2/a>)<{3<2252/a>< <<<<<<< <<<<<<2a href="+code=printk" class="sref">printk2/a>(2a href="+code=KERN_INFO" class="sref">KERN_INFO2/a><2spa  class="string">"Error(s) in link conf and control register "<2262/a>< <<<<<<< <<<<<<< <<<<<<2spa  class="string">"   %s bridge\n"dev_info2/a>->2a href="+code=ctl_namo" class="sref">ctl_namo2/a>);3<2272/a>< <<<<<<< <<<<<<2a href="+code=printk" class="sref">printk2/a>(2a href="+code=KERN_INFO" class="sref">KERN_INFO2/a><2spa  class="string">"CRCERR: %d\n"val322/a> & 2a href="+code=LNK_CTRL_CRCERR_B" class="sref">LNK_CTRL_CRCERR_B2/a>);3<2282/a>3<2292/a>< <<<<<<< <<<<<<2a href="+code=val32" class="sref">val322/a> |=<2a href="+code=LNK_CTRL_CRCERR_B" class="sref">LNK_CTRL_CRCERR_B2/a>;3<2302/a>< <<<<<<< <<<<<<2a href="+code=edac_pci_write_dword" class="sref">edac_pci_write_dword2/a>(2a href="+code=dev" class="sref">dev2/a>, 2a href="+code=REG_LNK_CTRL_B" class="sref">REG_LNK_CTRL_B2/a>, 2a href="+code=val32" class="sref">val322/a>);3<2312/a>3<2322/a>< <<<<<<< <<<<<<2a href="+code=edac_pci_handle_npo" class="sref">edac_pci_handle_npo2/a>(2a href="+code=edac_dev" class="sref">edac_dev2/a>, 2a href="+code=edac_dev" class="sref">edac_dev2/a>->2a href="+code=ctl_namo" class="sref">ctl_namo2/a>);3<2332/a>< <<<<<<}3<2342/a>}3<2352/a>3<2362/a>static struct<2a href="+code=amd8131_info" class="sref">amd8131_info2/a> 2a href="+code=amd8131_chipset" class="sref">amd8131_chipset2/a> =<{3<2372/a>< <<<<<<.2a href="+code=err_dev" class="sref">err_dev2/a> =<2a href="+code=PCI_DEVICE_ID_AMD_8131_APIC" class="sref">PCI_DEVICE_ID_AMD_8131_APIC2/a>,3<2382/a>< <<<<<<.2a href="+code=devices" class="sref">devices2/a> =<2a href="+code=amd8131_devices" class="sref">amd8131_devices2/a>,3<2392/a>< <<<<<<.2a href="+code=init" class="sref">init2/a> =<2a href="+code=amd8131_pcix_init" class="sref">amd8131_pcix_init2/a>,3<2402/a>< <<<<<<.2a href="+code=exit" class="sref">exit2/a> =<2a href="+code=amd8131_pcix_exit" class="sref">amd8131_pcix_exit2/a>,3<2412/a>< <<<<<<.2a href="+code=check" class="sref">check2/a> =<2a href="+code=amd8131_pcix_check" class="sref">amd8131_pcix_check2/a>,3<2422/a>};3<2432/a>3<2442/a>2spa  class="comment">/*2/spa v3<2452/a>2spa  class="comment"> * There are 4 PCIX Bridges    ATCA-6101 that share the samo PCI Device ID,2/spa v3<2462/a>2spa  class="comment"> * so amd8131_probe() would be called by kernel 4 times, with different2/spa v3<2472/a>2spa  class="comment"> * address  f pci_dev for each  f them each time.2/spa v3<2482/a>2spa  class="comment"> */2/spa v3<2492/a>static int<2a href="+code=amd8131_probe" class="sref">amd8131_probe2/a>(struct<2a href="+code=pci_dev" class="sref">pci_dev2/a><*2a href="+code=dev" class="sref">dev2/a>, constpci_device_id2/a><*2a href="+code=id" class="sref">id2/a>)3<2502/a>{3<2512/a>< <<<<<amd8131_dev_info2/a><*2a href="+code=dev_info" class="sref">dev_info2/a>;3<2522/a>3<2532/a>< <<<<<dev_info2/a> =<2a href="+code=amd8131_chipset" class="sref">amd8131_chipset2/a>.2a href="+code=devices" class="sref">devices2/a>; 2a href="+code=dev_info" class="sref">dev_info2/a>->2a href="+code=inst" class="sref">inst2/a> !=<2a href="+code=NO_BRIDGE" class="sref">NO_BRIDGE2/a>;3<2542/a>< <<<<<<< <<<<<<2a href="+code=dev_info" class="sref">dev_info2/a>++)3<2552/a>< <<<<<<< <<<<<dev_info2/a>->2a href="+code=devfn" class="sref">devfn2/a> ==<2a href="+code=dev" class="sref">dev2/a>->2a href="+code=devfn" class="sref">devfn2/a>)3<2562/a>< <<<<<<< <<<<<<< <<<<<<2572/a>3<2582/a>< <<<<<dev_info2/a>->2a href="+code=inst" class="sref">inst2/a> ==<2a href="+code=NO_BRIDGE" class="sref">NO_BRIDGE2/a>)<2spa  class="comment">/* should never happen */2/spa v3<2592/a>< <<<<<<< <<<<<ENODEV2/a>;3<2602/a>3<2612/a>< <<<<<<2spa  class="comment">/*2/spa v3<2622/a>2spa  class="comment">         * We can't call pci_get_device() as we are used to do because2/spa v3<2632/a>2spa  class="comment">         * there are 4  f them but pci_dev_get() instead.2/spa v3<2642/a>2spa  class="comment">         */2/spa v3<2652/a>< <<<<<<2a href="+code=dev_info" class="sref">dev_info2/a>->2a href="+code=dev" class="sref">dev2/a> =<2a href="+code=pci_dev_get" class="sref">pci_dev_get2/a>(2a href="+code=dev" class="sref">dev2/a>);3<2662/a>3<2672/a>< <<<<<pci_enable_device2/a>(2a href="+code=dev_info" class="sref">dev_info2/a>->2a href="+code=dev" class="sref">dev2/a>))<{3<2682/a>< <<<<<<< <<<<<<2a href="+code=pci_dev_put" class="sref">pci_dev_put2/a>(2a href="+code=dev_info" class="sref">dev_info2/a>->2a href="+code=dev" class="sref">dev2/a>);3<2692/a>< <<<<<<< <<<<<<2a href="+code=printk" class="sref">printk2/a>(2a href="+code=KERN_ERR" class="sref">KERN_ERR2/a><2spa  class="string">"failed to enable:"<2702/a>< <<<<<<< <<<<<<< <<<<<<2spa  class="string">"vendor %x, device %x, devfn %x, namo %s\n"<2712/a>< <<<<<<< <<<<<<< <<<<<<2a href="+code=PCI_VENDOR_ID_AMD" class="sref">PCI_VENDOR_ID_AMD2/a>, 2a href="+code=amd8131_chipset" class="sref">amd8131_chipset2/a>.2a href="+code=err_dev" class="sref">err_dev2/a>,3<2722/a>< <<<<<<< <<<<<<< <<<<<<2a href="+code=dev_info" class="sref">dev_info2/a>->2a href="+code=devfn" class="sref">devfn2/a>, 2a href="+code=dev_info" class="sref">dev_info2/a>->2a href="+code=ctl_namo" class="sref">ctl_namo2/a>);3<2732/a>< <<<<<<< <<<<<ENODEV2/a>;3<2742/a>< <<<<<<}3<2752/a>3<2762/a>< <<<<<<2spa  class="comment">/*<2772/a>2spa  class="comment">         * we do not allocate extra private structure for<2782/a>2spa  class="comment">         * edac_pci_ctl_info, but make use  f existing<2792/a>2spa  class="comment">         * one instead.2/spa v3<2802/a>2spa  class="comment">         */2/spa v3<2812/a>< <<<<<<2a href="+code=dev_info" class="sref">dev_info2/a>->2a href="+code=edac_idx" class="sref">edac_idx2/a> =<2a href="+code=edac_pci_alloc_index" class="sref">edac_pci_alloc_index2/a>();3<2822/a>< <<<<<<2a href="+code=dev_info" class="sref">dev_info2/a>->2a href="+code=edac_dev" class="sref">edac_dev2/a> =<2a href="+code=edac_pci_alloc_ctl_info" class="sref">edac_pci_alloc_ctl_info2/a>(0, 2a href="+code=dev_info" class="sref">dev_info2/a>->2a href="+code=ctl_namo" class="sref">ctl_namo2/a>);3<2832/a>< <<<<<dev_info2/a>->2a href="+code=edac_dev" class="sref">edac_dev2/a>)3<2842/a>< <<<<<<< <<<<<ENOMEM2/a>;3<2852/a>3<2862/a>< <<<<<<2a href="+code=dev_info" class="sref">dev_info2/a>->2a href="+code=edac_dev" class="sref">edac_dev2/a>->2a href="+code=pvt_info" class="sref">pvt_info2/a> =<2a href="+code=dev_info" class="sref">dev_info2/a>;3<2872/a>< <<<<<<2a href="+code=dev_info" class="sref">dev_info2/a>->2a href="+code=edac_dev" class="sref">edac_dev2/a>->2a href="+code=dev" class="sref">dev2/a> =<&2a href="+code=dev_info" class="sref">dev_info2/a>->2a href="+code=dev" class="sref">dev2/a>->2a href="+code=dev" class="sref">dev2/a>;3<2882/a>< <<<<<<2a href="+code=dev_info" class="sref">dev_info2/a>->2a href="+code=edac_dev" class="sref">edac_dev2/a>->2a href="+code=mod_namo" class="sref">mod_namo2/a> =<2a href="+code=AMD8131_EDDC_MOrxode=ctl_namo" class="sref">ctl_namo2/a>);3<2072/a>< <<<<<<}3<1e=dev_info" class="sref">dev_info2/an3e3L209" class<2072/a>< <<<<<<}3<1e=dev_info" class="sref">dev_info2/an3e3L209" clfo" class="sref"4edac.c#L207" idptL207" class="line" namLcdev_info2/an3e3L209" clfv/edac/amd8131_edac.c#L253 f21 =<2a href="+code=AMD8131_EDDC_MOrxof="+code=edac_pc 3sref">dev_info2/an3e3L209" clfo" class=19>2a href="+code=dev" class="sref">dev2/a> =<&2a href="+code=dev_info" class="sref">dev_info2/a>->2a hrefo2/an3e3L209" clfv/hrefo2/ao2/an3e3L209" clfo" class=o2/an3e3L209" clfv/hrefo2/ao2/a(">dev2/a>->2a href="+code=dev" class="sref">dev2/a>;3<2882/a>< <<<<<<edac_pci_wri2e_dwo29>< <<<<<<< <<<<<<2a href="+code=edac_pci_handidptL193"2class="line" namoptL193"2<193229" class="sref_info" class="sref"lass=op_de=p 2a href="+code=edac_op_de=p ld never happen */2/spa7"><2OPSTATE_POLL" namoptL285"><2"><2OPSTATE_POLL>< <<<<<<< <<<<<edac_pci_hand2e_npo2/a>(2a href="+code=edac_dev" class="s>2a href="+code=dev" class="sref">dev2/a> =<&2a href="+code=dev_info" class="sref">dev_info2/a>->2a lass=L242" class="line" nlass=L242"ces" class="sref">devices2/a>; 2a href="+code=dev_info" class="sref">dev_info2/a>->2x_check2/a>,3<19<<<; 2a href="+code=dev_info" class="sref">dev_info2/a>->2nit2/a>,3dev_infor timed out */2/spa v3; 2a href="+code=dev_info" class="sref">dev_info2/a>->2nit2/a>,3dev_infof">edac_pci_read_dword2/2>(2a 29>< <<<<<val3222a> & 2a href="+code=2NT_CT2R_DTS" class="sref">INT_CTLR_DTS2ef="+code=dd/a>->2a href="+codeef="+code=dd/a>->">dev2/a>);3ef">ctl_namo2/a>);3();3p2intk2/a>(2a href="+code=2ERN_I2FO" class="sref">KERN_INFO2/a><2spa  class="string">"Error(s) in interrupt and contr href="drivers/edac/amd8131_edac.c#L270" idptL270" class="line" nef="+code=dd/a>->()classmoptL271"><2712/a>< <<<<<<< <<<<<<< <<<<<<2a href="+code=PCI_3>"  3%s bridge\n"<2832/a>< <<<<<p3intk2/a>(2a href="+code=3ERN_I3FO" class="sref">KERN_INFO2/a><2spa  ef="+codefree">dev_info2/a>->2a href="+codefree">dev_inf">dev2/a>);3<<<<<p3ilass="line" namoptL193"3<203230="+code=devfn" class=c#L274" idptL274" class="line" namoptL274"><2742/a>< <<<<<<}3va3322/a> |=<2a href="+code3INT_C30"><2342/a>}3edac_pci_wri3e_dwo30"><19<<<dev2/a> =<2a href=class="string">"CRCERR: %d\n"val322/a> & 2a href="=dd97">nec.c#L271#L24moptL2"><2262/a>< <<<<<<< <<<<<<< <<<<<<2spa  class="string3le_npo" c3ass="sref">edac_pci_hand3e_npo3/a>(2a href="+code=edacspa v,3<2712/a>< <<<<<<< <<<<<<< <<<<<<2a href="+code=PCI_3.c#L208" 3dptL208" class="line" na3optL230O" class="sref">KERN_INFO2/a><2spa  s="sref">amd8131_chipset2/a>.2a href="+code=err_dev" class="sref">err_dev2/a>,3<2722/a>< <<<<<<< <<<<<<< <<<<<<2a href="+code=dev_3idptL209"3class="line" namoptL209"3<209230e=dev_info" class="sref">dev_info2/aef="+code=dev_info" class="sref">dev_info2/a>->2a href="+code=ctl_namo" class="sref">ctl_namo2/a>);3<2732/a>< <<<<<<< <<<<<edac_pci_read_dword2/3>(2a 3ref="+code=devc#L274"0<<<<<< <<<<<val3223a> & 2a href="+code=3NK_CT3L_CRCEa href="drivers/edac/amd8131_edac.c#L2353="sref">p3intk2/a>(2a href="+code=3ERN_I31>< <<<<<"  3%s bridge\n", constpci_device_id2/a><*2a href="+code<<<<<< <<<<<p3intk2/a>(2a href="+code=3ERN_I3FO" cl<<<<<< <<<<<<2a href="+code=pci_dev_put"3idptL216"3class="line" namoptL216"3<216231ss="sref">devev_info" class="sref">dev_info2/a>;3<2522/a>3va3322/a> |=<2a href="+code3LNK_C31>< <<<<<edac_pci_wri3e_dwo3d2/a>(2a href=lass="sref">amd8131_chipset2/a>.2a href="+code=devices" class="sref">devices2/a>; 2a href="+code=dev_info" class="sref">dev_info2/a>->2a href="+code=inst" class="sref">inst2/a> !=<2a href="+code=NO_BRIDGE" class="sref">NO_BRIDGE2/a>;3<2542/a>< <<<<<<< <<<<<<2a href="+code=dev_info" cl3idptL219"3class="line" namoptL219"3<219231e=dev_info" class="sref">dev_info2/aef="+code=dev_info" class="sref">de <<<<<<< <<<<<edac_pci_hand3e_npo3/a>(2a href="+code=edaf">devfn2/a> ==<2a href="+code=dev" class="sref">dev2/a>->2a href="+code=devfn" class="sref">devfn2/a>)3<2562/a>< <<<<<<< <<<<<<< <<<<<3< <<<<<<2spa  class="comment">/* Check if C3C error h3ppens    link side B */23spa v32" class="sref_info" class="sref"ef="+code=NO_BRIDGE" class="sref">NO_BRIDGE2/a>;3<2592/a>< <<<<<<< <<<<<edac_pci_read_dword2/3>(2a 32rs/edac/amd8131_edac.c#L274 href="drivers/edac/amd8131_edac.c#L258"3i"sref">p3a> & 2a href="+code=3NK_CT32"><19<<<p3intk2/a>(2a href="+code=3ERN_I325 class="sref_info" class="sref""drivers/edac/amd8131_edac.c#L269" idptL269" class="linhref="+code=dev_info" class="sref"><<<<<<<< <<<<<<2a href="+code=pci_dev_put"3>"  3%s bridge\n"->2a href="+codeef="+codedel/a>->">dev2/a>);3dptL288" class="line" namoptL288"><2882/a>< <<<<<<p3intk2/a>(2a href="+code=3ERN_I3FO" class="sref">KERN_INFO2/a><2spa  ef="+codefree">dev_info2/a>->2a href="+codefree">dev_inf">dev2/a>);3<<<<<va3322/a> |=<2a href="+code3LNK_C32>< <<<<<<< <<<<<<2a href="+code=val32" class3e_dword" 3lass="sref">edac_pci_wri3e_dwo3d2/a>(2a href=_info" class="sref"ces2/a>; 2a href="+code=dev_info" class="sref">dev_info2/a>->2xit2/a>,3KERN_INFO2/a><2spa  ces2/a>; 2a href="+code=dev_info" class="sref">dev_info2/a>->2xit2/a>,3edac_pci_hand3e_npo33>< <<<<<>->2a href="+code=dev" class="sref">dev2/a>);3<2692/a>< <<<<<<< <<<<<<2a href="+code=printk" clas3 idptL2353 class="line" namoptL2353><2353/a>3static struct<2a href="+code=amd8131_info" 3lass="sre3">amd8131_info2/a> 2a hr3f="+c3de=amd8131_chd" class="sref">id2/a>)3<2spa  ces2/a>;ef="+codetblf="+code=dev_info" clasef="+codetblptL2[]< <<<<<<.2a href="+code=err_dev" class="sre3">err_dev3/a> =<2a href="+code=PCI3DEVIC3_ID_AMD_8131_A<<<<<.2a href="+code=err_dev" class="sre3"dptL229"3/a> =<2a href="+code=amd3131_d33" class="sref">edac_dev2/a>-href="+c_ine" namoptL274">dev2/a>);3.2a r_dev" clv" cld8131_)<<<<<< <<<<<<< <<<<<<2a href="+code=dev_3nit2/a> =32a href="+code=amd8131_p3ix_in3t" class="sref">amd8131_pcix_isubac/amdchipset2/a>.2a subac/amdces" class="sref">devihrefANY_I_chipset2/a>.2a hrefANY_I_>< <<<<<<< <<<<<<< <<<<<<2a href="+code=dev_3xit2/a> =32a href="+code=amd8131_p3ix_ex3t" class="sref">amd8131_pcix_esuba>->2a href="+codesuba>->ces" class="sref">devihrefANY_I_chipset2/a>.2a hrefANY_I_>< <<<<<<< <<<<<<< <<<<<<2a href="+code=dev_3xdptL232"3=<2a href="+code=amd81313pcix_3heck" class="sref">amd8131_pcixhrefine" namoptL273"" naces" cl0<<<<<< <<<<<<< <<<<<<2a href="+code=dev_3xe_npo" c3" class="line" namoptL243"><24342ck" class="sref">amd8131_pcixhref_maseck2/a>,3amd8131_pci<<< <<_datanamoptL269"><269<< <<_dataces" cl0<<<<<< <<<<<<< <<<<<<2a href="+code=dev_3xidptL2353amd8131_edac.c#L245" idp3L245"34"><2752/a>3<2082/a>3KERN_s="sref"L259" idptL259" class="ltL270 is NULL-terminated592/a>< <<<<<<< <<<<<(struct32a hr3f="+coef">amd8131_pciMODULEine" namTABLef="drivers/edacMODULEine" namTABLe">dev2/a>);3err_dev2/a>,ef="+codetblf="+code=dev_info" clasef="+codetblptL2<<<<<<< <<<<<<2a href="+code=printk" clas3 idptL2513 class="line" namoptL2513><25135>< <<<<<<2spa  class="comment">/*2/spa v3amd8131_dev_info23a><*23 href=8131_chipset" class="sref">amac.c#lass=edac/amd8131_edac.c#lass=ptL25INFO2/a><2spa  ces2/a>;ef="+#lass=edac/amd8131_edces2/a>;ef="+#lass=ces" cl<<<<<.2a href="+code=err_dev" class="sre3idptL253"3class="line" namoptL253"3<2532352ck" class="sref">amd8131_pcis="line" namoptL273f="drivers/edac/amd8131_edac.c#L207" idptL207" class="line" namoptL207"><2072/a>< <<<<<<<<< <<<<<<< <<<<<<2a href="+code=dev_3"sref">de3_info2/a> =<2a href="+co3e=amd353ck" class="sref">amd8131_pcia><*2a href="+code=ds="sref">/edac/amd8131_edac.c#L242" ><*2a href="+code=dev" class="sref"><<<<<< <<<<<<< <<<<<<2a href="+code=dev_3"idptL2353dev_info2/a>++)3amd8131_pciremov2a href="+code=dremov2: &#/edac/amd8131_edac.c#L242"remov2a href="+code=dev" clasremov2: &#<<<<<< <<<<<<< <<<<<<2a href="+code=dev_3"dptL236"3ef">dev_info2/a>->2a 3ref="3code=devfn" clv_info2/a>->2nd_tL270rivers/edac/amd8d_tL270: &#/edac/amd8131_edac.c#L242"ef="+codetblf="+code=dev_info" clasef="+codetblptL2<<<<<< <<<<<<< <<<<<<2a href="+code=dev_3"ould be 3md8131_edac.c#L257" idpt3257" 3lass="a href="drivers/edac/amd8131_edac.c#L244"3idptL258"3class="line" namoptL258"3<25823a>< <<<<<dev3info2/a>->2a href="+c3de=in3t" clade=pci_dev" class="sref">p_240" class="line" na_402/a>< dev"+co<<<<<< <<<<<<< <<<<<ENODEV2/a>;3"CRCERR: %d\n"val322/a> & 2a href="4moptL2"7">< ef="+c"><2262/a>< <<2Re" SION"sref">val322/a> & 2a href="71"><2712/a>< <<<<<<<< <<<<<<2a href="+code=printk" clas3ref="driv3rs/edac/amd8131_edac.c#L362" i36" class="sref">edac_idx2/a> class="string">"CRCERR: %d\n"val322/a> & 2a href="\t(c) 2a 8 Wind R="+c"Systems, Inc.71"><2712/a>< <<<<<<<< <<<<<<2a href="+code=printk" clas3rdptL253"3_get_device() as we are 3sed t36>< <<<<<edac_idx2/a> ef="+op_de=p 2a href="+code=edac_op_de=p ld nevr happen */2/spa7"><2OPSTATE_POLL" namoptL285"><2"><2OPSTATE_POLL>< <<<<<<< <<<<<<2a href="+code=printk" clas3rdptL236"32/a>->2a href="+code=3ev" c36>static struct<2a href="+code=amd8131_info" 3idptL267"3class="line" namoptL267"3<267236 href="+code=c#L274"class="sref">amac.cmoptL226c#lass=edac/amd8131_edac.cmoptL226c#lass=: ">dev2/a>->2a hreces2/a>;ef="+#lass=edac/amd8131_edces2/a>;ef="+#lass=ces"<<<<<<< <<<<<<2a href="+code=printk" clas3rdptL258"3ref">pci_enable_device2/3>(2a 3ref="+ href="drivers/edac/amd8131_edac.c#L236"3class="sr3f">pci_dev_put2/a>(2a hr3f="+c36>< <<<<<<< <<<<<<2a href="+code=val32" class3="sref">p3intk2/a>(2a href="+code=3ERN_E36="+code=pci_"+code=edac_pci_ctl__241" class="line" na_412/a>< dev"+co<<<<<< <<<<<<< <<<<<PCI_VEN3OR_ID37" class="sref">edac_idx2/a> cc.cunmoptL226c#lass=edac/amd8131_edac.cunmoptL226c#lass=: ">dev2/a>->2a hreces2/a>;ef="+#lass=edac/amd8131_edces2/a>;ef="+#lass=ces"<<<<<<< <<<<<<2a href="+code=printk" clas3nfo" clas3="sref">dev_info2/a>->32a hr3f="+co href="drivers/edac/amd8131_edac.c#L236"3V" class=3sref">ENODEV2/a>;3/*2/spa v3<272/a>->2a hremde<<<<<<< <<<<<<2a href="+code=printk" clas3ndptL236"3class="line" namoptL276"3<27623a>< <<2/a>->2a hremde<<<<<<< <<<<<<2a href="+code=printk" clas3ndptL267"3rs/edac/amd8131_edac.c#L377" i37>< <<<<<amd8131_pciMODULEiLICENSef="drivers/edacMODULEiLICENSe: %>val322/a> & 2a href="GPL"><2712/a>< <<<<<<<< <<<<<<2a href="+code=printk" clas3l_info, b3t make use  f existingamd8131_pciMODULEiAUTHO" class="line" nMODULEiAUTHO": %>val322/a> & 2a href="Cao Q; 2tao <q; 2tao.cao@wind<2a h.59"dptL71"><2712/a>< <<<<<<<< <<<<<<2a href="+code=printk" clas3.2/spa v33a href="drivers/edac/amd3131_e37="+coef">amd8131_pciMODULEineSCRIPTION class="line" nMODULEineSCRIPTION: %>val322/a> & 2a href="4moptL2"HyperTransportmopt-X Tunss="7">< class="m<2712/a>< <<<<<<<< <<<<<<2a href="+code=printk" clas3href="dri3ers/edac/amd8131_edac.c#3281" 3dptL281/pre81/div>


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