linux/drivers/dma/mv_xor.h
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   1/*
   2 * Copyright (C) 2007, 2008, Marvell International Ltd.
   3 *
   4 * This program is free software; you can redistribute it and/or modify
   5 * it under the terms and conditions of the GNU General Public License,
   6 * version 2, as published by the Free Software Foundation.
   7 *
   8 * This program is distributed in the hope it will be useful, but WITHOUT
   9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  11 * for more details.
  12 *
  13 * You should have received a copy of the GNU General Public License
  14 * along with this program; if not, write to the Free Software Foundation,
  15 * Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  16 */
  17
  18#ifndef MV_XOR_H
  19#define MV_XOR_H
  20
  21#include <linux/types.h>
  22#include <linux/io.h>
  23#include <linux/dmaengine.h>
  24#include <linux/interrupt.h>
  25
  26#define USE_TIMER
  27#define MV_XOR_POOL_SIZE                PAGE_SIZE
  28#define MV_XOR_SLOT_SIZE                64
  29#define MV_XOR_THRESHOLD                1
  30#define MV_XOR_MAX_CHANNELS             2
  31
  32#define XOR_OPERATION_MODE_XOR          0
  33#define XOR_OPERATION_MODE_MEMCPY       2
  34#define XOR_OPERATION_MODE_MEMSET       4
  35
  36#define XOR_CURR_DESC(chan)     (chan->mmr_base + 0x210 + (chan->idx * 4))
  37#define XOR_NEXT_DESC(chan)     (chan->mmr_base + 0x200 + (chan->idx * 4))
  38#define XOR_BYTE_COUNT(chan)    (chan->mmr_base + 0x220 + (chan->idx * 4))
  39#define XOR_DEST_POINTER(chan)  (chan->mmr_base + 0x2B0 + (chan->idx * 4))
  40#define XOR_BLOCK_SIZE(chan)    (chan->mmr_base + 0x2C0 + (chan->idx * 4))
  41#define XOR_INIT_VALUE_LOW(chan)        (chan->mmr_base + 0x2E0)
  42#define XOR_INIT_VALUE_HIGH(chan)       (chan->mmr_base + 0x2E4)
  43
  44#define XOR_CONFIG(chan)        (chan->mmr_base + 0x10 + (chan->idx * 4))
  45#define XOR_ACTIVATION(chan)    (chan->mmr_base + 0x20 + (chan->idx * 4))
  46#define XOR_INTR_CAUSE(chan)    (chan->mmr_base + 0x30)
  47#define XOR_INTR_MASK(chan)     (chan->mmr_base + 0x40)
  48#define XOR_ERROR_CAUSE(chan)   (chan->mmr_base + 0x50)
  49#define XOR_ERROR_ADDR(chan)    (chan->mmr_base + 0x60)
  50#define XOR_INTR_MASK_VALUE     0x3F5
  51
  52#define WINDOW_BASE(w)          (0x250 + ((w) << 2))
  53#define WINDOW_SIZE(w)          (0x270 + ((w) << 2))
  54#define WINDOW_REMAP_HIGH(w)    (0x290 + ((w) << 2))
  55#define WINDOW_BAR_ENABLE(chan) (0x240 + ((chan) << 2))
  56#define WINDOW_OVERRIDE_CTRL(chan)      (0x2A0 + ((chan) << 2))
  57
  58struct mv_xor_device {
  59        void __iomem         *xor_base;
  60        void __iomem         *xor_high_base;
  61        struct clk           *clk;
  62        struct mv_xor_chan   *channels[MV_XOR_MAX_CHANNELS];
  63};
  64
  65/**
  66 * struct mv_xor_chan - internal representation of a XOR channel
  67 * @pending: allows batching of hardware operations
  68 * @lock: serializes enqueue/dequeue operations to the descriptors pool
  69 * @mmr_base: memory mapped register base
  70 * @idx: the index of the xor channel
  71 * @chain: device chain view of the descriptors
  72 * @completed_slots: slots completed by HW but still need to be acked
  73 * @device: parent device
  74 * @common: common dmaengine channel object members
  75 * @last_used: place holder for allocation to continue from where it left off
  76 * @all_slots: complete domain of slots usable by the channel
  77 * @slots_allocated: records the actual size of the descriptor slot pool
  78 * @irq_tasklet: bottom half where mv_xor_slot_cleanup runs
  79 */
  80struct mv_xor_chan {
  81        int                     pending;
  82        spinlock_t              lock; /* protects the descriptor slot pool */
  83        void __iomem            *mmr_base;
  84        unsigned int            idx;
  85        int                     irq;
  86        enum dma_transaction_type       current_type;
  87        struct list_head        chain;
  88        struct list_head        completed_slots;
  89        dma_addr_t              dma_desc_pool;
  90        void                    *dma_desc_pool_virt;
  91        size_t                  pool_size;
  92        struct dma_device       dmadev;
  93        struct dma_chan         dmachan;
  94        struct mv_xor_desc_slot *last_used;
  95        struct list_head        all_slots;
  96        int                     slots_allocated;
  97        struct tasklet_struct   irq_tasklet;
  98#ifdef USE_TIMER
  99        unsigned long           cleanup_time;
 100        u32                     current_on_last_cleanup;
 101#endif
 102};
 103
 104/**
 105 * struct mv_xor_desc_slot - software descriptor
 106 * @slot_node: node on the mv_xor_chan.all_slots list
 107 * @chain_node: node on the mv_xor_chan.chain list
 108 * @completed_node: node on the mv_xor_chan.completed_slots list
 109 * @hw_desc: virtual address of the hardware descriptor chain
 110 * @phys: hardware address of the hardware descriptor chain
 111 * @group_head: first operation in a transaction
 112 * @slot_cnt: total slots used in an transaction (group of operations)
 113 * @slots_per_op: number of slots per operation
 114 * @idx: pool index
 115 * @unmap_src_cnt: number of xor sources
 116 * @unmap_len: transaction bytecount
 117 * @tx_list: list of slots that make up a multi-descriptor transaction
 118 * @async_tx: support for the async_tx api
 119 * @xor_check_result: result of zero sum
 120 * @crc32_result: result crc calculation
 121 */
 122struct mv_xor_desc_slot {
 123        struct list_head        slot_node;
 124        struct list_head        chain_node;
 125        struct list_head        completed_node;
 126        enum dma_transaction_type       type;
 127        void                    *hw_desc;
 128        struct mv_xor_desc_slot *group_head;
 129        u16                     slot_cnt;
 130        u16                     slots_per_op;
 131        u16                     idx;
 132        u16                     unmap_src_cnt;
 133        u32                     value;
 134        size_t                  unmap_len;
 135        struct list_head        tx_list;
 136        struct dma_async_tx_descriptor  async_tx;
 137        union {
 138                u32             *xor_check_result;
 139                u32             *crc32_result;
 140        };
 141#ifdef USE_TIMER
 142        unsigned long           arrival_time;
 143        struct timer_list       timeout;
 144#endif
 145};
 146
 147/* This structure describes XOR descriptor size 64bytes */
 148struct mv_xor_desc {
 149        u32 status;             /* descriptor execution status */
 150        u32 crc32_result;       /* result of CRC-32 calculation */
 151        u32 desc_command;       /* type of operation to be carried out */
 152        u32 phy_next_desc;      /* next descriptor address pointer */
 153        u32 byte_count;         /* size of src/dst blocks in bytes */
 154        u32 phy_dest_addr;      /* destination block address */
 155        u32 phy_src_addr[8];    /* source block addresses */
 156        u32 reserved0;
 157        u32 reserved1;
 158};
 159
 160#define to_mv_sw_desc(addr_hw_desc)             \
 161        container_of(addr_hw_desc, struct mv_xor_desc_slot, hw_desc)
 162
 163#define mv_hw_desc_slot_idx(hw_desc, idx)       \
 164        ((void *)(((unsigned long)hw_desc) + ((idx) << 5)))
 165
 166#define MV_XOR_MIN_BYTE_COUNT   (128)
 167#define XOR_MAX_BYTE_COUNT      ((16 * 1024 * 1024) - 1)
 168#define MV_XOR_MAX_BYTE_COUNT   XOR_MAX_BYTE_COUNT
 169
 170
 171#endif
 172
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