linux/drivers/atm/iphase.h
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   1/******************************************************************************
   2             Device driver for Interphase ATM PCI adapter cards 
   3                    Author: Peter Wang  <pwang@iphase.com>            
   4                   Interphase Corporation  <www.iphase.com>           
   5                               Version: 1.0   
   6               iphase.h:  This is the header file for iphase.c. 
   7*******************************************************************************
   8      
   9      This software may be used and distributed according to the terms
  10      of the GNU General Public License (GPL), incorporated herein by reference.
  11      Drivers based on this skeleton fall under the GPL and must retain
  12      the authorship (implicit copyright) notice.
  13
  14      This program is distributed in the hope that it will be useful, but
  15      WITHOUT ANY WARRANTY; without even the implied warranty of
  16      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  17      General Public License for more details.
  18      
  19      Modified from an incomplete driver for Interphase 5575 1KVC 1M card which 
  20      was originally written by Monalisa Agrawal at UNH. Now this driver 
  21      supports a variety of varients of Interphase ATM PCI (i)Chip adapter 
  22      card family (See www.iphase.com/products/ClassSheet.cfm?ClassID=ATM) 
  23      in terms of PHY type, the size of control memory and the size of 
  24      packet memory. The followings are the change log and history:
  25     
  26          Bugfix the Mona's UBR driver.
  27          Modify the basic memory allocation and dma logic.
  28          Port the driver to the latest kernel from 2.0.46.
  29          Complete the ABR logic of the driver, and added the ABR work-
  30              around for the hardware anormalies.
  31          Add the CBR support.
  32          Add the flow control logic to the driver to allow rate-limit VC.
  33          Add 4K VC support to the board with 512K control memory.
  34          Add the support of all the variants of the Interphase ATM PCI 
  35          (i)Chip adapter cards including x575 (155M OC3 and UTP155), x525
  36          (25M UTP25) and x531 (DS3 and E3).
  37          Add SMP support.
  38
  39      Support and updates available at: ftp://ftp.iphase.com/pub/atm
  40
  41*******************************************************************************/
  42  
  43#ifndef IPHASE_H  
  44#define IPHASE_H  
  45
  46
  47/************************ IADBG DEFINE *********************************/
  48/* IADebugFlag Bit Map */ 
  49#define IF_IADBG_INIT_ADAPTER   0x00000001        // init adapter info
  50#define IF_IADBG_TX             0x00000002        // debug TX
  51#define IF_IADBG_RX             0x00000004        // debug RX
  52#define IF_IADBG_QUERY_INFO     0x00000008        // debug Request call
  53#define IF_IADBG_SHUTDOWN       0x00000010        // debug shutdown event
  54#define IF_IADBG_INTR           0x00000020        // debug interrupt DPC
  55#define IF_IADBG_TXPKT          0x00000040        // debug TX PKT
  56#define IF_IADBG_RXPKT          0x00000080        // debug RX PKT
  57#define IF_IADBG_ERR            0x00000100        // debug system error
  58#define IF_IADBG_EVENT          0x00000200        // debug event
  59#define IF_IADBG_DIS_INTR       0x00001000        // debug disable interrupt
  60#define IF_IADBG_EN_INTR        0x00002000        // debug enable interrupt
  61#define IF_IADBG_LOUD           0x00004000        // debugging info
  62#define IF_IADBG_VERY_LOUD      0x00008000        // excessive debugging info
  63#define IF_IADBG_CBR            0x00100000        //
  64#define IF_IADBG_UBR            0x00200000        //
  65#define IF_IADBG_ABR            0x00400000        //
  66#define IF_IADBG_DESC           0x01000000        //
  67#define IF_IADBG_SUNI_STAT      0x02000000        // suni statistics
  68#define IF_IADBG_RESET          0x04000000        
  69
  70#define IF_IADBG(f) if (IADebugFlag & (f))
  71
  72#ifdef  CONFIG_ATM_IA_DEBUG   /* Debug build */
  73
  74#define IF_LOUD(A) IF_IADBG(IF_IADBG_LOUD) { A }
  75#define IF_ERR(A) IF_IADBG(IF_IADBG_ERR) { A }
  76#define IF_VERY_LOUD(A) IF_IADBG( IF_IADBG_VERY_LOUD ) { A }
  77
  78#define IF_INIT_ADAPTER(A) IF_IADBG( IF_IADBG_INIT_ADAPTER ) { A }
  79#define IF_INIT(A) IF_IADBG( IF_IADBG_INIT_ADAPTER ) { A }
  80#define IF_SUNI_STAT(A) IF_IADBG( IF_IADBG_SUNI_STAT ) { A }
  81#define IF_QUERY_INFO(A) IF_IADBG( IF_IADBG_QUERY_INFO ) { A }
  82#define IF_COPY_OVER(A) IF_IADBG( IF_IADBG_COPY_OVER ) { A }
  83
  84#define IF_INTR(A) IF_IADBG( IF_IADBG_INTR ) { A }
  85#define IF_DIS_INTR(A) IF_IADBG( IF_IADBG_DIS_INTR ) { A }
  86#define IF_EN_INTR(A) IF_IADBG( IF_IADBG_EN_INTR ) { A }
  87
  88#define IF_TX(A) IF_IADBG( IF_IADBG_TX ) { A }
  89#define IF_RX(A) IF_IADBG( IF_IADBG_RX ) { A }
  90#define IF_TXPKT(A) IF_IADBG( IF_IADBG_TXPKT ) { A }
  91#define IF_RXPKT(A) IF_IADBG( IF_IADBG_RXPKT ) { A }
  92
  93#define IF_SHUTDOWN(A) IF_IADBG(IF_IADBG_SHUTDOWN) { A }
  94#define IF_CBR(A) IF_IADBG( IF_IADBG_CBR ) { A }
  95#define IF_UBR(A) IF_IADBG( IF_IADBG_UBR ) { A }
  96#define IF_ABR(A) IF_IADBG( IF_IADBG_ABR ) { A }
  97#define IF_EVENT(A) IF_IADBG( IF_IADBG_EVENT) { A }
  98
  99#else /* free build */
 100#define IF_LOUD(A)
 101#define IF_VERY_LOUD(A)
 102#define IF_INIT_ADAPTER(A)
 103#define IF_INIT(A)
 104#define IF_SUNI_STAT(A)
 105#define IF_PVC_CHKPKT(A)
 106#define IF_QUERY_INFO(A)
 107#define IF_COPY_OVER(A)
 108#define IF_HANG(A)
 109#define IF_INTR(A)
 110#define IF_DIS_INTR(A)
 111#define IF_EN_INTR(A)
 112#define IF_TX(A)
 113#define IF_RX(A)
 114#define IF_TXDEBUG(A)
 115#define IF_VC(A)
 116#define IF_ERR(A) 
 117#define IF_CBR(A)
 118#define IF_UBR(A)
 119#define IF_ABR(A)
 120#define IF_SHUTDOWN(A)
 121#define DbgPrint(A)
 122#define IF_EVENT(A)
 123#define IF_TXPKT(A) 
 124#define IF_RXPKT(A)
 125#endif /* CONFIG_ATM_IA_DEBUG */ 
 126
 127#define isprint(a) ((a >=' ')&&(a <= '~'))  
 128#define ATM_DESC(skb) (skb->protocol)
 129#define IA_SKB_STATE(skb) (skb->protocol)
 130#define IA_DLED   1
 131#define IA_TX_DONE 2
 132
 133/* iadbg defines */
 134#define IA_CMD   0x7749
 135typedef struct {
 136        int cmd;
 137        int sub_cmd;
 138        int len;
 139        u32 maddr;
 140        int status;
 141        void __user *buf;
 142} IA_CMDBUF, *PIA_CMDBUF;
 143
 144/* cmds */
 145#define MEMDUMP                 0x01
 146
 147/* sub_cmds */
 148#define MEMDUMP_SEGREG          0x2
 149#define MEMDUMP_DEV             0x1
 150#define MEMDUMP_REASSREG        0x3
 151#define MEMDUMP_FFL             0x4
 152#define READ_REG                0x5
 153#define WAKE_DBG_WAIT           0x6
 154
 155/************************ IADBG DEFINE END ***************************/
 156
 157#define Boolean(x)      ((x) ? 1 : 0)
 158#define NR_VCI 1024             /* number of VCIs */  
 159#define NR_VCI_LD 10            /* log2(NR_VCI) */  
 160#define NR_VCI_4K 4096          /* number of VCIs */  
 161#define NR_VCI_4K_LD 12         /* log2(NR_VCI) */  
 162#define MEM_VALID 0xfffffff0    /* mask base address with this */  
 163  
 164#ifndef PCI_VENDOR_ID_IPHASE  
 165#define PCI_VENDOR_ID_IPHASE 0x107e  
 166#endif  
 167#ifndef PCI_DEVICE_ID_IPHASE_5575  
 168#define PCI_DEVICE_ID_IPHASE_5575 0x0008  
 169#endif  
 170#define DEV_LABEL       "ia"  
 171#define PCR     207692  
 172#define ICR     100000  
 173#define MCR     0  
 174#define TBE     1000  
 175#define FRTT    1  
 176#define RIF     2                 
 177#define RDF     4  
 178#define NRMCODE 5       /* 0 - 7 */  
 179#define TRMCODE 3       /* 0 - 7 */  
 180#define CDFCODE 6  
 181#define ATDFCODE 2      /* 0 - 15 */  
 182  
 183/*---------------------- Packet/Cell Memory ------------------------*/  
 184#define TX_PACKET_RAM   0x00000 /* start of Trasnmit Packet memory - 0 */  
 185#define DFL_TX_BUF_SZ   10240   /* 10 K buffers */  
 186#define DFL_TX_BUFFERS     50   /* number of packet buffers for Tx   
 187                                        - descriptor 0 unused */  
 188#define REASS_RAM_SIZE 0x10000  /* for 64K 1K VC board */  
 189#define RX_PACKET_RAM   0x80000 /* start of Receive Packet memory - 512K */  
 190#define DFL_RX_BUF_SZ   10240   /* 10k buffers */  
 191#define DFL_RX_BUFFERS      50  /* number of packet buffers for Rx   
 192                                        - descriptor 0 unused */  
 193  
 194struct cpcs_trailer 
 195{  
 196        u_short control;  
 197        u_short length;  
 198        u_int   crc32;  
 199};  
 200
 201struct cpcs_trailer_desc
 202{
 203        struct cpcs_trailer *cpcs;
 204        dma_addr_t dma_addr;
 205};
 206
 207struct ia_vcc 
 208{ 
 209        int rxing;       
 210        int txing;               
 211        int NumCbrEntry;
 212        u32 pcr;
 213        u32 saved_tx_quota;
 214        int flow_inc;
 215        struct sk_buff_head txing_skb; 
 216        int  ltimeout;                  
 217        u8  vc_desc_cnt;                
 218                
 219};  
 220  
 221struct abr_vc_table 
 222{  
 223        u_char status;  
 224        u_char rdf;  
 225        u_short air;  
 226        u_int res[3];  
 227        u_int req_rm_cell_data1;  
 228        u_int req_rm_cell_data2;  
 229        u_int add_rm_cell_data1;  
 230        u_int add_rm_cell_data2;  
 231};  
 232    
 233/* 32 byte entries */  
 234struct main_vc 
 235{  
 236        u_short         type;  
 237#define ABR     0x8000  
 238#define UBR     0xc000  
 239#define CBR     0x0000  
 240        /* ABR fields */  
 241        u_short         nrm;     
 242        u_short         trm;       
 243        u_short         rm_timestamp_hi;  
 244        u_short         rm_timestamp_lo:8,  
 245                        crm:8;            
 246        u_short         remainder;      /* ABR and UBR fields - last 10 bits*/  
 247        u_short         next_vc_sched;  
 248        u_short         present_desc;   /* all classes */  
 249        u_short         last_cell_slot; /* ABR and UBR */  
 250        u_short         pcr;  
 251        u_short         fraction;  
 252        u_short         icr;  
 253        u_short         atdf;  
 254        u_short         mcr;  
 255        u_short         acr;             
 256        u_short         unack:8,  
 257                        status:8;       /* all classes */  
 258#define UIOLI 0x80  
 259#define CRC_APPEND 0x40                 /* for status field - CRC-32 append */  
 260#define ABR_STATE 0x02  
 261  
 262};  
 263  
 264  
 265/* 8 byte entries */  
 266struct ext_vc 
 267{  
 268        u_short         atm_hdr1;  
 269        u_short         atm_hdr2;  
 270        u_short         last_desc;  
 271        u_short         out_of_rate_link;   /* reserved for UBR and CBR */  
 272};  
 273  
 274  
 275#define DLE_ENTRIES 256  
 276#define DMA_INT_ENABLE 0x0002   /* use for both Tx and Rx */  
 277#define TX_DLE_PSI 0x0001  
 278#define DLE_TOTAL_SIZE (sizeof(struct dle)*DLE_ENTRIES)
 279  
 280/* Descriptor List Entries (DLE) */  
 281struct dle 
 282{  
 283        u32     sys_pkt_addr;  
 284        u32     local_pkt_addr;  
 285        u32     bytes;  
 286        u16     prq_wr_ptr_data;  
 287        u16     mode;  
 288};  
 289  
 290struct dle_q 
 291{  
 292        struct dle      *start;  
 293        struct dle      *end;  
 294        struct dle      *read;  
 295        struct dle      *write;  
 296};  
 297  
 298struct free_desc_q 
 299{  
 300        int     desc;   /* Descriptor number */  
 301        struct free_desc_q *next;  
 302};  
 303  
 304struct tx_buf_desc {  
 305        unsigned short desc_mode;  
 306        unsigned short vc_index;  
 307        unsigned short res1;            /* reserved field */  
 308        unsigned short bytes;  
 309        unsigned short buf_start_hi;  
 310        unsigned short buf_start_lo;  
 311        unsigned short res2[10];        /* reserved field */  
 312};  
 313          
 314  
 315struct rx_buf_desc { 
 316        unsigned short desc_mode;
 317        unsigned short vc_index;
 318        unsigned short vpi; 
 319        unsigned short bytes; 
 320        unsigned short buf_start_hi;  
 321        unsigned short buf_start_lo;  
 322        unsigned short dma_start_hi;  
 323        unsigned short dma_start_lo;  
 324        unsigned short crc_upper;  
 325        unsigned short crc_lower;  
 326        unsigned short res:8, timeout:8;  
 327        unsigned short res2[5]; /* reserved field */  
 328};  
 329  
 330/*--------SAR stuff ---------------------*/  
 331  
 332#define EPROM_SIZE 0x40000      /* says 64K in the docs ??? */  
 333#define MAC1_LEN        4                                                 
 334#define MAC2_LEN        2  
 335   
 336/*------------ PCI Memory Space Map, 128K SAR memory ----------------*/  
 337#define IPHASE5575_PCI_CONFIG_REG_BASE  0x0000  
 338#define IPHASE5575_BUS_CONTROL_REG_BASE 0x1000  /* offsets 0x00 - 0x3c */  
 339#define IPHASE5575_FRAG_CONTROL_REG_BASE 0x2000  
 340#define IPHASE5575_REASS_CONTROL_REG_BASE 0x3000  
 341#define IPHASE5575_DMA_CONTROL_REG_BASE 0x4000  
 342#define IPHASE5575_FRONT_END_REG_BASE IPHASE5575_DMA_CONTROL_REG_BASE  
 343#define IPHASE5575_FRAG_CONTROL_RAM_BASE 0x10000  
 344#define IPHASE5575_REASS_CONTROL_RAM_BASE 0x20000  
 345  
 346/*------------ Bus interface control registers -----------------*/  
 347#define IPHASE5575_BUS_CONTROL_REG      0x00  
 348#define IPHASE5575_BUS_STATUS_REG       0x01    /* actual offset 0x04 */  
 349#define IPHASE5575_MAC1                 0x02  
 350#define IPHASE5575_REV                  0x03  
 351#define IPHASE5575_MAC2                 0x03    /*actual offset 0x0e-reg 0x0c*/  
 352#define IPHASE5575_EXT_RESET            0x04  
 353#define IPHASE5575_INT_RESET            0x05    /* addr 1c ?? reg 0x06 */  
 354#define IPHASE5575_PCI_ADDR_PAGE        0x07    /* reg 0x08, 0x09 ?? */  
 355#define IPHASE5575_EEPROM_ACCESS        0x0a    /* actual offset 0x28 */  
 356#define IPHASE5575_CELL_FIFO_QUEUE_SZ   0x0b  
 357#define IPHASE5575_CELL_FIFO_MARK_STATE 0x0c  
 358#define IPHASE5575_CELL_FIFO_READ_PTR   0x0d  
 359#define IPHASE5575_CELL_FIFO_WRITE_PTR  0x0e  
 360#define IPHASE5575_CELL_FIFO_CELLS_AVL  0x0f    /* actual offset 0x3c */  
 361  
 362/* Bus Interface Control Register bits */  
 363#define CTRL_FE_RST     0x80000000  
 364#define CTRL_LED        0x40000000  
 365#define CTRL_25MBPHY    0x10000000  
 366#define CTRL_ENCMBMEM   0x08000000  
 367#define CTRL_ENOFFSEG   0x01000000  
 368#define CTRL_ERRMASK    0x00400000  
 369#define CTRL_DLETMASK   0x00100000  
 370#define CTRL_DLERMASK   0x00080000  
 371#define CTRL_FEMASK     0x00040000  
 372#define CTRL_SEGMASK    0x00020000  
 373#define CTRL_REASSMASK  0x00010000  
 374#define CTRL_CSPREEMPT  0x00002000  
 375#define CTRL_B128       0x00000200  
 376#define CTRL_B64        0x00000100  
 377#define CTRL_B48        0x00000080  
 378#define CTRL_B32        0x00000040  
 379#define CTRL_B16        0x00000020  
 380#define CTRL_B8         0x00000010  
 381  
 382/* Bus Interface Status Register bits */  
 383#define STAT_CMEMSIZ    0xc0000000  
 384#define STAT_ADPARCK    0x20000000  
 385#define STAT_RESVD      0x1fffff80  
 386#define STAT_ERRINT     0x00000040  
 387#define STAT_MARKINT    0x00000020  
 388#define STAT_DLETINT    0x00000010  
 389#define STAT_DLERINT    0x00000008  
 390#define STAT_FEINT      0x00000004  
 391#define STAT_SEGINT     0x00000002  
 392#define STAT_REASSINT   0x00000001  
 393  
 394  
 395/*--------------- Segmentation control registers -----------------*/  
 396/* The segmentation registers are 16 bits access and the addresses  
 397        are defined as such so the addresses are the actual "offsets" */  
 398#define IDLEHEADHI      0x00  
 399#define IDLEHEADLO      0x01  
 400#define MAXRATE         0x02  
 401/* Values for MAXRATE register for 155Mbps and 25.6 Mbps operation */  
 402#define RATE155         0x64b1 // 16 bits float format 
 403#define MAX_ATM_155     352768 // Cells/second p.118
 404#define RATE25          0x5f9d  
 405  
 406#define STPARMS         0x03  
 407#define STPARMS_1K      0x008c  
 408#define STPARMS_2K      0x0049  
 409#define STPARMS_4K      0x0026  
 410#define COMP_EN         0x4000  
 411#define CBR_EN          0x2000  
 412#define ABR_EN          0x0800  
 413#define UBR_EN          0x0400  
 414  
 415#define ABRUBR_ARB      0x04  
 416#define RM_TYPE         0x05  
 417/*Value for RM_TYPE register for ATM Forum Traffic Mangement4.0 support*/  
 418#define RM_TYPE_4_0     0x0100  
 419  
 420#define SEG_COMMAND_REG         0x17  
 421/* Values for the command register */  
 422#define RESET_SEG 0x0055  
 423#define RESET_SEG_STATE 0x00aa  
 424#define RESET_TX_CELL_CTR 0x00cc  
 425  
 426#define CBR_PTR_BASE    0x20  
 427#define ABR_SBPTR_BASE  0x22  
 428#define UBR_SBPTR_BASE  0x23  
 429#define ABRWQ_BASE      0x26  
 430#define UBRWQ_BASE      0x27  
 431#define VCT_BASE        0x28  
 432#define VCTE_BASE       0x29  
 433#define /*  433#define  334>RATE25          0x5f9d  
 415CBR_PTR_BASE    0x20  
 426IDLEHEADLO      0x01  
 337ABR_SBPTR_BASE  0x22  
 338UBR_SBPTR_BASE  0x23  
 339ABRUBR_ARB      0x04  
 340RESET_SEG 0x0055  
 341ABRWQ_BASE      0x26  
 342UBRWQ_BASE      0x27  
 343Iefine Iefinlass="srAT_ERRINT     0x00000040  
 344IDLEHEADLO      0x01  
 415I I E" class="sr4"sref">RESET_SEG 0x0055  
 426 421  
 297  
 348Ihref="+code=IPHAMODEef">IhE" class="sr4f">ABRWQ_BASE      0x26  
 349Ih_VAASE5575_CELL_FIFMODEef">Ih_VAAlass="sref">UB class="line" name="L421"> 421  
 351UBRWQ_BASE      0x27  
 352VCT_BASE        0x28  
 353        0x28  
 354line" name="L421"> 421// Cells/second p.118
 395                                an clasment">/* Ths wellThs s="cmask>/* Values for the command register */  
 357VCTE_BASE       0x29  
 358VCTE_BASE       0x29  
 259 360 361  
 362/* T for the command register */  
 363VCTE_BASE       0x29  
 364RESET_SEG_STATE 0x00aa  
 365 366RESET_SEG_STATE 0x00aa  
 367   0x0b  
 368#define  369<=ABRWQWR_BA=IPHASE5575_BUS=ABRWQWR_BAmH2" clas4"6f*  433#define  370<=ABRWQRD_BA=IPHASE5575_BUS=ABRWQRD_BAmH2" clas4"7T_ERRINT     0x00000040  
 371IDLEHEADLO      0x01  
 372ABR_SBPTR_BASE  0x22  
 373UBR_SBPTR_BASE  0x23  
 374<_SBPTRVC RESET_SEG 0x0055  
 375ABRWQ_BASE      0x26  
 376<_SBNEXTLINe VCT_BASE        0x28  
 377VCTE_BASE       0x29  
 361  
 279  
 280  
 421/* The segmentation registers are 16 bits access and the addresses  
 382 class="n class="comment">        are defined as such so the addresses are the actual "offsets" */  
 383SE5575_CELL_FIFMODEef">B16" class="srefot;offsets" */  
 384 421  
 385 387 388<" clasK" ccode=IPHASE5575_BUS" clasK" ccodelass="sref">ABR_SBPTR_BASE  0x22  
 389<" clasINTRhref="+code=IPHASE5575_BUS" clasINTRhref="+codeclass="sref">STPARMS         0x03  
 280/* Interface Status Register bits */  
 391CBR_EN          0x2000  
 392<"X_ERRclas_OF=IPHASE5575_BUS"X_ERRclas_OFclass="sr4f">CBR_EN          0x2000  
 423CBR_EN          0x2000  
 384       0x00000200  
 385<"X_EXCPQ_FASE5575_CELL_FIF"X_EXCPQ_FA" class="sreTRL_B48        0x00000080  
 416 387<"X_EXCP_RCne  398<"X_PKTcRCne ABRUBR_ARB      0x04  
 399<"X_RAWcRCne  391ABRUBR_ARB      0x04  
 402RESET_SEG 0x0055  
 403 404 0x0c  
 375RATE25          0x5f9d  
 406<" class=fine #define  417/* Values for the command register */  
 408RESET_SEG 0x0055  
 409<" _CEL" clae RESET_SEG_STATE 0x00aa  
 410  
 411ABR_SBPTR_BASE  0x22  
 412    0x00000008  
 413aref="+code=SEG_" _CEL" claeALref">as="sref"fff*  433#define  414  
 415<" claeDESCIefine  414  
 416  
 387<" claeTABL>Iefine Iefins="sref1f">ABR_SBPTR_BASE  0x22  
 418Iefine Iefins="sref1f">STPARMS         0x03  
 409ABRWQ_BASE      0x26  
 420 351 422VCTE_BASE       0x29  
 423 0x0c  
 424RATE25          0x5f9d  
 415_LKUPdefine   0x0e  
 426ABRUBR_ARB      0x04  
 427RESET_SEG 0x0055  
 428ABRWQ_BASE      0x26  
 429 430VCT_BASE        0x28  
 431VCTE_BASE       0x29  
 432 433 334/*  433#define  415>RATE25          0x5f9d  
 426LL_FIFO_WRITE_PTR  0x0e  
 337f*  433#define  338ABRUBR_ARB      0x04  
 339RESET_SEG 0x0055  
 340ABRWQ_BASE      0x26  
 341         0x17  
 342< VCT_BASE        0x28  
 343ABR_SBPTR_BASE  0x22  
 344ABRUBR_ARB      0x04  
 415ABRUBR_ARB      0x04  
 426RESET_SEG 0x0055  
 347 348 279  
 280/* Bus Interface Status Register bits */  
 351 352    0x00000010  
 353ABRUBR_ARB      0x04  
 414  
 414  
 396/* Values/ DMA--------- control rol registers -----------------*/  
 417 382 class="eg:- 2 class=s gessn 800, a00 clasrx---un cls access and the addresses  
 382 class="similarly many osucrts access and the addresses  
 280s="Remembclsagain suat suchclass=s  as so be 4*/* Valuesnumbcl,     access and the addresses  
 421 class="correct suchline" ns hereM  access and the addresses  
 362egisters -----------------*/  
 363 421  
 364 421  
 365 421  
 366 421  
 297  
 382  
 382/*ae=embly- RAMeb 
  
 421/*---comment"Memory mapdegisters -----------------*/  
 372CBline" name="L382"> 382  
 373CBline" name="L382"> 382  
 374CBline" name="L382"> 382  
 375 CBline" name="L382"> 382  
 376 CBline" name="L382"> 382  
 377CBline" name="L382"> 382  
 378 CBline" name="L382"> 382  
 379CBline" name="L382"> 382  
 380 CBline" name="L382"> 382  
 351 CBline" name="L382"> 382  
 342< CHEDSCBline" name="L382"> 382USBsScheduling TablLssizLs for the command register */  
 383ISCBline" name="L382"> 382 3rinedin sueaTransmit-  access and the addresses  
 395                                        >  
 414  
 396  
 387  
 388 389STPARMS         0x03  
 390ABRUBR_ARB      0x04  
 391RESET_SEG 0x0055  
RESET_SEG 0x0055  
 362  
 384ABR_EN          0x0800  
 385RM_TYPE_4_0     0x0100  
 416UBR_EN          0x0400  
 387R_EN          0x0400  
 361  
 399IADDeElaref="+code=SEG_TABL>IADDeElass="(me="L399"> 399 399 399 361  
 399 399 399 361  
 361  
 362  
 403CBline" name="L382"> 382  
 404 CBline" name="L382"> 382  
 375CBline" name="L382"> 382  
 406CBline" name="L382"> 382  
 407CBline" name="L382"> 382  
 408e CBline" name="L382"> 382  
 409<"X_VCeTABL> " class="sr78">CBline" name="L382"> 382  
 410 CBline" name="L382"> 382  
 411ISCBline" name="L382"> 382 3rinedin sueaReceer -  access and the addresses  
 382 class="                                >  
 413IS 382 3rinedin VPTablLs for the coommand register */  
 384ISCBline" name="L382"> 382 3rinedin VCsTablLs for the coommand register */  
 415<" claeTABL>ISCBline" name="L382"> 382 3rinedin Reme=embly-TablLs for the command register */  
 382  
 387<"X_AC href="+code=CTRRX_AC lass="sr8f">CBR_EN          0x2000  
 418CBR_EN          0x2000  
 409     0x00000040  
 420<"X_TRA=IPHASE5575_BUSTX_TRAlass="sreTST_DLERINT    0x00000008  
 351<"X_P href="+code=RESETX_P hlass="sreTSf">ABRUBR_ARB      0x04  
 422ABR_SBPTR_BASE  0x22  
 423  0x22  
 395  
 426 427e es="sref4f">CBR_EN          0x2000  
 428e CBR_EN          0x2000  
 429CBR_EN          0x2000  
 430<" claeABA=IPHASE5575_BUST_claeABAB16" class=_C2f">CBR_EN          0x2000  
 361  
 362  
 433Iefine  366Iefine Iefinss="line" name="L361"> 361  
 334 366 361  
 415 366Iefine Iefinss="line" name="L361"> 361  
 426Iefine  366Iefine Iefinss="line" name="L361"> 361  
 337 366Iefine Iefinss="line" name="L361"> 361  
 361  
 337 337 361  
 337 337 361  
 361  
 337<_ffredn_36  361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 3 Par" iSegme        for the ne" name="L361"> 361  
 337 337 382 361  
 337 337 382 361  
 337 337 361  
 337 337 382/* Valuesaaaaaaaaaaaaaaaaaaaa for the ne" name="L361"> 361  
 337 337 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 361  
 337 337 382 361  
 337 337 382>>>>>>>>>>>>>>>>>>>>>>> for the ne" name="L361"> 361  
 337 337 382 361  
 337 337 361  
 337 337 382 361  
 337 337 382Ae defi ssssss for the ne" name="L361"> 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382Ae defi s for the ne" name="L361"> 361  
 337 337 382 361  
 337 337 382 361  
 337 337 361  
 337 337 382TCQsssssssss for the ne" name="L361"> 361  
 337 337 382 361  
 337 337 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382/* Valuesaaaaaaaaaaa for the ne" name="L361"> 361  
 337 337 382/* Bus                         for the ne" name="L361"> 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382/* Valuesaaaaaaaaaaa           for the ne" name="L361"> 361  
 337 337 361  
 337 337 382 3 descriptlasnum   for the ne" name="L361"> 361  
 337 337 382 361  
 337 337 382 361  
 337 337 361  
 337 337 3_slot_c 36  382 3 slots--un                    for the ne" name="L361"> 361  
 337 337 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 361  
 361  
 337<_rfredn_36  361  
 337 337 382 361  
 337 337 382 361  
 337 337 382/* Bus                         for the ne" name="L361"> 361  
 337 337 382/* Valuesaaaaaaaaaaa for the ne" name="L361"> 361  
 337 337 382 361  
 337 337 382 361  
 337 337 361  
 337 337 382 361  
 337 337 361  
 337 337 382 361  
 337 337 382 361  
 337 337 361  
 337 337 382/* Valuesaaaaaaaaaaaaaaaaaaaa for the ne" name="L361"> 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 361  
 337 337 382--un  /* Valuesaaa for the ne" name="L361"> 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 361  
 337 337 382 361  
 337 337 382/* Valuesaaaaaaaaaaaaaaaaaa for the ne" name="L361"> 361  
 337 337 382 361  
 337 337 361  
 337 337 382 361  
 337 337 382ae defi ssssssasa for the ne" name="L361"> 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382ae defi sss for the ne" name="L361"> 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382ae defi ssssssasa for the ne" name="L361"> 361  
 337 337 382 361  
 337 337 382 361  
 337 337 361  
 337 337 382 361  
 337 337 382ae defi ssssssasasssssss for the ne" name="L361"> 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382/* Bus                        for the ne" name="L361"> 361  
 337 337 361  
 337 337 382 361  
 337 337 361  
 337 337 382RM  for the ne" name="L361"> 361  
 337 337 361  
 337 337 382 361  
 337 337 382 361  
 337 337 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 361  
 361  
 361  
 382 361  
 337 337 382 361  
 337 337 382 361  
 337 361  
 361  
 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337rved6tm/iphase="+coddef>rved6ss=";CBB   line" name="L382"> 382 361  
 337 337 382 361  
 337 337rved1  382rvedsssssssssssss for the ne" name="L361"> 361  
 337 337rved1/tm/iphase="+coddef>rved1/ss=";CBB  line" name="L382"> 382rvedsssssssssssss for the ne" name="L361"> 361  
 337 337rved1atm/iphase="+coddef>rved1ass=";CBB  line" name="L382"> 382rvedsssssssssssss for the ne" name="L361"> 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 3ry6  361  
 361  
 361  
 337 337 382+ RDFclass="   for the ne" name="L361"> 361  
 337 337 382 361  
 337 337rvedatm/iphase="+coddef>rved4ss="[14];  line" name="L382"> 382rvedsssssssssssss for the ne" name="L361"> 361  
 337 3ry6  361  
 361  
 337 361  
 361  
 337 361  
 337 337 382 361  
 337 337 382 361  
 382 s for the ne" name="L361"> 361  
 337 337 382 361  
 337 337 382 361  
 361  
 382 s for the ne" name="L361"> 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 3 BuffuesExposuret(24-bit)s for the ne" name="L361"> 361  
 337 337 382Trip"Timet(24-bit)s for the ne" name="L361"> 361  
 361  
 382 sof TM 4.0  for the ne" name="L361"> 361  
 337 361  
 361  
 337 337 36  337 337 337 337 337 337 337 337 337 337 361  
 361  
 382 361  
 361  
 337 337 382RMor the ne" name="L361"> 361  
 382CBB      BBass="                        cellT(3-bit)s for the ne" name="L361"> 361  
 337 337 382RM cellsT(3-bit)s for the ne" name="L361"> 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 3aFactlas(4-bit)s for the ne" name="L361"> 361  
 337 337 382 361  
 337 337rvedtm/iphase="+coddef>rvedss=";CBB      B Bline" name="L382"> 382aligned  for the ne" name="L361"> 361  
 337 361  
 361  
 337 361  
 337 337 361  
 337 337 361  
 337 337 361  
 361  
 361  
 361  
 337 337 361  
 337 337 361  
 337 361  
 361  
 361  
 337 337 361  
 337 337 361  
 337 337 361  
 337 337 361  
 337 361  
 337 361  
 337 361  
 337 361  
 361  
 337 361  
 337 337 382 361  
 337 337 382ae defi ssssssasa for the ne" name="L361"> 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382ae defi sss for the ne" name="L361"> 361  
 337 337 382 361  
 337 337 382 361  
 361  
 361  
 337 361  
 337 337 382 361  
 337 337 382Ae defi ssssss for the ne" name="L361"> 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382Ae defi s for the ne" name="L361"> 361  
 337 337 382 361  
 361  
 361  
 337 361  
 337 337 361  
 337 337 361  
 337 337 361  
 361  
 361  
 337 361  
 337 337 361  
 337 337 337 361  
 337 361  
 361  
 337 361  
 337 361  
 337 382t nt">Id> 3itysss for the ne" name="L361"> 361  
 337 382 361  
 337 382 361  
 337 382rvedsssssssssssssssssssssssss for the ne" name="L361"> 361  
 337 382 361  
 337 382 361  
 382rveds(10)ssssssssssssssssssss for the ne" name="L361"> 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 361  
 337 382 361  
 337 382 361  
 382rveds(2)sssssssssssssssssssss for the ne" name="L361"> 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 361  
 337 382 361  
 337 382 361  
 382rveds(14)ssssssssssssssssssss for the ne" name="L361"> 361  
 337 382 361  
 337 382 361  
 337 382rvedssssssssssssssssssss for the ne" name="L361"> 361  
 337 382 361  
 382rveds(3)sssssssssssssssssssss for the ne" name="L361"> 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 382rveds(4)ssssssssssssssssssss  for the ne" name="L361"> 361  
 337 382 361  
 337 382 361  
 337 382 361  
 382rveds(2)sssssssssssssssssssss for the ne" name="L361"> 361  
 337 382 361  
 337 382 361  
 337 382rvedssssssssssssssssssss for the ne" name="L361"> 361  
 337 382 361  
 337 382 361  
 382rveds(6)sssssssssssssssssssss for the ne" name="L361"> 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 382rveds(10)ssssssssssssssssssss for the ne" name="L361"> 361  
 337 382 361  
 337 382 361  
 337 382 361  
 382rveds(5)sssssssssssssssssssss for the ne" name="L361"> 361  
 382rveds(24)ssssssssssssssssssss for the ne" name="L361"> 361  
 382 361  
 382CBB      /aSUNI_MASTER_TEST     ="0x200,    SUNI Ma Bus Testsssssssssssssssss for the ne" name="L361"> 361  
 337 382rvedsclasTestsssssssssss for the ne" name="L361"> 361  
 361  
 361  
 337<_SUNI_STATS_tm/iphase="+cod_SUNI_STATS_ss="ne" name="L361"> 361  
 361  
 337 337 382 361  
 337 337 382 361  
 382head processorss the ne" name="L361"> 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 382head processorss the ne" name="L361"> 361  
 337 337 382rece61" failuress the ne" name="L361"> 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 382head processorss the ne" name="L361"> 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382 361  
 382 361  
 337 337 382 361  
 337 337 382 361  
 337 337 382run coun ss the ne" name="L361"> 361  
 337 337 382 361  
 337 337 382 361  
 337 361  
 361  
 337 361  
 382ae defi ineces for the iline" name="L361"> 361  
 337 337<__iomemref="+code=IPHA__iomemss="c*me="L337"> 337 382 361  
 337 337<__iomemref="+code=IPHA__iomemss="c*me="L337"> 337 382 361  
 337 337<__iomemref="+code=IPHA__iomemss="c*me="L337"> 337 382 361  
 337 337<__iomemref="+code=IPHA__iomemss="c*me="L337"> 337 382 3at5Mbsengh#Ls or the ne" name="L361"> 361  
 382CBB                                             in clbal regi Busss for the ilne" name="L361"> 361  
 337 337<__iomemref="+code=IPHA__iomemss="c*me="L337"> 337 382 361  
 382CBB                                             in clbal regi Busss for the ilne" name="L361"> 361  
 337 337<__iomemref="+code=IPHA__iomemss="c*me="L337"> 337 382 361  
 337<__iomemref="+code=IPHA__iomemss="c*me="L337"> 337 361  
 337<__iomemref="+code=IPHA__iomemss="c*me="L337"> 337 361  
10f=ss="class=" struct me="L337"> 337 337 361  
 337 337 361  
 337 337 337 361  
 337 337 361  
 337 337 361  
 337 337 361  
 337 337 361  
 337 337 361  
 337 337 361  
 337 337 337 337 361  
 337 337 337 361  
 337<__iomemref="+code=IPHA__iomemss="c*me="L337"> 337 337 337 361  
 337 337 361  
 337 337 361  
 337 337 361  
 337 337 361  
 337<61<_vcc6  337 382 361  
 337 337 337 337 361  
 337 337 337 361  
 337 361  
 337<__iomemref="+code=IPHA__iomemss="c*me="L337"> 337 361  
 337 337 337 337 337 361  
 337<61<_de1tm/iphase="+cod61<_de1ss="c*me="L337"> 337 382  
< de1icess for the ilne" name="L361"> 361  
 337 337 361  
 337 361  
 337 382virtu"l b 
< ae defi  for the ilne" name="L361"> 361  
 337<__iomemref="+code=IPHA__iomemss="c*me="L337"> 337 361  
 337 382 361  
 337 361  
 337 361  
 337 361  
 337 337 361  
 337 337 337 337 361  
 337 337 361  
 337 337 361  
 382 361  
 382 361  
 337 361  
 382 361  
 382 361  
 337 382 3s on dma queuLor the ne" name="L361"> 361  
 337 382 3s on rx dma queuLor the ne" name="L361"> 361  
 337 382 361  
 382 361  
 337 382 3s on mark queuLor the ne" name="L361"> 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 382 361  
 337 337 337 361  
 337 361  
 337 337 361  
 337 337 361  
 337 337 361  
 337 337 361  
 337 337 361  
 337 361  
 361  
 361  
 337 337 337 337 337 361  
 337 337<1tm/iphase="+codvss=") ((struct me="L337"> 337 337<1tm/iphase="+codvss=")->me="L337"> 337 361  
 361  
 382 361  
 337 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 nt">HECasn cui/control"/for the ne" name="L361"> 361  
 337 361  
 337 361  
 361  
 361  
 382 361  
 382C/aMa Bus Controlor the ne" name="L361"> 361  
 382C/for the ne" name="L361"> 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 361  
 382 361  
 382C/aIn clruptaSn cuior the ne" name="L361"> 361  
 382C/for the ne" name="L361"> 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382run ssssssssssss for the ne" name="L361"> 361  
 361  
 382 361  
 382C/aDiagnostic Controlor the ne" name="L361"> 361  
 382C/for the ne" name="L361"> 361  
 337 382 361  
110ass="#defh#Lsme="L337"> 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
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 337 382 361  
 337 382 361  
 337 361  
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 337 382 361  
 337 382 361  
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 382 361  
 337 361  
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 337 382 361  
 337 382 361  
 337 382Id> 3ity /for the ne" name="L361"> 361  
 337 361  
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120ass="liass=" me="L337"> 337 361  
 337 361  
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 382 361  
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 382 361  
 337 361  
 382 361  
 361  
 361  
 337 337 361  
 337 382 361  
 337 382 361  
 382 361  
 382C/aSUNI_PM7345 Configurat5Mbor the ne" name="L361"> 361  
 382C/for the ne" name="L361"> 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 382 361  
 382C/aDS3 FRMR In clruptaEnablLor the ne" name="L361"> 361  
 382C/for the ne" name="L361"> 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 361  
 382 361  
 382C/aDS3 FRMR Sn cuior the ne" name="L361"> 361  
 382C/for the ne" name="L361"> 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 361  
 382 361  
 382C/aE3 FRMR In clrupt/Sn cuior the ne" name="L361"> 361  
 382C/for the ne" name="L361"> 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 337 382 361  
 361  
 382 361  
 382C/aE3 FRMR Main enance Sn cuior the ne" name="L361"> 361  
 382C/for the ne" name="L361"> 361  
 337 382 361  
 337 382 361  
 337 382 361  
 361  
 382 361  
 382C/aRXCP Control/Sn cuior the ne" name="L361"> 361  
 382C/for the ne" name="L361"> 361  
 337 382 3612 hr1129"driver12/atm/iphase.h#L366" id="12/a7 382 361  
<2 hr1129"driver12/atm/iphase.h#L367" id="12/a7 382 361  
<2 hr1129"driver12/atm/iphase.h#L368" id="12/aHC me="L337"> 337 382 361  
<2 hr1129"driver12/atm/iphase.h#L369" id="12/aBLOC me="L337"> 337 382 361  
<3 hr1230"driver12/atm/iphase.h#L370" id="12/aDSCs="class=" me="L337">12/aDSCsMASTER_TESTtm/im/iphase="+codSUNI_PM7345_DLBss="clsx80clplass=" descss=bling L382"> 382 361  
<3 hr1230"driver12/atm/iphase.h#L371" id="12/at>C1266ss="#defh#Lsme="L337">t>C12MASTER_TESTtm/m/iphase="+codSUNI_PM7345_PLBss="classde"> 3" ss="ls="line" naL382"> 382 361  
<3 hr1230"driver12/atm/iphase.h#L372" id="12/as="cR2ss="class=" me="L337"12/as="cR2sE3_FERF_RAItm/iphase="+codSUNI_PM7345_CLBss="classs="clre ="0             L382"> 382 361  
<3 hr1230"driver12/atm/iphase.h#L373" id="12/at3="0x150,ne3 name="L361"> 361  
<3 hr1230"driver12/atm/iphase.h#L374" id="12/at>1274ss="mine" name="L382"> 3823for the ne3 name="L361"> 361  
<3 hr1230"driver12/atm/iphase.h#L375" id="121251ss="mine" naass="mine" name="L382"> 382C/aRXCP Control/Sn c3="0x160,ne3 name="L361"> 361  
<3 hr1230"driver12/atm/iphase.h#L376" id="12/at>1276ss="mine" name="L382"> 382C3="0x164,ne3 name="L361"> 361  
<3 hr1230"driver12/atm/iphase.h#L367" id="12/at>C1259ss="#defh#Lsme="L337"> 3CDSUNI_DS3_COFAEtm/iphase="+codSUNI_DS3_COFAEss="cIs="ls="0x1,lass=" sin CDS   L382"> 382 361  
<3 hr1230"driver12/atm/iphase.h#L368" id="12/aHC126ass="#defh#Lsme="L337">HC12 382 361  
<3 hr1230"driver12/atm/iphase.h#L369" id="12/as="c56ss="#defh#Lsme="L337"> 3="c5UNI_DS3_CBITVtm/iphase="+codSUNI_DS3_CBITVss="cIs="ls="0x1,lunco 7 382 361  
<3 hr1231"driver12/atm/iphase.h#L370" id="12/a 3CDss="#defh#Lsme="L337"12/a 3CDsUNI_DS3_FERFVtm/iphase="+codSUNI_DS3_FERFVss="cSYNCass=" ss="line" name="   L382"> 382 361  
<3 hr1231"driver12/atm/iphase.h#L371" id="12/aU7 382 361  
<3 hr1231"driver12/atm/iphase.h#L372" id="12/aCOC9ss="#defh#Lsme="L337"12/aCOC9sUNI_DS3_COOFItm/iphase="+codSUNI_E3_OOFIss="claCorr. 7 382 361  
<3 hr1231"driver12/atm/iphase.h#L353" id="12/aFOVRss="#defh#Lsme="L337"12/aFOVRsUNI_DS3_C_LOStm/iphase="+codSUNI_E3_LOSss="class="clov1ss=n="line" name="   L382"> 382 361  
<3 hr1231"driver12/atm/iphase.h#L354" id="12/aFUDRss="#defh#Lsme="L337"12/aFUDRsUNI_DS3_C_OOFtm/iphase="+codSUNI_E3_OOFss="class="clund1ss=n="line" name="  L382"> 382 361  
<3 hr1231"driver12/atm/iphase.h#L335" id="12/at3="0x188,ne3 name="L361"> 361  
<3 hr1231"driver12/atm/iphase.h#L376///////////////////d="12/at>124PHY DEFINE END /////////////////////////////82"> 382 361  
<3 hr1237"driv2 361  
<3 hr1238"driv="+codSUNI_E3_OOFss="clasia_eeprom r12/atL382"> 382 361  
<3 hr1231"driver12/atm/iphase.h#L369"MEM_SIZEss=" me="L337"> 337 382 361  
<3 hr1232"driver12/atm/iphase.h#L370"MEM_SIZEs128 me="L337"> 337 382 361  
<3 hr1232"driver12/atm/iphase.h#L371"MEM_SIZEs512 me="L337"> 337 382 361  
<3 hr1232"driver12/atm/iphase.h#L372"MEM_SIZEs1Mme="L337"> 337 382 361  
<3 hr1232_PAT_H3tm/iphaseeeeeeeeeeeeeeeeeeeeeeeeeeeeee="+codSUNI_E3_OOFss="clas0x3 tos0xF arelre =rved for fute" nL382"> 382 361  
<3 hr1232"driver12/atm/iphase.h#L384" id="12/at3="0x1ac,ne3 name="L361"> 361  
<3 hr1232"driver12/atm/iphase.h#L395"FEss=" me="L337"> 337 382 361  
<3 hr1232"driver12/atm/iphase.h#L366"FE_MULTI_M1158ss="class=" meFE_MULTI_M115 382 361  
<3 hr1232"driver12/atm/iphase.h#L367"FE_SINGCP_I1158ss="class=" meFE_SINGCP_I115UNI_DS3_C010Ftm/iphase="+codSUNI_E3_OOFss="clas155 MBit single mlassUNIer L382"> 382 361  
<3 hr1232"driver12/atm/iphase.h#L368"FE_UTPTIONStm8ss="class=" meFE_UTPTIONStm 382 361  
<3 hr1239"driv2 361  
<3 hr1233"driver12/atm/iphase.h#L370"NOVRAM_SIZE8ss="class=" meNOVRAM_SIZEtm/iphase642 361  
<3 hr1233"driver12/atm/iphase.h#L371"CMD_Lss="liass=" me="LCMD_Lsstm/iphaseSUNI102 361  
<3 hr1232"driv2 361  
<3 hr1233"driver12/atm/iphase.h#L393/***********82"> 382 361  
<3 hr1233"driver12/atm/iphase.h#L394" 82"> 382 361  
<3 hr1233"driver12/atm/iphase.h#L375" iiiiiiSwitches and r12/ats for head1s0files.82"> 382 361  
<3 hr1233"driver12/atm/iphase.h#L376" 82"> 382 361  
<3 hr1233"driver12/atm/iphase.h#L387" iiiiiiThssfollowing r12/ats arelused toste"n on and off82"> 382 361  
<3 hr1233"driv="+codSUNI_E3_OOFss="c" iiiiiivarious op ss="lin thsshead1s0files. Primarilyluseful82"> 382 361  
<3 hr1239"driver12/atm/iphase.h#L339" iiiiiifor debugging.82"> 382 361  
<3 hr123="driver12/atm/iphase.h#L340" 82"> 382 361  
<3 hr1231"driver12/atm/iphase.h#L341"           382"> 382 361  
<3 hr1234"driv2 361  
<3 hr1234"driver12/atm/iphase.h#L393/*82"> 382 361  
<3 hr1234"driver12/atm/iphase.h#L394"  a lisx01clthssse.handslthat c2/abe s#L3 tosthssNOVRAM82"> 382 361  
<3 hr127"> 337er12/atm/iphase.h#L376" id="12/at>1276ss="mine" name="L382"> 382C3for the ne3 name="L361"> 361  
<3 hr127"> 337t>1276ss="mine" name="L382"> 382C3f"0x164,ne3 name="L361"> 361  
<3 hr1237"driver12/atm/iphase.h#L347"EXTE=" me="L337"> 337EXTE="UNI_DS3_FE02 361  
<3 hr1238"driver12/atm/iphase.h#L348"IAWR1255ss="#defh#LsmeIAWR125UNI_D+codS2 361  
<3 hr1239"driver12/atm/iphase.h#L349"IARElass=" me="L337">IARElaUNI_DS3_F8S2 361  
<3 hr1235"driver12/atm/iphase.h#L370"ERA126ass="#defh#LsmERA12 361  
<3 hr1235"driver12/atm/iphase.h#L391" id="12/at3Lor the ne3 name="L361"> 361  
<3 hr1235"driver12/atm/iphase.h#L372"EWDss="#defh#Lsme="EWDs37 361  
<3 hr1233"driver12/atm/iphase.h#L353"WRA="#defh#Lsme="L3WRA=37 361  
<3 hr1234"driver12/atm/iphase.h#L354"ERA="#defh#Lsme="L3ERA=37 361  
<3 hr1235"driver12/atm/iphase.h#L355"EWss="liass=" me="LEWss37 361  
<3 hr1235> 337t>1276ss="mine" name="L382"> 382C3for the ne3 name="L361"> 361  
<3 hr1235"driver12/atm/iphase.h#L387/*82"> 382 361  
<3 hr1235"driv="+codSUNI_E3_OOFss="c" ithsse0clas rux20clae thsshw_flip.h regisx1s0settingine" name="L382"> 382C/aRXCP Control/Sn c3for the ne3 name="L361"> 361  
<3 hr1235"driver12/atm/iphase.h#L339" inote: how thssdata in / out0clas arelr12/atdlin thssflipp1s0specifs=" ss="ne" name="L382"> 382C/aRXCP Control/Sn c3for the ne3 name="L361"> 361  
<3 hr1236"driver12/atm/iphase.h#L340" id="12/at>1276ss="mine" name="L382"> 382C3for the ne3 name="L361"> 361  
<3 hr1236"driver12/atm/iphase.h#L391" id="12/at3261ss="lne3 name="L361"> 361  
<3 hr1236"driver12/atm/iphase.h#L372"NV>1265ss="#defh#LsNV>137 361  
<3 hr1236"driver12/atm/iphase.h#L353"NV" me="L337"> 337 361  
<3 hr1236"driver12/atm/iphase.h#L354"NVDOme="L337"> 337 361  
<3 hr1235"driver12/atm/iphase.h#L365"NVDss="#defh#Lsme="NVDs37 361  
<3 hr1236"driver12/atm/iphase.h#L376/***********************d="12/at>1276ss="mine" name="L382"> 382C3for the ne3 name="L361"> 361  
<3 hr1236"driver12/atm/iphase.h#L387" d="12/at>1276ss="mine" name="L382"> 382C3for the ne3 name="L361"> 361  
<3 hr1236"driv="+codSUNI_E3_OOFss="c" iThis r12/ae andsltheivalue andlthsssurr#L3 c ss=" regisx1s0andlputine" name="L382"> 382C/aRXCP Control/Sn c3for the ne3 name="L361"> 361  
<3 hr1236"driver12/atm/iphase.h#L339" ithssresultlin thssc ss=" regisx1sne" name="L382"> 382C/aRXCP Control/Sn c3for the ne3 name="L361"> 361  
<3 hr1237"driver12/atm/iphase.h#L340" 82"> 382 361  
<3 hr1237"driver12/atm/iphase.h#L341"                       id="12/at>1276ss="mine" name="L382"> 382C3for the ne3 name="L361"> 361  
<3 hr1237"driv2 361  
<3 hr1237"driver12/atm/iphase.h#L353"CFG_A=" me="L337"> 337CFG_A="driv(/iphase.h#L353"val me="L337"> 337valdriv) { \2 361  
<3 hr1237SUNI_RESERVED4tm/ipha/iphase.h#L353"u name="L361"> 337u2"drive/iphase.h#L353"I_PM7345_Tss="cm7 361  
<3 hr1237_PAT_H5tm/iphase/ipha/iphase.h#L353"I_PM7345_Tss="cm7 337readldriv(/iphase.h#L353"iadev me="L337"> 337iadevdriv->/iphase.h#L353"reg me="L337"> 337regdriv+/iphase.h#L349"IPHA125575_EEPROM_ACCE5ss="#defh#Lsme="IPHA125575_EEPROM_ACCE5sdriv); \2 361  
<3 hr12376PAT_H5tm/iphase/ipha/iphase.h#L353"I_PM7345_Tss="cm7 337valdriv); \2 361  
<3 hr12377PAT_H5tm/iphase/ipha/iphase.h#L353"writel me="L337"> 337writeldriv(/iphase.h#L353"I_PM7345_Tss="cm7 337iadevdriv->/iphase.h#L353"reg me="L337"> 337regdriv+/iphase.h#L349"IPHA125575_EEPROM_ACCE5ss="#defh#Lsme="IPHA125575_EEPROM_ACCE5sdriv); \2 361  
<3 hr1237"driver12/atm}2 361  
<3 hr1237"driv2 361  
<3 hr1238"driver12/atm/iphase.h#L350" **********************d="12/at>1276ss="mine" name="L382"> 382C3for the ne3 name="L361"> 361  
<3 hr1238"driver12/atm/iphase.h#L341" d="12/at>1276ss="mine" name="L382"> 382C3for the ne3 name="L361"> 361  
<3 hr1238"driver12/atm/iphase.h#L352" iThis r12/ae  namtheivalue andlthsssurr#L3 c ss=" regisx1s0andlputine" name="L382"> 382C/aRXCP Control/Sn c3for the ne3 name="L361"> 361  
<3 hr1238"driver12/atm/iphase.h#L393" ithssresultlin thssc ss=" regisx1sne" name="L382"> 382C/aRXCP Control/Sn c3for the ne3 name="L361"> 361  
<3 hr1238"driver12/atm/iphase.h#L394" 82"> 382 361  
<3 hr1235"driver12/atm/iphase.h#L385"                       id="12/at>1276ss="mine" name="L382"> 382C3/or the ne3 name="L361"> 361  
<3 hr1238> 337t>1276ss="mine" name="L382"> 382C3ior the ne3 name="L361"> 361  
<3 hr1238"driver12/atm/iphase.h#L347"CFG_Os="class=" me="LCFG_Osdriv(/iphase.h#L353"val me="L337"> 337valdriv) { \2 361  
<3 hr12388UNI_RESERVED4tm/ipha/iphase.h#L353"u name="L361"> 337u2"drive/iphase.h#L353"I_PM7345_Tss="cm7 361  
<3 hr12389PAT_H5tm/iphase/ipha/iphase.h#L353"I_PM7345_Tss="cm7 337readldriv(/iphase.h#L353"iadev me="L337"> 337iadevdriv->/iphase.h#L353"reg me="L337"> 337regdriv+/iphase.h#L349"IPHA125575_EEPROM_ACCE5ss="#defh#Lsme="IPHA125575_EEPROM_ACCE5sdriv); \2 361  
<3 hr12390PAT_H5tm/iphase/ipha/iphase.h#L353"I_PM7345_Tss="cm7 337valdriv); \2 361  
<3 hr1239_PAT_H1tm/iphase/ipha/iphase.h#L353"writel me="L337"> 337writeldriv(/iphase.h#L353"I_PM7345_Tss="cm7 337iadevdriv->/iphase.h#L353"reg me="L337"> 337regdriv+/iphase.h#L349"IPHA125575_EEPROM_ACCE5ss="#defh#Lsme="IPHA125575_EEPROM_ACCE5sdriv); \2 361  
<3 hr12392driver12/atm}2 361  
<3 hr1239"driver12/atm/iphase.h#L373" id="12/at3ior the ne3 name="L361"> 361  
<3 hr1234"driver12/atm/iphase.h#L394" **********************d="12/at>1276ss="mine" name="L382"> 382C3for the ne3 name="L361"> 361  
<3 hr1239"driver12/atm/iphase.h#L385" d="12/at>1276ss="mine" name="L382"> 382C3for the ne3,ne" name="L361"> 3613 hr1139"driver12/atm/iphase.h#L386" iSs=d asse.hand tosthssNOVRAM,lthssse.hand i"lin cmd.82"> 382 361  
<3 hr1139"driver12/atm/iphase.h#L387" d="12/at>1276ss="mine" name="L382"> 382C34or the ne3 name="L361"> 361  
<3 hr1139"driv="+codSUNI_E3_OOFss="c" iclear CE0andlSK.iThsn NI_ert CE.82"> 382 361  
<3 hr1139"driver12/atm/iphase.h#L339" iCs=" seach01clthssse.hand0clas out0in thssc rr#ct  nd1s0x80cl" 37"> 382 361  
<4 hr1240"driver12/atm/iphase.h#L340" iexit0x80clCE0still NI_erted37"> 382 361  
<4 hr1240"driver12/atm/iphase.h#L341" d="12/at>1276ss="mine" name="L382"> 382C4=20x140,ne4 name="L361"> 361  
<4 hr1240"driver12/atm/iphase.h#L352"                       id="12/at>1276ss="mine" name="L382"> 382C4="0x14c,ne4 name="L361"> 361  
<4 hr1240"driver12/atm/iphase.h#L373" id="12/at4="0x150,ne4 name="L361"> 361  
<4 hr1240"driver12/atm/iphase.h#L354"NVRAM_CM" me="L337"> 337NVRAM_CM"driv(/iphase.h#L353"cmd me="L337"> 337cmddriv) { \2 361  
<4 hr1240_PAT_H5tm/iphase/iphaint/ipha/iphase.h#L353"i me="L337"> 337i 361  
<4 hr12406PAT_H5tm/iphase/ipha/iphase.h#L353"u_shorI_PM7345_Tss="cmu_shorIdrive/iphase.h#L353"c me="L337"> 337c 337cmddriv; \2 361  
<4 hr12407PAT_H5tm/iphase/ipha/iphase.h#L353"CFG_A=" me="L337"> 337CFG_A="driv(~(/iphase.h#L353"NV>1265ss="#defh#LsNV>137 337 361  
<4 hr12408UNI_RESERVED4tm/ipha/iphase.h#L353"CFG_Os="class=" me="LCFG_Osdriv(/iphase.h#L353"NV>1265ss="#defh#LsNV>137 361  
<4 hr12409PAT_H5tm/iphase/iphafor (/iphase.h#L353"i me="L337"> 337i 337i 337i 361  
<4 hr12410PAT_H5tm/iphase/ipha4tm/ipha/iphase.h#L353"NVRAM_CLKOUss="class=" me="NVRAM_CLKOUsdriv((/iphase.h#L353"c me="L337"> 337c 361  
<4 hr1241_PAT_H1tm/iphase/ipha4tm/ipha/iphase.h#L353"c me="L337"> 337c 361  
<4 hr12412PAT_H1tm/iphase/ipha} \2 361  
<4 hr1241_PAT_H3tm/iph}2 361  
<4 hr1241"driver12/atm/iphase.h#L384" id="12/at4=or the ne4 name="L361"> 361  
<4 hr1241"driver12/atm/iphase.h#L385" **********************d="12/at>1276ss="mine" name="L382"> 382C4="0x188,ne4 name="L361"> 361  
<4 hr1241"driver12/atm/iphase.h#L376" d="12/at>1276ss="mine" name="L382"> 382C4="0x164,ne4 name="L361"> 361  
<4 hr1241"driver12/atm/iphase.h#L387" iclear thssCE,lthi"lmustabe used afx1s0each0se.hand i"lse.pletame="L382"> 382C/aDS3 FRMR In clruptaEnab4=80x164,ne4 name="L361"> 361  
<4 hr1248"driv="+codSUNI_E3_OOFss="c" d="12/at>1276ss="mine" name="L382"> 382C4=90x164,ne4 name="L361"> 361  
<4 hr1241"driver12/atm/iphase.h#L339"                       id="12/at>1276ss="mine" name="L382"> 382C4="0x198,ne4 name="L361"> 361  
<4 hr1242"drivt>1276ss="mine" name="L382"> 382C4="0x174,ne4 name="L361"> 361  
<4 hr1242"driver12/atm/iphase.h#L371"NVRAM_CLR_>1265ss="#defh#LsNVRAM_CLR_>1PAT_H3tm{/iphase.h#L353"CFG_A=" me="L337"> 337CFG_A="driv(~/iphase.h#L353"NV>1265ss="#defh#LsNV>137 361  
<4 hr1242"driv2 361  
<4 hr1242"driver12/atm/iphase.h#L393/***********************d="12/at>1276ss="mine" name="L382"> 382C4="0x150,ne4 name="L361"> 361  
<4 hr1242"driver12/atm/iphase.h#L394" 82"> 382 361  
<4 hr1242"driver12/atm/iphase.h#L375" ics=" sthssdata clasin claval out0tosthssNOVRAM.iiThssclaval mustabe82"> 382 361  
<4 hr1242"driver12/atm/iphase.h#L386" ia 1 or 0, or thsscs=" out0opeine" nai"lund12/atd82"> 382 361  
<4 hr1242"driver12/atm/iphase.h#L387" d="12/at>1276ss="mine" name="L382"> 382C4=80x164,ne4 name="L361"> 361  
<4 hr1242"driv="+codSUNI_E3_OOFss="c"                       id="12/at>1276ss="mine" name="L382"> 382C4=90x164,ne4 name="L361"> 361  
<4 hr1249"driv2 361  
<4 hr1243"driver12/atm/iphase.h#L370"NVRAM_CLKOUss="class=" me="NVRAM_CLKOUsdriv(/iphase.h#L370"clavals="class=" me="clavaldriv) { \2 361  
<4 hr1243_PAT_H1tm/iphase/ipha/iphase.h#L353"CFG_A=" me="L337"> 337CFG_A="driv(~/iphase.h#L353"NVDss="#defh#Lsme="NVDs37 361  
<4 hr12432PAT_H1tm/iphase/ipha/iphase.h#L353"CFG_Os="class=" me="LCFG_Osdriv((/iphase.h#L370"clavals="class=" me="clavaldriv) ?m/iphase.h#L365"NVDss="#defh#Lsme="NVDs37 361  
<4 hr1243_PAT_H3tm/iphaseeeeee/iphase.h#L353"CFG_Os="class=" me="LCFG_Osdriv(/iphase.h#L353"NV" me="L337"> 337 361  
<4 hr1243SUNI_RESERVED4tm/ipha/iphase.h#L353"CFG_A=" me="L337"> 337CFG_A="driv( ~/iphase.h#L353"NV" me="L337"> 337 361  
<4 hr1243_PAT_H5tm/iph}2 361  
<4 hr1243> 337t>1276ss="mine" name="L382"> 382C4f"0x164,ne4 name="L361"> 361  
<4 hr1243"driver12/atm/iphase.h#L387/***********************d="12/at>1276ss="mine" name="L382"> 382C4f80x164,ne4 name="L361"> 361  
<4 hr1243"driv="+codSUNI_E3_OOFss="c" d="12/at>1276ss="mine" name="L382"> 382C4f90x164,ne4 name="L361"> 361  
<4 hr1249"driver12/atm/iphase.h#L339" ics=" sthssdata clasin and rete"n a 1 or 0, depending onmtheivalued="12/at>1276ss="mine" name="L382"> 382C4/or the ne4 name="L361"> 361  
<4 hr124="driver12/atm/iphase.h#L340" lthat was re=" ssd fromsthssNOVRAM82"> 382 361  
<4 hr1241"driver12/atm/iphase.h#L341" 82"> 382 361  
<4 hr1244"driver12/atm/iphase.h#L352"                       id="12/at>1276ss="mine" name="L382"> 382C4for the ne4 name="L361"> 361  
<4 hr1244"driver12/atm/iphase.h#L373" id="12/at4for the ne4 name="L361"> 361  
<4 hr1244"driver12/atm/iphase.h#L354"NVRAM_CLKIs="liass=" me="LNVRAM_CLKIsdriv(/iphase.h#L353"value me="L337"> 337valued=iv) { \2 361  
<4 hr1244_PAT_H5tm/iphase/ipha/iphase.h#L353"u name="L361"> 337u2"drive/iphase.h#L353"_I_PM7345_Tss="cm_7 361  
<4 hr12446PAT_H5tm/iphase/ipha/iphase.h#L353"CFG_Os="class=" me="LCFG_Osdriv(/iphase.h#L353"NV" me="L337"> 337 361  
<4 hr12447PAT_H5tm/iphase/ipha/iphase.h#L353"CFG_A=" me="L337"> 337CFG_A="driv(~/iphase.h#L353"NV" me="L337"> 337 361  
<4 hr12448UNI_RESERVED4tm/ipha/iphase.h#L353"_I_PM7345_Tss="cm_7 337readldriv(/iphase.h#L353"iadev me="L337"> 337iadevdriv->/iphase.h#L353"reg me="L337"> 337regdriv+/iphase.h#L349"IPHA125575_EEPROM_ACCE5ss="#defh#Lsme="IPHA125575_EEPROM_ACCE5sdriv); \2 361  
<4 hr12449PAT_H5tm/iphase/ipha/iphase.h#L353"value me="L337"> 337valued=iv = (/iphase.h#L353"_I_PM7345_Tss="cm_7 337 361  
<4 hr12450PAT_H5tm/iph}2 361  
<4 hr1245"driver12/atm/iphase.h#L391" id="12/at4Lor the ne4 name="L361"> 361  
<4 hr1245"driv2 361  
<4 hr1243"driveendife="+codSUNI_DS3_CBITVss="cIPHA12_H" id="12/at>1276ss="mine" name="L382"> 382C4for the ne4 name="L361"> 361  
<4 hr1244"driv


Thssorigie" nLXR softwarelbysthss>1276ss="http://sourceforge.net/projects/lxr">LXR 3_CBunity1276ss="mailto:lxr@"> ux.no">lxr@"> ux.no lxr."> ux.no kindly hosted bys>1276ss="http://www.redpill-"> pro.no">Redpillas0xpro AS