linux/drivers/ata/pdc_adma.c
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   1/*
   2 *  pdc_adma.c - Pacific Digital Corporation ADMA
   3 *
   4 *  Maintained by:  Mark Lord <mlord@pobox.com>
   5 *
   6 *  Copyright 2005 Mark Lord
   7 *
   8 *  This program is free software; you can redistribute it and/or modify
   9 *  it under the terms of the GNU General Public License as published by
  10 *  the Free Software Foundation; either version 2, or (at your option)
  11 *  any later version.
  12 *
  13 *  This program is distributed in the hope that it will be useful,
  14 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 *  GNU General Public License for more details.
  17 *
  18 *  You should have received a copy of the GNU General Public License
  19 *  along with this program; see the file COPYING.  If not, write to
  20 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  21 *
  22 *
  23 *  libata documentation is available via 'make {ps|pdf}docs',
  24 *  as Documentation/DocBook/libata.*
  25 *
  26 *
  27 *  Supports ATA disks in single-packet ADMA mode.
  28 *  Uses PIO for everything else.
  29 *
  30 *  TODO:  Use ADMA transfers for ATAPI devices, when possible.
  31 *  This requires careful attention to a number of quirks of the chip.
  32 *
  33 */
  34
  35#include <linux/kernel.h>
  36#include <linux/module.h>
  37#include <linux/gfp.h>
  38#include <linux/pci.h>
  39#include <linux/init.h>
  40#include <linux/blkdev.h>
  41#include <linux/delay.h>
  42#include <linux/interrupt.h>
  43#include <linux/device.h>
  44#include <scsi/scsi_host.h>
  45#include <linux/libata.h>
  46
  47#define DRV_NAME        "pdc_adma"
  48#define DRV_VERSION     "1.0"
  49
  50/* macro to calculate base address for ATA regs */
  51#define ADMA_ATA_REGS(base, port_no)    ((base) + ((port_no) * 0x40))
  52
  53/* macro to calculate base address for ADMA regs */
  54#define ADMA_REGS(base, port_no)        ((base) + 0x80 + ((port_no) * 0x20))
  55
  56/* macro to obtain addresses from ata_port */
  57#define ADMA_PORT_REGS(ap) \
  58        ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no)
  59
  60enum {
  61        ADMA_MMIO_BAR           = 4,
  62
  63        ADMA_PORTS              = 2,
  64        ADMA_CPB_BYTES          = 40,
  65        ADMA_PRD_BYTES          = LIBATA_MAX_PRD * 16,
  66        ADMA_PKT_BYTES          = ADMA_CPB_BYTES + ADMA_PRD_BYTES,
  67
  68        ADMA_DMA_BOUNDARY       = 0xffffffff,
  69
  70        /* global register offsets */
  71        ADMA_MODE_LOCK          = 0x00c7,
  72
  73        /* per-channel register offsets */
  74        ADMA_CONTROL            = 0x0000, /* ADMA control */
  75        ADMA_STATUS             = 0x0002, /* ADMA status */
  76        ADMA_CPB_COUNT          = 0x0004, /* CPB count */
  77        ADMA_CPB_CURRENT        = 0x000c, /* current CPB address */
  78        ADMA_CPB_NEXT           = 0x000c, /* next CPB address */
  79        ADMA_CPB_LOOKUP         = 0x0010, /* CPB lookup table */
  80        ADMA_FIFO_IN            = 0x0014, /* input FIFO threshold */
  81        ADMA_FIFO_OUT           = 0x0016, /* output FIFO threshold */
  82
  83        /* ADMA_CONTROL register bits */
  84        aNIEN                   = (1 << 8), /* irq mask: 1==masked */
  85        aGO                     = (1 << 7), /* packet trigger ("Go!") */
  86        aRSTADM                 = (1 << 5), /* ADMA logic reset */
  87        aPIOMD4                 = 0x0003,   /* PIO mode 4 */
  88
  89        /* ADMA_STATUS register bits */
  90        aPSD                    = (1 << 6),
  91        aUIRQ                   = (1 << 4),
  92        aPERR                   = (1 << 0),
  93
  94        /* CPB bits */
  95        cDONE                   = (1 << 0),
  96        cATERR                  = (1 << 3),
  97
  98        cVLD                    = (1 << 0),
  99        cDAT                    = (1 << 2),
 100        cIEN                    = (1 << 3),
 101
 102        /* PRD bits */
 103        pORD                    = (1 << 4),
 104        pDIRO                   = (1 << 5),
 105        pEND                    = (1 << 7),
 106
 107        /* ATA register flags */
 108        rIGN                    = (1 << 5),
 109        rEND                    = (1 << 7),
 110
 111        /* ATA register addresses */
 112        ADMA_REGS_CONTROL       = 0x0e,
 113        ADMA_REGS_SECTOR_COUNT  = 0x12,
 114        ADMA_REGS_LBA_LOW       = 0x13,
 115        ADMA_REGS_LBA_MID       = 0x14,
 116        ADMA_REGS_LBA_HIGH      = 0x15,
 117        ADMA_REGS_DEVICE        = 0x16,
 118        ADMA_REGS_COMMAND       = 0x17,
 119
 120        /* PCI device IDs */
 121        board_1841_idx          = 0,    /* ADMA 2-port controller */
 122};
 123
 124typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;
 125
 126struct adma_port_priv {
 127        u8                      *pkt;
 128        dma_addr_t              pkt_dma;
 129        adma_state_t            state;
 130};
 131
 132static int adma_ata_init_one(struct pci_dev *pdev,
 133                                const struct pci_device_id *ent);
 134static int adma_port_start(struct ata_port *ap);
 135static void adma_port_stop(struct ata_port *ap);
 136static void adma_qc_prep(struct ata_queued_cmd *qc);
 137static unsigned int adma_qc_issue(struct ata_queued_cmd *qc);
 138static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
 139static void adma_freeze(struct ata_port *ap);
 140static void adma_thaw(struct ata_port *ap);
 141static int adma_prereset(struct ata_link *link, unsigned long deadline);
 142
 143static struct scsi_host_template adma_ata_sht = {
 144        ATA_BASE_SHT(DRV_NAME),
 145        .sg_tablesize           = LIBATA_MAX_PRD,
 146        .dma_boundary           = ADMA_DMA_BOUNDARY,
 147};
 148
 149static struct ata_port_operations adma_ata_ops = {
 150        .inherits               = &ata_sff_port_ops,
 151
 152        .lost_interrupt         = ATA_OP_NULL,
 153
 154        .check_atapi_dma        = adma_check_atapi_dma,
 155        .qc_prep                = adma_qc_prep,
 156        .qc_issue               = adma_qc_issue,
 157
 158        .freeze                 = adma_freeze,
 159        .thaw                   = adma_thaw,
 160        .prereset               = adma_prereset,
 161
 162        .port_start             = adma_port_start,
 163        .port_stop              = adma_port_stop,
 164};
 165
 166static struct ata_port_info adma_port_info[] = {
 167        /* board_1841_idx */
 168        {
 169                .flags          = ATA_FLAG_SLAVE_POSS | ATA_FLAG_PIO_POLLING,
 170                .pio_mask       = ATA_PIO4_ONLY,
 171                .udma_mask      = ATA_UDMA4,
 172                .port_ops       = &adma_ata_ops,
 173        },
 174};
 175
 176static const struct pci_device_id adma_ata_pci_tbl[] = {
 177        { PCI_VDEVICE(PDC, 0x1841), board_1841_idx },
 178
 179        { }     /* terminate list */
 180};
 181
 182static struct pci_driver adma_ata_pci_driver = {
 183        .name                   = DRV_NAME,
 184        .id_table               = adma_ata_pci_tbl,
 185        .probe                  = adma_ata_init_one,
 186        .remove                 = ata_pci_remove_one,
 187};
 188
 189static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
 190{
 191        return 1;       /* ATAPI DMA not yet supported */
 192}
 193
 194static void adma_reset_engine(struct ata_port *ap)
 195{
 196        void __iomem *chan = ADMA_PORT_REGS(ap);
 197
 198        /* reset ADMA to idle state */
 199        writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
 200        udelay(2);
 201        writew(aPIOMD4, chan + ADMA_CONTROL);
 202        udelay(2);
 203}
 204
 205static void adma_reinit_engine(struct ata_port *ap)
 206{
 207        struct adma_port_priv *pp = ap->private_data;
 208        void __iomem *chan = ADMA_PORT_REGS(ap);
 209
 210        /* mask/clear ATA interrupts */
 211        writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
 212        ata_sff_check_status(ap);
 213
 214        /* reset the ADMA engine */
 215        adma_reset_engine(ap);
 216
 217        /* set in-FIFO threshold to 0x100 */
 218        writew(0x100, chan + ADMA_FIFO_IN);
 219
 220        /* set CPB pointer */
 221        writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);
 222
 223        /* set out-FIFO threshold to 0x100 */
 224        writew(0x100, chan + ADMA_FIFO_OUT);
 225
 226        /* set CPB count */
 227        writew(1, chan + ADMA_CPB_COUNT);
 228
 229        /* read/discard ADMA status */
 230        readb(chan + ADMA_STATUS);
 231}
 232
 233static inline void adma_enter_reg_mode(struct ata_port *ap)
 234{
 235        void __iomem *chan = ADMA_PORT_REGS(ap);
 236
 237        writew(aPIOMD4, chan + ADMA_CONTROL);
 238        readb(chan + ADMA_STATUS);      /* flush */
 239}
 240
 241static void adma_freeze(struct ata_port *ap)
 242{
 243        void __iomem *chan = ADMA_PORT_REGS(ap);
 244
 245        /* mask/clear ATA interrupts */
 246        writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
 247        ata_sff_check_status(ap);
 248
 249        /* reset ADMA to idle state */
 250        writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
 251        udelay(2);
 252        writew(aPIOMD4 | aNIEN, chan + ADMA_CONTROL);
 253        udelay(2);
 254}
 255
 256static void adma_thaw(struct ata_port *ap)
 257{
 258        adma_reinit_engine(ap);
 259}
 260
 261static int adma_prereset(struct ata_link *link, unsigned long deadline)
 262{
 263        struct ata_port *ap = link->ap;
 264        struct adma_port_priv *pp = ap->private_data;
 265
 266        if (pp->state != adma_state_idle) /* healthy paranoia */
 267                pp->state = adma_state_mmio;
 268        adma_reinit_engine(ap);
 269
 270        return ata_sff_prereset(link, deadline);
 271}
 272
 273static int adma_fill_sg(struct ata_queued_cmd *qc)
 274{
 275        struct scatterlist *sg;
 276        struct ata_port *ap = qc->ap;
 277        struct adma_port_priv *pp = ap->private_data;
 278        u8  *buf = pp->pkt, *last_buf = NULL;
 279        int i = (2 + buf[3]) * 8;
 280        u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
 281        unsigned int si;
 282
 283        for_each_sg(qc->sg, sg, qc->n_elem, si) {
 284                u32 addr;
 285                u32 len;
 286
 287                addr = (u32)sg_dma_address(sg);
 288                *(__le32 *)(buf + i) = cpu_to_le32(addr);
 289                i += 4;
 290
 291                len = sg_dma_len(sg) >> 3;
 292                *(__le32 *)(buf + i) = cpu_to_le32(len);
 293                i += 4;
 294
 295                last_buf = &buf[i];
 296                buf[i++] = pFLAGS;
 297                buf[i++] = qc->dev->dma_mode & 0xf;
 298                buf[i++] = 0;   /* pPKLW */
 299                buf[i++] = 0;   /* reserved */
 300
 301                *(__le32 *)(buf + i) =
 302                        (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
 303                i += 4;
 304
 305                VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4,
 306                                        (unsigned long)addr, len);
 307        }
 308
 309        if (likely(last_buf))
 310                *last_buf |= pEND;
 311
 312        return i;
 313}
 314
 315static void adma_qc_prep(struct ata_queued_cmd *qc)
 316{
 317        struct adma_port_priv *pp = qc->ap->private_data;
 318        u8  *buf = pp->pkt;
 319        u32 pkt_dma = (u32)pp->pkt_dma;
 320        int i = 0;
 321
 322        VPRINTK("ENTER\n");
 323
 324        adma_enter_reg_mode(qc->ap);
 325        if (qc->tf.protocol != ATA_PROT_DMA)
 326                return;
 327
 328        buf[i++] = 0;   /* Response flags */
 329        buf[i++] = 0;   /* reserved */
 330        buf[i++] = cVLD | cDAT | cIEN;
 331        i++;            /* cLEN, gets filled in below */
 332
 333        *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma);      /* cNCPB */
 334        i += 4;         /* cNCPB */
 335        i += 4;         /* cPRD, gets filled in below */
 336
 337        buf[i++] = 0;   /* reserved */
 338        buf[i++] = 0;   /* reserved */
 339        buf[i++] = 0;   /* reserved */
 340        buf[i++] = 0;   /* reserved */
 341
 342        /* ATA registers; must be a multiple of 4 */
 343        buf[i++] = qc->tf.device;
 344        buf[i++] = ADMA_REGS_DEVICE;
 345        if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
 346                buf[i++] = qc->tf.hob_nsect;
 347                buf[i++] = ADMA_REGS_SECTOR_COUNT;
 348                buf[i++] = qc->tf.hob_lbal;
 349                buf[i++] = ADMA_REGS_LBA_LOW;
 350                buf[i++] = qc->tf.hob_lbam;
 351                buf[i++] = ADMA_REGS_LBA_MID;
 352                buf[i++] = qc->tf.hob_lbah;
 353                buf[i++] = ADMA_REGS_LBA_HIGH;
 354        }
 355        buf[i++] = qc->tf.nsect;
 356        buf[i++] = ADMA_REGS_SECTOR_COUNT;
 357        buf[i++] = qc->tf.lbal;
 358        buf[i++] = ADMA_REGS_LBA_LOW;
 359        buf[i++] = qc->tf.lbam;
 360        buf[i++] = ADMA_REGS_LBA_MID;
 361        buf[i++] = qc->tf.lbah;
 362        buf[i++] = ADMA_REGS_LBA_HIGH;
 363        buf[i++] = 0;
 364        buf[i++] = ADMA_REGS_CONTROL;
 365        buf[i++] = rIGN;
 366        buf[i++] = 0;
 367        buf[i++] = qc->tf.command;
 368        buf[i++] = ADMA_REGS_COMMAND | rEND;
 369
 370        buf[3] = (i >> 3) - 2;                          /* cLEN */
 371        *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i);  /* cPRD */
 372
 373        i = adma_fill_sg(qc);
 374        wmb();  /* flush PRDs and pkt to memory */
 375#if 0
 376        /* dump out CPB + PRDs for debug */
 377        {
 378                int j, len = 0;
 379                static char obuf[2048];
 380                for (j = 0; j < i; ++j) {
 381                        len += sprintf(obuf+len, "%02x ", buf[j]);
 382                        if ((j & 7) == 7) {
 383                                printk("%s\n", obuf);
 384                                len = 0;
 385                        }
 386                }
 387                if (len)
 388                        printk("%s\n", obuf);
 389        }
 390#endif
 391}
 392
 393static inline void adma_packet_start(struct ata_queued_cmd *qc)
 394{
 395        struct ata_port *ap = qc->ap;
 396        void __iomem *chan = ADMA_PORT_REGS(ap);
 397
 398        VPRINTK("ENTER, ap %p\n", ap);
 399
 400        /* fire up the ADMA engine */
 401        writew(aPIOMD4 | aGO, chan + ADMA_CONTROL);
 402}
 403
 404static unsigned int adma_qc_issue(struct ata_queued_cmd *qc)
 405{
 406        struct adma_port_priv *pp = qc->ap->private_data;
 407
 408        switch (qc->tf.protocol) {
 409        case ATA_PROT_DMA:
 410                pp->state = adma_state_pkt;
 411                adma_packet_start(qc);
 412                return 0;
 413
 414        case ATAPI_PROT_DMA:
 415                BUG();
 416                break;
 417
 418        default:
 419                break;
 420        }
 421
 422        pp->state = adma_state_mmio;
 423        return ata_sff_qc_issue(qc);
 424}
 425
 426static inline unsigned int adma_intr_pkt(struct ata_host *host)
 427{
 428        unsigned int handled = 0, port_no;
 429
 430        for (port_no = 0; port_no < host->n_ports; ++port_no) {
 431                struct ata_port *ap = host->ports[port_no];
 432                struct adma_port_priv *pp;
 433                struct ata_queued_cmd *qc;
 434                void __iomem *chan = ADMA_PORT_REGS(ap);
 435                u8 status = readb(chan + ADMA_STATUS);
 436
 437                if (status == 0)
 438                        continue;
 439                handled = 1;
 440                adma_enter_reg_mode(ap);
 441                pp = ap->private_data;
 442                if (!pp || pp->state != adma_state_pkt)
 443                        continue;
 444                qc = ata_qc_from_tag(ap, ap->link.active_tag);
 445                if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
 446                        if (status & aPERR)
 447                                qc->err_mask |= AC_ERR_HOST_BUS;
 448                        else if ((status & (aPSD | aUIRQ)))
 449                                qc->err_mask |= AC_ERR_OTHER;
 450
 451                        if (pp->pkt[0] & cATERR)
 452                                qc->err_mask |= AC_ERR_DEV;
 453                        else if (pp->pkt[0] != cDONE)
 454                                qc->err_mask |= AC_ERR_OTHER;
 455
 456                        if (!qc->err_mask)
 457                                ata_qc_complete(qc);
 458                        else {
 459                                struct ata_eh_info *ehi = &ap->link.eh_info;
 460                                ata_ehi_clear_desc(ehi);
 461                                ata_ehi_push_desc(ehi,
 462                                        "ADMA-status 0x%02X", status);
 463                                ata_ehi_push_desc(ehi,
 464                                        "pkt[0] 0x%02X", pp->pkt[0]);
 465
 466                                if (qc->err_mask == AC_ERR_DEV)
 467                                        ata_port_abort(ap);
 468                                else
 469                                        ata_port_freeze(ap);
 470                        }
 471                }
 472        }
 473        return handled;
 474}
 475
 476static inline unsigned int adma_intr_mmio(struct ata_host *host)
 477{
 478        unsigned int handled = 0, port_no;
 479
 480        for (port_no = 0; port_no < host->n_ports; ++port_no) {
 481                struct ata_port *ap = host->ports[port_no];
 482                struct adma_port_priv *pp = ap->private_data;
 483                struct ata_queued_cmd *qc;
 484
 485                if (!pp || pp->state != adma_state_mmio)
 486                        continue;
 487                qc = ata_qc_from_tag(ap, ap->link.active_tag);
 488                if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
 489
 490                        /* check main status, clearing INTRQ */
 491                        u8 status = ata_sff_check_status(ap);
 492                        if ((status & ATA_BUSY))
 493                                continue;
 494                        DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
 495                                ap->print_id, qc->tf.protocol, status);
 496
 497                        /* complete taskfile transaction */
 498                        pp->state = adma_state_idle;
 499                        qc->err_mask |= ac_err_mask(status);
 500                        if (!qc->err_mask)
 501                                ata_qc_complete(qc);
 502                        else {
 503                                struct ata_eh_info *ehi = &ap->link.eh_info;
 504                                ata_ehi_clear_desc(ehi);
 505                                ata_ehi_push_desc(ehi, "status 0x%02X", status);
 506
 507                                if (qc->err_mask == AC_ERR_DEV)
 508                                        ata_port_abort(ap);
 509                                else
 510                                        ata_port_freeze(ap);
 511                        }
 512                        handled = 1;
 513                }
 514        }
 515        return handled;
 516}
 517
 518static irqreturn_t adma_intr(int irq, void *dev_instance)
 519{
 520        struct ata_host *host = dev_instance;
 521        unsigned int handled = 0;
 522
 523        VPRINTK("ENTER\n");
 524
 525        spin_lock(&host->lock);
 526        handled  = adma_intr_pkt(host) | adma_intr_mmio(host);
 527        spin_unlock(&host->lock);
 528
 529        VPRINTK("EXIT\n");
 530
 531        return IRQ_RETVAL(handled);
 532}
 533
 534static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base)
 535{
 536        port->cmd_addr          =
 537        port->data_addr         = base + 0x000;
 538        port->error_addr        =
 539        port->feature_addr      = base + 0x004;
 540        port->nsect_addr        = base + 0x008;
 541        port->lbal_addr         = base + 0x00c;
 542        port->lbam_addr         = base + 0x010;
 543        port->lbah_addr         = base + 0x014;
 544        port->device_addr       = base + 0x018;
 545        port->status_addr       =
 546        port->command_addr      = base + 0x01c;
 547        port->altstatus_addr    =
 548        port->ctl_addr          = base + 0x038;
 549}
 550
 551static int adma_port_start(struct ata_port *ap)
 552{
 553        struct device *dev = ap->host->dev;
 554        struct adma_port_priv *pp;
 555
 556        adma_enter_reg_mode(ap);
 557        pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
 558        if (!pp)
 559                return -ENOMEM;
 560        pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
 561                                      GFP_KERNEL);
 562        if (!pp->pkt)
 563                return -ENOMEM;
 564        /* paranoia? */
 565        if ((pp->pkt_dma & 7) != 0) {
 566                printk(KERN_ERR "bad alignment for pp->pkt_dma: %08x\n",
 567                                                (u32)pp->pkt_dma);
 568                return -ENOMEM;
 569        }
 570        memset(pp->pkt, 0, ADMA_PKT_BYTES);
 571        ap->private_data = pp;
 572        adma_reinit_engine(ap);
 573        return 0;
 574}
 575
 576static void adma_port_stop(struct ata_port *ap)
 577{
 578        adma_reset_engine(ap);
 579}
 580
 581static void adma_host_init(struct ata_host *host, unsigned int chip_id)
 582{
 583        unsigned int port_no;
 584
 585        /* enable/lock aGO operation */
 586        writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK);
 587
 588        /* reset the ADMA logic */
 589        for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
 590                adma_reset_engine(host->ports[port_no]);
 591}
 592
 593static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
 594{
 595        int rc;
 596
 597        rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 598        if (rc) {
 599                dev_err(&pdev->dev, "32-bit DMA enable failed\n");
 600                return rc;
 601        }
 602        rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 603        if (rc) {
 604                dev_err(&pdev->dev, "32-bit consistent DMA enable failed\n");
 605                return rc;
 606        }
 607        return 0;
 608}
 609
 610static int adma_ata_init_one(struct pci_dev *pdev,
 611                             const struct pci_device_id *ent)
 612{
 613        unsigned int board_idx = (unsigned int) ent->driver_data;
 614        const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL };
 615        struct ata_host *host;
 616        void __iomem *mmio_base;
 617        int rc, port_no;
 618
 619        ata_print_version_once(&pdev->dev, DRV_VERSION);
 620
 621        /* alloc host */
 622        host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS);
 623        if (!host)
 624                return -ENOMEM;
 625
 626        /* acquire resources and fill host */
 627        rc = pcim_enable_device(pdev);
 628        if (rc)
 629                return rc;
 630
 631        if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0)
 632                return -ENODEV;
 633
 634        rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME);
 635        if (rc)
 636                return rc;
 637        host->iomap = pcim_iomap_table(pdev);
 638        mmio_base = host->iomap[ADMA_MMIO_BAR];
 639
 640        rc = adma_set_dma_masks(pdev, mmio_base);
 641        if (rc)
 642                return rc;
 643
 644        for (port_no = 0; port_no < ADMA_PORTS; ++port_no) {
 645                struct ata_port *ap = host->ports[port_no];
 646                void __iomem *port_base = ADMA_ATA_REGS(mmio_base, port_no);
 647                unsigned int offset = port_base - mmio_base;
 648
 649                adma_ata_setup_port(&ap->ioaddr, port_base);
 650
 651                ata_port_pbar_desc(ap, ADMA_MMIO_BAR, -1, "mmio");
 652                ata_port_pbar_desc(ap, ADMA_MMIO_BAR, offset, "port");
 653        }
 654
 655        /* initialize adapter */
 656        adma_host_init(host, board_idx);
 657
 658        pci_set_master(pdev);
 659        return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED,
 660                                 &adma_ata_sht);
 661}
 662
 663module_pci_driver(adma_ata_pci_driver);
 664
 665MODULE_AUTHOR("Mark Lord");
 666MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
 667MODULE_LICENSE("GPL");
 668MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
 669MODULE_VERSION(DRV_VERSION);
 670
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