linux/drivers/ata/pata_legacy.c
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   1/*
   2 *   pata-legacy.c - Legacy port PATA/SATA controller driver.
   3 *   Copyright 2005/2006 Red Hat, all rights reserved.
   4 *
   5 *  This program is free software; you can redistribute it and/or modify
   6 *  it under the terms of the GNU General Public License as published by
   7 *  the Free Software Foundation; either version 2, or (at your option)
   8 *  any later version.
   9 *
  10 *  This program is distributed in the hope that it will be useful,
  11 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 *  GNU General Public License for more details.
  14 *
  15 *  You should have received a copy of the GNU General Public License
  16 *  along with this program; see the file COPYING.  If not, write to
  17 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  18 *
  19 *   An ATA driver for the legacy ATA ports.
  20 *
  21 *   Data Sources:
  22 *      Opti 82C465/82C611 support: Data sheets at opti-inc.com
  23 *      HT6560 series:
  24 *      Promise 20230/20620:
  25 *              http://www.ryston.cz/petr/vlb/pdc20230b.html
  26 *              http://www.ryston.cz/petr/vlb/pdc20230c.html
  27 *              http://www.ryston.cz/petr/vlb/pdc20630.html
  28 *      QDI65x0:
  29 *              http://www.ryston.cz/petr/vlb/qd6500.html
  30 *              http://www.ryston.cz/petr/vlb/qd6580.html
  31 *
  32 *      QDI65x0 probe code based on drivers/ide/legacy/qd65xx.c
  33 *      Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by
  34 *      Samuel Thibault <samuel.thibault@ens-lyon.org>
  35 *
  36 *  Unsupported but docs exist:
  37 *      Appian/Adaptec AIC25VL01/Cirrus Logic PD7220
  38 *
  39 *  This driver handles legacy (that is "ISA/VLB side") IDE ports found
  40 *  on PC class systems. There are three hybrid devices that are exceptions
  41 *  The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and
  42 *  the MPIIX where the tuning is PCI side but the IDE is "ISA side".
  43 *
  44 *  Specific support is included for the ht6560a/ht6560b/opti82c611a/
  45 *  opti82c465mv/promise 20230c/20630/qdi65x0/winbond83759A
  46 *
  47 *  Support for the Winbond 83759A when operating in advanced mode.
  48 *  Multichip mode is not currently supported.
  49 *
  50 *  Use the autospeed and pio_mask options with:
  51 *      Appian ADI/2 aka CLPD7220 or AIC25VL01.
  52 *  Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with
  53 *      Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759,
  54 *      Winbond W83759A, Promise PDC20230-B
  55 *
  56 *  For now use autospeed and pio_mask as above with the W83759A. This may
  57 *  change.
  58 *
  59 */
  60
  61#include <linux/async.h>
  62#include <linux/kernel.h>
  63#include <linux/module.h>
  64#include <linux/pci.h>
  65#include <linux/init.h>
  66#include <linux/blkdev.h>
  67#include <linux/delay.h>
  68#include <scsi/scsi_host.h>
  69#include <linux/ata.h>
  70#include <linux/libata.h>
  71#include <linux/platform_device.h>
  72
  73#define DRV_NAME "pata_legacy"
  74#define DRV_VERSION "0.6.5"
  75
  76#define NR_HOST 6
  77
  78static int all;
  79module_param(all, int, 0444);
  80MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)");
  81
  82enum controller {
  83        BIOS = 0,
  84        SNOOP = 1,
  85        PDC20230 = 2,
  86        HT6560A = 3,
  87        HT6560B = 4,
  88        OPTI611A = 5,
  89        OPTI46X = 6,
  90        QDI6500 = 7,
  91        QDI6580 = 8,
  92        QDI6580DP = 9,          /* Dual channel mode is different */
  93        W83759A = 10,
  94
  95        UNKNOWN = -1
  96};
  97
  98struct legacy_data {
  99        unsigned long timing;
 100        u8 clock[2];
 101        u8 last;
 102        int fast;
 103        enum controller type;
 104        struct platform_device *platform_dev;
 105};
 106
 107struct legacy_probe {
 108        unsigned char *name;
 109        unsigned long port;
 110        unsigned int irq;
 111        unsigned int slot;
 112        enum controller type;
 113        unsigned long private;
 114};
 115
 116struct legacy_controller {
 117        const char *name;
 118        struct ata_port_operations *ops;
 119        unsigned int pio_mask;
 120        unsigned int flags;
 121        unsigned int pflags;
 122        int (*setup)(struct platform_device *, struct legacy_probe *probe,
 123                struct legacy_data *data);
 124};
 125
 126static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
 127
 128static struct legacy_probe probe_list[NR_HOST];
 129static struct legacy_data legacy_data[NR_HOST];
 130static struct ata_host *legacy_host[NR_HOST];
 131static int nr_legacy_host;
 132
 133
 134static int probe_all;           /* Set to check all ISA port ranges */
 135static int ht6560a;             /* HT 6560A on primary 1, second 2, both 3 */
 136static int ht6560b;             /* HT 6560A on primary 1, second 2, both 3 */
 137static int opti82c611a;         /* Opti82c611A on primary 1, sec 2, both 3 */
 138static int opti82c46x;          /* Opti 82c465MV present(pri/sec autodetect) */
 139static int autospeed;           /* Chip present which snoops speed changes */
 140static int pio_mask = ATA_PIO4; /* PIO range for autospeed devices */
 141static int iordy_mask = 0xFFFFFFFF;     /* Use iordy if available */
 142
 143/* Set to probe QDI controllers */
 144#ifdef CONFIG_PATA_QDI_MODULE
 145static int qdi = 1;
 146#else
 147static int qdi;
 148#endif
 149
 150#ifdef CONFIG_PATA_WINBOND_VLB_MODULE
 151static int winbond = 1;         /* Set to probe Winbond controllers,
 152                                        give I/O port if non standard */
 153#else
 154static int winbond;             /* Set to probe Winbond controllers,
 155                                        give I/O port if non standard */
 156#endif
 157
 158/**
 159 *      legacy_probe_add        -       Add interface to probe list
 160 *      @port: Controller port
 161 *      @irq: IRQ number
 162 *      @type: Controller type
 163 *      @private: Controller specific info
 164 *
 165 *      Add an entry into the probe list for ATA controllers. This is used
 166 *      to add the default ISA slots and then to build up the table
 167 *      further according to other ISA/VLB/Weird device scans
 168 *
 169 *      An I/O port list is used to keep ordering stable and sane, as we
 170 *      don't have any good way to talk about ordering otherwise
 171 */
 172
 173static int legacy_probe_add(unsigned long port, unsigned int irq,
 174                                enum controller type, unsigned long private)
 175{
 176        struct legacy_probe *lp = &probe_list[0];
 177        int i;
 178        struct legacy_probe *free = NULL;
 179
 180        for (i = 0; i < NR_HOST; i++) {
 181                if (lp->port == 0 && free == NULL)
 182                        free = lp;
 183                /* Matching port, or the correct slot for ordering */
 184                if (lp->port == port || legacy_port[i] == port) {
 185                        free = lp;
 186                        break;
 187                }
 188                lp++;
 189        }
 190        if (free == NULL) {
 191                printk(KERN_ERR "pata_legacy: Too many interfaces.\n");
 192                return -1;
 193        }
 194        /* Fill in the entry for later probing */
 195        free->port = port;
 196        free->irq = irq;
 197        free->type = type;
 198        free->private = private;
 199        return 0;
 200}
 201
 202
 203/**
 204 *      legacy_set_mode         -       mode setting
 205 *      @link: IDE link
 206 *      @unused: Device that failed when error is returned
 207 *
 208 *      Use a non standard set_mode function. We don't want to be tuned.
 209 *
 210 *      The BIOS configured everything. Our job is not to fiddle. Just use
 211 *      whatever PIO the hardware is using and leave it at that. When we
 212 *      get some kind of nice user driven API for control then we can
 213 *      expand on this as per hdparm in the base kernel.
 214 */
 215
 216static int legacy_set_mode(struct ata_link *link, struct ata_device **unused)
 217{
 218        struct ata_device *dev;
 219
 220        ata_for_each_dev(dev, link, ENABLED) {
 221                ata_dev_info(dev, "configured for PIO\n");
 222                dev->pio_mode = XFER_PIO_0;
 223                dev->xfer_mode = XFER_PIO_0;
 224                dev->xfer_shift = ATA_SHIFT_PIO;
 225                dev->flags |= ATA_DFLAG_PIO;
 226        }
 227        return 0;
 228}
 229
 230static struct scsi_host_template legacy_sht = {
 231        ATA_PIO_SHT(DRV_NAME),
 232};
 233
 234static const struct ata_port_operations legacy_base_port_ops = {
 235        .inherits       = &ata_sff_port_ops,
 236        .cable_detect   = ata_cable_40wire,
 237};
 238
 239/*
 240 *      These ops are used if the user indicates the hardware
 241 *      snoops the commands to decide on the mode and handles the
 242 *      mode selection "magically" itself. Several legacy controllers
 243 *      do this. The mode range can be set if it is not 0x1F by setting
 244 *      pio_mask as well.
 245 */
 246
 247static struct ata_port_operations simple_port_ops = {
 248        .inherits       = &legacy_base_port_ops,
 249        .sff_data_xfer  = ata_sff_data_xfer_noirq,
 250};
 251
 252static struct ata_port_operations legacy_port_ops = {
 253        .inherits       = &legacy_base_port_ops,
 254        .sff_data_xfer  = ata_sff_data_xfer_noirq,
 255        .set_mode       = legacy_set_mode,
 256};
 257
 258/*
 259 *      Promise 20230C and 20620 support
 260 *
 261 *      This controller supports PIO0 to PIO2. We set PIO timings
 262 *      conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA
 263 *      support is weird being DMA to controller and PIO'd to the host
 264 *      and not supported.
 265 */
 266
 267static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)
 268{
 269        int tries = 5;
 270        int pio = adev->pio_mode - XFER_PIO_0;
 271        u8 rt;
 272        unsigned long flags;
 273
 274        /* Safe as UP only. Force I/Os to occur together */
 275
 276        local_irq_save(flags);
 277
 278        /* Unlock the control interface */
 279        do {
 280                inb(0x1F5);
 281                outb(inb(0x1F2) | 0x80, 0x1F2);
 282                inb(0x1F2);
 283                inb(0x3F6);
 284                inb(0x3F6);
 285                inb(0x1F2);
 286                inb(0x1F2);
 287        }
 288        while ((inb(0x1F2) & 0x80) && --tries);
 289
 290        local_irq_restore(flags);
 291
 292        outb(inb(0x1F4) & 0x07, 0x1F4);
 293
 294        rt = inb(0x1F3);
 295        rt &= 0x07 << (3 * adev->devno);
 296        if (pio)
 297                rt |= (1 + 3 * pio) << (3 * adev->devno);
 298
 299        udelay(100);
 300        outb(inb(0x1F2) | 0x01, 0x1F2);
 301        udelay(100);
 302        inb(0x1F5);
 303
 304}
 305
 306static unsigned int pdc_data_xfer_vlb(struct ata_device *dev,
 307                        unsigned char *buf, unsigned int buflen, int rw)
 308{
 309        int slop = buflen & 3;
 310        struct ata_port *ap = dev->link->ap;
 311
 312        /* 32bit I/O capable *and* we need to write a whole number of dwords */
 313        if (ata_id_has_dword_io(dev->id) && (slop == 0 || slop == 3)
 314                                        && (ap->pflags & ATA_PFLAG_PIO32)) {
 315                unsigned long flags;
 316
 317                local_irq_save(flags);
 318
 319                /* Perform the 32bit I/O synchronization sequence */
 320                ioread8(ap->ioaddr.nsect_addr);
 321                ioread8(ap->ioaddr.nsect_addr);
 322                ioread8(ap->ioaddr.nsect_addr);
 323
 324                /* Now the data */
 325                if (rw == READ)
 326                        ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
 327                else
 328                        iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
 329
 330                if (unlikely(slop)) {
 331                        __le32 pad;
 332                        if (rw == READ) {
 333                                pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
 334                                memcpy(buf + buflen - slop, &pad, slop);
 335                        } else {
 336                                memcpy(&pad, buf + buflen - slop, slop);
 337                                iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
 338                        }
 339                        buflen += 4 - slop;
 340                }
 341                local_irq_restore(flags);
 342        } else
 343                buflen = ata_sff_data_xfer_noirq(dev, buf, buflen, rw);
 344
 345        return buflen;
 346}
 347
 348static struct ata_port_operations pdc20230_port_ops = {
 349        .inherits       = &legacy_base_port_ops,
 350        .set_piomode    = pdc20230_set_piomode,
 351        .sff_data_xfer  = pdc_data_xfer_vlb,
 352};
 353
 354/*
 355 *      Holtek 6560A support
 356 *
 357 *      This controller supports PIO0 to PIO2 (no IORDY even though higher
 358 *      timings can be loaded).
 359 */
 360
 361static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev)
 362{
 363        u8 active, recover;
 364        struct ata_timing t;
 365
 366        /* Get the timing data in cycles. For now play safe at 50Mhz */
 367        ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
 368
 369        active = clamp_val(t.active, 2, 15);
 370        recover = clamp_val(t.recover, 4, 15);
 371
 372        inb(0x3E6);
 373        inb(0x3E6);
 374        inb(0x3E6);
 375        inb(0x3E6);
 376
 377        iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
 378        ioread8(ap->ioaddr.status_addr);
 379}
 380
 381static struct ata_port_operations ht6560a_port_ops = {
 382        .inherits       = &legacy_base_port_ops,
 383        .set_piomode    = ht6560a_set_piomode,
 384};
 385
 386/*
 387 *      Holtek 6560B support
 388 *
 389 *      This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO
 390 *      setting unless we see an ATAPI device in which case we force it off.
 391 *
 392 *      FIXME: need to implement 2nd channel support.
 393 */
 394
 395static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev)
 396{
 397        u8 active, recover;
 398        struct ata_timing t;
 399
 400        /* Get the timing data in cycles. For now play safe at 50Mhz */
 401        ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
 402
 403        active = clamp_val(t.active, 2, 15);
 404        recover = clamp_val(t.recover, 2, 16) & 0x0F;
 405
 406        inb(0x3E6);
 407        inb(0x3E6);
 408        inb(0x3E6);
 409        inb(0x3E6);
 410
 411        iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
 412
 413        if (adev->class != ATA_DEV_ATA) {
 414                u8 rconf = inb(0x3E6);
 415                if (rconf & 0x24) {
 416                        rconf &= ~0x24;
 417                        outb(rconf, 0x3E6);
 418                }
 419        }
 420        ioread8(ap->ioaddr.status_addr);
 421}
 422
 423static struct ata_port_operations ht6560b_port_ops = {
 424        .inherits       = &legacy_base_port_ops,
 425        .set_piomode    = ht6560b_set_piomode,
 426};
 427
 428/*
 429 *      Opti core chipset helpers
 430 */
 431
 432/**
 433 *      opti_syscfg     -       read OPTI chipset configuration
 434 *      @reg: Configuration register to read
 435 *
 436 *      Returns the value of an OPTI system board configuration register.
 437 */
 438
 439static u8 opti_syscfg(u8 reg)
 440{
 441        unsigned long flags;
 442        u8 r;
 443
 444        /* Uniprocessor chipset and must force cycles adjancent */
 445        local_irq_save(flags);
 446        outb(reg, 0x22);
 447        r = inb(0x24);
 448        local_irq_restore(flags);
 449        return r;
 450}
 451
 452/*
 453 *      Opti 82C611A
 454 *
 455 *      This controller supports PIO0 to PIO3.
 456 */
 457
 458static void opti82c611a_set_piomode(struct ata_port *ap,
 459                                                struct ata_device *adev)
 460{
 461        u8 active, recover, setup;
 462        struct ata_timing t;
 463        struct ata_device *pair = ata_dev_pair(adev);
 464        int clock;
 465        int khz[4] = { 50000, 40000, 33000, 25000 };
 466        u8 rc;
 467
 468        /* Enter configuration mode */
 469        ioread16(ap->ioaddr.error_addr);
 470        ioread16(ap->ioaddr.error_addr);
 471        iowrite8(3, ap->ioaddr.nsect_addr);
 472
 473        /* Read VLB clock strapping */
 474        clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03];
 475
 476        /* Get the timing data in cycles */
 477        ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
 478
 479        /* Setup timing is shared */
 480        if (pair) {
 481                struct ata_timing tp;
 482                ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
 483
 484                ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
 485        }
 486
 487        active = clamp_val(t.active, 2, 17) - 2;
 488        recover = clamp_val(t.recover, 1, 16) - 1;
 489        setup = clamp_val(t.setup, 1, 4) - 1;
 490
 491        /* Select the right timing bank for write timing */
 492        rc = ioread8(ap->ioaddr.lbal_addr);
 493        rc &= 0x7F;
 494        rc |= (adev->devno << 7);
 495        iowrite8(rc, ap->ioaddr.lbal_addr);
 496
 497        /* Write the timings */
 498        iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
 499
 500        /* Select the right bank for read timings, also
 501           load the shared timings for address */
 502        rc = ioread8(ap->ioaddr.device_addr);
 503        rc &= 0xC0;
 504        rc |= adev->devno;      /* Index select */
 505        rc |= (setup << 4) | 0x04;
 506        iowrite8(rc, ap->ioaddr.device_addr);
 507
 508        /* Load the read timings */
 509        iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
 510
 511        /* Ensure the timing register mode is right */
 512        rc = ioread8(ap->ioaddr.lbal_addr);
 513        rc &= 0x73;
 514        rc |= 0x84;
 515        iowrite8(rc, ap->ioaddr.lbal_addr);
 516
 517        /* Exit command mode */
 518        iowrite8(0x83,  ap->ioaddr.nsect_addr);
 519}
 520
 521
 522static struct ata_port_operations opti82c611a_port_ops = {
 523        .inherits       = &legacy_base_port_ops,
 524        .set_piomode    = opti82c611a_set_piomode,
 525};
 526
 527/*
 528 *      Opti 82C465MV
 529 *
 530 *      This controller supports PIO0 to PIO3. Unlike the 611A the MVB
 531 *      version is dual channel but doesn't have a lot of unique registers.
 532 */
 533
 534static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev)
 535{
 536        u8 active, recover, setup;
 537        struct ata_timing t;
 538        struct ata_device *pair = ata_dev_pair(adev);
 539        int clock;
 540        int khz[4] = { 50000, 40000, 33000, 25000 };
 541        u8 rc;
 542        u8 sysclk;
 543
 544        /* Get the clock */
 545        sysclk = opti_syscfg(0xAC) & 0xC0;      /* BIOS set */
 546
 547        /* Enter configuration mode */
 548        ioread16(ap->ioaddr.error_addr);
 549        ioread16(ap->ioaddr.error_addr);
 550        iowrite8(3, ap->ioaddr.nsect_addr);
 551
 552        /* Read VLB clock strapping */
 553        clock = 1000000000 / khz[sysclk];
 554
 555        /* Get the timing data in cycles */
 556        ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
 557
 558        /* Setup timing is shared */
 559        if (pair) {
 560                struct ata_timing tp;
 561                ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
 562
 563                ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
 564        }
 565
 566        active = clamp_val(t.active, 2, 17) - 2;
 567        recover = clamp_val(t.recover, 1, 16) - 1;
 568        setup = clamp_val(t.setup, 1, 4) - 1;
 569
 570        /* Select the right timing bank for write timing */
 571        rc = ioread8(ap->ioaddr.lbal_addr);
 572        rc &= 0x7F;
 573        rc |= (adev->devno << 7);
 574        iowrite8(rc, ap->ioaddr.lbal_addr);
 575
 576        /* Write the timings */
 577        iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
 578
 579        /* Select the right bank for read timings, also
 580           load the shared timings for address */
 581        rc = ioread8(ap->ioaddr.device_addr);
 582        rc &= 0xC0;
 583        rc |= adev->devno;      /* Index select */
 584        rc |= (setup << 4) | 0x04;
 585        iowrite8(rc, ap->ioaddr.device_addr);
 586
 587        /* Load the read timings */
 588        iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
 589
 590        /* Ensure the timing register mode is right */
 591        rc = ioread8(ap->ioaddr.lbal_addr);
 592        rc &= 0x73;
 593        rc |= 0x84;
 594        iowrite8(rc, ap->ioaddr.lbal_addr);
 595
 596        /* Exit command mode */
 597        iowrite8(0x83,  ap->ioaddr.nsect_addr);
 598
 599        /* We need to know this for quad device on the MVB */
 600        ap->host->private_data = ap;
 601}
 602
 603/**
 604 *      opt82c465mv_qc_issue            -       command issue
 605 *      @qc: command pending
 606 *
 607 *      Called when the libata layer is about to issue a command. We wrap
 608 *      this interface so that we can load the correct ATA timings. The
 609 *      MVB has a single set of timing registers and these are shared
 610 *      across channels. As there are two registers we really ought to
 611 *      track the last two used values as a sort of register window. For
 612 *      now we just reload on a channel switch. On the single channel
 613 *      setup this condition never fires so we do nothing extra.
 614 *
 615 *      FIXME: dual channel needs ->serialize support
 616 */
 617
 618static unsigned int opti82c46x_qc_issue(struct ata_queued_cmd *qc)
 619{
 620        struct ata_port *ap = qc->ap;
 621        struct ata_device *adev = qc->dev;
 622
 623        /* If timings are set and for the wrong channel (2nd test is
 624           due to a libata shortcoming and will eventually go I hope) */
 625        if (ap->host->private_data != ap->host
 626            && ap->host->private_data != NULL)
 627                opti82c46x_set_piomode(ap, adev);
 628
 629        return ata_sff_qc_issue(qc);
 630}
 631
 632static struct ata_port_operations opti82c46x_port_ops = {
 633        .inherits       = &legacy_base_port_ops,
 634        .set_piomode    = opti82c46x_set_piomode,
 635        .qc_issue       = opti82c46x_qc_issue,
 636};
 637
 638/**
 639 *      qdi65x0_set_piomode             -       PIO setup for QDI65x0
 640 *      @ap: Port
 641 *      @adev: Device
 642 *
 643 *      In single channel mode the 6580 has one clock per device and we can
 644 *      avoid the requirement to clock switch. We also have to load the timing
 645 *      into the right clock according to whether we are master or slave.
 646 *
 647 *      In dual channel mode the 6580 has one clock per channel and we have
 648 *      to software clockswitch in qc_issue.
 649 */
 650
 651static void qdi65x0_set_piomode(struct ata_port *ap, struct ata_device *adev)
 652{
 653        struct ata_timing t;
 654        struct legacy_data *ld_qdi = ap->host->private_data;
 655        int active, recovery;
 656        u8 timing;
 657
 658        /* Get the timing data in cycles */
 659        ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
 660
 661        if (ld_qdi->fast) {
 662                active = 8 - clamp_val(t.active, 1, 8);
 663                recovery = 18 - clamp_val(t.recover, 3, 18);
 664        } else {
 665                active = 9 - clamp_val(t.active, 2, 9);
 666                recovery = 15 - clamp_val(t.recover, 0, 15);
 667        }
 668        timing = (recovery << 4) | active | 0x08;
 669        ld_qdi->clock[adev->devno] = timing;
 670
 671        if (ld_qdi->type == QDI6580)
 672                outb(timing, ld_qdi->timing + 2 * adev->devno);
 673        else
 674                outb(timing, ld_qdi->timing + 2 * ap->port_no);
 675
 676        /* Clear the FIFO */
 677        if (ld_qdi->type != QDI6500 && adev->class != ATA_DEV_ATA)
 678                outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3);
 679}
 680
 681/**
 682 *      qdi_qc_issue            -       command issue
 683 *      @qc: command pending
 684 *
 685 *      Called when the libata layer is about to issue a command. We wrap
 686 *      this interface so that we can load the correct ATA timings.
 687 */
 688
 689static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc)
 690{
 691        struct ata_port *ap = qc->ap;
 692        struct ata_device *adev = qc->dev;
 693        struct legacy_data *ld_qdi = ap->host->private_data;
 694
 695        if (ld_qdi->clock[adev->devno] != ld_qdi->last) {
 696                if (adev->pio_mode) {
 697                        ld_qdi->last = ld_qdi->clock[adev->devno];
 698                        outb(ld_qdi->clock[adev->devno], ld_qdi->timing +
 699                                                        2 * ap->port_no);
 700                }
 701        }
 702        return ata_sff_qc_issue(qc);
 703}
 704
 705static unsigned int vlb32_data_xfer(struct ata_device *adev, unsigned char *buf,
 706                                        unsigned int buflen, int rw)
 707{
 708        struct ata_port *ap = adev->link->ap;
 709        int slop = buflen & 3;
 710
 711        if (ata_id_has_dword_io(adev->id) && (slop == 0 || slop == 3)
 712                                        && (ap->pflags & ATA_PFLAG_PIO32)) {
 713                if (rw == WRITE)
 714                        iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
 715                else
 716                        ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
 717
 718                if (unlikely(slop)) {
 719                        __le32 pad;
 720                        if (rw == WRITE) {
 721                                memcpy(&pad, buf + buflen - slop, slop);
 722                                iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
 723                        } else {
 724                                pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
 725                                memcpy(buf + buflen - slop, &pad, slop);
 726                        }
 727                }
 728                return (buflen + 3) & ~3;
 729        } else
 730                return ata_sff_data_xfer(adev, buf, buflen, rw);
 731}
 732
 733static int qdi_port(struct platform_device *dev,
 734                        struct legacy_probe *lp, struct legacy_data *ld)
 735{
 736        if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL)
 737                return -EBUSY;
 738        ld->timing = lp->private;
 739        return 0;
 740}
 741
 742static struct ata_port_operations qdi6500_port_ops = {
 743        .inherits       = &legacy_base_port_ops,
 744        .set_piomode    = qdi65x0_set_piomode,
 745        .qc_issue       = qdi_qc_issue,
 746        .sff_data_xfer  = vlb32_data_xfer,
 747};
 748
 749static struct ata_port_operations qdi6580_port_ops = {
 750        .inherits       = &legacy_base_port_ops,
 751        .set_piomode    = qdi65x0_set_piomode,
 752        .sff_data_xfer  = vlb32_data_xfer,
 753};
 754
 755static struct ata_port_operations qdi6580dp_port_ops = {
 756        .inherits       = &legacy_base_port_ops,
 757        .set_piomode    = qdi65x0_set_piomode,
 758        .qc_issue       = qdi_qc_issue,
 759        .sff_data_xfer  = vlb32_data_xfer,
 760};
 761
 762static DEFINE_SPINLOCK(winbond_lock);
 763
 764static void winbond_writecfg(unsigned long port, u8 reg, u8 val)
 765{
 766        unsigned long flags;
 767        spin_lock_irqsave(&winbond_lock, flags);
 768        outb(reg, port + 0x01);
 769        outb(val, port + 0x02);
 770        spin_unlock_irqrestore(&winbond_lock, flags);
 771}
 772
 773static u8 winbond_readcfg(unsigned long port, u8 reg)
 774{
 775        u8 val;
 776
 777        unsigned long flags;
 778        spin_lock_irqsave(&winbond_lock, flags);
 779        outb(reg, port + 0x01);
 780        val = inb(port + 0x02);
 781        spin_unlock_irqrestore(&winbond_lock, flags);
 782
 783        return val;
 784}
 785
 786static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev)
 787{
 788        struct ata_timing t;
 789        struct legacy_data *ld_winbond = ap->host->private_data;
 790        int active, recovery;
 791        u8 reg;
 792        int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2);
 793
 794        reg = winbond_readcfg(ld_winbond->timing, 0x81);
 795
 796        /* Get the timing data in cycles */
 797        if (reg & 0x40)         /* Fast VLB bus, assume 50MHz */
 798                ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
 799        else
 800                ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
 801
 802        active = (clamp_val(t.active, 3, 17) - 1) & 0x0F;
 803        recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F;
 804        timing = (active << 4) | recovery;
 805        winbond_writecfg(ld_winbond->timing, timing, reg);
 806
 807        /* Load the setup timing */
 808
 809        reg = 0x35;
 810        if (adev->class != ATA_DEV_ATA)
 811                reg |= 0x08;    /* FIFO off */
 812        if (!ata_pio_need_iordy(adev))
 813                reg |= 0x02;    /* IORDY off */
 814        reg |= (clamp_val(t.setup, 0, 3) << 6);
 815        winbond_writecfg(ld_winbond->timing, timing + 1, reg);
 816}
 817
 818static int winbond_port(struct platform_device *dev,
 819                        struct legacy_probe *lp, struct legacy_data *ld)
 820{
 821        if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL)
 822                return -EBUSY;
 823        ld->timing = lp->private;
 824        return 0;
 825}
 826
 827static struct ata_port_operations winbond_port_ops = {
 828        .inherits       = &legacy_base_port_ops,
 829        .set_piomode    = winbond_set_piomode,
 830        .sff_data_xfer  = vlb32_data_xfer,
 831};
 832
 833static struct legacy_controller controllers[] = {
 834        {"BIOS",        &legacy_port_ops,       ATA_PIO4,
 835                        ATA_FLAG_NO_IORDY,      0,                      NULL },
 836        {"Snooping",    &simple_port_ops,       ATA_PIO4,
 837                        0,                      0,                      NULL },
 838        {"PDC20230",    &pdc20230_port_ops,     ATA_PIO2,
 839                        ATA_FLAG_NO_IORDY,
 840                        ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE,        NULL },
 841        {"HT6560A",     &ht6560a_port_ops,      ATA_PIO2,
 842                        ATA_FLAG_NO_IORDY,      0,                      NULL },
 843        {"HT6560B",     &ht6560b_port_ops,      ATA_PIO4,
 844                        ATA_FLAG_NO_IORDY,      0,                      NULL },
 845        {"OPTI82C611A", &opti82c611a_port_ops,  ATA_PIO3,
 846                        0,                      0,                      NULL },
 847        {"OPTI82C46X",  &opti82c46x_port_ops,   ATA_PIO3,
 848                        0,                      0,                      NULL },
 849        {"QDI6500",     &qdi6500_port_ops,      ATA_PIO2,
 850                        ATA_FLAG_NO_IORDY,
 851                        ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE,    qdi_port },
 852        {"QDI6580",     &qdi6580_port_ops,      ATA_PIO4,
 853                        0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
 854        {"QDI6580DP",   &qdi6580dp_port_ops,    ATA_PIO4,
 855                        0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
 856        {"W83759A",     &winbond_port_ops,      ATA_PIO4,
 857                        0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE,
 858                                                                winbond_port }
 859};
 860
 861/**
 862 *      probe_chip_type         -       Discover controller
 863 *      @probe: Probe entry to check
 864 *
 865 *      Probe an ATA port and identify the type of controller. We don't
 866 *      check if the controller appears to be driveless at this point.
 867 */
 868
 869static __init int probe_chip_type(struct legacy_probe *probe)
 870{
 871        int mask = 1 << probe->slot;
 872
 873        if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) {
 874                u8 reg = winbond_readcfg(winbond, 0x81);
 875                reg |= 0x80;    /* jumpered mode off */
 876                winbond_writecfg(winbond, 0x81, reg);
 877                reg = winbond_readcfg(winbond, 0x83);
 878                reg |= 0xF0;    /* local control */
 879                winbond_writecfg(winbond, 0x83, reg);
 880                reg = winbond_readcfg(winbond, 0x85);
 881                reg |= 0xF0;    /* programmable timing */
 882                winbond_writecfg(winbond, 0x85, reg);
 883
 884                reg = winbond_readcfg(winbond, 0x81);
 885
 886                if (reg & mask)
 887                        return W83759A;
 888        }
 889        if (probe->port == 0x1F0) {
 890                unsigned long flags;
 891                local_irq_save(flags);
 892                /* Probes */
 893                outb(inb(0x1F2) | 0x80, 0x1F2);
 894                inb(0x1F5);
 895                inb(0x1F2);
 896                inb(0x3F6);
 897                inb(0x3F6);
 898                inb(0x1F2);
 899                inb(0x1F2);
 900
 901                if ((inb(0x1F2) & 0x80) == 0) {
 902                        /* PDC20230c or 20630 ? */
 903                        printk(KERN_INFO  "PDC20230-C/20630 VLB ATA controller"
 904                                                        " detected.\n");
 905                        udelay(100);
 906                        inb(0x1F5);
 907                        local_irq_restore(flags);
 908                        return PDC20230;
 909                } else {
 910                        outb(0x55, 0x1F2);
 911                        inb(0x1F2);
 912                        inb(0x1F2);
 913                        if (inb(0x1F2) == 0x00)
 914                                printk(KERN_INFO "PDC20230-B VLB ATA "
 915                                                     "controller detected.\n");
 916                        local_irq_restore(flags);
 917                        return BIOS;
 918                }
 919                local_irq_restore(flags);
 920        }
 921
 922        if (ht6560a & mask)
 923                return HT6560A;
 924        if (ht6560b & mask)
 925                return HT6560B;
 926        if (opti82c611a & mask)
 927                return OPTI611A;
 928        if (opti82c46x & mask)
 929                return OPTI46X;
 930        if (autospeed & mask)
 931                return SNOOP;
 932        return BIOS;
 933}
 934
 935
 936/**
 937 *      legacy_init_one         -       attach a legacy interface
 938 *      @pl: probe record
 939 *
 940 *      Register an ISA bus IDE interface. Such interfaces are PIO and we
 941 *      assume do not support IRQ sharing.
 942 */
 943
 944static __init int legacy_init_one(struct legacy_probe *probe)
 945{
 946        struct legacy_controller *controller = &controllers[probe->type];
 947        int pio_modes = controller->pio_mask;
 948        unsigned long io = probe->port;
 949        u32 mask = (1 << probe->slot);
 950        struct ata_port_operations *ops = controller->ops;
 951        struct legacy_data *ld = &legacy_data[probe->slot];
 952        struct ata_host *host = NULL;
 953        struct ata_port *ap;
 954        struct platform_device *pdev;
 955        struct ata_device *dev;
 956        void __iomem *io_addr, *ctrl_addr;
 957        u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY;
 958        int ret;
 959
 960        iordy |= controller->flags;
 961
 962        pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0);
 963        if (IS_ERR(pdev))
 964                return PTR_ERR(pdev);
 965
 966        ret = -EBUSY;
 967        if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL ||
 968            devm_request_region(&pdev->dev, io + 0x0206, 1,
 969                                                        "pata_legacy") == NULL)
 970                goto fail;
 971
 972        ret = -ENOMEM;
 973        io_addr = devm_ioport_map(&pdev->dev, io, 8);
 974        ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1);
 975        if (!io_addr || !ctrl_addr)
 976                goto fail;
 977        ld->type = probe->type;
 978        if (controller->setup)
 979                if (controller->setup(pdev, probe, ld) < 0)
 980                        goto fail;
 981        host = ata_host_alloc(&pdev->dev, 1);
 982        if (!host)
 983                goto fail;
 984        ap = host->ports[0];
 985
 986        ap->ops = ops;
 987        ap->pio_mask = pio_modes;
 988        ap->flags |= ATA_FLAG_SLAVE_POSS | iordy;
 989        ap->pflags |= controller->pflags;
 990        ap->ioaddr.cmd_addr = io_addr;
 991        ap->ioaddr.altstatus_addr = ctrl_addr;
 992        ap->ioaddr.ctl_addr = ctrl_addr;
 993        ata_sff_std_ports(&ap->ioaddr);
 994        ap->host->private_data = ld;
 995
 996        ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206);
 997
 998        ret = ata_host_activate(host, probe->irq, ata_sff_interrupt, 0,
 999                                &legacy_sht);
1000        if (ret)
1001                goto fail;
1002        async_synchronize_full();
1003        ld->platform_dev = pdev;
1004
1005        /* Nothing found means we drop the port as its probably not there */
1006
1007        ret = -ENODEV;
1008        ata_for_each_dev(dev, &ap->link, ALL) {
1009                if (!ata_dev_absent(dev)) {
1010                        legacy_host[probe->slot] = host;
1011                        ld->platform_dev = pdev;
1012                        return 0;
1013                }
1014        }
1015        ata_host_detach(host);
1016fail:
1017        platform_device_unregister(pdev);
1018        return ret;
1019}
1020
1021/**
1022 *      legacy_check_special_cases      -       ATA special cases
1023 *      @p: PCI device to check
1024 *      @master: set this if we find an ATA master
1025 *      @master: set this if we find an ATA secondary
1026 *
1027 *      A small number of vendors implemented early PCI ATA interfaces
1028 *      on bridge logic without the ATA interface being PCI visible.
1029 *      Where we have a matching PCI driver we must skip the relevant
1030 *      device here. If we don't know about it then the legacy driver
1031 *      is the right driver anyway.
1032 */
1033
1034static void __init legacy_check_special_cases(struct pci_dev *p, int *primary,
1035                                                                int *secondary)
1036{
1037        /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */
1038        if (p->vendor == 0x1078 && p->device == 0x0000) {
1039                *primary = *secondary = 1;
1040                return;
1041        }
1042        /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */
1043        if (p->vendor == 0x1078 && p->device == 0x0002) {
1044                *primary = *secondary = 1;
1045                return;
1046        }
1047        /* Intel MPIIX - PIO ATA on non PCI side of bridge */
1048        if (p->vendor == 0x8086 && p->device == 0x1234) {
1049                u16 r;
1050                pci_read_config_word(p, 0x6C, &r);
1051                if (r & 0x8000) {
1052                        /* ATA port enabled */
1053                        if (r & 0x4000)
1054                                *secondary = 1;
1055                        else
1056                                *primary = 1;
1057                }
1058                return;
1059        }
1060}
1061
1062static __init void probe_opti_vlb(void)
1063{
1064        /* If an OPTI 82C46X is present find out where the channels are */
1065        static const char *optis[4] = {
1066                "3/463MV", "5MV",
1067                "5MVA", "5MVB"
1068        };
1069        u8 chans = 1;
1070        u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6;
1071
1072        opti82c46x = 3; /* Assume master and slave first */
1073        printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n",
1074                                                                optis[ctrl]);
1075        if (ctrl == 3)
1076                chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1;
1077        ctrl = opti_syscfg(0xAC);
1078        /* Check enabled and this port is the 465MV port. On the
1079           MVB we may have two channels */
1080        if (ctrl & 8) {
1081                if (chans == 2) {
1082                        legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1083                        legacy_probe_add(0x170, 15, OPTI46X, 0);
1084                }
1085                if (ctrl & 4)
1086                        legacy_probe_add(0x170, 15, OPTI46X, 0);
1087                else
1088                        legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1089        } else
1090                legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1091}
1092
1093static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port)
1094{
1095        static const unsigned long ide_port[2] = { 0x170, 0x1F0 };
1096        /* Check card type */
1097        if ((r & 0xF0) == 0xC0) {
1098                /* QD6500: single channel */
1099                if (r & 8)
1100                        /* Disabled ? */
1101                        return;
1102                legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
1103                                                                QDI6500, port);
1104        }
1105        if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) {
1106                /* QD6580: dual channel */
1107                if (!request_region(port + 2 , 2, "pata_qdi")) {
1108                        release_region(port, 2);
1109                        return;
1110                }
1111                res = inb(port + 3);
1112                /* Single channel mode ? */
1113                if (res & 1)
1114                        legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
1115                                                                QDI6580, port);
1116                else { /* Dual channel mode */
1117                        legacy_probe_add(0x1F0, 14, QDI6580DP, port);
1118                        /* port + 0x02, r & 0x04 */
1119                        legacy_probe_add(0x170, 15, QDI6580DP, port + 2);
1120                }
1121                release_region(port + 2, 2);
1122        }
1123}
1124
1125static __init void probe_qdi_vlb(void)
1126{
1127        unsigned long flags;
1128        static const unsigned long qd_port[2] = { 0x30, 0xB0 };
1129        int i;
1130
1131        /*
1132         *      Check each possible QD65xx base address
1133         */
1134
1135        for (i = 0; i < 2; i++) {
1136                unsigned long port = qd_port[i];
1137                u8 r, res;
1138
1139
1140                if (request_region(port, 2, "pata_qdi")) {
1141                        /* Check for a card */
1142                        local_irq_save(flags);
1143                        /* I have no h/w that needs this delay but it
1144                           is present in the historic code */
1145                        r = inb(port);
1146                        udelay(1);
1147                        outb(0x19, port);
1148                        udelay(1);
1149                        res = inb(port);
1150                        udelay(1);
1151                        outb(r, port);
1152                        udelay(1);
1153                        local_irq_restore(flags);
1154
1155                        /* Fail */
1156                        if (res == 0x19) {
1157                                release_region(port, 2);
1158                                continue;
1159                        }
1160                        /* Passes the presence test */
1161                        r = inb(port + 1);
1162                        udelay(1);
1163                        /* Check port agrees with port set */
1164                        if ((r & 2) >> 1 == i)
1165                                qdi65_identify_port(r, res, port);
1166                        release_region(port, 2);
1167                }
1168        }
1169}
1170
1171/**
1172 *      legacy_init             -       attach legacy interfaces
1173 *
1174 *      Attach legacy IDE interfaces by scanning the usual IRQ/port suspects.
1175 *      Right now we do not scan the ide0 and ide1 address but should do so
1176 *      for non PCI systems or systems with no PCI IDE legacy mode devices.
1177 *      If you fix that note there are special cases to consider like VLB
1178 *      drivers and CS5510/20.
1179 */
1180
1181static __init int legacy_init(void)
1182{
1183        int i;
1184        int ct = 0;
1185        int primary = 0;
1186        int secondary = 0;
1187        int pci_present = 0;
1188        struct legacy_probe *pl = &probe_list[0];
1189        int slot = 0;
1190
1191        struct pci_dev *p = NULL;
1192
1193        for_each_pci_dev(p) {
1194                int r;
1195                /* Check for any overlap of the system ATA mappings. Native
1196                   mode controllers stuck on these addresses or some devices
1197                   in 'raid' mode won't be found by the storage class test */
1198                for (r = 0; r < 6; r++) {
1199                        if (pci_resource_start(p, r) == 0x1f0)
1200                                primary = 1;
1201                        if (pci_resource_start(p, r) == 0x170)
1202                                secondary = 1;
1203                }
1204                /* Check for special cases */
1205                legacy_check_special_cases(p, &primary, &secondary);
1206
1207                /* If PCI bus is present then don't probe for tertiary
1208                   legacy ports */
1209                pci_present = 1;
1210        }
1211
1212        if (winbond == 1)
1213                winbond = 0x130;        /* Default port, alt is 1B0 */
1214
1215        if (primary == 0 || all)
1216                legacy_probe_add(0x1F0, 14, UNKNOWN, 0);
1217        if (secondary == 0 || all)
1218                legacy_probe_add(0x170, 15, UNKNOWN, 0);
1219
1220        if (probe_all || !pci_present) {
1221                /* ISA/VLB extra ports */
1222                legacy_probe_add(0x1E8, 11, UNKNOWN, 0);
1223                legacy_probe_add(0x168, 10, UNKNOWN, 0);
1224                legacy_probe_add(0x1E0, 8, UNKNOWN, 0);
1225                legacy_probe_add(0x160, 12, UNKNOWN, 0);
1226        }
1227
1228        if (opti82c46x)
1229                probe_opti_vlb();
1230        if (qdi)
1231                probe_qdi_vlb();
1232
1233        for (i = 0; i < NR_HOST; i++, pl++) {
1234                if (pl->port == 0)
1235                        continue;
1236                if (pl->type == UNKNOWN)
1237                        pl->type = probe_chip_type(pl);
1238                pl->slot = slot++;
1239                if (legacy_init_one(pl) == 0)
1240                        ct++;
1241        }
1242        if (ct != 0)
1243                return 0;
1244        return -ENODEV;
1245}
1246
1247static __exit void legacy_exit(void)
1248{
1249        int i;
1250
1251        for (i = 0; i < nr_legacy_host; i++) {
1252                struct legacy_data *ld = &legacy_data[i];
1253                ata_host_detach(legacy_host[i]);
1254                platform_device_unregister(ld->platform_dev);
1255        }
1256}
1257
1258MODULE_AUTHOR("Alan Cox");
1259MODULE_DESCRIPTION("low-level driver for legacy ATA");
1260MODULE_LICENSE("GPL");
1261MODULE_VERSION(DRV_VERSION);
1262MODULE_ALIAS("pata_qdi");
1263MODULE_ALIAS("pata_winbond");
1264
1265module_param(probe_all, int, 0);
1266module_param(autospeed, int, 0);
1267module_param(ht6560a, int, 0);
1268module_param(ht6560b, int, 0);
1269module_param(opti82c611a, int, 0);
1270module_param(opti82c46x, int, 0);
1271module_param(qdi, int, 0);
1272module_param(winbond, int, 0);
1273module_param(pio_mask, int, 0);
1274module_param(iordy_mask, int, 0);
1275
1276module_init(legacy_init);
1277module_exit(legacy_exit);
1278
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