linux/drivers/ata/ahci.c
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   1/*
   2 *  ahci.c - AHCI SATA support
   3 *
   4 *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
   5 *                  Please ALWAYS copy linux-ide@vger.kernel.org
   6 *                  on emails.
   7 *
   8 *  Copyright 2004-2005 Red Hat, Inc.
   9 *
  10 *
  11 *  This program is free software; you can redistribute it and/or modify
  12 *  it under the terms of the GNU General Public License as published by
  13 *  the Free Software Foundation; either version 2, or (at your option)
  14 *  any later version.
  15 *
  16 *  This program is distributed in the hope that it will be useful,
  17 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 *  GNU General Public License for more details.
  20 *
  21 *  You should have received a copy of the GNU General Public License
  22 *  along with this program; see the file COPYING.  If not, write to
  23 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  24 *
  25 *
  26 * libata documentation is available via 'make {ps|pdf}docs',
  27 * as Documentation/DocBook/libata.*
  28 *
  29 * AHCI hardware documentation:
  30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
  31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
  32 *
  33 */
  34
  35#include <linux/kernel.h>
  36#include <linux/module.h>
  37#include <linux/pci.h>
  38#include <linux/init.h>
  39#include <linux/blkdev.h>
  40#include <linux/delay.h>
  41#include <linux/interrupt.h>
  42#include <linux/dma-mapping.h>
  43#include <linux/device.h>
  44#include <linux/dmi.h>
  45#include <linux/gfp.h>
  46#include <scsi/scsi_host.h>
  47#include <scsi/scsi_cmnd.h>
  48#include <linux/libata.h>
  49#include "ahci.h"
  50
  51#define DRV_NAME        "ahci"
  52#define DRV_VERSION     "3.0"
  53
  54enum {
  55        AHCI_PCI_BAR_STA2X11    = 0,
  56        AHCI_PCI_BAR_ENMOTUS    = 2,
  57        AHCI_PCI_BAR_STANDARD   = 5,
  58};
  59
  60enum board_ids {
  61        /* board IDs by feature in alphabetical order */
  62        board_ahci,
  63        board_ahci_ign_iferr,
  64        board_ahci_nosntf,
  65        board_ahci_yes_fbs,
  66
  67        /* board IDs for specific chipsets in alphabetical order */
  68        board_ahci_mcp65,
  69        board_ahci_mcp77,
  70        board_ahci_mcp89,
  71        board_ahci_mv,
  72        board_ahci_sb600,
  73        board_ahci_sb700,       /* for SB700 and SB800 */
  74        board_ahci_vt8251,
  75
  76        /* aliases */
  77        board_ahci_mcp_linux    = board_ahci_mcp65,
  78        board_ahci_mcp67        = board_ahci_mcp65,
  79        board_ahci_mcp73        = board_ahci_mcp65,
  80        board_ahci_mcp79        = board_ahci_mcp77,
  81};
  82
  83static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
  84static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
  85                                 unsigned long deadline);
  86static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
  87                                unsigned long deadline);
  88#ifdef CONFIG_PM
  89static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
  90static int ahci_pci_device_resume(struct pci_dev *pdev);
  91#endif
  92
  93static struct scsi_host_template ahci_sht = {
  94        AHCI_SHT("ahci"),
  95};
  96
  97static struct ata_port_operations ahci_vt8251_ops = {
  98        .inherits               = &ahci_ops,
  99        .hardreset              = ahci_vt8251_hardreset,
 100};
 101
 102static struct ata_port_operations ahci_p5wdh_ops = {
 103        .inherits               = &ahci_ops,
 104        .hardreset              = ahci_p5wdh_hardreset,
 105};
 106
 107static const struct ata_port_info ahci_port_info[] = {
 108        /* by features */
 109        [board_ahci] = {
 110                .flags          = AHCI_FLAG_COMMON,
 111                .pio_mask       = ATA_PIO4,
 112                .udma_mask      = ATA_UDMA6,
 113                .port_ops       = &ahci_ops,
 114        },
 115        [board_ahci_ign_iferr] = {
 116                AHCI_HFLAGS     (AHCI_HFLAG_IGN_IRQ_IF_ERR),
 117                .flags          = AHCI_FLAG_COMMON,
 118                .pio_mask       = ATA_PIO4,
 119                .udma_mask      = ATA_UDMA6,
 120                .port_ops       = &ahci_ops,
 121        },
 122        [board_ahci_nosntf] = {
 123                AHCI_HFLAGS     (AHCI_HFLAG_NO_SNTF),
 124                .flags          = AHCI_FLAG_COMMON,
 125                .pio_mask       = ATA_PIO4,
 126                .udma_mask      = ATA_UDMA6,
 127                .port_ops       = &ahci_ops,
 128        },
 129        [board_ahci_yes_fbs] = {
 130                AHCI_HFLAGS     (AHCI_HFLAG_YES_FBS),
 131                .flags          = AHCI_FLAG_COMMON,
 132                .pio_mask       = ATA_PIO4,
 133                .udma_mask      = ATA_UDMA6,
 134                .port_ops       = &ahci_ops,
 135        },
 136        /* by chipsets */
 137        [board_ahci_mcp65] = {
 138                AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
 139                                 AHCI_HFLAG_YES_NCQ),
 140                .flags          = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
 141                .pio_mask       = ATA_PIO4,
 142                .udma_mask      = ATA_UDMA6,
 143                .port_ops       = &ahci_ops,
 144        },
 145        [board_ahci_mcp77] = {
 146                AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
 147                .flags          = AHCI_FLAG_COMMON,
 148                .pio_mask       = ATA_PIO4,
 149                .udma_mask      = ATA_UDMA6,
 150                .port_ops       = &ahci_ops,
 151        },
 152        [board_ahci_mcp89] = {
 153                AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA),
 154                .flags          = AHCI_FLAG_COMMON,
 155                .pio_mask       = ATA_PIO4,
 156                .udma_mask      = ATA_UDMA6,
 157                .port_ops       = &ahci_ops,
 158        },
 159        [board_ahci_mv] = {
 160                AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
 161                                 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
 162                .flags          = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
 163                .pio_mask       = ATA_PIO4,
 164                .udma_mask      = ATA_UDMA6,
 165                .port_ops       = &ahci_ops,
 166        },
 167        [board_ahci_sb600] = {
 168                AHCI_HFLAGS     (AHCI_HFLAG_IGN_SERR_INTERNAL |
 169                                 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
 170                                 AHCI_HFLAG_32BIT_ONLY),
 171                .flags          = AHCI_FLAG_COMMON,
 172                .pio_mask       = ATA_PIO4,
 173                .udma_mask      = ATA_UDMA6,
 174                .port_ops       = &ahci_pmp_retry_srst_ops,
 175        },
 176        [board_ahci_sb700] = {  /* for SB700 and SB800 */
 177                AHCI_HFLAGS     (AHCI_HFLAG_IGN_SERR_INTERNAL),
 178                .flags          = AHCI_FLAG_COMMON,
 179                .pio_mask       = ATA_PIO4,
 180                .udma_mask      = ATA_UDMA6,
 181                .port_ops       = &ahci_pmp_retry_srst_ops,
 182        },
 183        [board_ahci_vt8251] = {
 184                AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
 185                .flags          = AHCI_FLAG_COMMON,
 186                .pio_mask       = ATA_PIO4,
 187                .udma_mask      = ATA_UDMA6,
 188                .port_ops       = &ahci_vt8251_ops,
 189        },
 190};
 191
 192static const struct pci_device_id ahci_pci_tbl[] = {
 193        /* Intel */
 194        { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
 195        { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
 196        { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
 197        { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
 198        { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
 199        { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
 200        { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
 201        { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
 202        { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
 203        { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
 204        { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
 205        { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
 206        { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
 207        { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
 208        { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
 209        { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
 210        { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
 211        { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
 212        { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
 213        { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
 214        { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
 215        { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
 216        { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
 217        { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
 218        { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
 219        { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
 220        { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
 221        { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
 222        { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
 223        { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
 224        { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
 225        { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
 226        { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
 227        { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
 228        { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
 229        { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
 230        { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
 231        { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
 232        { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
 233        { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
 234        { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
 235        { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
 236        { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
 237        { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
 238        { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
 239        { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
 240        { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
 241        { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
 242        { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
 243        { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
 244        { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
 245        { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
 246        { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
 247        { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
 248        { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
 249        { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
 250        { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
 251        { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
 252        { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
 253        { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
 254        { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
 255        { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
 256        { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
 257        { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
 258        { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
 259        { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
 260        { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
 261        { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
 262        { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
 263        { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
 264        { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
 265        { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
 266        { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
 267        { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
 268        { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
 269        { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
 270        { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
 271        { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
 272        { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
 273        { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
 274        { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
 275        { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
 276        { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
 277        { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
 278        { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
 279        { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
 280        { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
 281        { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
 282        { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
 283        { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
 284        { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
 285        { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
 286        { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
 287        { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
 288        { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
 289        { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
 290        { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
 291        { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
 292
 293        /* JMicron 360/1/3/5/6, match class to avoid IDE function */
 294        { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 295          PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
 296        /* JMicron 362B and 362C have an AHCI function with IDE class code */
 297        { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
 298        { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
 299
 300        /* ATI */
 301        { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
 302        { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
 303        { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
 304        { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
 305        { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
 306        { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
 307        { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
 308
 309        /* AMD */
 310        { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
 311        /* AMD is using RAID class only for ahci controllers */
 312        { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 313          PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
 314
 315        /* VIA */
 316        { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
 317        { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
 318
 319        /* NVIDIA */
 320        { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 },      /* MCP65 */
 321        { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 },      /* MCP65 */
 322        { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 },      /* MCP65 */
 323        { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 },      /* MCP65 */
 324        { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 },      /* MCP65 */
 325        { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 },      /* MCP65 */
 326        { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 },      /* MCP65 */
 327        { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 },      /* MCP65 */
 328        { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 },      /* MCP67 */
 329        { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 },      /* MCP67 */
 330        { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 },      /* MCP67 */
 331        { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 },      /* MCP67 */
 332        { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 },      /* MCP67 */
 333        { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 },      /* MCP67 */
 334        { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 },      /* MCP67 */
 335        { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 },      /* MCP67 */
 336        { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 },      /* MCP67 */
 337        { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 },      /* MCP67 */
 338        { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 },      /* MCP67 */
 339        { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 },      /* MCP67 */
 340        { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux },  /* Linux ID */
 341        { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux },  /* Linux ID */
 342        { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux },  /* Linux ID */
 343        { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux },  /* Linux ID */
 344        { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux },  /* Linux ID */
 345        { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux },  /* Linux ID */
 346        { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux },  /* Linux ID */
 347        { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux },  /* Linux ID */
 348        { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux },  /* Linux ID */
 349        { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux },  /* Linux ID */
 350        { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux },  /* Linux ID */
 351        { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux },  /* Linux ID */
 352        { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux },  /* Linux ID */
 353        { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux },  /* Linux ID */
 354        { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux },  /* Linux ID */
 355        { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux },  /* Linux ID */
 356        { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 },      /* MCP73 */
 357        { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 },      /* MCP73 */
 358        { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 },      /* MCP73 */
 359        { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 },      /* MCP73 */
 360        { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 },      /* MCP73 */
 361        { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 },      /* MCP73 */
 362        { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 },      /* MCP73 */
 363        { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 },      /* MCP73 */
 364        { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 },      /* MCP73 */
 365        { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 },      /* MCP73 */
 366        { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 },      /* MCP73 */
 367        { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 },      /* MCP73 */
 368        { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 },      /* MCP77 */
 369        { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 },      /* MCP77 */
 370        { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 },      /* MCP77 */
 371        { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 },      /* MCP77 */
 372        { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 },      /* MCP77 */
 373        { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 },      /* MCP77 */
 374        { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 },      /* MCP77 */
 375        { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 },      /* MCP77 */
 376        { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 },      /* MCP77 */
 377        { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 },      /* MCP77 */
 378        { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 },      /* MCP77 */
 379        { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 },      /* MCP77 */
 380        { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 },      /* MCP79 */
 381        { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 },      /* MCP79 */
 382        { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 },      /* MCP79 */
 383        { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 },      /* MCP79 */
 384        { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 },      /* MCP79 */
 385        { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 },      /* MCP79 */
 386        { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 },      /* MCP79 */
 387        { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 },      /* MCP79 */
 388        { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 },      /* MCP79 */
 389        { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 },      /* MCP79 */
 390        { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 },      /* MCP79 */
 391        { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 },      /* MCP79 */
 392        { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 },      /* MCP89 */
 393        { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 },      /* MCP89 */
 394        { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 },      /* MCP89 */
 395        { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 },      /* MCP89 */
 396        { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 },      /* MCP89 */
 397        { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 },      /* MCP89 */
 398        { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 },      /* MCP89 */
 399        { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 },      /* MCP89 */
 400        { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 },      /* MCP89 */
 401        { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 },      /* MCP89 */
 402        { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 },      /* MCP89 */
 403        { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 },      /* MCP89 */
 404
 405        /* SiS */
 406        { PCI_VDEVICE(SI, 0x1184), board_ahci },                /* SiS 966 */
 407        { PCI_VDEVICE(SI, 0x1185), board_ahci },                /* SiS 968 */
 408        { PCI_VDEVICE(SI, 0x0186), board_ahci },                /* SiS 968 */
 409
 410        /* ST Microelectronics */
 411        { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci },           /* ST ConneXt */
 412
 413        /* Marvell */
 414        { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv },        /* 6145 */
 415        { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv },        /* 6121 */
 416        { PCI_DEVICE(0x1b4b, 0x9123),
 417          .class = PCI_CLASS_STORAGE_SATA_AHCI,
 418          .class_mask = 0xffffff,
 419          .driver_data = board_ahci_yes_fbs },                  /* 88se9128 */
 420        { PCI_DEVICE(0x1b4b, 0x9125),
 421          .driver_data = board_ahci_yes_fbs },                  /* 88se9125 */
 422        { PCI_DEVICE(0x1b4b, 0x917a),
 423          .driver_data = board_ahci_yes_fbs },                  /* 88se9172 */
 424        { PCI_DEVICE(0x1b4b, 0x9192),
 425          .driver_data = board_ahci_yes_fbs },                  /* 88se9172 on some Gigabyte */
 426        { PCI_DEVICE(0x1b4b, 0x91a3),
 427          .driver_data = board_ahci_yes_fbs },
 428
 429        /* Promise */
 430        { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci },   /* PDC42819 */
 431
 432        /* Asmedia */
 433        { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci },   /* ASM1060 */
 434        { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci },   /* ASM1060 */
 435        { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci },   /* ASM1061 */
 436        { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci },   /* ASM1062 */
 437
 438        /* Enmotus */
 439        { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
 440
 441        /* Generic, PCI class code for AHCI */
 442        { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 443          PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
 444
 445        { }     /* terminate list */
 446};
 447
 448
 449static struct pci_driver ahci_pci_driver = {
 450        .name                   = DRV_NAME,
 451        .id_table               = ahci_pci_tbl,
 452        .probe                  = ahci_init_one,
 453        .remove                 = ata_pci_remove_one,
 454#ifdef CONFIG_PM
 455        .suspend                = ahci_pci_device_suspend,
 456        .resume                 = ahci_pci_device_resume,
 457#endif
 458};
 459
 460#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
 461static int marvell_enable;
 462#else
 463static int marvell_enable = 1;
 464#endif
 465module_param(marvell_enable, int, 0644);
 466MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
 467
 468
 469static void ahci_pci_save_initial_config(struct pci_dev *pdev,
 470                                         struct ahci_host_priv *hpriv)
 471{
 472        unsigned int force_port_map = 0;
 473        unsigned int mask_port_map = 0;
 474
 475        if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
 476                dev_info(&pdev->dev, "JMB361 has only one port\n");
 477                force_port_map = 1;
 478        }
 479
 480        /*
 481         * Temporary Marvell 6145 hack: PATA port presence
 482         * is asserted through the standard AHCI port
 483         * presence register, as bit 4 (counting from 0)
 484         */
 485        if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
 486                if (pdev->device == 0x6121)
 487                        mask_port_map = 0x3;
 488                else
 489                        mask_port_map = 0xf;
 490                dev_info(&pdev->dev,
 491                          "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
 492        }
 493
 494        ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
 495                                 mask_port_map);
 496}
 497
 498static int ahci_pci_reset_controller(struct ata_host *host)
 499{
 500        struct pci_dev *pdev = to_pci_dev(host->dev);
 501
 502        ahci_reset_controller(host);
 503
 504        if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 505                struct ahci_host_priv *hpriv = host->private_data;
 506                u16 tmp16;
 507
 508                /* configure PCS */
 509                pci_read_config_word(pdev, 0x92, &tmp16);
 510                if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
 511                        tmp16 |= hpriv->port_map;
 512                        pci_write_config_word(pdev, 0x92, tmp16);
 513                }
 514        }
 515
 516        return 0;
 517}
 518
 519static void ahci_pci_init_controller(struct ata_host *host)
 520{
 521        struct ahci_host_priv *hpriv = host->private_data;
 522        struct pci_dev *pdev = to_pci_dev(host->dev);
 523        void __iomem *port_mmio;
 524        u32 tmp;
 525        int mv;
 526
 527        if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
 528                if (pdev->device == 0x6121)
 529                        mv = 2;
 530                else
 531                        mv = 4;
 532                port_mmio = __ahci_port_base(host, mv);
 533
 534                writel(0, port_mmio + PORT_IRQ_MASK);
 535
 536                /* clear port IRQ */
 537                tmp = readl(port_mmio + PORT_IRQ_STAT);
 538                VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
 539                if (tmp)
 540                        writel(tmp, port_mmio + PORT_IRQ_STAT);
 541        }
 542
 543        ahci_init_controller(host);
 544}
 545
 546static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
 547                                 unsigned long deadline)
 548{
 549        struct ata_port *ap = link->ap;
 550        bool online;
 551        int rc;
 552
 553        DPRINTK("ENTER\n");
 554
 555        ahci_stop_engine(ap);
 556
 557        rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
 558                                 deadline, &online, NULL);
 559
 560        ahci_start_engine(ap);
 561
 562        DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
 563
 564        /* vt8251 doesn't clear BSY on signature FIS reception,
 565         * request follow-up softreset.
 566         */
 567        return online ? -EAGAIN : rc;
 568}
 569
 570static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
 571                                unsigned long deadline)
 572{
 573        struct ata_port *ap = link->ap;
 574        struct ahci_port_priv *pp = ap->private_data;
 575        u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
 576        struct ata_taskfile tf;
 577        bool online;
 578        int rc;
 579
 580        ahci_stop_engine(ap);
 581
 582        /* clear D2H reception area to properly wait for D2H FIS */
 583        ata_tf_init(link->device, &tf);
 584        tf.command = 0x80;
 585        ata_tf_to_fis(&tf, 0, 0, d2h_fis);
 586
 587        rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
 588                                 deadline, &online, NULL);
 589
 590        ahci_start_engine(ap);
 591
 592        /* The pseudo configuration device on SIMG4726 attached to
 593         * ASUS P5W-DH Deluxe doesn't send signature FIS after
 594         * hardreset if no device is attached to the first downstream
 595         * port && the pseudo device locks up on SRST w/ PMP==0.  To
 596         * work around this, wait for !BSY only briefly.  If BSY isn't
 597         * cleared, perform CLO and proceed to IDENTIFY (achieved by
 598         * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
 599         *
 600         * Wait for two seconds.  Devices attached to downstream port
 601         * which can't process the following IDENTIFY after this will
 602         * have to be reset again.  For most cases, this should
 603         * suffice while making probing snappish enough.
 604         */
 605        if (online) {
 606                rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
 607                                          ahci_check_ready);
 608                if (rc)
 609                        ahci_kick_engine(ap);
 610        }
 611        return rc;
 612}
 613
 614#ifdef CONFIG_PM
 615static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
 616{
 617        struct ata_host *host = dev_get_drvdata(&pdev->dev);
 618        struct ahci_host_priv *hpriv = host->private_data;
 619        void __iomem *mmio = hpriv->mmio;
 620        u32 ctl;
 621
 622        if (mesg.event & PM_EVENT_SUSPEND &&
 623            hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
 624                dev_err(&pdev->dev,
 625                        "BIOS update required for suspend/resume\n");
 626                return -EIO;
 627        }
 628
 629        if (mesg.event & PM_EVENT_SLEEP) {
 630                /* AHCI spec rev1.1 section 8.3.3:
 631                 * Software must disable interrupts prior to requesting a
 632                 * transition of the HBA to D3 state.
 633                 */
 634                ctl = readl(mmio + HOST_CTL);
 635                ctl &= ~HOST_IRQ_EN;
 636                writel(ctl, mmio + HOST_CTL);
 637                readl(mmio + HOST_CTL); /* flush */
 638        }
 639
 640        return ata_pci_device_suspend(pdev, mesg);
 641}
 642
 643static int ahci_pci_device_resume(struct pci_dev *pdev)
 644{
 645        struct ata_host *host = dev_get_drvdata(&pdev->dev);
 646        int rc;
 647
 648        rc = ata_pci_device_do_resume(pdev);
 649        if (rc)
 650                return rc;
 651
 652        if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
 653                rc = ahci_pci_reset_controller(host);
 654                if (rc)
 655                        return rc;
 656
 657                ahci_pci_init_controller(host);
 658        }
 659
 660        ata_host_resume(host);
 661
 662        return 0;
 663}
 664#endif
 665
 666static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
 667{
 668        int rc;
 669
 670        /*
 671         * If the device fixup already set the dma_mask to some non-standard
 672         * value, don't extend it here. This happens on STA2X11, for example.
 673         */
 674        if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
 675                return 0;
 676
 677        if (using_dac &&
 678            !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
 679                rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
 680                if (rc) {
 681                        rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 682                        if (rc) {
 683                                dev_err(&pdev->dev,
 684                                        "64-bit DMA enable failed\n");
 685                                return rc;
 686                        }
 687                }
 688        } else {
 689                rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 690                if (rc) {
 691                        dev_err(&pdev->dev, "32-bit DMA enable failed\n");
 692                        return rc;
 693                }
 694                rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 695                if (rc) {
 696                        dev_err(&pdev->dev,
 697                                "32-bit consistent DMA enable failed\n");
 698                        return rc;
 699                }
 700        }
 701        return 0;
 702}
 703
 704static void ahci_pci_print_info(struct ata_host *host)
 705{
 706        struct pci_dev *pdev = to_pci_dev(host->dev);
 707        u16 cc;
 708        const char *scc_s;
 709
 710        pci_read_config_word(pdev, 0x0a, &cc);
 711        if (cc == PCI_CLASS_STORAGE_IDE)
 712                scc_s = "IDE";
 713        else if (cc == PCI_CLASS_STORAGE_SATA)
 714                scc_s = "SATA";
 715        else if (cc == PCI_CLASS_STORAGE_RAID)
 716                scc_s = "RAID";
 717        else
 718                scc_s = "unknown";
 719
 720        ahci_print_info(host, scc_s);
 721}
 722
 723/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
 724 * hardwired to on-board SIMG 4726.  The chipset is ICH8 and doesn't
 725 * support PMP and the 4726 either directly exports the device
 726 * attached to the first downstream port or acts as a hardware storage
 727 * controller and emulate a single ATA device (can be RAID 0/1 or some
 728 * other configuration).
 729 *
 730 * When there's no device attached to the first downstream port of the
 731 * 4726, "Config Disk" appears, which is a pseudo ATA device to
 732 * configure the 4726.  However, ATA emulation of the device is very
 733 * lame.  It doesn't send signature D2H Reg FIS after the initial
 734 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
 735 *
 736 * The following function works around the problem by always using
 737 * hardreset on the port and not depending on receiving signature FIS
 738 * afterward.  If signature FIS isn't received soon, ATA class is
 739 * assumed without follow-up softreset.
 740 */
 741static void ahci_p5wdh_workaround(struct ata_host *host)
 742{
 743        static struct dmi_system_id sysids[] = {
 744                {
 745                        .ident = "P5W DH Deluxe",
 746                        .matches = {
 747                                DMI_MATCH(DMI_SYS_VENDOR,
 748                                          "ASUSTEK COMPUTER INC"),
 749                                DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
 750                        },
 751                },
 752                { }
 753        };
 754        struct pci_dev *pdev = to_pci_dev(host->dev);
 755
 756        if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
 757            dmi_check_system(sysids)) {
 758                struct ata_port *ap = host->ports[1];
 759
 760                dev_info(&pdev->dev,
 761                         "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
 762
 763                ap->ops = &ahci_p5wdh_ops;
 764                ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
 765        }
 766}
 767
 768/* only some SB600 ahci controllers can do 64bit DMA */
 769static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
 770{
 771        static const struct dmi_system_id sysids[] = {
 772                /*
 773                 * The oldest version known to be broken is 0901 and
 774                 * working is 1501 which was released on 2007-10-26.
 775                 * Enable 64bit DMA on 1501 and anything newer.
 776                 *
 777                 * Please read bko#9412 for more info.
 778                 */
 779                {
 780                        .ident = "ASUS M2A-VM",
 781                        .matches = {
 782                                DMI_MATCH(DMI_BOARD_VENDOR,
 783                                          "ASUSTeK Computer INC."),
 784                                DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
 785                        },
 786                        .driver_data = "20071026",      /* yyyymmdd */
 787                },
 788                /*
 789                 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
 790                 * support 64bit DMA.
 791                 *
 792                 * BIOS versions earlier than 1.5 had the Manufacturer DMI
 793                 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
 794                 * This spelling mistake was fixed in BIOS version 1.5, so
 795                 * 1.5 and later have the Manufacturer as
 796                 * "MICRO-STAR INTERNATIONAL CO.,LTD".
 797                 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
 798                 *
 799                 * BIOS versions earlier than 1.9 had a Board Product Name
 800                 * DMI field of "MS-7376". This was changed to be
 801                 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
 802                 * match on DMI_BOARD_NAME of "MS-7376".
 803                 */
 804                {
 805                        .ident = "MSI K9A2 Platinum",
 806                        .matches = {
 807                                DMI_MATCH(DMI_BOARD_VENDOR,
 808                                          "MICRO-STAR INTER"),
 809                                DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
 810                        },
 811                },
 812                /*
 813                 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
 814                 * 64bit DMA.
 815                 *
 816                 * This board also had the typo mentioned above in the
 817                 * Manufacturer DMI field (fixed in BIOS version 1.5), so
 818                 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
 819                 */
 820                {
 821                        .ident = "MSI K9AGM2",
 822                        .matches = {
 823                                DMI_MATCH(DMI_BOARD_VENDOR,
 824                                          "MICRO-STAR INTER"),
 825                                DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
 826                        },
 827                },
 828                /*
 829                 * All BIOS versions for the Asus M3A support 64bit DMA.
 830                 * (all release versions from 0301 to 1206 were tested)
 831                 */
 832                {
 833                        .ident = "ASUS M3A",
 834                        .matches = {
 835                                DMI_MATCH(DMI_BOARD_VENDOR,
 836                                          "ASUSTeK Computer INC."),
 837                                DMI_MATCH(DMI_BOARD_NAME, "M3A"),
 838                        },
 839                },
 840                { }
 841        };
 842        const struct dmi_system_id *match;
 843        int year, month, date;
 844        char buf[9];
 845
 846        match = dmi_first_match(sysids);
 847        if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
 848            !match)
 849                return false;
 850
 851        if (!match->driver_data)
 852                goto enable_64bit;
 853
 854        dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
 855        snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
 856
 857        if (strcmp(buf, match->driver_data) >= 0)
 858                goto enable_64bit;
 859        else {
 860                dev_warn(&pdev->dev,
 861                         "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
 862                         match->ident);
 863                return false;
 864        }
 865
 866enable_64bit:
 867        dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
 868        return true;
 869}
 870
 871static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
 872{
 873        static const struct dmi_system_id broken_systems[] = {
 874                {
 875                        .ident = "HP Compaq nx6310",
 876                        .matches = {
 877                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 878                                DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
 879                        },
 880                        /* PCI slot number of the controller */
 881                        .driver_data = (void *)0x1FUL,
 882                },
 883                {
 884                        .ident = "HP Compaq 6720s",
 885                        .matches = {
 886                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 887                                DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
 888                        },
 889                        /* PCI slot number of the controller */
 890                        .driver_data = (void *)0x1FUL,
 891                },
 892
 893                { }     /* terminate list */
 894        };
 895        const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
 896
 897        if (dmi) {
 898                unsigned long slot = (unsigned long)dmi->driver_data;
 899                /* apply the quirk only to on-board controllers */
 900                return slot == PCI_SLOT(pdev->devfn);
 901        }
 902
 903        return false;
 904}
 905
 906static bool ahci_broken_suspend(struct pci_dev *pdev)
 907{
 908        static const struct dmi_system_id sysids[] = {
 909                /*
 910                 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
 911                 * to the harddisk doesn't become online after
 912                 * resuming from STR.  Warn and fail suspend.
 913                 *
 914                 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
 915                 *
 916                 * Use dates instead of versions to match as HP is
 917                 * apparently recycling both product and version
 918                 * strings.
 919                 *
 920                 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
 921                 */
 922                {
 923                        .ident = "dv4",
 924                        .matches = {
 925                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 926                                DMI_MATCH(DMI_PRODUCT_NAME,
 927                                          "HP Pavilion dv4 Notebook PC"),
 928                        },
 929                        .driver_data = "20090105",      /* F.30 */
 930                },
 931                {
 932                        .ident = "dv5",
 933                        .matches = {
 934                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 935                                DMI_MATCH(DMI_PRODUCT_NAME,
 936                                          "HP Pavilion dv5 Notebook PC"),
 937                        },
 938                        .driver_data = "20090506",      /* F.16 */
 939                },
 940                {
 941                        .ident = "dv6",
 942                        .matches = {
 943                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 944                                DMI_MATCH(DMI_PRODUCT_NAME,
 945                                          "HP Pavilion dv6 Notebook PC"),
 946                        },
 947                        .driver_data = "20090423",      /* F.21 */
 948                },
 949                {
 950                        .ident = "HDX18",
 951                        .matches = {
 952                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 953                                DMI_MATCH(DMI_PRODUCT_NAME,
 954                                          "HP HDX18 Notebook PC"),
 955                        },
 956                        .driver_data = "20090430",      /* F.23 */
 957                },
 958                /*
 959                 * Acer eMachines G725 has the same problem.  BIOS
 960                 * V1.03 is known to be broken.  V3.04 is known to
 961                 * work.  Between, there are V1.06, V2.06 and V3.03
 962                 * that we don't have much idea about.  For now,
 963                 * blacklist anything older than V3.04.
 964                 *
 965                 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
 966                 */
 967                {
 968                        .ident = "G725",
 969                        .matches = {
 970                                DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
 971                                DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
 972                        },
 973                        .driver_data = "20091216",      /* V3.04 */
 974                },
 975                { }     /* terminate list */
 976        };
 977        const struct dmi_system_id *dmi = dmi_first_match(sysids);
 978        int year, month, date;
 979        char buf[9];
 980
 981        if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
 982                return false;
 983
 984        dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
 985        snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
 986
 987        return strcmp(buf, dmi->driver_data) < 0;
 988}
 989
 990static bool ahci_broken_online(struct pci_dev *pdev)
 991{
 992#define ENCODE_BUSDEVFN(bus, slot, func)                        \
 993        (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
 994        static const struct dmi_system_id sysids[] = {
 995                /*
 996                 * There are several gigabyte boards which use
 997                 * SIMG5723s configured as hardware RAID.  Certain
 998                 * 5723 firmware revisions shipped there keep the link
 999                 * online but fail to answer properly to SRST or
1000                 * IDENTIFY when no device is attached downstream
1001                 * causing libata to retry quite a few times leading
1002                 * to excessive detection delay.
1003                 *
1004                 * As these firmwares respond to the second reset try
1005                 * with invalid device signature, considering unknown
1006                 * sig as offline works around the problem acceptably.
1007                 */
1008                {
1009                        .ident = "EP45-DQ6",
1010                        .matches = {
1011                                DMI_MATCH(DMI_BOARD_VENDOR,
1012                                          "Gigabyte Technology Co., Ltd."),
1013                                DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1014                        },
1015                        .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1016                },
1017                {
1018                        .ident = "EP45-DS5",
1019                        .matches = {
1020                                DMI_MATCH(DMI_BOARD_VENDOR,
1021                                          "Gigabyte Technology Co., Ltd."),
1022                                DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1023                        },
1024                        .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1025                },
1026                { }     /* terminate list */
1027        };
1028#undef ENCODE_BUSDEVFN
1029        const struct dmi_system_id *dmi = dmi_first_match(sysids);
1030        unsigned int val;
1031
1032        if (!dmi)
1033                return false;
1034
1035        val = (unsigned long)dmi->driver_data;
1036
1037        return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1038}
1039
1040#ifdef CONFIG_ATA_ACPI
1041static void ahci_gtf_filter_workaround(struct ata_host *host)
1042{
1043        static const struct dmi_system_id sysids[] = {
1044                /*
1045                 * Aspire 3810T issues a bunch of SATA enable commands
1046                 * via _GTF including an invalid one and one which is
1047                 * rejected by the device.  Among the successful ones
1048                 * is FPDMA non-zero offset enable which when enabled
1049                 * only on the drive side leads to NCQ command
1050                 * failures.  Filter it out.
1051                 */
1052                {
1053                        .ident = "Aspire 3810T",
1054                        .matches = {
1055                                DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1056                                DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1057                        },
1058                        .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1059                },
1060                { }
1061        };
1062        const struct dmi_system_id *dmi = dmi_first_match(sysids);
1063        unsigned int filter;
1064        int i;
1065
1066        if (!dmi)
1067                return;
1068
1069        filter = (unsigned long)dmi->driver_data;
1070        dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1071                 filter, dmi->ident);
1072
1073        for (i = 0; i < host->n_ports; i++) {
1074                struct ata_port *ap = host->ports[i];
1075                struct ata_link *link;
1076                struct ata_device *dev;
1077
1078                ata_for_each_link(link, ap, EDGE)
1079                        ata_for_each_dev(dev, link, ALL)
1080                                dev->gtf_filter |= filter;
1081        }
1082}
1083#else
1084static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1085{}
1086#endif
1087
1088static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1089{
1090        unsigned int board_id = ent->driver_data;
1091        struct ata_port_info pi = ahci_port_info[board_id];
1092        const struct ata_port_info *ppi[] = { &pi, NULL };
1093        struct device *dev = &pdev->dev;
1094        struct ahci_host_priv *hpriv;
1095        struct ata_host *host;
1096        int n_ports, i, rc;
1097        int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1098
1099        VPRINTK("ENTER\n");
1100
1101        WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1102
1103        ata_print_version_once(&pdev->dev, DRV_VERSION);
1104
1105        /* The AHCI driver can only drive the SATA ports, the PATA driver
1106           can drive them all so if both drivers are selected make sure
1107           AHCI stays out of the way */
1108        if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1109                return -ENODEV;
1110
1111        /*
1112         * For some reason, MCP89 on MacBook 7,1 doesn't work with
1113         * ahci, use ata_generic instead.
1114         */
1115        if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1116            pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1117            pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1118            pdev->subsystem_device == 0xcb89)
1119                return -ENODEV;
1120
1121        /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1122         * At the moment, we can only use the AHCI mode. Let the users know
1123         * that for SAS drives they're out of luck.
1124         */
1125        if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1126                dev_info(&pdev->dev,
1127                         "PDC42819 can only drive SATA devices with this driver\n");
1128
1129        /* Both Connext and Enmotus devices use non-standard BARs */
1130        if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1131                ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1132        else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1133                ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1134
1135        /* acquire resources */
1136        rc = pcim_enable_device(pdev);
1137        if (rc)
1138                return rc;
1139
1140        /* AHCI controllers often implement SFF compatible interface.
1141         * Grab all PCI BARs just in case.
1142         */
1143        rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1144        if (rc == -EBUSY)
1145                pcim_pin_device(pdev);
1146        if (rc)
1147                return rc;
1148
1149        if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1150            (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1151                u8 map;
1152
1153                /* ICH6s share the same PCI ID for both piix and ahci
1154                 * modes.  Enabling ahci mode while MAP indicates
1155                 * combined mode is a bad idea.  Yield to ata_piix.
1156                 */
1157                pci_read_config_byte(pdev, ICH_MAP, &map);
1158                if (map & 0x3) {
1159                        dev_info(&pdev->dev,
1160                                 "controller is in combined mode, can't enable AHCI mode\n");
1161                        return -ENODEV;
1162                }
1163        }
1164
1165        hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1166        if (!hpriv)
1167                return -ENOMEM;
1168        hpriv->flags |= (unsigned long)pi.private_data;
1169
1170        /* MCP65 revision A1 and A2 can't do MSI */
1171        if (board_id == board_ahci_mcp65 &&
1172            (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1173                hpriv->flags |= AHCI_HFLAG_NO_MSI;
1174
1175        /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1176        if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1177                hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1178
1179        /* only some SB600s can do 64bit DMA */
1180        if (ahci_sb600_enable_64bit(pdev))
1181                hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1182
1183        if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1184                pci_intx(pdev, 1);
1185
1186        hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1187
1188        /* save initial config */
1189        ahci_pci_save_initial_config(pdev, hpriv);
1190
1191        /* prepare host */
1192        if (hpriv->cap & HOST_CAP_NCQ) {
1193                pi.flags |= ATA_FLAG_NCQ;
1194                /*
1195                 * Auto-activate optimization is supposed to be
1196                 * supported on all AHCI controllers indicating NCQ
1197                 * capability, but it seems to be broken on some
1198                 * chipsets including NVIDIAs.
1199                 */
1200                if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1201                        pi.flags |= ATA_FLAG_FPDMA_AA;
1202        }
1203
1204        if (hpriv->cap & HOST_CAP_PMP)
1205                pi.flags |= ATA_FLAG_PMP;
1206
1207        ahci_set_em_messages(hpriv, &pi);
1208
1209        if (ahci_broken_system_poweroff(pdev)) {
1210                pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1211                dev_info(&pdev->dev,
1212                        "quirky BIOS, skipping spindown on poweroff\n");
1213        }
1214
1215        if (ahci_broken_suspend(pdev)) {
1216                hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1217                dev_warn(&pdev->dev,
1218                         "BIOS update required for suspend/resume\n");
1219        }
1220
1221        if (ahci_broken_online(pdev)) {
1222                hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1223                dev_info(&pdev->dev,
1224                         "online status unreliable, applying workaround\n");
1225        }
1226
1227        /* CAP.NP sometimes indicate the index of the last enabled
1228         * port, at other times, that of the last possible port, so
1229         * determining the maximum port number requires looking at
1230         * both CAP.NP and port_map.
1231         */
1232        n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1233
1234        host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1235        if (!host)
1236                return -ENOMEM;
1237        host->private_data = hpriv;
1238
1239        if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1240                host->flags |= ATA_HOST_PARALLEL_SCAN;
1241        else
1242                printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1243
1244        if (pi.flags & ATA_FLAG_EM)
1245                ahci_reset_em(host);
1246
1247        for (i = 0; i < host->n_ports; i++) {
1248                struct ata_port *ap = host->ports[i];
1249
1250                ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1251                ata_port_pbar_desc(ap, ahci_pci_bar,
1252                                   0x100 + ap->port_no * 0x80, "port");
1253
1254                /* set enclosure management message type */
1255                if (ap->flags & ATA_FLAG_EM)
1256                        ap->em_message_type = hpriv->em_msg_type;
1257
1258
1259                /* disabled/not-implemented port */
1260                if (!(hpriv->port_map & (1 << i)))
1261                        ap->ops = &ata_dummy_port_ops;
1262        }
1263
1264        /* apply workaround for ASUS P5W DH Deluxe mainboard */
1265        ahci_p5wdh_workaround(host);
1266
1267        /* apply gtf filter quirk */
1268        ahci_gtf_filter_workaround(host);
1269
1270        /* initialize adapter */
1271        rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1272        if (rc)
1273                return rc;
1274
1275        rc = ahci_pci_reset_controller(host);
1276        if (rc)
1277                return rc;
1278
1279        ahci_pci_init_controller(host);
1280        ahci_pci_print_info(host);
1281
1282        pci_set_master(pdev);
1283        return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1284                                 &ahci_sht);
1285}
1286
1287module_pci_driver(ahci_pci_driver);
1288
1289MODULE_AUTHOR("Jeff Garzik");
1290MODULE_DESCRIPTION("AHCI SATA low-level driver");
1291MODULE_LICENSE("GPL");
1292MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1293MODULE_VERSION(DRV_VERSION);
1294
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