linux/drivers/spi/spi-dw-pci.c
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 L1">2 21./a>.spaa class="comment">/*./spaalu
 L2">2 22./a>.spaa class="comment"> * PCI interface driver for DW SPI Core./spaalu
 L3">2 23./a>.spaa class="comment"> *./spaalu
 L4">2 24./a>.spaa class="comment"> * Copyright (c) 2009, Intel Corporan va../spaalu
 L5">2 25./a>.spaa class="comment"> *./spaalu
 L6">2 26./a>.spaa class="comment"> * This program is free software; you caa redistribute it and/or modify it./spaalu
 L7">2 27./a>.spaa class="comment"> * under the terms and condin vas of the GNU General Public License,./spaalu
 L8">2 28./a>.spaa class="comment"> * vers2.8"2, as published by the Free Software Foundan va../spaalu
 L9">2 29./a>.spaa class="comment"> *./spaalu
 L10">2 n vaa>.spaa class="comment"> * This program is distributed in the hope it will be useful, but WITHOUT./spaalu
 L11">2 11./a>.spaa class="comment"> * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or./spaalu
 L12">2 12./a>.spaa class="comment"> * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for./spaalu
 L13">2 13./a>.spaa class="comment"> * more details../spaalu
 L14">2 14./a>.spaa class="comment"> *./spaalu
 L15">2 15./a>.spaa class="comment"> * You should have received a copy of the GNU General Public License along./spaalu
 L16">2 16./a>.spaa class="comment"> * with this program; if not, write to the Free Software Foundan va,./spaalu
 L17">2 17./a>.spaa class="comment"> * Inc., 51 Franklin St - Fifth Floor, Bostva, MA 02110-1301 USA../spaalu
 L18">2 18./a>.spaa class="comment"> */./spaalu
 L19">2 19./a>u
 L20">2 2 vaa>#include <linux/interrupt.hvaa>>u
 L21">2 21vaa>#include <linux/pci.hvaa>>u
 L22">2 22vaa>#include <linux/slab.hvaa>>u
 L23">2 23vaa>#include <linux/spi/spi.hvaa>>u
 L24">2 24vaa>#include <linux/module.hvaa>>u
 L25">2 25./a>u
 L26">2 26vaa>#include "spi-dw.hvaa>"u
 L27">2 27./a>u
 L28">2 28./a>#define2.a href="+code=DRIVER_NAME" class="sref">DRIVER_NAME./a> .spaa class="string">"dw_spi_pci"
 L29">2 29./a>u
 L30">2 3 vaa>struct2.a href="+code=dw_spi_pci" class="sref">dw_spi_pci./a> {u
 L31">2 31vaa>        struct2.a href="+code=pci_dev" class="sref">pci_devvaa>  *.a href="+code=pdev" class="sref">pdevvaa>;u
 L32">2 32vaa>        struct2.a href="+code=dw_spi" class="sref">dw_spivaa>   .a href="+code=dws" class="sref">dwsvaa>;u
 L33">2 33vaa>};u
 L34">2 34./a>u
 L35">2 35vaa>static int .a href="+code=spi_pci_probe" class="sref">spi_pci_probevaa>(struct2.a href="+code=pci_dev" class="sref">pci_devvaa> *.a href="+code=pdev" class="sref">pdevvaa>,u
 L36">2 36vaa>        const struct2.a href="+code=pci_device_id" class="sref">pci_device_idvaa> *.a href="+code=ent" class="sref">entvaa>)u
 L37">2 37./a>{u
 L38">2 38vaa>        struct2.a href="+code=dw_spi_pci" class="sref">dw_spi_pci./a> *.a href="+code=dwpci" class="sref">dwpci./a>;u
 L39">2 39vaa>        struct2.a href="+code=dw_spi" class="sref">dw_spivaa> *.a href="+code=dws" class="sref">dwsvaa>;u
 L40">2 40vaa>        int .a href="+code=pci_bar" class="sref">pci_barvaa> = 0;u
 L41">2 41vaa>        int .a href="+code=ret" class="sref">retvaa>;u
 L42">2 42./a>u
 L43">2 43vaa>        .a href="+code=printk" class="sref">printkvaa>(.a href="+code=KERN_INFO" class="sref">KERN_INFO./a> .spaa class="string">"DW: found PCI SPI controller(ID: %04x:%04x)\n"
 L44">2 44vaa>                .a href="+code=pdev" class="sref">pdevvaa>->.a href="+code=vendor" class="sref">vendorvaa>, .a href="+code=pdev" class="sref">pdevvaa>->.a href="+code=device" class="sref">devicevaa>);u
 L45">2 45./a>u
 L46">2 46vaa>        .a href="+code=ret" class="sref">retvaa> = .a href="+code=pci_enable_device" class="sref">pci_enable_devicevaa>(.a href="+code=pdev" class="sref">pdevvaa>);u
 L47">2 47vaa>        if (.a href="+code=ret" class="sref">retvaa>)u
 L48">2 48vaa>                return .a href="+code=ret" class="sref">retvaa>;u
 L49">2 49./a>u
 L50">2 50vaa>        .a href="+code=dwpci" class="sref">dwpci./a> = .a href="+code=kzalloc" class="sref">kzallocvaa>(sizeof(struct2.a href="+code=dw_spi_pci" class="sref">dw_spi_pci./a>), .a href="+code=GFP_KERNEL" class="sref">GFP_KERNELvaa>);u
 L51">2 51vaa>        if (!.a href="+code=dwpci" class="sref">dwpci./a>) {u
 L52">2 52vaa>                .a href="+code=ret" class="sref">retvaa> = -.a href="+code=ENOMEM" class="sref">ENOMEMvaa>;u
 L53">2 53vaa>                goto .a href="+code=err_disable" class="sref">err_disablevaa>;u
 L54">2 54vaa>        }u
 L55">2 55./a>u
 L56">2 56vaa>        .a href="+code=dwpci" class="sref">dwpci./a>->.a href="+code=pdev" class="sref">pdevvaa> = .a href="+code=pdev" class="sref">pdevvaa>;u
 L57">2 57vaa>        .a href="+code=dws" class="sref">dwsvaa> = &.a href="+code=dwpci" class="sref">dwpci./a>->.a href="+code=dws" class="sref">dwsvaa>;u
 L58">2 58./a>u
 L59">2 59vaa>        .spaa class="comment">/* Get basic io resource and map it */./spaalu
 L60">2 60vaa>        .a href="+code=dws" class="sref">dwsvaa>->.a href="+code=paddr" class="sref">paddrvaa> = .a href="+code=pci_resource_start" class="sref">pci_resource_startvaa>(.a href="+code=pdev" class="sref">pdevvaa>, .a href="+code=pci_bar" class="sref">pci_barvaa>);u
 L61">2 61vaa>        .a href="+code=dws" class="sref">dwsvaa>->.a href="+code=iolen" class="sref">iolenvaa> = .a href="+code=pci_resource_len" class="sref">pci_resource_lenvaa>(.a href="+code=pdev" class="sref">pdevvaa>, .a href="+code=pci_bar" class="sref">pci_barvaa>);u
 L62">2 62./a>u
 L63">2 63vaa>        .a href="+code=ret" class="sref">retvaa> = .a href="+code=pci_request_region" class="sref">pci_request_regionvaa>(.a href="+code=pdev" class="sref">pdevvaa>, .a href="+code=pci_bar" class="sref">pci_barvaa>, .a href="+code=dev_nam>" class="sref">dev_nam>vaa>(&.a href="+code=pdev" class="sref">pdevvaa>->.a href="+code=dev" class="sref">devvaa>));u
 L64">2 64vaa>        if (.a href="+code=ret" class="sref">retvaa>)u
 L65">2 65vaa>                goto .a href="+code=err_kfree" class="sref">err_kfreevaa>;u
 L66">2 66./a>u
 L67">2 67vaa>        .a href="+code=dws" class="sref">dwsvaa>->.a href="+code=regs" class="sref">regsvaa> = .a href="+code=ioremap_nocache" class="sref">ioremap_nocachevaa>((unsigned long).a href="+code=dws" class="sref">dwsvaa>->.a href="+code=paddr" class="sref">paddrvaa>,u
 L68">2 68vaa>                                .a href="+code=pci_resource_len" class="sref">pci_resource_lenvaa>(.a href="+code=pdev" class="sref">pdevvaa>, .a href="+code=pci_bar" class="sref">pci_barvaa>));u
 L69">2 69vaa>        if (!.a href="+code=dws" class="sref">dwsvaa>->.a href="+code=regs" class="sref">regsvaa>) {u
 L70">2 70vaa>                .a href="+code=ret" class="sref">retvaa> = -.a href="+code=ENOMEM" class="sref">ENOMEMvaa>;u
 L71">2 71vaa>                goto .a href="+code=err_release_reg" class="sref">err_release_regvaa>;u
 L72">2 72vaa>        }u
 L73">2 73./a>u
 L74">2 74vaa>        .a href="+code=dws" class="sref">dwsvaa>->.a href="+code=parent_dev" class="sref">parent_devvaa> = &.a href="+code=pdev" class="sref">pdevvaa>->.a href="+code=dev" class="sref">devvaa>;u
 L75">2 75vaa>        .a href="+code=dws" class="sref">dwsvaa>->.a href="+code=bus_num" class="sref">bus_numvaa> = 0;u
 L76">2 76vaa>        .a href="+code=dws" class="sref">dwsvaa>->.a href="+code=num_cs" class="sref">num_csvaa> = 4;u
 L77">2 77vaa>        .a href="+code=dws" class="sref">dwsvaa>->.a href="+code=irq" class="sref">irqvaa> = .a href="+code=pdev" class="sref">pdevvaa>->.a href="+code=irq" class="sref">irqvaa>;u
 L78">2 78./a>u
 L79">2 79vaa>        .spaa class="comment">/*./spaalu
 L80">2 8 vaa>.spaa class="comment">         * Specific handling for Intel MID paltforms, like dma setup,./spaalu
 L81">2 81./a>.spaa class="comment">         * clock rate, FIFO depth../spaalu
 L82">2 82./a>.spaa class="comment">         */./spaalu
 L83">2 83vaa>        if (.a href="+code=pdev" class="sref">pdevvaa>->.a href="+code=device" class="sref">devicevaa> == 0x0800) {u
 L84">2 84vaa>                .a href="+code=ret" class="sref">retvaa> = .a href="+code=dw_spi_mid_init" class="sref">dw_spi_mid_initvaa>(.a href="+code=dws" class="sref">dwsvaa>);u
 L85">2 85vaa>                if (.a href="+code=ret" class="sref">retvaa>)u
 L86">2 86vaa>                        goto .a href="+code=err_unmap" class="sref">err_unmapvaa>;u
 L87">2 87vaa>        }u
 L88">2 88./a>u
 L89">2 89vaa>        .a href="+code=ret" class="sref">retvaa> = .a href="+code=dw_spi_add_host" class="sref">dw_spi_add_hostvaa>(.a href="+code=dws" class="sref">dwsvaa>);u
 L90">2 90vaa>        if (.a href="+code=ret" class="sref">retvaa>)u
 L91">2 91vaa>                goto .a href="+code=err_unmap" class="sref">err_unmapvaa>;u
 L92">2 92./a>u
 L93">2 93vaa>        .spaa class="comment">/* PCI hook and SPI hook use the sam> drv data */./spaalu
 L94">2 94vaa>        .a href="+code=pci_set_drvdata" class="sref">pci_set_drvdatavaa>(.a href="+code=pdev" class="sref">pdevvaa>, .a href="+code=dwpci" class="sref">dwpci./a>);u
 L95">2 95vaa>        return 0;u
 L96">2 96./a>u
 L97">2 97./a>.a href="+code=err_unmap" class="sref">err_unmapvaa>:u
 L98">2 98vaa>        .a href="+code=iounmap" class="sref">iounmapvaa>(.a href="+code=dws" class="sref">dwsvaa>->.a href="+code=regs" class="sref">regsvaa>);u
 L99">2 99./a>.a href="+code=err_release_reg" class="sref">err_release_regvaa>:u
 L100">2100vaa>        .a href="+code=pci_release_region" class="sref">pci_release_regionvaa>(.a href="+code=pdev" class="sref">pdevvaa>, .a href="+code=pci_bar" class="sref">pci_barvaa>);u
 L101">2101./a>.a href="+code=err_kfree" class="sref">err_kfreevaa>:u
 L102">2102vaa>        .a href="+code=kfree" class="sref">kfreevaa>(.a href="+code=dwpci" class="sref">dwpci./a>);u
 L103">2103./a>.a href="+code=err_disable" class="sref">err_disablevaa>:u
 L104">2104vaa>        .a href="+code=pci_disable_device" class="sref">pci_disable_devicevaa>(.a href="+code=pdev" class="sref">pdevvaa>);u
 L105">2105vaa>        return .a href="+code=ret" class="sref">retvaa>;u
 L106">2106./a>}u
 L107">2107./a>u
 L108">2108vaa>static void .a href="+code=spi_pci_remove" class="sref">spi_pci_removevaa>(struct2.a href="+code=pci_dev" class="sref">pci_devvaa> *.a href="+code=pdev" class="sref">pdevvaa>)u
 L109">2109./a>{u
 L110">2110vaa>        struct2.a href="+code=dw_spi_pci" class="sref">dw_spi_pci./a> *.a href="+code=dwpci" class="sref">dwpci./a> = .a href="+code=pci_get_drvdata" class="sref">pci_get_drvdatavaa>(.a href="+code=pdev" class="sref">pdevvaa>);u
 L111">2111./a>u
 L112">2112vaa>        .a href="+code=pci_set_drvdata" class="sref">pci_set_drvdatavaa>(.a href="+code=pdev" class="sref">pdevvaa>, .a href="+code=NULL" class="sref">NULLvaa>);u
 L113">2113vaa>        .a href="+code=dw_spi_remove_host" class="sref">dw_spi_remove_hostvaa>(&.a href="+code=dwpci" class="sref">dwpci./a>->.a href="+code=dws" class="sref">dwsvaa>);u
 L114">2114vaa>        .a href="+code=iounmap" class="sref">iounmapvaa>(.a href="+code=dwpci" class="sref">dwpci./a>->.a href="+code=dws" class="sref">dwsvaa>..a href="+code=regs" class="sref">regsvaa>);u
 L115">2115vaa>        .a href="+code=pci_release_region" class="sref">pci_release_regionvaa>(.a href="+code=pdev" class="sref">pdevvaa>, 0);u
 L116">2116vaa>        .a href="+code=kfree" class="sref">kfreevaa>(.a href="+code=dwpci" class="sref">dwpci./a>);u
 L117">2117vaa>        .a href="+code=pci_disable_device" class="sref">pci_disable_devicevaa>(.a href="+code=pdev" class="sref">pdevvaa>);u
 L118">2118./a>}u
 L119">2119./a>u
 L120">212 vaa>#ifdef .a href="+code=CONFIG_PM" class="sref">CONFIG_PM./a>u
 L121">2121vaa>static int .a href="+code=spi_suspend" class="sref">spi_suspendvaa>(struct2.a href="+code=pci_dev" class="sref">pci_devvaa> *.a href="+code=pdev" class="sref">pdevvaa>, .a href="+code=pm_message_t" class="sref">pm_message_tvaa> .a href="+code=state" class="sref">statevaa>)u
 L122">2122vaa>{u
 L123">2123vaa>        struct2.a href="+code=dw_spi_pci" class="sref">dw_spi_pci./a> *.a href="+code=dwpci" class="sref">dwpci./a> = .a href="+code=pci_get_drvdata" class="sref">pci_get_drvdatavaa>(.a href="+code=pdev" class="sref">pdevvaa>);u
 L124">2124vaa>        int .a href="+code=ret" class="sref">retvaa>;u
 L125">2125./a>u
 L126">2126vaa>        .a href="+code=ret" class="sref">retvaa> = .a href="+code=dw_spi_suspend_host" class="sref">dw_spi_suspend_hostvaa>(&.a href="+code=dwpci" class="sref">dwpci./a>->.a href="+code=dws" class="sref">dwsvaa>);u
 L127">2127vaa>        if (.a href="+code=ret" class="sref">retvaa>)u
 L128">2128vaa>                return .a href="+code=ret" class="sref">retvaa>;u
 L129">2129vaa>        .a href="+code=pci_save_state" class="sref">pci_save_statevaa>(.a href="+code=pdev" class="sref">pdevvaa>);u
 L130">2130vaa>        .a href="+code=pci_disable_device" class="sref">pci_disable_devicevaa>(.a href="+code=pdev" class="sref">pdevvaa>);u
 L131">2131vaa>        .a href="+code=pci_set_power_state" class="sref">pci_set_power_statevaa>(.a href="+code=pdev" class="sref">pdevvaa>, .a href="+code=pci_choose_state" class="sref">pci_choose_statevaa>(.a href="+code=pdev" class="sref">pdevvaa>, .a href="+code=state" class="sref">statevaa>));u
 L132">2132vaa>        return .a href="+code=ret" class="sref">retvaa>;u
 L133">2133vaa>}u
 L134">2134./a>u
 L135">2135vaa>static int .a href="+code=spi_resum>" class="sref">spi_resum>vaa>(struct2.a href="+code=pci_dev" class="sref">pci_devvaa> *.a href="+code=pdev" class="sref">pdevvaa>)u
 L136">2136vaa>{u
 L137">2137vaa>        struct2.a href="+code=dw_spi_pci" class="sref">dw_spi_pci./a> *.a href="+code=dwpci" class="sref">dwpci./a> = .a href="+code=pci_get_drvdata" class="sref">pci_get_drvdatavaa>(.a href="+code=pdev" class="sref">pdevvaa>);u
 L138">2138vaa>        int .a href="+code=ret" class="sref">retvaa>;u
 L139">2139./a>u
 L140">2140vaa>        .a href="+code=pci_set_power_state" class="sref">pci_set_power_statevaa>(.a href="+code=pdev" class="sref">pdevvaa>, .a href="+code=PCI_D0" class="sref">PCI_D0vaa>);u
 L141">2141vaa>        .a href="+code=pci_restore_state" class="sref">pci_restore_statevaa>(.a href="+code=pdev" class="sref">pdevvaa>);u
 L142">2142vaa>        .a href="+code=ret" class="sref">retvaa> = .a href="+code=pci_enable_device" class="sref">pci_enable_devicevaa>(.a href="+code=pdev" class="sref">pdevvaa>);u
 L143">2143vaa>        if (.a href="+code=ret" class="sref">retvaa>)u
 L144">2144vaa>                return .a href="+code=ret" class="sref">retvaa>;u
 L145">2145vaa>        return .a href="+code=dw_spi_resum>_host" class="sref">dw_spi_resum>_hostvaa>(&.a href="+code=dwpci" class="sref">dwpci./a>->.a href="+code=dws" class="sref">dwsvaa>);u
 L146">2146./a>}u
 L147">2147vaa>#elseu
 L148">2148./a>#define2.a href="+code=spi_suspend" class="sref">spi_suspendvaa>     .a href="+code=NULL" class="sref">NULLvaa>u
 L149">2149./a>#define2.a href="+code=spi_resum>" class="sref">spi_resum>vaa>      .a href="+code=NULL" class="sref">NULLvaa>u
 L150">2150vaa>#endifu
 L151">2151./a>u
 L152">2152vaa>static .a href="+code=DEFINE_PCI_DEVICE_TABLE" class="sref">DEFINE_PCI_DEVICE_TABLEvaa>(.a href="+code=pci_ids" class="sref">pci_idsvaa>) = {u
 L153">2153vaa>        .spaa class="comment">/* Intel MID platform SPI controller 0 */./spaalu
 L154">2154vaa>        { .a href="+code=PCI_DEVICE" class="sref">PCI_DEVICEvaa>(.a href="+code=PCI_VENDOR_ID_INTEL" class="sref">PCI_VENDOR_ID_INTELvaa>, 0x0800) },u
 L155">2155vaa>        {},u
 L156">2156vaa>};u
 L157">2157./a>u
 L158">2158vaa>static struct2.a href="+code=pci_driver" class="sref">pci_drivervaa> .a href="+code=dw_spi_driver" class="sref">dw_spi_drivervaa> = {u
 L159">2159vaa>        ..a href="+code=nam>" class="sref">nam>vaa> =         .a href="+code=DRIVER_NAME" class="sref">DRIVER_NAME./a>,u
 L160">2160vaa>        ..a href="+code=id_table" class="sref">id_tablevaa> =     .a href="+code=pci_ids" class="sref">pci_idsvaa>,u
 L161">2161vaa>        ..a href="+code=probe" class="sref">probevaa> =        .a href="+code=spi_pci_probe" class="sref">spi_pci_probevaa>,u
 L162">2162vaa>        ..a href="+code=remove" class="sref">removevaa> =       .a href="+code=spi_pci_remove" class="sref">spi_pci_removevaa>,u
 L163">2163vaa>        ..a href="+code=suspend" class="sref">suspendvaa> =      .a href="+code=spi_suspend" class="sref">spi_suspendvaa>,u
 L164">2164vaa>        ..a href="+code=resum>" class="sref">resum>vaa> =       .a href="+code=spi_resum>" class="sref">spi_resum>vaa>,u
 L165">2165vaa>};u
 L166">2166./a>u
 L167">2167./a>.a href="+code=module_pci_driver" class="sref">module_pci_drivervaa>(.a href="+code=dw_spi_driver" class="sref">dw_spi_drivervaa>);u
 L168">2168./a>u
 L169">2169./a>.a href="+code=MODULE_AUTHOR" class="sref">MODULE_AUTHORvaa>(.spaa class="string">"Feng Tang <feng.tang@intel.com>"
 L170">2170vaa>.a href="+code=MODULE_DESCRIPTION" class="sref">MODULE_DESCRIPTIONvaa>(.spaa class="string">"PCI interface driver for DW SPI Core"
 L171">2171./a>.a href="+code=MODULE_LICENSE" class="sref">MODULE_LICENSEvaa>(.spaa class="string">"GPL v2"
 L172">2172vaa>
The original LXR software by the LXR communityvaa>, this experimental vers2.8"by lxr@linux.novaa>. ./divlu.div class="subfooter"> lxr.linux.no kindly hosted by Redpill Linpro ASvaa>, provider of Linux consulting and operan vas services since 1995. ./divlu ./bodylu./htmllu