linux/drivers/rtc/rtc-rp5c01.c
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   1/*
   2 *  Ricoh RP5C01 RTC Driver
   3 *
   4 *  Copyright 2009 Geert Uytterhoeven
   5 *
   6 *  Based on the A3000 TOD code in arch/m68k/amiga/config.c
   7 *  Copyright (C) 1993 Hamish Macdonald
   8 */
   9
  10#include <linux/io.h>
  11#include <linux/kernel.h>
  12#include <linux/module.h>
  13#include <linux/platform_device.h>
  14#include <linux/rtc.h>
  15#include <linux/slab.h>
  16
  17
  18enum {
  19        RP5C01_1_SECOND         = 0x0,  /* MODE 00 */
  20        RP5C01_10_SECOND        = 0x1,  /* MODE 00 */
  21        RP5C01_1_MINUTE         = 0x2,  /* MODE 00 and MODE 01 */
  22        RP5C01_10_MINUTE        = 0x3,  /* MODE 00 and MODE 01 */
  23        RP5C01_1_HOUR           = 0x4,  /* MODE 00 and MODE 01 */
  24        RP5C01_10_HOUR          = 0x5,  /* MODE 00 and MODE 01 */
  25        RP5C01_DAY_OF_WEEK      = 0x6,  /* MODE 00 and MODE 01 */
  26        RP5C01_1_DAY            = 0x7,  /* MODE 00 and MODE 01 */
  27        RP5C01_10_DAY           = 0x8,  /* MODE 00 and MODE 01 */
  28        RP5C01_1_MONTH          = 0x9,  /* MODE 00 */
  29        RP5C01_10_MONTH         = 0xa,  /* MODE 00 */
  30        RP5C01_1_YEAR           = 0xb,  /* MODE 00 */
  31        RP5C01_10_YEAR          = 0xc,  /* MODE 00 */
  32
  33        RP5C01_12_24_SELECT     = 0xa,  /* MODE 01 */
  34        RP5C01_LEAP_YEAR        = 0xb,  /* MODE 01 */
  35
  36        RP5C01_MODE             = 0xd,  /* all modes */
  37        RP5C01_TEST             = 0xe,  /* all modes */
  38        RP5C01_RESET            = 0xf,  /* all modes */
  39};
  40
  41#define RP5C01_12_24_SELECT_12  (0 << 0)
  42#define RP5C01_12_24_SELECT_24  (1 << 0)
  43
  44#define RP5C01_10_HOUR_AM       (0 << 1)
  45#define RP5C01_10_HOUR_PM       (1 << 1)
  46
  47#define RP5C01_MODE_TIMER_EN    (1 << 3)        /* timer enable */
  48#define RP5C01_MODE_ALARM_EN    (1 << 2)        /* alarm enable */
  49
  50#define RP5C01_MODE_MODE_MASK   (3 << 0)
  51#define RP5C01_MODE_MODE00      (0 << 0)        /* time */
  52#define RP5C01_MODE_MODE01      (1 << 0)        /* alarm, 12h/24h, leap year */
  53#define RP5C01_MODE_RAM_BLOCK10 (2 << 0)        /* RAM 4 bits x 13 */
  54#define RP5C01_MODE_RAM_BLOCK11 (3 << 0)        /* RAM 4 bits x 13 */
  55
  56#define RP5C01_RESET_1HZ_PULSE  (1 << 3)
  57#define RP5C01_RESET_16HZ_PULSE (1 << 2)
  58#define RP5C01_RESET_SECOND     (1 << 1)        /* reset divider stages for */
  59                                                /* seconds or smaller units */
  60#define RP5C01_RESET_ALARM      (1 << 0)        /* reset all alarm registers */
  61
  62
  63struct rp5c01_priv {
  64        u32 __iomem *regs;
  65        struct rtc_device *rtc;
  66        spinlock_t lock;        /* against concurrent RTC/NVRAM access */
  67        struct bin_attribute nvram_attr;
  68};
  69
  70static inline unsigned int rp5c01_read(struct rp5c01_priv *priv,
  71                                       unsigned int reg)
  72{
  73        return __raw_readl(&priv->regs[reg]) & 0xf;
  74}
  75
  76static inline void rp5c01_write(struct rp5c01_priv *priv, unsigned int val,
  77                                unsigned int reg)
  78{
  79        __raw_writel(val, &priv->regs[reg]);
  80}
  81
  82static void rp5c01_lock(struct rp5c01_priv *priv)
  83{
  84        rp5c01_write(priv, RP5C01_MODE_MODE00, RP5C01_MODE);
  85}
  86
  87static void rp5c01_unlock(struct rp5c01_priv *priv)
  88{
  89        rp5c01_write(priv, RP5C01_MODE_TIMER_EN | RP5C01_MODE_MODE01,
  90                     RP5C01_MODE);
  91}
  92
  93static int rp5c01_read_time(struct device *dev, struct rtc_time *tm)
  94{
  95        struct rp5c01_priv *priv = dev_get_drvdata(dev);
  96
  97        spin_lock_irq(&priv->lock);
  98        rp5c01_lock(priv);
  99
 100        tm->tm_sec  = rp5c01_read(priv, RP5C01_10_SECOND) * 10 +
 101                      rp5c01_read(priv, RP5C01_1_SECOND);
 102        tm->tm_min  = rp5c01_read(priv, RP5C01_10_MINUTE) * 10 +
 103                      rp5c01_read(priv, RP5C01_1_MINUTE);
 104        tm->tm_hour = rp5c01_read(priv, RP5C01_10_HOUR) * 10 +
 105                      rp5c01_read(priv, RP5C01_1_HOUR);
 106        tm->tm_mday = rp5c01_read(priv, RP5C01_10_DAY) * 10 +
 107                      rp5c01_read(priv, RP5C01_1_DAY);
 108        tm->tm_wday = rp5c01_read(priv, RP5C01_DAY_OF_WEEK);
 109        tm->tm_mon  = rp5c01_read(priv, RP5C01_10_MONTH) * 10 +
 110                      rp5c01_read(priv, RP5C01_1_MONTH) - 1;
 111        tm->tm_year = rp5c01_read(priv, RP5C01_10_YEAR) * 10 +
 112                      rp5c01_read(priv, RP5C01_1_YEAR);
 113        if (tm->tm_year <= 69)
 114                tm->tm_year += 100;
 115
 116        rp5c01_unlock(priv);
 117        spin_unlock_irq(&priv->lock);
 118
 119        return rtc_valid_tm(tm);
 120}
 121
 122static int rp5c01_set_time(struct device *dev, struct rtc_time *tm)
 123{
 124        struct rp5c01_priv *priv = dev_get_drvdata(dev);
 125
 126        spin_lock_irq(&priv->lock);
 127        rp5c01_lock(priv);
 128
 129        rp5c01_write(priv, tm->tm_sec / 10, RP5C01_10_SECOND);
 130        rp5c01_write(priv, tm->tm_sec % 10, RP5C01_1_SECOND);
 131        rp5c01_write(priv, tm->tm_min / 10, RP5C01_10_MINUTE);
 132        rp5c01_write(priv, tm->tm_min % 10, RP5C01_1_MINUTE);
 133        rp5c01_write(priv, tm->tm_hour / 10, RP5C01_10_HOUR);
 134        rp5c01_write(priv, tm->tm_hour % 10, RP5C01_1_HOUR);
 135        rp5c01_write(priv, tm->tm_mday / 10, RP5C01_10_DAY);
 136        rp5c01_write(priv, tm->tm_mday % 10, RP5C01_1_DAY);
 137        if (tm->tm_wday != -1)
 138                rp5c01_write(priv, tm->tm_wday, RP5C01_DAY_OF_WEEK);
 139        rp5c01_write(priv, (tm->tm_mon + 1) / 10, RP5C01_10_MONTH);
 140        rp5c01_write(priv, (tm->tm_mon + 1) % 10, RP5C01_1_MONTH);
 141        if (tm->tm_year >= 100)
 142                tm->tm_year -= 100;
 143        rp5c01_write(priv, tm->tm_year / 10, RP5C01_10_YEAR);
 144        rp5c01_write(priv, tm->tm_year % 10, RP5C01_1_YEAR);
 145
 146        rp5c01_unlock(priv);
 147        spin_unlock_irq(&priv->lock);
 148        return 0;
 149}
 150
 151static const struct rtc_class_ops rp5c01_rtc_ops = {
 152        .read_time      = rp5c01_read_time,
 153        .set_time       = rp5c01_set_time,
 154};
 155
 156
 157/*
 158 * The NVRAM is organized as 2 blocks of 13 nibbles of 4 bits.
 159 * We provide access to them like Ah/m6OS loe name="L142"> 142                 159/*,e=rp5low-rp5c01cef ent">/1="L159" class="line" name="L159"> 159  67      1ef="drive1rs/rtc/rtc-rp5c01.c#L63"1 id="163" class="line" name="L63">  63struct1 r      = locs hr" 5c01_rtc_ops = {
priv68" idriv">->tc_class_ops p83435c01_ef="+code=dev_ge834p class="sref">p834p href=tc_class_ops lokobjec 5c01_ef="+code=dev_gekobjclass="sref">lokobj154" class="line" name="L154"> 154};
<  u3216">tm-> nvram_attrnam_attr" class="sref">n154" class="line" name="L154"> 154};
< ref="drivrp5c01_reaaaaaaaaaaaach id=f="+code=dev_ge"ufam_attr" class="uf href="+code=tm_year"loff" class="sref">loloff" 5c01_rtc_ops = {povers/rtc/rtc-rp5pov href="+code=tm_year"s hr" class="sref">loc hr" 5c01_rtc_ops = {c hrclass="sref">loc hrL148"class="line" name="L154"> 154};
< f="driverss/rtc/rtc-rp5c01.c#L17" i id="f">spi class="line" name="L152"> 152      struct 1bin_attribute dev, struct rtc_c01_set_time,
reftade=r_ofam_attr" class=reftade=r_ofa href="drivers/rtc/kobjclass="sref">lokobj154" bin_attribute dev, struct f="+code=tm_year"kobjclass="sref">lokobj154"" class="line" name="L148"> 148    href="dri1vers/rtc/rtc-rp5c01.c#L619" id168ass="sref">bin_attribute priv = dev_get_drvdata(dev);
 125
rp5c01_write(locs hr" 5c01_rtc_ops = {coun class="sref">locoun 5c01 class="line" name="L125"> 125
i17151" class="line" name="L151"> 151stat         1                        1unsig17ef">rp5c01_write(priv->lock);
 127    ref="driv1ers/rtc/rtc-rp5c01.c#L731" id=173" class="line" name="L63">  63struct1  return 1__r" id="drivers/rtc/rtcoun class="sref">locoun 5c01n>
<;_rtc_ops = {c hrclass="sref">loc hrL148 id=" 0t;);
);
locoun 5c01++f="+code=tm_year"s hrclass="sref">loc hrL148--)" class="line" name="L152"> 152    ref="driv1ers/rtc/rtc-rp5c01.c#L751" id=17">tm->lou85c01_rtc_ops = {de=dev" class="sref" 127    rref="drivrs/rtc/rtc-rp5c01.c#L76"1 id="176" class="line" name="L76">  76static1 i176>tm->priv, tm->  76static1  struct 1                 unsigne1d int1reE);
RP5C01_MODE_MODE01,
 (2 << 0)        /* RAMfass="line" name="L76">  76static1 ref="dri1ers/rtc/rtc-rp5c01.c#L791" id=17lass="sref">rp5c01_wrass="sref">reE);
 127    rf="drive1="+code=__raw_writel" cl1ass="17  (priv, RP5C01_10_YEAR) * povers/rtc/rtc-rp5pov hre)all alarm 4 class="line" name="L127"> 127    ref="driv1ers/rtc/rtc-rp5c01.c#L811" id=18ad" class="sref">rp5c"+code=tm_year"="+code=priv" class="sref">priv, tm->  76static1ef="drive1rs/rtc/rtc-rp5c01.c#L82"1 id="18d int RP5C01_MODE_MODE01,
 (2 << 0)        /* RAMfass="line" name="L76">  76static1eef="driv1href="+code=rp5c01_lock"1 clas18ad" class="sref">rp5c01_rearef">reE);
 127    ref="driv1ers/rtc/rtc-rp5c01.c#L841" id=18ad" class="sref">rp5crtc_ops = {de=dev" class="sref"(priv, RP5C01_10_YEAR) * povers/rtc/rtc-rp5pov hre++" class="line" name="L127"> 127    ref="driv1="+code=rp5c01_write" cl1ass="18">tm->priv, tm-> | RP5C01_MODE_MODE01,
  90      1ref="driv1ers/rtc/rtc-rp5c01.c#L861" id=18ad" class="sref">rp5c01_reaaaaaaaaE);
 127    r 127     void  150
 129      rp5c01_write(priv->lock);
 148             1      locoun 5c01 class="line" name="L125"> 125
  92
  93static1 int r      = locs hr" 5c01_rtc_ops = {
priv->tc_class_ops p83435c01_ef="+code=dev_ge834p class="sref">p834p href=tc_class_ops lokobjec 5c01_ef="+code=dev_gekobjclass="sref">lokobj154" class="line" name="L154"> 154};
tm-> nvram_attrnam_attr" class="sref">n154" class="line" name="L154"> 154};
<  struct 1rp5c01_reaaaaaaaaaaaaach id=f="+code=dev_ge"ufam_attr" class="uf href="+code=tm_year"loff" class="sref">loloff" 5c01_rtc_ops = {povers/rtc/rtc-rp5pov href="+code=tm_year"s hr" class="sref">loc hr" 5c01_rtc_ops = {c hrclass="sref">loc hrL148"class="line" name="L154"> 154};
< spi class="line" name="L152"> 152      bin_attribute dev, struct rtc_c01_set_time,
reftade=r_ofam_attr" class=reftade=r_ofa href="drivers/rtc/kobjclass="sref">lokobj154" bin_attribute dev, struct f="+code=tm_year"kobjclass="sref">lokobj154"" class="line" name="L148"> 148      bin_attribute priv = dev_get_drvdata(dev);
 128      rp5c01_write(locs hr" 5c01_rtc_ops = {coun class="sref">locoun 5c01 class="line" name="L125"> 125
 151sta2         2        rp5c01_write(priv->lock);
 127   2      93static2         2        __r" id="drivers/rtc/rtcoun class="sref">locoun 5c01n>
<;_rtc_ops = {c hrclass="sref">loc hrL148 id=" 0t;);
);
locoun 5c01++f="+code=tm_year"s hrclass="sref">loc hrL148--)" class="line" name="L152"> 152   2    tm->lou85c01_rtc_ops = {de=dev" class="sref"
=f="+code=dev_ge"ufam_attr" class="uf hre++ class="line" name="L127"> 127   2 5    76static2    priv, tm->  76static2         2        rp5c01_reaa href="+code=tm_year"="drivers/rRP5C01_MODE_MODE01,
 (2 << 0)        /* RAMfass="line" name="L76">  76static2    rp5c01_wrass="sref">reE);
 127   2     = {="+code=priv" class="sref">priv, tm->) * povers/rtc/rtc-rp5pov hre) class="line" name="L127"> 127   2         2        rp5c"+code=tm_year"="+code=priv" class="sref">priv, tm->  76static2    RP5C01_MODE_MODE01,
 (2 << 0)        /* RAMfass="line" name="L76">  76static2         2        rp5c01_rearef">reE);
 127   2    if (<2 href="+code=tm" class="2ref">21ad" class="sref">rp5crtc_ops = {="+code=priv" class="sref">priv, tm->) * povers/rtc/rtc-rp5pov hre++" class="line" name="L127"> 127   2         2  tm->priv, tm-> | RP5C01_MODE_MODE01,
7"> 127   2 5  rp5c01_reaaaaaaaaE);
 127   2    rp5c01_ulass="line" name="L92">  92
  92
priv->lock);
 148   2    retur2 rtc_valid_tm(locoun 5c01 class="line" name="L125"> 125
 121
 122sta2ic int rp5c01_set_time(s__ini class="sref">lo__ini 5c01_rtc_ops = {
_probers/rtc/rtc-rp5c01.c#L15">_probe>->tc_class_ops devrtc_"class="line" name="L154"> 154};
2 href="dr2vers/rtc/rtc-rp5c01.c#L124" id2"L124" class="line" name="L124"> 124   2    struc2 rp5c01_priv *devdev 125
rp5c01_priv *priv = dev class="line" name="L125"> 125
spin_loctc_class_ops devdev class="line" name="L125"> 125
rp5c01_loc5c01_set_time(serronam_attr" class=erron>dev class="line" name="L125"> 125
 129   2    rp5c01_write(dev(dev 148   2    rp5c01_wrref=!ite(dev 154};
2    (devdev class="line" name="L125"> 125
  93static2    rp5c01_write(dev_get_drvdata(lokzalid=>->tizeof(ef="+code=dev_get_drvdata" class="sref">dev)f="+code=tm_year"GFP_KERNELvdata" class="sGFP_KERNELL148" class="line" name="L148"> 148   2    rp5c01_wrref=!ite(  88{
rp5cc_valid-ite(dev class="line" name="L125"> 125
 15723"sref">spin_unlock_irq(&" class="sref">lock);
dev(pioremaphref="drivers/rtc/rt=ess="sref">devlocefr L125f="+code=tm_year""esouras_s hrclass="sref">lo"esouras_s hrhref="drivers/rtc/rt=ess="sref">dev 148   2    rref=!ite(dev 152   2     = {erronam_attr" class=erron>dev_ge-ite(dev class="line" name="L125"> 125
rp5cgotonrtc_ops = {out_free=priv" class="sref">out_free=priv>dev class="line" name="L125"> 125
2m-> 121
  93static2    rp5c01_write(n_ini class="sref">losysfs_"sref">n_ini >->lock);
nam_attr" class=68" idf">nL148" class="line" name="L148"> 148   2    rp5c01_write(lock);
nam_attr" class=68" idf">nL148       = nam_attr" class=f">nL148       = "68" i"L67" cl class="line" name="L148"> 148   2    rp5c01_write(lock);
nam_attr" class=68" idf">nL148       = nam_attr" class=f">nL148       = (RP5C01_MODE_MODE01S_IWUSs/rtc/rtc-rp5c01S_IWUSs>dev class="line" name="L125"> 125
rp5c01_unlock(lock);
nam_attr" class=68" idf">nL148       = pr (priv68" idriv">-&g class="line" name="L125"> 125
spin_unlock_irq(&" class="sref">lock);
nam_attr" class=68" idf">nL148       = >, (priv-&g class="line" name="L125"> 125
lock);
nam_attr" class=68" idf">nL148       = loc hrL148 ead( 125
 125
rp5c01_write(privlosref">priv->lock);
 148   2ic const 2truct  122sta2    .read_time( 147   2    .set_class="line" name="L147"> 147   2    rp5c01_write(devread("7"> 147_rivers/rtc/rtc-rp5c01.c#L152" id="L1lass="line" name="L90">7"> 127   2href="dri2ers/rtc/rtc-rp5c01.c#L152" id=25ad" class="sref">rp5c01_reaaaaaaaaaaaaaref="+code=lockTHISid="ULrtc/rtc-rp5c01.cTHISid="ULrL147" class="line" name="L147"> 147   2    rp5c01_uref="+code=tm_year"ISiERs/rtc/rtc-rp5c01ISiERshref="drivers/rtc/rt=t=RP5C01_1_SECOND"t=>dev))" class="line" name="L152"> 152   2n class="2omment">/*
rp5crtc_ops = {erronam_attr" class=erron>dev_gertc_ops = {PTRiERs/rtc/rtc-rp5c01PTRiERshref="drivers/rtc/rt=t=RP5C01_1_SECOND"t=>dev) class="line" name="L147"> 147   2     * The NVRAM is 2rgani25lass="sref">rp5c01_wrgotonrtc_ops = {out_unmap class="sref">pout_unmap91" Lclass="line" name="L125"> 125
 * We provide ac2ess t25   121
rp5c01_write(devread(dev class="line" name="L125"> 125
 122sta2ef="drive2rs/rtc/rtc-rp5c01.c#L63"2 id="26">read_time(dev_gertc_ops = {sysfs_crivte_"sre8343 class="sref">psysfs_crivte_"sre8343>->lokobj154" b;lock);
nam_attr" class=68" idf">nL148" class="line" name="L148"> 148   2 devlass="line" name="L88">  88{
u3226">tm-> = {out_unrigistenam_attr" class=out_unrigisten>dev class="line" name="L125"> 125
  76static2 f="drive2ss/rtc/rtc-rp5c01.c#L17"2i id=26ref">rp5c01_ud="L149" class="line" name="L149"> 149}
<2  struct 2  92
 = {out_unrigistenam_attr" class=out_unrigisten>dev:ass="line" name="L92">  92
rp5c01_write(dev) class="line" name="L147"> 147   2 i27151" rtc_ops = {out_unmap class="sref">pout_unmap91" :ass="line" name="L92">  92
rp5c01_write( 147   2 f="drive2ers/rtc/rtc-rp5c01.c#L732" id=27">read_time(piounmaphref="drivers/rtc/rttc-rp5c01.c#L88" id="L88" ca href="drivers/rtc/regss="sref">dev 147   2 out_free=priv>dev:ass="line" name="L92">  92
rp5c01_write(lokfreehref="drivers/rtc/rttc-rp5c01.c#L88" id="L88" c) class="line" name="L147"> 147   2 ref="dri2rs/rtc/rtc-rp5c01.c#L76"2 id="275ef">rp5c01_ud="L149"+code=tm_year"erronam_attr" class=erron>dev class="line" name="L147"> 147   2 f="drive2"+code=inline" class="sr2ef">i276>tm< class="line" name="L121"> 121
  92
rp5c01_set_time(s__exi class="sref">lo__exi ef">rref="+code=lock01.c#L15">_removers/rtc/rtc-rp5c01.c#L15">_removehref=tc_class_ops devrtc_"class="line" name="L154"> 154};
2rf="drive2="+code=__raw_writel" cl2ass="27   152   2ref="driv2ers/rtc/rtc-rp5c01.c#L812" id=28ad" class="srin_attribute priv = dev_get_drvdata();
 128   2ef="drive2rs/rtc/rtc-rp5c01.c#L82"2 id="28122" class="line" name="L122"> 122sta2eef="driv2href="+code=rp5c01_lock"2 clas28">read_time(psysfs_remove_"sre8343>->lokobj154" b;lock);
nam_attr" class=68" idf">nL148" class="line" name="L122"> 122sta2erp5c01_write(dev" class="line" name="L122"> 122sta2e rp5c01_write(piounmaphref="drivers/rtc/rttc-rp5c01.c#L88" id="L88" ca href="drivers/rtc/regss="sref">dev 147   2ref="driv2ers/rtc/rtc-rp5c01.c#L862" id=28ef">rp5c01_write(lokfreehref="drivers/rtc/rttc-rp5c01.c#L88" id="L88" c) class="line" name="L147"> 147   2rrp5c01_ud="L149" class="line" name="L149"> 149}
<2 void  121
 129   2  rref">rptc_class_ops devrref="+code=lock01.c#L15">_"" nams="sref">dev_"" nam>dev_ge class="line" name="L152"> 152   2         2      devdev_ge class="line" name="L152"> 152   2 f="drive2ers/rtc/rtc-rp5c01.c#L922" id=29d int "7"> 147 152   2 ef="driv2rs/rtc/rtc-rp5c01.c#L93"2 id="29ad" class="sref">rp5c       = ( 152   2 rp5c01_wr},class="line" name="L152"> 152   2  tm->       = (<__exi _p class="sref">p__exi _phref="drivers/rtc/rt=1.c#L15">_removers/rtc/rtc-rp5c01.c#L15">_removehref),class="line" name="L152"> 152   2 ef="driv2 155
 157rp5c01_set_time(s__ini class="sref">lo__ini 5c01_rtc_ops = {
_ini class="sref">lo
_ini href=void"class="line" name="L154"> 154};
2   152   2  rtc_valid_tm(->_"" nams="sref">dev_"" nam>devf="+code=tm_year""_probers/rtc/rtc-rp5c01.c#L15">_probe>-&g) class="line" name="L147"> 147   3     121
 122sta3    rpvoid1_set_time(s__exi class="sref">lo__exi ef">rref="+code=lock01.c#L15">_finirs/rtc/rtc-rp5c01.c#L15">_finihref=void"class="line" name="L154"> 154};
3         3         124   3    rp5c01_write(->_"" nams="sref">dev_"" nam>dev) class="line" name="L147"> 147   3 5   121
tm 157lomodule_ini href="drivers/rtc/rt=1.c#L15">_ini class="sref">lo
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