linux/drivers/pci/quirks.c
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   1/*
   2 *  This file contains work-arounds for many known PCI hardware
   3 *  bugs.  Devices present only on certain architectures (host
   4 *  bridges et cetera) should be handled in arch-specific code.
   5 *
   6 *  Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
   7 *
   8 *  Copyright (c) 1999 Martin Mares <mj@ucw.cz>
   9 *
  10 *  Init/reset quirks for USB host controllers should be in the
  11 *  USB quirks file, where their drivers can access reuse it.
  12 *
  13 *  The bridge optimization stuff has been removed. If you really
  14 *  have a silly BIOS which is unable to set your host bridge right,
  15 *  use the PowerTweak utility (see http://powertweak.sourceforge.net).
  16 */
  17
  18#include <linux/types.h>
  19#include <linux/kernel.h>
  20#include <linux/export.h>
  21#include <linux/pci.h>
  22#include <linux/init.h>
  23#include <linux/delay.h>
  24#include <linux/acpi.h>
  25#include <linux/kallsyms.h>
  26#include <linux/dmi.h>
  27#include <linux/pci-aspm.h>
  28#include <linux/ioport.h>
  29#include <linux/sched.h>
  30#include <linux/ktime.h>
  31#include <asm/dma.h>    /* isa_dma_bridge_buggy */
  32#include "pci.h"
  33
  34/*
  35 * Decoding should be disabled for a PCI device during BAR sizing to avoid
  36 * conflict. But doing so may cause problems on host bridge and perhaps other
  37 * key system devices. For devices that need to have mmio decoding always-on,
  38 * we need to set the dev->mmio_always_on bit.
  39 */
  40static void quirk_mmio_always_on(struct pci_dev *dev)
  41{
  42        dev->mmio_always_on = 1;
  43}
  44DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
  45                                PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
  46
  47/* The Mellanox Tavor device gives false positive parity errors
  48 * Mark this device with a broken_parity_status, to allow
  49 * PCI scanning code to "skip" this now blacklisted device.
  50 */
  51static void quirk_mellanox_tavor(struct pci_dev *dev)
  52{
  53        dev->broken_parity_status = 1;  /* This device gives false positives */
  54}
  55DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
  56DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
  57
  58/* Deal with broken BIOS'es that neglect to enable passive release,
  59   which can cause problems in combination with the 82441FX/PPro MTRRs */
  60static void quirk_passive_release(struct pci_dev *dev)
  61{
  62        struct pci_dev *d = NULL;
  63        unsigned char dlc;
  64
  65        /* We have to make sure a particular bit is set in the PIIX3
  66           ISA bridge, so we have to go out and find it. */
  67        while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
  68                pci_read_config_byte(d, 0x82, &dlc);
  69                if (!(dlc & 1<<1)) {
  70                        dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
  71                        dlc |= 1<<1;
  72                        pci_write_config_byte(d, 0x82, dlc);
  73                }
  74        }
  75}
  76DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82441,      quirk_passive_release);
  77DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82441,      quirk_passive_release);
  78
  79/*  The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
  80    but VIA don't answer queries. If you happen to have good contacts at VIA
  81    ask them for me please -- Alan 
  82    
  83    This appears to be BIOS not version dependent. So presumably there is a 
  84    chipset level fix */
  85    
  86static void quirk_isa_dma_hangs(struct pci_dev *dev)
  87{
  88        if (!isa_dma_bridge_buggy) {
  89                isa_dma_bridge_buggy=1;
  90                dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
  91        }
  92}
  93        /*
  94         * Its not totally clear which chipsets are the problematic ones
  95         * We know 82C586 and 82C596 variants are affected.
  96         */
  97DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C586_0,     quirk_isa_dma_hangs);
  98DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C596,       quirk_isa_dma_hangs);
  99DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82371SB_0,  quirk_isa_dma_hangs);
 100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,       PCI_DEVICE_ID_AL_M1533,         quirk_isa_dma_hangs);
 101DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,      PCI_DEVICE_ID_NEC_CBUS_1,       quirk_isa_dma_hangs);
 102DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,      PCI_DEVICE_ID_NEC_CBUS_2,       quirk_isa_dma_hangs);
 103DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,      PCI_DEVICE_ID_NEC_CBUS_3,       quirk_isa_dma_hangs);
 104
 105/*
 106 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
 107 * for some HT machines to use C4 w/o hanging.
 108 */
 109static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
 110{
 111        u32 pmbase;
 112        u16 pm1a;
 113
 114        pci_read_config_dword(dev, 0x40, &pmbase);
 115        pmbase = pmbase & 0xff80;
 116        pm1a = inw(pmbase);
 117
 118        if (pm1a & 0x10) {
 119                dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
 120                outw(0x10, pmbase);
 121        }
 122}
 123DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
 124
 125/*
 126 *      Chipsets where PCI->PCI transfers vanish or hang
 127 */
 128static void quirk_nopcipci(struct pci_dev *dev)
 129{
 130        if ((pci_pci_problems & PCIPCI_FAIL)==0) {
 131                dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
 132                pci_pci_problems |= PCIPCI_FAIL;
 133        }
 134}
 135DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI,       PCI_DEVICE_ID_SI_5597,          quirk_nopcipci);
 136DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI,       PCI_DEVICE_ID_SI_496,           quirk_nopcipci);
 137
 138static void quirk_nopciamd(struct pci_dev *dev)
 139{
 140        u8 rev;
 141        pci_read_config_byte(dev, 0x08, &rev);
 142        if (rev == 0x13) {
 143                /* Erratum 24 */
 144                dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
 145                pci_pci_problems |= PCIAGP_FAIL;
 146        }
 147}
 148DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,      PCI_DEVICE_ID_AMD_8151_0,       quirk_nopciamd);
 149
 150/*
 151 *      Triton requires workarounds to be used by the drivers
 152 */
 153static void quirk_triton(struct pci_dev *dev)
 154{
 155        if ((pci_pci_problems&PCIPCI_TRITON)==0) {
 156                dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
 157                pci_pci_problems |= PCIPCI_TRITON;
 158        }
 159}
 160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82437,      quirk_triton);
 161DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82437VX,    quirk_triton);
 162DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82439,      quirk_triton);
 163DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82439TX,    quirk_triton);
 164
 165/*
 166 *      VIA Apollo KT133 needs PCI latency patch
 167 *      Made according to a windows driver based patch by George E. Breese
 168 *      see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
 169 *      and http://www.georgebreese.com/net/software/#PCI
 170 *      Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
 171 *      the info on which Mr Breese based his work.
 172 *
 173 *      Updated based on further information from the site and also on
 174 *      information provided by VIA 
 175 */
 176static void quirk_vialatency(struct pci_dev *dev)
 177{
 178        struct pci_dev *p;
 179        u8 busarb;
 180        /* Ok we have a potential problem chipset here. Now see if we have
 181           a buggy southbridge */
 182           
 183        p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
 184        if (p!=NULL) {
 185                /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
 186                /* Check for buggy part revisions */
 187                if (p->revision < 0x40 || p->revision > 0x42)
 188                        goto exit;
 189        } else {
 190                p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
 191                if (p==NULL)    /* No problem parts */
 192                        goto exit;
 193                /* Check for buggy part revisions */
 194                if (p->revision < 0x10 || p->revision > 0x12)
 195                        goto exit;
 196        }
 197        
 198        /*
 199         *      Ok we have the problem. Now set the PCI master grant to 
 200         *      occur every master grant. The apparent bug is that under high
 201         *      PCI load (quite common in Linux of course) you can get data
 202         *      loss when the CPU is held off the bus for 3 bus master requests
 203         *      This happens to include the IDE controllers....
 204         *
 205         *      VIA only apply this fix when an SB Live! is present but under
 206         *      both Linux and Windows this isn't enough, and we have seen
 207         *      corruption without SB Live! but with things like 3 UDMA IDE
 208         *      controllers. So we ignore that bit of the VIA recommendation..
 209         */
 210
 211        pci_read_config_byte(dev, 0x76, &busarb);
 212        /* Set bit 4 and bi 5 of byte 76 to 0x01 
 213           "Master priority rotation on every PCI master grant */
 214        busarb &= ~(1<<5);
 215        busarb |= (1<<4);
 216        pci_write_config_byte(dev, 0x76, busarb);
 217        dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
 218exit:
 219        pci_dev_put(p);
 220}
 221DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_8363_0,       quirk_vialatency);
 222DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_8371_1,       quirk_vialatency);
 223DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_8361,         quirk_vialatency);
 224/* Must restore this on a resume from RAM */
 225DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8363_0,       quirk_vialatency);
 226DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8371_1,       quirk_vialatency);
 227DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8361,         quirk_vialatency);
 228
 229/*
 230 *      VIA Apollo VP3 needs ETBF on BT848/878
 231 */
 232static void quirk_viaetbf(struct pci_dev *dev)
 233{
 234        if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
 235                dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
 236                pci_pci_problems |= PCIPCI_VIAETBF;
 237        }
 238}
 239DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C597_0,     quirk_viaetbf);
 240
 241static void quirk_vsfx(struct pci_dev *dev)
 242{
 243        if ((pci_pci_problems&PCIPCI_VSFX)==0) {
 244                dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
 245                pci_pci_problems |= PCIPCI_VSFX;
 246        }
 247}
 248DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C576,       quirk_vsfx);
 249
 250/*
 251 *      Ali Magik requires workarounds to be used by the drivers
 252 *      that DMA to AGP space. Latency must be set to 0xA and triton
 253 *      workaround applied too
 254 *      [Info kindly provided by ALi]
 255 */     
 256static void quirk_alimagik(struct pci_dev *dev)
 257{
 258        if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
 259                dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
 260                pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
 261        }
 262}
 263DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,       PCI_DEVICE_ID_AL_M1647,         quirk_alimagik);
 264DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,       PCI_DEVICE_ID_AL_M1651,         quirk_alimagik);
 265
 266/*
 267 *      Natoma has some interesting boundary conditions with Zoran stuff
 268 *      at least
 269 */
 270static void quirk_natoma(struct pci_dev *dev)
 271{
 272        if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
 273                dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
 274                pci_pci_problems |= PCIPCI_NATOMA;
 275        }
 276}
 277DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82441,      quirk_natoma);
 278DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443LX_0,  quirk_natoma);
 279DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443LX_1,  quirk_natoma);
 280DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443BX_0,  quirk_natoma);
 281DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443BX_1,  quirk_natoma);
 282DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443BX_2,  quirk_natoma);
 283
 284/*
 285 *  This chip can cause PCI parity errors if config register 0xA0 is read
 286 *  while DMAs are occurring.
 287 */
 288static void quirk_citrine(struct pci_dev *dev)
 289{
 290        dev->cfg_size = 0xA0;
 291}
 292DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM,     PCI_DEVICE_ID_IBM_CITRINE,      quirk_citrine);
 293
 294/*
 295 *  S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
 296 *  If it's needed, re-allocate the region.
 297 */
 298static void quirk_s3_64M(struct pci_dev *dev)
 299{
 300        struct resource *r = &dev->resource[0];
 301
 302        if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
 303                r->start = 0;
 304                r->end = 0x3ffffff;
 305        }
 306}
 307DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3,      PCI_DEVICE_ID_S3_868,           quirk_s3_64M);
 308DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3,      PCI_DEVICE_ID_S3_968,           quirk_s3_64M);
 309
 310/*
 311 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
 312 * ver. 1.33  20070103) don't set the correct ISA PCI region header info.
 313 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
 314 * (which conflicts w/ BAR1's memory range).
 315 */
 316static void quirk_cs5536_vsa(struct pci_dev *dev)
 317{
 318        if (pci_resource_len(dev, 0) != 8) {
 319                struct resource *res = &dev->resource[0];
 320                res->end = res->start + 8 - 1;
 321                dev_info(&dev->dev, "CS5536 ISA bridge bug detected "
 322                                "(incorrect header); workaround applied.\n");
 323        }
 324}
 325DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
 326
 327static void quirk_io_region(struct pci_dev *dev, unsigned region,
 328        unsigned size, int nr, const char *name)
 329{
 330        region &= ~(size-1);
 331        if (region) {
 332                struct pci_bus_region bus_region;
 333                struct resource *res = dev->resource + nr;
 334
 335                res->name = pci_name(dev);
 336                res->start = region;
 337                res->end = region + size - 1;
 338                res->flags = IORESOURCE_IO;
 339
 340                /* Convert from PCI bus to resource space.  */
 341                bus_region.start = res->start;
 342                bus_region.end = res->end;
 343                pcibios_bus_to_resource(dev, res, &bus_region);
 344
 345                if (pci_claim_resource(dev, nr) == 0)
 346                        dev_info(&dev->dev, "quirk: %pR claimed by %s\n",
 347                                 res, name);
 348        }
 349}       
 350
 351/*
 352 *      ATI Northbridge setups MCE the processor if you even
 353 *      read somewhere between 0x3b0->0x3bb or read 0x3d3
 354 */
 355static void quirk_ati_exploding_mce(struct pci_dev *dev)
 356{
 357        dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
 358        /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
 359        request_region(0x3b0, 0x0C, "RadeonIGP");
 360        request_region(0x3d3, 0x01, "RadeonIGP");
 361}
 362DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI,      PCI_DEVICE_ID_ATI_RS100,   quirk_ati_exploding_mce);
 363
 364/*
 365 * Let's make the southbridge information explicit instead
 366 * of having to worry about people probing the ACPI areas,
 367 * for example.. (Yes, it happens, and if you read the wrong
 368 * ACPI register it will put the machine to sleep with no
 369 * way of waking it up again. Bummer).
 370 *
 371 * ALI M7101: Two IO regions pointed to by words at
 372 *      0xE0 (64 bytes of ACPI registers)
 373 *      0xE2 (32 bytes of SMB registers)
 374 */
 375static void quirk_ali7101_acpi(struct pci_dev *dev)
 376{
 377        u16 region;
 378
 379        pci_read_config_word(dev, 0xE0, &region);
 380        quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
 381        pci_read_config_word(dev, 0xE2, &region);
 382        quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
 383}
 384DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL,      PCI_DEVICE_ID_AL_M7101,         quirk_ali7101_acpi);
 385
 386static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
 387{
 388        u32 devres;
 389        u32 mask, size, base;
 390
 391        pci_read_config_dword(dev, port, &devres);
 392        if ((devres & enable) != enable)
 393                return;
 394        mask = (devres >> 16) & 15;
 395        base = devres & 0xffff;
 396        size = 16;
 397        for (;;) {
 398                unsigned bit = size >> 1;
 399                if ((bit & mask) == bit)
 400                        break;
 401                size = bit;
 402        }
 403        /*
 404         * For now we only print it out. Eventually we'll want torks.c#L404" id="L404" class="line" name="5" id="L40f">mask = (         * reserve it (at least if it's in the 0x1000+ range), butrks.c#L404" id="L404" class="line" name="6" id="L406" class="line" name="L406"> 406         * let's get enough confirmation reports first. rks.c#L404" id="L404" class="line" name="7" id="L407" class="line" name="L407"> 407         */
 408        base &= -size;
 409        dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
 410}
 411
 412static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
 413{
 414        u32 devres;
 415        u32 mask, size, base;
 416
 417        pci_read_config_dword(dev, port, &devres);
 418        if ((devres & enable) != enable)
 419                return;
 420        base = devres & 0xffff0000;
 421        mask = (devres & 0x3f) << 16;
 422        size = 128 << 16;
 423        for (;;) {
 424                unsigned bit = size >> 1;
 425                if ((bit & mask) == bit)
 426                        break;
 427                size = bit;
 428        }
 429        /*
 430         * For now we only print it out. Eventually we'll want torks.c#L404" id="L404" class="line" name=31" id="L431" class="line" name="L431"> 431         * reserve it, but let's get enough confirmation reports first. rks.c#L404" id="L404" class="line" name=32" id="L432" class="line" name="L432"> 432         */
 433        base &= -size;
 434        dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
 435}
 436
 437/*
 438 * PIIX4 ACPI: Two IO regions pointed to by longwords at
 439 *      0x40 (64 bytes of ACPI registers)
 440 *      0x90 (16 bytes of SMB registers)
 441 * and a few strange programmable PIIX4 device resources.
 442 */
 443static void quirk_piix4_acpi(struct pci_dev *dev)
 444{
 445        u32 region, res_a;
 446
 447        pci_read_config_dword(dev, 0x40, &region);
 448        quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
 449        pci_read_config_dword(dev, 0x90, &region);
 450        quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
 451
 452        /* Device resource A has enables for some of the other ones */
 453        pci_read_config_dword(dev, 0x5c, &res_a);
 454
 455        piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
 456        piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
 457
 458        /* Device resource D is just bitfields for static resources */
 459
 460        /* Device 12 enabled? */
 461        if (res_a & (1 << 29)) {
 462                piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
 463                piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
 464        }
 465        /* Device 13 enabled? */
 466        if (res_a & (1 << 30)) {
 467                piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
 468                piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
 469        }
 470        piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
 471        piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
 472}
 473DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82371AB_3,  quirk_piix4_acpi);
 474DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82443MX_3,  quirk_piix4_acpi);
 475
 476#define ICH_PMBASE      0x40
 477#define ICH_ACPI_CNTL   0x44
 478#define  ICH4_ACPI_EN   0x10
 479#define  ICH6_ACPI_EN   0x80
 480#define ICH4_GPIOBASE   0x58
 481#define ICH4_GPIO_CNTL  0x5c
 482#define  ICH4_GPIO_EN   0x10
 483#define ICH6_GPIOBASE   0x48
 484#define ICH6_GPIO_CNTL  0x4c
 485#define  ICH6_GPIO_EN   0x10
 486
 487/*
 488 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
 489 *      0x40 (128 bytes of ACPI, GPIO & TCO registers)
 490 *      0x58 (64 bytes of GPIO I/O space)
 491 */
 492static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
 493{
 494        u32 region;
 495        u8 enable;
 496
 497        /*
 498         * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
 499         * with low legacy (and fixed) ports. We don't know the decoding
 500         * priority and can't tell whether the legacy device or the one created
 501         * here is really at that address.  This happens on boards with broken
 502         * BIOSes.
 503        */
 504
mask = (        pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
 506        if (enable & ICH4_ACPI_EN) {
 507                pci_read_config_dword(dev, ICH_PMBASE, &region);
 508                region &= PCI_BASE_ADDRESS_IO_MASK;
 509                if (region >= PCIBIOS_MIN_IO)
 510                        quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
 511                                        "ICH4 ACPI/GPIO/TCO");
 512        }
 513
 514        pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
 515        if (enable & ICH4_GPIO_EN) {
 516                pci_read_config_dword(dev, ICH4_GPIOBASE, &region);
 517                region &= PCI_BASE_ADDRESS_IO_MASK;
 518                if (region >= PCIBIOS_MIN_IO)
 519                        quirk_io_region(dev, region, 64,
 520                                        PCI_BRIDGE_RESOURCES + 1, "ICH4 GPIO");
 521        }
 522}
 523DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801AA_0,         quirk_ich4_lpc_acpi);
 524DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801AB_0,         quirk_ich4_lpc_acpi);
 525DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801BA_0,         quirk_ich4_lpc_acpi);
 526DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801BA_10,        quirk_ich4_lpc_acpi);
 527DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801CA_0,         quirk_ich4_lpc_acpi);
 528DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801CA_12,        quirk_ich4_lpc_acpi);
 529DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801DB_0,         quirk_ich4_lpc_acpi);
 530DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801DB_12,        quirk_ich4_lpc_acpi);
 531DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801EB_0,         quirk_ich4_lpc_acpi);
 532DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_ESB_1,             quirk_ich4_lpc_acpi);
 533
 534static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
 535{
 536        u32 region;
 537        u8 enable;
 538
 539        pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
 540        if (enable & ICH6_ACPI_EN) {
 541                pci_read_config_dword(dev, ICH_PMBASE, &region);
 542                region &= PCI_BASE_ADDRESS_IO_MASK;
 543                if (region >= PCIBIOS_MIN_IO)
 544                        quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
 545                                        "ICH6 ACPI/GPIO/TCO");
 546        }
 547
 548        pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
 549        if (enable & ICH6_GPIO_EN) {
 550                pci_read_config_dword(dev, ICH6_GPIOBASE, &region);
 551                region &= PCI_BASE_ADDRESS_IO_MASK;
 552                if (region >= PCIBIOS_MIN_IO)
 553                        quirk_io_region(dev, region, 64,
 554                                        PCI_BRIDGE_RESOURCES + 1, "ICH6 GPIO");
 555        }
 556}
 557
 558static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
 559{
 560        u32 val;
 561        u32 size, base;
 562
 563        pci_read_config_dword(dev, reg, &val);
 564
 565        /* Enabled? */
 566        if (!(val & 1))
 567                return;
 568        base = val & 0xfffc;
 569        if (dynsize) {
 570                /*
 571                 * This is not correct. It is 16, 32 or 64 bytes depending on
 572                 * register D31:F0:ADh bits 5:4.
 573                 *
 574                 * But this gets us at least _part_ of it.
 575                 */
 576                size = 16;
 577        } else {
 578                size = 128;
 579        }
 580        base &= ~(size-1);
 581
 582        /* Just print it out for now. We should reserve it after more debugging */
 583        dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
 584}
 585
 586static void quirk_ich6_lpc(struct pci_dev *dev)
 587{
 588        /* Shared ACPI/GPIO decode with all ICH6+ */
 589        ich6_lpc_acpi_gpio(dev);
 590
 591        /* ICH6-specific generic IO decode */
 592        ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
 593        ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
 594}
 595DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
 596DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
 597
 598static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
 599{
 600        u32 val;
 601        u32 mask, base;
 602
 603        pci_read_config_dword(dev, reg, &val);
 604
mask = (        /* Enabled? */
 606        if (!(val & 1))
 607                return;
 608
 609        /*
 610         * IO base in bits 15:2, mask in bits 23:18, both
 611         * are dword-based
 612         */
 613        base = val & 0xfffc;
 614        mask = (val >> 16) & 0xfc;
 615        mask |= 3;
 616
 617        /* Just print it out for now. We should reserve it after more debugging */
 618        dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
 619}
 620
 621/* ICH7-10 has the same common LPC generic IO decode registers */
 622static void quirk_ich7_lpc(struct pci_dev *dev)
 623{
 624        /* We share the common ACPI/GPIO decode with ICH6 */
 625        ich6_lpc_acpi_gpio(dev);
 626
 627        /* And have 4 ICH7+ generic decodes */
 628        ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
 629        ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
 630        ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
 631        ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
 632}
 633DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
 634DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
 635DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
 636DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
 637DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
 638DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
 639DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
 640DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
 641DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
 642DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
 643DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
 644DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
 645DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
 646
 647/*
 648 * VIA ACPI: One IO region pointed to by longword at
 649 *      0x48 or 0x20 (256 bytes of ACPI registers)
 650 */
 651static void quirk_vt82c586_acpi(struct pci_dev *dev)
 652{
 653        u32 region;
 654
 655        if (dev->revision & 0x10) {
 656                pci_read_config_dword(dev, 0x48, &region);
 657                region &= PCI_BASE_ADDRESS_IO_MASK;
 658                quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
 659        }
 660}
 661DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_82C586_3,     quirk_vt82c586_acpi);
 662
 663/*
 664 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
 665 *      0x48 (256 bytes of ACPI registers)
 666 *      0x70 (128 bytes of hardware monitoring register)
 667 *      0x90 (16 bytes of SMB registers)
 668 */
 669static void quirk_vt82c686_acpi(struct pci_dev *dev)
 670{
 671        u16 hm;
 672        u32 smb;
 673
 674        quirk_vt82c586_acpi(dev);
 675
 676        pci_read_config_word(dev, 0x70, &hm);
 677        hm &= PCI_BASE_ADDRESS_IO_MASK;
 678        quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
 679
 680        pci_read_config_dword(dev, 0x90, &smb);
 681        smb &= PCI_BASE_ADDRESS_IO_MASK;
 682        quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
 683}
 684DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_82C686_4,     quirk_vt82c686_acpi);
 685
 686/*
 687 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
 688 *      0x88 (128 bytes of power management registers)
 689 *      0xd0 (16 bytes of SMB registers)
 690 */
 691static void quirk_vt8235_acpi(struct pci_dev *dev)
 692{
 693        u16 pm, smb;
 694
 695        pci_read_config_word(dev, 0x88, &pm);
 696        pm &= PCI_BASE_ADDRESS_IO_MASK;
 697        quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
 698
 699        pci_read_config_word(dev, 0xd0, &smb);
 700        smb &= PCI_BASE_ADDRESS_IO_MASK;
 701        quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
 702}
 703DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
 704
mask = (/*
 706 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
 707 *      Disable fast back-to-back on the secondary bus segment
 708 */
 709static void quirk_xio2000a(struct pci_dev *dev)
 710{
 711        struct pci_dev *pdev;
 712        u16 command;
 713
 714        dev_warn(&dev->dev, "TI XIO2000a quirk detected; "
 715                "secondary bus fast back-to-back transfers disabled\n");
 716        list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
 717                pci_read_config_word(pdev, PCI_COMMAND, &command);
 718                if (command & PCI_COMMAND_FAST_BACK)
 719                        pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
 720        }
 721}
 722DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
 723                        quirk_xio2000a);
 724
 725#ifdef CONFIG_X86_IO_APIC 
 726
 727#include <asm/io_apic.h>
 728
 729/*
 730 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
 731 * devices to the external APIC.
 732 *
 733 * TODO: When we have device-specific interrupt routers,
 734 * this code will go away from quirks.
 735 */
 736static void quirk_via_ioapic(struct pci_dev *dev)
 737{
 738        u8 tmp;
 739        
 740        if (nr_ioapics < 1)
 741                tmp = 0;    /* nothing routed to external APIC */
 742        else
 743                tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
 744                
 745        dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
 746               tmp == 0 ? "Disa" : "Ena");
 747
 748        /* Offset 0x58: External APIC IRQ output control */
 749        pci_write_config_byte (dev, 0x58, tmp);
 750}
 751DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C686,       quirk_via_ioapic);
 752DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,       PCI_DEVICE_ID_VIA_82C686,       quirk_via_ioapic);
 753
 754/*
 755 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
 756 * This leads to doubled level interrupt rates.
 757 * Set this bit to get rid of cycle wastage.
 758 * Otherwise uncritical.
 759 */
 760static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
 761{
 762        u8 misc_control2;
 763#define BYPASS_APIC_DEASSERT 8
 764
 765        pci_read_config_byte(dev, 0x5B, &misc_control2);
 766        if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
 767                dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
 768                pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
 769        }
 770}
 771DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_8237,         quirk_via_vt8237_bypass_apic_deassertivers href="drref="dria7quirk77c#L752" id="L752" class="line" name="L752"> 752DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA<,      PCI_DEVICE_ID_VIA_8237,         quirk_via_vt8237_bypass_apic_deontrol2;
 6737/a>
 754dev);
ommebox wL733id=eass irqn cl">baed> * Otherwise uncri675"> 6757/a>
ommeprmeprod>quion!) 21"> 62bug * Otherwise uncri6SERT)>);
raed NoFix * Otherwise uncri6ot;;
 * Otherwise uncri6ASSERT);
 733 * TI * Otherwise uncri679"> 6797/a>
 For"> 62mommentwe 21sume it9;t s1"> 62erratum."W> m> * Otherwise uncrief">smb);
 "> 62adnL766so.> * Otherwise uncri_IO_MASK<7a>;
 759quirk_via_vt8237_bypass_apic_deassert(struct pci_dev * 683<7a>}
BYPASS_APIC_DEA86_acpi);
 655        if (dev->BYPASS_APIC_DEA685"> 6857/a>
 714        dev_warn(&dev->nt"an in+cability tryquot;Bypassing VIA 8237 APIC De-Assert Message\n&qnt">/*
 714        dev_warn(&dev->
 771DECLARE_PCIAMDUME_EARLY(PCI_VENDOR_AMDDEVPER_74a>)
 */
quirk_via_vt8237_bypass_apic_deassert(struct pci_dev * 692<7a>{
BYPASS_APIC_DEAref">smb<7a>;
 655        if ( 714   fn          ef="+misc_control2" class=ame="L655"> 655        if ( 740      bu"      if ( 6857>);
/*;
 771DECLARE_PCISFIXUP_FINAL(PCANYcodIXUP_FINAL(,        759 6987/a>
smb);
 754 7settrinTI 7ata co="coms="cso block canng"> * This leads to doubled level interrupt8uot;);
 7-X Tunnel Ra>-> Guide* This leads to doubled level interrupt8u3t;>{
 759quirk_via_vt8237_bypass_apic_deassert(struct pci_dev * 7048/a>
BYPASS_APIC_DE8nt">/*
 655        if (dev-> 655        if (dev->BYPASS_APIC_DE8-back:
 767                dev_info(&dev-> ss="sx, "TI XIO2000a quirk detected;8egment
 7-X MMRBCg">"%sbcontrol2" class=ame="L655"> 655        if (dev-> */
 655        if (dev-> 740      bu"_flag"#L719|(misc8ref">dev<8a>)
 72810"> 710<8a>{
pdev<8a>;
 722DECLARE_PCIAMDUME_EARLY(PCI_VENDOR_AMDD8131_"+code)
,        7138/a>
 754omat via_vt8237=quirkname="L754"> 754/*);
 ed>  It shows up 21"30 754  The"> ore* This leads to doubled level interrupt8command);
ommep(struc9;t s1"9;t sirq9;t se731"> * This leads to doubled level interrupt8c"> */)
 * Set this bit to get rid of cycle w8ST_BACK);
 * Set this bit to get rid of cycle w8S0"> 710<8  }
 759 721<8a>}
quirk_vt8235_acpi(struct  655_dev *BYPASS_APIC_DE8io2000a);
 754 7248/a>
pci_wr 689 754/* 
 759 762         7irqcode=misc_control2" class="sref">misc8pic.h8gt;
 765         655_dev,e="L2 7irqcodeVIA 8237 APIC De-Assert Message\n&8728"> 7288/a>
 7irqcode      /*
 7irqcode      misc_c" class="line" nirq name="L762"> 7irqcode != 2) * 655_dev  if ( 7irqcode  7irqcode=misc_control2" class="sref">misc8 APIC.
 *
 703DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIIA_82Ca>,      
 684DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,      7248an>
 */
dev<8a>)
 754 737<8a>{
 * Set this bit to get rid of cycle w8ref">tmp<8a>;
 759 759        8237_="dktruc_l code 
 *quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *BYPASS_APIC_DE8         8   
 733ne" name="L759"> 759 */,
 655        if ( 655  spa_devBYPASS_APIC_DE8uot;);
PCI_VENDOR_ID_VIA,       BYPASS_APIC_DE8u7"> 737<8/a>
tmp);
 759 750<8a>}
        8237_="dktruc_l code PCSLOontrol2|PCSLOoconfig_byte" class="sme="L655"> 655        if ( 714   fn    VIA 8237 APIC De-Assert Message\n&8_ioapic);
PCSLOontrol2|PCSLOoconfig_byte" class="sme="L655"> 655        if ( 714   fn    VIA 8237 APIC De-Assert Message\n&8_t"> *);

PCI_VENDOR_ID_VIA<,      BYPASS_APIC_DE8nt">/*
PCI_VENDOR_ID_VIA<, BYPASS_APIC_DE8n"> */
        8237_="dktruc_l code 
 737<8an>
PCI_VENDOR_ID_VIA<<5, BYPASS_APIC_DE8nol */
        8237_="dktruc_l code  */
dev<8a>)
PCI_VENDOR_ID_VIA<<1, BYPASS_APIC_DE861"> 761<8a>{
PCI_VENDOR_ID_VIA<<3_>)
BYPASS_APIC_DE86t"> *;
PCI_VENDOR_ID_VIA<<3I, BYPASS_APIC_DE8EASSERT 8
PCI_VENDOR_ID_VIA<<3C_>)
BYPASS_APIC_DE86t">/*
        8237_="dktruc_l code  */);
 684DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIAPCI_DEVICE_ID_Vbspan f="+code=quirk_via_vt8237bspan s="sVIA 8237 APIC De-Assert Message\n&8     8  }
 684DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VI<1, PCI_DEVICE_ID_Vbspan f="+code=quirk_via_vt8237bspan s="sVIA 8237 APIC De-Assert Message\n&8dev<8a>}
 684DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VI<3_>)
PCI_DEVICE_ID_Vbspan f="+code=quirk_via_vt8237bspan s="sVIA 8237 APIC De-Assert Message\n&8<1"> 761<8>ivers href="drref="dria8quirk87c#L752" id="L752" class="line" name="L684"> 684DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VI<3I, PCI_DEVICE_ID_Vbspan f="+code=quirk_via_vt8237bspan s="sVIA 8237 APIC De-Assert Message\n&8 *;
 703DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VI<3C_>)
 684DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VI<5, PCI_DEVICE_ID_Vbspan f="+code=quirk_via_vt8237bspan s="sVIA 8237 APIC De-Assert Message\n&8/*);
 684DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VI,      PCI_DEVICE_ID_Vbspan f="+code=quirk_via_vt8237bspan s="sVIA 8237 APIC De-Assert Message\n&8<"> */
 684DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VI, PCI_DEVICE_ID_Vbspan f="+code=quirk_via_vt8237bspan s="sVIA 8237 APIC De-Assert Message\n&8);
 754 754 6798/a>
>  spa_dname="L754"> 754dev<8>);
 754 761<8a>;
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omat ommeclas="drcclass="c which usually"is totccllevantrkname="L754"> 754 683<8a>}
pards,n classually"+codte"cso omat lass="coms57 754/*);
 7right placnt"> * Set this bit to get rid of cycle w8685"> 6858/a>
aa namsount"bspan 3"as, /*
 orm nam name="Lon"> 62monameboard (see via_vt8237bspan s=n we have device-specific interrupt r8not;
 * Set this bit to get rid of cycle w86ASSERT
 759 759 */
="dkf="+code=quirk_via_vt8237>="dks="sref">quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *BYPASS_APIC_DE892"> 692<8a>{
 762         7irqcodeDOVIA" class="srenew_irq name="L762"> 7new_irqcodeIA 8237 APIC De-Assert Message\n&8ref">smb<8a>;
 733 759 6858>);
        8237_="dktruc_l code < */*;
);
 6988/a>
 7new_irqcode   763" class="linsme="L655"> 655        if ( 7irqcode=misc_control2" class="sref">misc9ef">smb);
 759 62legacyeclasrnng"ne" name="L759"> 759 7new_irqcode ||L749" class="linnew_irq name="L762"> 7new_irqcode  if  15 *);
 7049/a>
 759 7049/);
 655        if ( 740      bu"      if (PCSLOontrol2|PCSLOoconfig_byte" class="sme="L655"> 655        if ( 714   fn    V  if  ss="line" name=8237_="dktruc_hif="+code=quirk_8237_="dktruc_hi     ||L759"> 759 7049/>;
PCSLOontrol2|PCSLOoconfig_byte" class="sme="L655"> 655        if ( 714   fn    V  lf  ss="line" name=8237_="dktruc_l 767        8237_="dktruc_l code * 7049/);
 7049/a>
dev<9a>)
 759 710<9a>{
 759pdev<9a>;
 765        dev-&49" class="lin">PCINTERRUPT_LINEntrol2|PCINTERRUPT_LINEv- href="+code=dev" clirq name="L762"> 7irqcodeVIA 8237 APIC De-Assert Message\n&9713"> 7139/a>
 7new_irqcode ! 7irqcodeBYPASS_APIC_DE9"
 767                dev_info(&dev-> ss="s7g">"%sbling VIA external APIC routing\n9&t">/*);
 7irqcodeDOVIA" class="srenew_irq name="L762"> 7new_irqcodeVIA 8237 APIC De-Assert Message\n&9774"> 7049) {
 76delay edne" name="L759"> 759 7049>);
 768                pci_write_config_byte<&49" class="lin">PCINTERRUPT_LINEntrol2|PCINTERRUPT_LINEv-VIA" class="srenew_irq name="L762"> 7new_irqcodeVIA 8237 APIC De-Assert Message\n&9794"> 7049a>)
 769ST_BACK);
 710<9  }
DECLARE_PCI_FIXUP_HEADER(DEANYcodIXUP_FINAL(="dkf="+code=quirk_via_vt8237>="dks="sVIA 8237 APIC De-Assert Message\n&921"> 721<9a>}
 75430d manye55 754 75ommecDI ormbackward clapatibilityt"> * Set this bit to get rid of cycle w97t">/* 
 t"> * VLswitch it"anf* VLb">307">oocclcognize"> 62clal"> * Set this bit to get rid of cycle w9774"> 7049/a>
 * Set this bit to get rid of cycle w9784"> 7049gt;
 759 7289/a>
 655quirk_via_vt8237_bypass_apic_deassert(struct pci_dev */*
BYPASS_APIC_DE9n-chip
 768                pci_write_config_byte<0xfce<0VIA 8237 APIC De-Assert Message\n&9 APIC.
 655pci_write_config_byte<&49" class="lin">PCe=PCI_DEV,  655        if ( 655  spa_dev
 684DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA597_>)
 655
 */
 754dev<9a>)
 6m" name="L754"> 754 7049a>{
82365 pcmcia  href="l> 754tmp<9a>;
nL766ommeLinux"CardBus 4<"is totcloa ed,Lb"caus s=n we have device-specific interrupt r99    9   
82365 4<"doesanot (30d shouldanot)pannd7">CardBust"> * Set this bit to get rid of cycle w99-chip 759 655quirk_via_vt8237_bypass_apic_deassert(struct pci_dev * *BYPASS_APIC_DE9PIC */
 768  dwors="L655"> 655 768  dworsonfig_byte" class="sref">pci_write_config_byte<&49" class="lin">PCCB_LEGACY_MODE_BASEntrol2|PCCB_LEGACY_MODE_BASE_byte<0 */,
 722_HEADER" class="sref">DEANYcodIXUP_FINAL(DEANYcodIXUP_FINAL(dev<9>);
|PCC="SSL"+code_CARDBUS_VIA_88_8 class="line" name="Lpardbu"_legacy="L655"> 655 7049/a>
 752 752DEANYcodIXUP_FINAL(DEANYcodIXUP_FINAL(tmp<9an>
|PCC="SSL"+code_CARDBUS_VIA_88_8 class="line" name="Lpardbu"_legacy="L655"> 655tmp);
 759 750<9a>}
 754 62AMD762. Ian clmanotrkname="L754"> 754 *);
wmat ommedesign>smokde= 5ut let9;t s1"not inhale..> * Otherwise uncr9_IC */
 * Otherwise uncr9_        9an>
fair"oocAMD," XIf="low1"> 62 cla byea>fault, > = 55 */
dev<9an>
 759 737<9an>
 655quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *BYPASS_APIC_DE9t"> */

 763c#L762rk_via_vt8237_bypaC686,       ypaC#L76IA 8237 APIC De-Assert Message\n&9ref">dev<9a>)
 655pci_write_config_byte<0x4C>- href="+code=dev" clypaC686,       ypaC#L76 761<9a>{
BYPASS_APIC_DE96t"> *;
 714        dev_warn(&dev-> * VLe"707"e0" ndards clapliance;sfixrin>omameerrorquot;Bypassing VIA 8237 APIC De-Assert Message\n&96t">/*
 768  dwors="L655"> 655 768  dworsonfig_byte" class="sref">pci_write_config_byte<0x4C>-="+code=dev" clypaC686,       ypaC#L76 */);
 655pci_write_config_byte<0x84>- href="+code=dev" clypaC686,       ypaC#L76dev<9) {
,       ypaC#L769| 759 768  dwors="L655"> 655 768  dworsonfig_byte" class="sref">pci_write_config_byte<0x84>-="+code=dev" clypaC686,       ypaC#L76);
 769     9  }
dev<9a>}
 722DECLARE_PCIAMDUME_EARLY( 655 761<9>ivers href="drref="dria9quirk97c#L752" id="L752" class="line" name="L752"> 752 752DEECLARE_PCIAMDUME_EARLY( 655 *;
 754/*);
 754 */
 754dev<9>);
30d clspo0d"L731addressesanot appars="ly" name="L754"> 754 * VLit."We forcomat" name="L754"> 754get" pu"> 7o="Lose* VLit." name="L754"> 754 6799/a>
 759dev<9>);
 655quirk_via_vt8237_bypass_apic_deassert(struct pci_dev * 761<9a>;
BYPASS_APIC_DE96t"> *);
quirk_via_vt8237_bresourpa="L655"> 655 655        if ( 655 683<9a>}
 740      r      if (/*);
 740      r      if ( 655 */
/*
 684DECLARE_PCI_DUNORDUME_EARLY( 655
 75482380FB mobilmeaockde=  href="l><: > = bspan s=n we have device-specific interrupt r9t"> */
omams=n we have device-specific interrupt r9t1"> 761<9a>)
 62ProgIf. Unfortunamely,"> 62ProgIf"valueIis wroe= -<0x80s=n we have device-specific interrupt r9tt"> *{
 754smb<9a>;
 759quirk_via_vt8237_bypass_apic_deassert(struct pci_dev * 6859>);
BYPASS_APIC_DE9tt">/*;
 655        if ( 655);
 6989/a>
 684DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_ss="line" name=">PCcode=PCI_DINTE>_82380FBIXUP_FINAL(_82380FB_VENDOR_I class="line" name="Ltranspars="Vbspan f="+code=quirk_via_vttranspars="Vbspan s="ssmb);
 684DECLARE_PCI_TOSHIBXUP_HEADER();> 8237 APIC De-Assert Message\n&10e1">smbn>
smb>)
 754smb>{
 urams="*mas="c omat will"> * Set this bit to get rid of cycle w1004">smb>;
b30dwidth from 70MB/"L73125MB/". LSemeommeGXM/GXLV/GX1"> * Set this bit to get rid of cycle w1005">smba>
 754smb);
 = ao. L lf chrss="c@weinigel.se if ( name="L754"> 754smb>;
 759smb);
quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *smba>
BYPASS_APIC_DE101f">smb)
 762         655smb{
        dev-0x41>- href="+code=dev" clre=="L655"> 655smb;
 655BYPASS_APIC_DE10a3">smb;
 655smb
 767                dev_info(&dev->"%sba_byte" class="sre=="L655"> 655smb
 768                pci_write_config_byte<0x41>-_byte" class="sre=="L655"> 655smb);
smb10a7#L762" id="L702" class="line" name="L10a8">smb);
 722DECLARE_PCICYRIXUP_HEADER( 684 _VIA_8 class="line" name="Lmediagx_mas="cf="+code=quirk_via_vtmediagx_mas="cs="ssmb)
 > UP_FINAL" class="sref">DECLARE_PCICYRIXUP_HEADER( 684 _VIA_8 class="line" name="Lmediagx_mas="cf="+code=quirk_via_vtmediagx_mas="cs="ssmb);
smb10>c#L731" id="L731" class="line" name="L754"> 754smb}
C0"rev clst"+cmde= ame=ff.LTmamei1"normally"dodr by" name="L754"> 754smb,
 62oddLcas"Lit"is totc> 62clsul = 2rmeco="coms="" name="L754"> 754smb);
 754smb
 759smb 
 655quirk_via_vt8237_bypass_apic_deassert(struct smb
BYPASS_APIC_DE1028">smb10>c#L768" id="Lss="line" name=u>);
 76ac#L656ss="line" name=pci_wr;
 7pci_wr#L76IA 8237 APIC De-Assert Message\n&1029">smb
smb
pci_dev  if ( 655s>omamee" name="L759"> 759smb
smb
 655 7pci_wr#L76smb
 7pci_wr#L76- href (1 lf  lf 6)BYPASS_APIC_DE1034">smb
 7pci_wr#L76- href= ~(1 lf  lf 6)IA 8237 APIC De-Assert Message\n&1035">smb
 768  wors="L655"> 655 768  worsonfig_byte" class="sps_apic_deassertpci_deve<0x40>-="+code=dev" clpci_wr;
 7pci_wr#L76smb
 767                pci_dev  if (dev->smb)
smb{
smb;
 722DECLARE_PCIINTE> 722DECLARE_PCI_INTE>_VENDOR__ss="line" name=">PCcode=PCI_DINTE>_82454NXUP_HEADER(_82454NX_VENDOR_I class="line" name="Ldis707"_pxb="L655"> 655smb10  #L764" id="L684" class="line" name="L752"> 752 752DEECLARE_PCIINTE> 722DECLARE_PCI_INTE>_VENDOR___ss="line" name=">PCcode=PCI_DINTE>_82454NXUP_HEADER(_82454NX_VENDOR_I class="line" name="Ldis707"_pxb="L655"> 655smb10 1#L728" id="L728" class="line" name="1042">smb
 655quirk_via_vt8237_bypass_apic_deassert(struct smb10 c#L69SERT" class="sref">BYPASS_APIC_DE10 4">smb
mamene" name="L759"> 759smb10 5#L741" id="Lss="line" name=u" name="L762"> 762         655smb,
smb);
        ( 655smb
 655BYPASS_APIC_DE1049">smb
         655smb);
 768                 655smb}
 768                smb);
 768                smb);
 768                 655smb
smb
pci_dev  if ( 7pa hr#L76 <(smb
 767                pci_dev  if (dev->mamequot;Bypassing VIA 8237 APIC De-Assert Message\n&1057">smb
smb
smb
 684DECLARE_PCI_ATaUP_HEADER( 655smb
 752 752DEECLARE_PCIATaUP_HEADER( 655smb)
 684DECLARE_PCI_ATaUP_HEADER( 655smb{
 752 752DEECLARE_PCIATaUP_HEADER( 655smb;
 684DECLARE_PCI_AMDUME_EARLY( 655smb 8
 752 752DEECLARE_PCIAMDUME_EARLY( 655smb
smb);
 754smb10ac#L757" id="L757" class="line""""""Sera> 754smb);
 759smb);
 655quirk_via_vt8237_bypass_apic_deassert(struct smb10  #L69SERT" class="sref">BYPASS_APIC_DE1071">smb}
 762         7pror#L76IA 8237 APIC De-Assert Message\n&1072">smbivers href="drref="dria10>iv>10 c#L762" id="L762" class="linref="+code=pci_r765        ( 7pror#L76VIA 8237 APIC De-Assert Message\n&1073">smb;
 7pror#L76- href 5BYPASS_APIC_DE1074">smb
 7pror#L76- href= ~5IA 8237 APIC De-Assert Message\n&1075">smb);
pci_dev  if ( 7pa hr#L76  href= ~5IA 8237 APIC De-Assert Message\n&1076">smb
 768                ( 7pror#L76VIA 8237 APIC De-Assert Message\n&1077">smb);
 759smb;
smb);
smb
DEECLARE_PCISERVERWORKSntrol2|PCECLARE_PCISERVERWORKS_VENDOss="line" name=">PCcode=PCI_DSERVERWORKS_CSB5IDPUP_HEADER( 655smb);
smb;
 754smb);
> 62 rs/" name="L754"> 754smb}
 759smb);
 655quirk_via_vt8237_bypass_apic_deassert(struct smb
BYPASS_APIC_DE10/7">smb
 762         7pror#L76IA 8237 APIC De-Assert Message\n&1088">smb
smb
        ( 7pror#L76VIA 8237 APIC De-Assert Message\n&109f">smb
smb
 7pror#L76- href 1)- href href !"="+code=dev" clpror;
 7pror#L76- href 4)) ||6"g_byte" class="syror;
 7pror#L76- href 4)- href href !"="+code=dev" clpror;
 7pror#L76- href 1))BYPASS_APIC_DE1092">smb)
 767                pci_dev  if (dev->smb{
 7pror#L76- href= ~5IA 8237 APIC De-Assert Message\n&1094">smb;
 7pa hr#L76  href= ~5IA 8237 APIC De-Assert Message\n&1095">smb
 768                ( 7pror#L76VIA 8237 APIC De-Assert Message\n&1096">smb);
smb;
smb);
DEECLARE_PCIINTE> 722DECLARE_PCI_INTE>_VENDOss="line" name=">PCcode=PCI_DINTE>_82801CA_10IXUP_FINAL(_82801CA_10_VIA_8 class="line" name="Lide_ rs/mame="L655"> 655smb
smb);
 754smbn>
 754smb>)
 759smb>{
smb>;
 655quirk_via_vt8237_bypass_apic_deassert(struct smba>
BYPASS_APIC_DE1106">smb);
pci_dev  if ( 7=de_flaga#L656|< 655PCcod_FLAGS_NO_D3#L76IA 8237 APIC De-Assert Message\n&1107">smb>;
smb);
> 62legacyeATA pciipameonly.LTmecAH/a>one= 2rmeokne" name="L759"> 759smba>
DEECLARE_PCISERVERWORKSntrol2|PCECLARE_PCISERVERWORKS_VENDOss="line" name=">PCANYcodIXUP_FINAL(smb)
( 655smb{
DEECLARE_PCIATaUP_HEADER(smb;
( 655smb;
 6n>clstorene" name="L759"> 759smb
DEECLARE_PCIA> 722DECLARE_PCI_A>_VENDOss="line" name=">PCANYcodIXUP_FINAL(smb
( 655smb);
 759smb111c#L757" id="L757" class="lin  occur w 6n>mamendetectde=ne" name="L759"> 759smb);
DEECLARE_PCIVIA 722DECLARE_PCI_VIA_VENDOss="line" name=">PCANYcodIXUP_FINAL(smb)
( 655smb);
smb11>c#L731" id="L731" class="lineLTmamewameoriginally"id=Alpha specifd="thrin, 5ut it really"f> = here." name="L754"> 754smb}
82375Lbspan  appear= 2sanon-"L732ifded. Fix omat." name="L754"> 754smb,
 759smb);
quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *smb
BYPASS_APIC_DE1126">smb 
dev_info(& 7pa hr#L76 <(smb
smb112c#L766" id="L684" class="line" name="L684"> 684DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_ss="line" name=">PCcode=PCI_DINTE>_823>);
(_823 c#L71DOid="Lss="line" name=ame="LeisaVbspan f="+code=quirk_via_vteisaVbspan s="sVIA 8237 APIC De-Assert Message\n&1129">smb
smb
smb
 754smb
 62SMBu=  62ICH2/4 southbspan s=n we have device-specific interrupt r1133">smb
 6y"doanot want > 6s=n we have device-specific interrupt r1134">smb
rritated by justLanoth"cL 62Win98 pciipas=n we have device-specific interrupt r1135">smb
 62lm_sensoci*s=n we have device-specific interrupt r1136">smb
smb)
smb{
  ri"> 62ICH LPC*s=n we have device-specific interrupt r1139">smb;
 isapciipa h2sano  ubvendor/ ubpciipa ID. SVLit*s=n we have device-specific interrupt r114f">smb114c#L730" id="L730" class="line"beclaamenecessary  VLdoa> isatw+ckL7i">wo  teps --"> 62chosen trigg"cs=n we have device-specific interrupt r1141">smb114c#L731" id="L731" class="linemis eith"cL> 62HostLbspan  (pdeverred) or on-board VGA  href="l><." name="L754"> 754smb
 754smb114c#L733" id="L733" class="line"Note omat we use * VLunhide"> 62SMBu= omat wayLon"Toshib32laptops name="L759"> 759smb
 6n>fou0d omat > 6 > 6rmal"managems="  ame="L759"> 759smb114c#L755" id="L755" class="line"wamedodr by2SMM name, which nauldLcauseLunsynchronize * hrcurrs="  ame="L759"> 759smb,
 62SMBu= regss="cs,"with potentially"bad effects. Tmu= you  ame="L759"> 759smb);
 7ul w 6n>ad"de= new s="ries:L766SMM is accessde= > 6s=n we have device-specific interrupt r1148">smb
 isais ac> 754smb
 754smb);
smb}
 6n>Linux"shauldLnot access/its=n we have device-specific interrupt r1152">smb);
 62SMBu= hidden"isaome right"thrin  VLdo. If you  ame="L759"> 759smb);
 62t707"Lbelow, ple3smefirstLdis7ssem07"  ame="L759"> 759smb
 62DSDT 30d dou07"-check omat > 6re"isano name"accessde= > 62SMBu=." name="L754"> 754smb
 759smb
 7asu=_hides_smbua#L76IA 8237 APIC De-Assert Message\n&1157">smb
smb
quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *smb
BYPASS_APIC_DE116f">smb
unlikely_HEADER" class="srefclass="sref">dev_info(&dev_i ubsys="m_vendor#L76 <<DECLARE_PCI_ASUSTEK_dev<BYPASS_APIC_DE1161">smb)
dev_info(&dev_infoipas=76 <<smb{
dev_info(&dev_i ubsys="m_=deipa_devBYPASS_APIC_DE1163">smb;
 759smb 8
 759smb
 759smb);
 759smb116c#L767" id="L767" claaaaaaaaaaaaaaaaark_via_vt8237_basu=_hides_smbua;
 7asu=_hides_smbua#L76 = 1IA 8237 APIC De-Assert Message\n&11a8">smb);
smb);
dev_info(&dev_infoipas=76 <<smb117)#L715" id="L715" cla5" id="LswitchDER" class="srefclass="sref">dev_info(&dev_i ubsys="m_=deipa_devBYPASS_APIC_DE1171">smb}
 759smbivers href="drref="dria11>iv>1172#L741" id="LLLLLLLLL5" id="Lcas"L0x80b2:as48" class="line" name="L<4PEne" name="L759"> 759smb;
 759smb
 7asu=_hides_smbua#L76 = 1IA 8237 APIC De-Assert Message\n&1175">smb);
smb
dev_info(&dev_infoipas=76 <<smb);
dev_info(&dev_i ubsys="m_=deipa_devBYPASS_APIC_DE1178">smb;
 759smb);
 7asu=_hides_smbua#L76 = 1IA 8237 APIC De-Assert Message\n&118f">smb
smb);
dev_info(&dev_infoipas=76 <<smb;
dev_info(&dev_i ubsys="m_=deipa_devBYPASS_APIC_DE1183">smb);
 759smb}
 7asu=_hides_smbua#L76 = 1IA 8237 APIC De-Assert Message\n&11/5">smb);
smb
dev_info(&dev_infoipas=76 <<smb
dev_info(&dev_i ubsys="m_=deipa_devBYPASS_APIC_DE1188">smb
 759smb
 7asu=_hides_smbua#L76 = 1IA 8237 APIC De-Assert Message\n&119f">smb
smb
dev_info(&dev_infoipas=76 <<smb)
dev_info(&dev_i ubsys="m_=deipa_devBYPASS_APIC_DE1193">smb{
 759smb;
 759smb
 759smb);
 7asu=_hides_smbua#L76 = 1IA 8237 APIC De-Assert Message\n&1197">smb;
smb);
dev_info(&dev_infoipas=76 <<smb
dev_info(&dev_i ubsys="m_=deipa_devBYPASS_APIC_DE12ef">smb);
 759smbn>
 759smb>)
 7asu=_hides_smbua#L76 = 1IA 8237 APIC De-Assert Message\n&1203">smb>{
smb>;
dev_info(&dev_infoipas=76 <<smba>
dev_info(&dev_i ubsys="m_=deipa_devBYPASS_APIC_DE12e6">smb);
 759smb>;
 7asu=_hides_smbua#L76 = 1IA 8237 APIC De-Assert Message\n&1208">smb);
smba>
dev_info(&dev_infoipas=76 <<smb)
dev_info(&dev_i ubsys="m_=deipa_devBYPASS_APIC_DE12a1">smb{
 759smb;
 759smb;
 7asu=_hides_smbua#L76 = 1IA 8237 APIC De-Assert Message\n&1214">smb
smb
unlikely_HEADER" class="srefclass="sref">dev_info(&dev_i ubsys="m_vendor#L76 <<DECLARE_PCI_HP_dev<BYPASS_APIC_DE12a6">smb);
dev_info(&dev_infoipas=76 <<<smb121c#L767" id="L767" claaaaaaaaaswitchDER" class="srefclass="sref">dev_info(&dev_i ubsys="m_=deipa_devBYPASS_APIC_DE1218">smb);
 759smb)
 759smb);
 7asu=_hides_smbua#L76 = 1IA 8237 APIC De-Assert Message\n&1221">smb122c#L741" id="LLLLLLLLL5" id="L2" id="L702" class="line" name="L12>2">smb}
dev_info(&dev_infoipas=76 <<smb,
dev_info(&dev_i ubsys="m_=deipa_devBYPASS_APIC_DE12>4">smb);
 759smb
 759smb 
 759smb
 7asu=_hides_smbua#L76 = 1IA 8237 APIC De-Assert Message\n&1228">smb1228#L767" id="L767" claaaaaaaaa2" id="L702" class="line" name="L1229">smb
dev_info(&dev_infoipas=76 <<smb
dev_info(&dev_i ubsys="m_=deipa_devBYPASS_APIC_DE1231">smb
 759smb
 7asu=_hides_smbua#L76 = 1IA 8237 APIC De-Assert Message\n&1233">smb
smb
unlikely_HEADER" class="srefclass="sref">dev_info(&dev_i ubsys="m_vendor#L76 <<BYPASS_APIC_DE1235">smb
dev_info(&dev_infoipas=76 <<<smb
dev_info(&dev_i ubsys="m_=deipa_devBYPASS_APIC_DE1237">smb)
 759smb{
 7asu=_hides_smbua#L76 = 1IA 8237 APIC De-Assert Message\n&1239">smb;
smb124)#L715" id="L}aels"Li66"="+code=dev" clunlikely" class="sref">unlikely_HEADER" class="srefclass="sref">dev_info(&dev_i ubsys="m_vendor#L76 <<BYPASS_APIC_DE1241">smb124c#L741" id="LLLLLLLLL766"="+code=dev" clclass="sref">dev_info(&dev_infoipas=76 <<smb
dev_info(&dev_i ubsys="m_=deipa_devBYPASS_APIC_DE1243">smb124c#L743" id="L743" claaaaaaaaacas"L0x0058:as48" class="line" name="LCompaq Evo N620cne" name="L759"> 759smb
 7asu=_hides_smbua#L76 = 1IA 8237 APIC De-Assert Message\n&12 5">smb124c#L715" id="L715" claaaaaaaaa2" id="L702" class="line" name="L12 6">smb,
dev_info(&dev_infoipas=76 << 655PCcode=PCI_DINTE>_82810_IG3_dev *smb);
dev_info(&dev_i ubsys="m_=deipa_devBYPASS_APIC_DE1248">smb
 759smb
 759smb);
 759smb}
 759smb);
 7asu=_hides_smbua#L76 = 1IA 8237 APIC De-Assert Message\n&1253">smb);
smb
dev_info(&dev_infoipas=76 << 655PCcode=PCI_DINTE>_82801DB_2_dev *smb
dev_info(&dev_i ubsys="m_=deipa_devBYPASS_APIC_DE1256">smb
 759smb
 759smb
 759smb
 759smb
 759smb)
dLis name="L759"> 759smb{
 759smb;
 759smb 8
 7asu=_hides_smbua#L76 = 1IA 8237 APIC De-Assert Message\n&1265">smb
smb);
dev_info(&dev_infoipas=76 << 655PCcode=PCI_DINTE>_82815_CGC_dev *smb126c#L767" id="L767" claaaaaaaaaswitch6"="+code=dev" clclass="sref">dev_info(&dev_i ubsys="m_=deipa_devBYPASS_APIC_DE12a8">smb);
 759smb);
 759smb127c#L730" id="L730" class="linnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn*  ubvendor/ ubpciipa ID=, > 6> 7orenchecking name="L759"> 759smb}
 759smbivers href="drref="dria12>iv>1272#L741" id="LLLLLLLLL5" id="Laaaaaaaas 7asu=_hides_smbua#L76 = 1IA 8237 APIC De-Assert Message\n&1273">smb;
smb
smb);
smb
 684DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_ss="line" name=">PCcode=PCI_DINTE>_82845_HBIXUP_FINAL(_82845_HB_devDOR_ss="line" name=asu=_hides_smbua_hostbspan f="+code=quirk_asu=_hides_smbua_hostbspan s="sVIA 8237 APIC De-Assert Message\n&1277">smb);
 684DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_ss="line" name=">PCcode=PCI_DINTE>_82845G_HBIXUP_FINAL(_82845G_HB_dev,R_ss="line" name=asu=_hides_smbua_hostbspan f="+code=quirk_asu=_hides_smbua_hostbspan s="sVIA 8237 APIC De-Assert Message\n&1278">smb;
 684DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_ss="line" name=">PCcode=PCI_DINTE>_82850_HBIXUP_FINAL(_82850_HB_devDOR_ss="line" name=asu=_hides_smbua_hostbspan f="+code=quirk_asu=_hides_smbua_hostbspan s="sVIA 8237 APIC De-Assert Message\n&1279">smb);
 684DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_ss="line" name=">PCcode=PCI_DINTE>_82865_HBIXUP_FINAL(_82865_HB_devDOR_ss="line" name=asu=_hides_smbua_hostbspan f="+code=quirk_asu=_hides_smbua_hostbspan s="sVIA 8237 APIC De-Assert Message\n&128f">smb
 684DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_ss="line" name=">PCcode=PCI_DINTE>_82875_HBIXUP_FINAL(_82875_HB_devDOR_ss="line" name=asu=_hides_smbua_hostbspan f="+code=quirk_asu=_hides_smbua_hostbspan s="sVIA 8237 APIC De-Assert Message\n&1281">smb);
 684DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_ss="line" name=">PCcode=PCI_DINTE>_7205_0IXUP_FINAL(_7205_0_dev,aaaaassmb;
 684DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_ss="line" name=">PCcode=PCI_DINTE>_E7501_MCHIXUP_FINAL(_E7501_MCH_dev,R_ss="line" name=asu=_hides_smbua_hostbspan f="+code=quirk_asu=_hides_smbua_hostbspan s="sVIA 8237 APIC De-Assert Message\n&1283">smb);
 684DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_ss="line" name=">PCcode=PCI_DINTE>_82855PM_HBIXUP_FINAL(_82855PM_HB_dev,_ss="line" name=asu=_hides_smbua_hostbspan f="+code=quirk_asu=_hides_smbua_hostbspan s="sVIA 8237 APIC De-Assert Message\n&1284">smb}
 684DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_ss="line" name=">PCcode=PCI_DINTE>_82855GM_HBIXUP_FINAL(_82855GM_HB_dev,_ss="line" name=asu=_hides_smbua_hostbspan f="+code=quirk_asu=_hides_smbua_hostbspan s="sVIA 8237 APIC De-Assert Message\n&1285">smb);
 684DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_ss="line" name=">PCcode=PCI_DINTE>_82915GM_HBIXUP_FINAL(_82915GM_HB_dev,_ss="line" name=asu=_hides_smbua_hostbspan f="+code=quirk_asu=_hides_smbua_hostbspan s="sVIA 8237 APIC De-Assert Message\n&1286">smb
smb
 684DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_ss="line" name=">PCcode=PCI_DINTE>_82810_IG3="L655"> 655PCcode=PCI_DINTE>_82810_IG3_dev,R_ss="line" name=asu=_hides_smbua_hostbspan f="+code=quirk_asu=_hides_smbua_hostbspan s="sVIA 8237 APIC De-Assert Message\n&1288">smb
 684DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_ss="line" name=">PCcode=PCI_DINTE>_82801DB_2="L655"> 655PCcode=PCI_DINTE>_82801DB_2_dev,R_ss="line" name=asu=_hides_smbua_hostbspan f="+code=quirk_asu=_hides_smbua_hostbspan s="sVIA 8237 APIC De-Assert Message\n&1289">smb
 684DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_ss="line" name=">PCcode=PCI_DINTE>_82815_CGC="L655"> 655PCcode=PCI_DINTE>_82815_CGC_dev,R_ss="line" name=asu=_hides_smbua_hostbspan f="+code=quirk_asu=_hides_smbua_hostbspan s="sVIA 8237 APIC De-Assert Message\n&129f">smb
smb
quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *smb)
BYPASS_APIC_DE1293">smb{
);
u1c#L656ref="+code=pci_val;
val#L65IA 8237 APIC De-Assert Message\n&1294">smb;
smb
likely_HEAD!s 7asu=_hides_smbua#L76) *smb);
smb;
smb);
pci_dev, 0xF2, &p;val#L65VIA 8237 APIC De-Assert Message\n&1299">smb
val#L65 &pL0x8BYPASS_APIC_DE13ef">smb);
(stwrite_config_word_HEADER" class="srefdev" class="sref">pci_dev, 0xF2, ="+code=dev" clval;
val#L65 &pL(~0x8smbn>
pci_dev, 0xF2, &p;val#L65VIA 8237 APIC De-Assert Message\n&13e2">smb>)
val#L65 &pL0x8smb>{
pci_info_HEAD&p;dev_info(&pci_dev, 1" id="L731" ef"ing">"i8012SMBu= pciipa  hreinuei* o play 'hide 30d seek'!L0x%x\n" name=", ="+code=dev" clval;
val#L65VIA 8237 APIC De-Assert Message\n&13e4">smb>;
smba>
pci_info_HEAD&p;dev_info(&pci_dev, 1" id="L731" ef"ing">"En707"dLi8012SMBu= pciipa\n" name="VIA 8237 APIC De-Assert Message\n&13e6">smb);
smb>;
smb);
 684DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_ss="line" name=">PCcode=PCI_DINTE>_82801AA_0IXUP_FINAL(_82801AA_0_dev,R_ss="line" name=asu=_hides_smbua_lpcf="+code=quirk_asu=_hides_smbua_lpc_HEAVIA 8237 APIC De-Assert Message\n&13e9">smba>
 684DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_ss="line" name=">PCcode=PCI_DINTE>_82801DB_0IXUP_FINAL(_82801DB_0_dev,R_ss="line" name=asu=_hides_smbua_lpcf="+code=quirk_asu=_hides_smbua_lpc_HEAVIA 8237 APIC De-Assert Message\n&131f">smb)
 684DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_ss="line" name=">PCcode=PCI_DINTE>_82801BA_0IXUP_FINAL(_82801BA_0_dev,R_ss="line" name=asu=_hides_smbua_lpcf="+code=quirk_asu=_hides_smbua_lpc_HEAVIA 8237 APIC De-Assert Message\n&13a1">smb{
 684DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_ss="line" name=">PCcode=PCI_DINTE>_82801CA_0IXUP_FINAL(_82801CA_0_dev,R_ss="line" name=asu=_hides_smbua_lpcf="+code=quirk_asu=_hides_smbua_lpc_HEAVIA 8237 APIC De-Assert Message\n&13a2">smb;
 684DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_ss="line" name=">PCcode=PCI_DINTE>_82801CA_12="L655"> 655PCcode=PCI_DINTE>_82801CA_12_dev,_ss="line" name=asu=_hides_smbua_lpcf="+code=quirk_asu=_hides_smbua_lpc_HEAVIA 8237 APIC De-Assert Message\n&13a3">smb;
 684DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_ss="line" name=">PCcode=PCI_DINTE>_82801DB_12="L655"> 655PCcode=PCI_DINTE>_82801DB_12_dev,_ss="line" name=asu=_hides_smbua_lpcf="+code=quirk_asu=_hides_smbua_lpc_HEAVIA 8237 APIC De-Assert Message\n&13a4">smb
 684DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_ss="line" name=">PCcode=PCI_DINTE>_82801EB_0IXUP_FINAL(_82801EB_0_dev,R_ss="line" name=asu=_hides_smbua_lpcf="+code=quirk_asu=_hides_smbua_lpc_HEAVIA 8237 APIC De-Assert Message\n&1315">smb
DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_R_ss="line" name=">PCcode=PCI_DINTE>_82801AA_0IXUP_FINAL(_82801AA_0_dev,R_ss="line" name=asu=_hides_smbua_lpcf="+code=quirk_asu=_hides_smbua_lpc_HEAVIA 8237 APIC De-Assert Message\n&13a6">smb);
DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_R_ss="line" name=">PCcode=PCI_DINTE>_82801DB_0IXUP_FINAL(_82801DB_0_dev,R_ss="line" name=asu=_hides_smbua_lpcf="+code=quirk_asu=_hides_smbua_lpc_HEAVIA 8237 APIC De-Assert Message\n&1317">smb131c#L76sDECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_R_ss="line" name=">PCcode=PCI_DINTE>_82801BA_0IXUP_FINAL(_82801BA_0_dev,R_ss="line" name=asu=_hides_smbua_lpcf="+code=quirk_asu=_hides_smbua_lpc_HEAVIA 8237 APIC De-Assert Message\n&13a8">smb);
DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_R_ss="line" name=">PCcode=PCI_DINTE>_82801CA_0IXUP_FINAL(_82801CA_0_dev,R_ss="line" name=asu=_hides_smbua_lpcf="+code=quirk_asu=_hides_smbua_lpc_HEAVIA 8237 APIC De-Assert Message\n&13a9">smb)
DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_R_ss="line" name=">PCcode=PCI_DINTE>_82801CA_12="L655"> 655PCcode=PCI_DINTE>_82801CA_12_dev,_ss="line" name=asu=_hides_smbua_lpcf="+code=quirk_asu=_hides_smbua_lpc_HEAVIA 8237 APIC De-Assert Message\n&132f">smb);
DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_R_ss="line" name=">PCcode=PCI_DINTE>_82801DB_12="L655"> 655PCcode=PCI_DINTE>_82801DB_12_dev,_ss="line" name=asu=_hides_smbua_lpcf="+code=quirk_asu=_hides_smbua_lpc_HEAVIA 8237 APIC De-Assert Message\n&1321">smb132c#L746" id="L684" class="line" name="LRESUME_EARLY684DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_R_ss="line" name=">PCcode=PCI_DINTE>_82801EB_0IXUP_FINAL(_82801EB_0_dev,R_ss="line" name=asu=_hides_smbua_lpcf="+code=quirk_asu=_hides_smbua_lpc_HEAVIA 8237 APIC De-Assert Message\n&13>2">smb}
smb,
 759smb);
smb
quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *smb 
BYPASS_APIC_DE1327">smb
 655 655smb1328#L76A 8237 APIC De-Assert Message\n&1329">smb
likely_HEAD!s 7asu=_hides_smbua#L76) *smb
smb
 7WARN_ON_HEADER" class="srefasu=_rcba_bas f="+code=quirk_asu=_rcba_bas #L65VIA 8237 APIC De-Assert Message\n&13a2">smb
smb
(stread_config_dwordpic_deassert(stread_config_dword_HEADER" class="srefdev" class="sref">pci_dev, 0xF0, &p; 655smb
 759smb
 655smb
 722_dev *smb)
smb{
smb;
smb134)#L710" id="L760" class="line" nasu=_hides_smbua_lpc_ich6_resume_early" class="sref">asu=_hides_smbua_lpc_ich6_resume_early_HEADef">quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *smb134c#L74SERT" class="sref">BYPASS_APIC_DE1342">smb
 655val#L65IA 8237 APIC De-Assert Message\n&1343">smb134c#L74A 8237 APIC De-Assert Message\n&1344">smb
likely_HEAD!s 7asu=_hides_smbua#L76 || !s *smb134c#L715" id="L715" clareturnIA 8237 APIC De-Assert Message\n&13 6">smb,
 759smb);
val#L65 <readl_HEADER" class="srefasu=_rcba_bas f="+code=quirk_asu=_rcba_bas #L65 + 0x34c8VIA 8237 APIC De-Assert Message\n&1348">smb
writel_HEADER" class="srefval;
val#L65 &pL0xFFFFFFF7,_ss="line" name=asu=_rcba_bas f="+code=quirk_asu=_rcba_bas #L65 + 0x34c8VILs48" class="line" name="Len707" > 6 SMBu= pciipa e" name="L759"> 759smb
smb);
smb}
asu=_hides_smbua_lpc_ich6_resume_HEADef">quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *smb);
BYPASS_APIC_DE1353">smb);
likely_HEAD!s 7asu=_hides_smbua#L76 || !s *smb
5">smb
smb
 722_devIA 8237 APIC De-Assert Message\n&1357">smb
pci_info_HEAD&p;dev_info(&pci_dev, 1" id="L731" ef"ing">"En707"dLICH6/i8012SMBu= pciipa\n" name="VIA 8237 APIC De-Assert Message\n&1358">smb
smb
smb
asu=_hides_smbua_lpc_ich6_HEADef">quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *smb)
BYPASS_APIC_DE1362">smb{
pci_devsmb;
asu=_hides_smbua_lpc_ich6_resume_early_HEADref="+code=pci_dev" class="sref">pci_devsmb 8
asu=_hides_smbua_lpc_ich6_resume_HEADref="+code=pci_dev" class="sref">pci_devsmb
smb);
 684DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_ss="line" name=">PCcode=PCI_DINTE>_ICH6_1 722DEcode=PCI_DINTE>_ICH6_1_VENDOR_R_ss="line" name=asu=_hides_smbua_lpc_ich6" class="sref">asu=_hides_smbua_lpc_ich6_HEAsmb136c#L76sDECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDORss="line" name=">PCcode=PCI_DINTE>_ICH6_1 722DEcode=PCI_DINTE>_ICH6_1_VENDOR_R_ss="line" name=asu=_hides_smbua_lpc_ich6_su=pendpic_deassertsmb);
DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_ss="line" name=">PCcode=PCI_DINTE>_ICH6_1 722DEcode=PCI_DINTE>_ICH6_1_VENDOR_R_ss="line" name=asu=_hides_smbua_lpc_ich6_resume" class="sref">asu=_hides_smbua_lpc_ich6_resume_HEAsmb);
DECLARE_PCI_INTE> 722DECLARE_PCI_INTE>_VENDOR_R_ss="line" name=">PCcode=PCI_DINTE>_ICH6_1 722DEcode=PCI_DINTE>_ICH6_1_VENDOR_R_ss="line" name=asu=_hides_smbua_lpc_ich6_resume_early" class="sref">asu=_hides_smbua_lpc_ich6_resume_early_HEAsmb137)#L71A 8237 APIC De-Assert Message\n&1371">smb}
 759smbivers href="drref="dria13>iv>137c#L732" id="L732" class="lin* SiS 96x southLbspan : BIOS typically hides2SMBu= pciipa... name="L759"> 759smb;
 759smb
 7ass="_sis_96x_smbua_HEADef">quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *smb);
BYPASS_APIC_DE1376">smb
u8#L741ref="+code=pci_val;
val#L65 = 0IA 8237 APIC De-Assert Message\n&1377">smb);
(stread_config_byte" class="sref">>(stread_config_byte_HEADER" class="srefdev" class="sref">pci_dev, 0x77, &p;val#L65VIA 8237 APIC De-Assert Message\n&1378">smb;
val#L65 &pL0x10BYPASS_APIC_DE1379">smb);
pci_info_HEAD&p;dev_info(&pci_dev, 1" id="L731" ef"ing">"En707ing SiS 96x SMBu=\n" name="VIA 8237 APIC De-Assert Message\n&138f">smb
>(stwrite_config_byte_HEADER" class="srefdev" class="sref">pci_dev, 0x77, ="+code=dev" clval;
val#L65 &pL~0x10smb);
smb;
smb);
 684DECLARE_PCI_SI 722DECLARE_PCI_SI_VENDOR_R__ss="line" name=">PCcode=PCI_DSI_961 722DEcode=PCI_DSI_961_VENDOR_R__R_R__ss="line" name=ass="_sis_96x_smbua;
 7ass="_sis_96x_smbua_HEAsmb}
 684DECLARE_PCI_SI 722DECLARE_PCI_SI_VENDOR_R__ss="line" name=">PCcode=PCI_DSI_962="L655"> 655PCcode=PCI_DSI_962_VENDOR_R__R_R__ss="line" name=ass="_sis_96x_smbua;
 7ass="_sis_96x_smbua_HEAsmb);
 684DECLARE_PCI_SI 722DECLARE_PCI_SI_VENDOR_R__ss="line" name=">PCcode=PCI_DSI_963="L655"> 655PCcode=PCI_DSI_963_VENDOR_R__R_R__ss="line" name=ass="_sis_96x_smbua;
 7ass="_sis_96x_smbua_HEAsmb
 684DECLARE_PCI_SI 722DECLARE_PCI_SI_VENDOR_R__ss="line" name=">PCcode=PCI_DSI_LPC="L655"> 655PCcode=PCI_DSI_LPC_VENDOR_R__R_R__ss="line" name=ass="_sis_96x_smbua;
 7ass="_sis_96x_smbua_HEAsmb
DECLARE_PCI_SI 722DECLARE_PCI_SI_VENDOR_R____ss="line" name=">PCcode=PCI_DSI_961 722DEcode=PCI_DSI_961_VENDOR_R__R_R__ss="line" name=ass="_sis_96x_smbua;
 7ass="_sis_96x_smbua_HEAsmb
DECLARE_PCI_SI 722DECLARE_PCI_SI_VENDOR_R____ss="line" name=">PCcode=PCI_DSI_962="L655"> 655PCcode=PCI_DSI_962_VENDOR_R__R_R__ss="line" name=ass="_sis_96x_smbua;
 7ass="_sis_96x_smbua_HEAsmb
DECLARE_PCI_SI 722DECLARE_PCI_SI_VENDOR_R____ss="line" name=">PCcode=PCI_DSI_963="L655"> 655PCcode=PCI_DSI_963_VENDOR_R__R_R__ss="line" name=ass="_sis_96x_smbua;
 7ass="_sis_96x_smbua_HEAsmb
DECLARE_PCI_SI 722DECLARE_PCI_SI_VENDOR_R____ss="line" name=">PCcode=PCI_DSI_LPC="L655"> 655PCcode=PCI_DSI_LPC_VENDOR_R__R_R__ss="line" name=ass="_sis_96x_smbua;
 7ass="_sis_96x_smbua_HEAsmb
smb)
 759smb{
 759smb;
 759smb
 759smb);
 759smb;
 759smb);
 6 sis96x bit in > 6 disco> 759smb
 759smb);
 684 #L7410x40L759"> 759smbn>
smb>)
 655quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *smb>{
BYPASS_APIC_DE14e4">smb>;
u8#L741ref="+code=pci_reg" class="sref">reg#L74IA 8237 APIC De-Assert Message\n&14e5">smba>
u1c#L656ref="+code=pci_pciidpic_deassertsmb);
smb>;
(stread_config_byte" class="sref">>(stread_config_byte_HEADER" class="srefdev" class="sref">pci_dev, ss="line" name=SISCcoTECTIREGIST> 684 #L74, &p;reg#L74smb);
>(stwrite_config_byte_HEADER" class="srefdev" class="sref">pci_dev, ss="line" name=SISCcoTECTIREGIST> 684 #L74, ;reg#L74 | (1 << 6smba>
(stread_config_wordpic_deassert(stread_config_word_HEADER" class="srefdev" class="sref">pci_dev, ss="line" name=">PCcode=PCI_="L655"> 655PCcode=PCI_#L74, &p;smb)
BYPASS_APIC_DE14a1">smb{
>(stwrite_config_byte_HEADER" class="srefdev" class="sref">pci_dev, ss="line" name=SISCcoTECTIREGIST> 684 #L74, ;reg#L74VIA 8237 APIC De-Assert Message\n&1412">smb;
smb;
smb
smb
 759smb);
 759smb141c#L763" id="L733" class="linnnnnnnnn* h30d in cas"Lit h3s already been processed. name="L759"> 759smb);
 759smb)
 759smb);
dev_info(&=deice#L65 = ref="+code=pci_pciidpic_deassertsmb142c#L741" id="Ls 7ass="_sis_96x_smbua_HEADref="+code=pci_dev" class="sref">pci_devsmb}
smb,
 684DECLARE_PCI_SI 722DECLARE_PCI_SI_VENDOR_R__ss="line" name=">PCcode=PCI_DSI_503="L655"> 655PCcode=PCI_DSI_503_VENDOR_R__R_R__ss="line" name=ass="_sis_503="L655"> 655smb);
DECLARE_PCI_SI 722DECLARE_PCI_SI_VENDOR_R____ss="line" name=">PCcode=PCI_DSI_503="L655"> 655PCcode=PCI_DSI_503_VENDOR_R__R_R__ss="line" name=ass="_sis_503="L655"> 655smb
smb 
smb
 759smb1428#L763" id="L733" class="line On ASUS A8V 30d A8V Deluxe boards, > 6 onboard AC97 audio  hreroller name="L759"> 759smb
P soundcard is name="L759"> 759smb
weaking > 6 VT8237 ISALbspan ,Len707"s > 6m. name="L759"> 759smb
 759smb
 759smb
quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *smb
BYPASS_APIC_DE1435">smb
u8#L741ref="+code=pci_val;
val#L65IA 8237 APIC De-Assert Message\n&14a6">smb
smb)
smb{
likely_HEADref="+code=pci_class="sref">dev_info(&dev_isubsystem_vendor#L65 == ref="+code=pci_">DECLARE_PCI_ASUSTEK 722DECLARE_PCI_ASUSTEK_dev<BYPASS_APIC_DE1439">smb;
dev_info(&=deice#L65 == ref="+code=pci_">DEcode=PCI_DVIA_8237="L655"> 655PCcode=PCI_DVIA_8237_dev *smb144)#L715" id="L715" cla5" id="LER" class="srefasu=_hides_ac97f="+code=quirk_asu=_hides_ac97#L65 = 1IA 8237 APIC De-Assert Message\n&1441">smb144c#L741" id="L2" id="L702" class="line" name="L1442">smb
smb144c#L743" id="Li66"!s *smb
smb144c#L71A 8237 APIC De-Assert Message\n&14 6">smb,
>(stread_config_byte_HEADER" class="srefdev" class="sref">pci_dev, 0x50, &p;val#L65VIA 8237 APIC De-Assert Message\n&1447">smb);
val#L65 &pL0xc0BYPASS_APIC_DE1448">smb
>(stwrite_config_byte_HEADER" class="srefdev" class="sref">pci_dev, 0x50, ="+code=dev" clval;
val#L65 &pL(~0xc0smb
>(stread_config_byte_HEADER" class="srefdev" class="sref">pci_dev, 0x50, &p;val#L65VIA 8237 APIC De-Assert Message\n&145f">smb);
val#L65 &pL0xc0smb}
pci_info_HEAD&p;dev_info(&pci_dev, 1" id="L731" ef"ing">"Onboard AC97/MC97 =deices  hreinue* o play 'hide 30d seek'!L0x%x\n" name=", ="+code=dev" clval;
val#L65VIA 8237 APIC De-Assert Message\n&1452">smb);
smb);
pci_info_HEAD&p;dev_info(&pci_dev, 1" id="L731" ef"ing">"En707"dLonboard AC97/MC97 =deices\n" name="VIA 8237 APIC De-Assert Message\n&1454">smb
smb
smb
 684DECLARE_PCI_VIA 722DECLARE_PCI_VIA_VENDOR_R_ref="+code=pci_">DEcode=PCI_DVIA_8237="L655"> 655PCcode=PCI_DVIA_8237_dev,_ss="line" name=asu=_hides_ac97_lpcf="+code=quirk_asu=_hides_ac97_lpc_HEAVIA 8237 APIC De-Assert Message\n&1457">smb
DECLARE_PCI_VIA 722DECLARE_PCI_VIA_VENDOR_R_R_ref="+code=pci_">DEcode=PCI_DVIA_8237="L655"> 655PCcode=PCI_DVIA_8237_dev,_ss="line" name=asu=_hides_ac97_lpcf="+code=quirk_asu=_hides_ac97_lpc_HEAVIA 8237 APIC De-Assert Message\n&1458">smb
smb
smb
smb)
 759smb{
 759smb;
 759smb 8
P scanning. name="L759"> 759smb
 759smb);
 655quirk_via_vt8237_bypass_apic_deassert(struct smb146c#L76SERT" class="sref">BYPASS_APIC_DE1468">smb);
 655smb);
u8#L741ref="+code=pci_hdrss="sref">dev_ihdr#L65IA 8237 APIC De-Assert Message\n&147f">smb147)#L71A 8237 APIC De-Assert Message\n&1471">smb}
 759smbivers href="drref="dria14>iv>1472#L741" id="Li66"="+code=dev" clECLARUNC="L655"> 655PCRUNC_HEADER" class="srefps_apic_deassertpci_dev(&pcifn_dev< 759smb;
smb
smb);
smb
smb);
smb;
 759smb);
 759smb
smb);
pci_dev(&=deice#L65BYPASS_APIC_DE1482">smb;
DEcode=PCI_DJMICRONDJMB3an>
PCcode=PCI_DJMICRONDJMB3an#L74:Ls48" class="line" name="LSATA single portne" name="L759"> 759smb);
DEcode=PCI_DJMICRONDJMB3a2="L655"> 655PCcode=PCI_DJMICRONDJMB3a2#L74:Ls48" class="line" name="LSATA dual portsne" name="L759"> 759smb}
DEcode=PCI_DJMICRONDJMB3a4="L655"> 655PCcode=PCI_DJMICRONDJMB3a4#L74:Ls48" class="line" name="LSATA dual portsne" name="L759"> 759smb);
 759smb
 759smb
smb
smb
DEcode=PCI_DJMICRONDJMB3a5 722DEcode=PCI_DJMICRONDJMB3a5#L74:A 8237 APIC De-Assert Message\n&149f">smb
DEcode=PCI_DJMICRONDJMB3a);
">DEcode=PCI_DJMICRONDJMB3a)#L74:A 8237 APIC De-Assert Message\n&1491">smb
 6 right spot/e" name="L759"> 759smb)
 759smb{
 759smb;
DEcode=PCI_DJMICRONDJMB3a1 722DEcode=PCI_DJMICRONDJMB3a1#L74:A 8237 APIC De-Assert Message\n&1495">smb
DEcode=PCI_DJMICRONDJMB3a3="L655"> 655PCcode=PCI_DJMICRONDJMB3a3#L74:A 8237 APIC De-Assert Message\n&1496">smb);
DEcode=PCI_DJMICRONDJMB3a9="L655"> 655PCcode=PCI_DJMICRONDJMB3a9#L74:A 8237 APIC De-Assert Message\n&1497">smb;
 759smb);
 759smb
 759smb);
smbn>
smb>)
DEcode=PCI_DJMICRONDJMB3a8" class="sref">">DEcode=PCI_DJMICRONDJMB3a8#L74:A 8237 APIC De-Assert Message\n&15e3">smb>{
 759smb>;
 759smba>
smb);
smb>;
smb);
smba>
(stwrite_config_dwordpic_deassert(stwrite_config_dword_HEADER" class="srefps_apic_deassertpci_dev, 0x80, ;smb)
smb{
 759smb;
(stread_config_byte" class="sref">>(stread_config_byte_HEADER" class="srefps_apic_deassertpci_dev, ref="+code=pci_">DE_FIXUP_TYPE684dev_ihdr#L65VIA 8237 APIC De-Assert Message\n&1513">smb;
pci_dev(&hdr_type#L743= ref="+code=pci_hdrss="sref">dev_ihdr#L65 &pL0x7fIA 8237 APIC De-Assert Message\n&1514">smb
pci_dev(&dev_ihdr#L65 &pL0x80smb
smb);
DECLASS_RodeSION684smb151c#L767" id="Lref="+code=pci_>s_apic_deassertpci_dev(&smb);
smb)
DECLARE_PCI_JMICRON 722DECLARE_PCI_JMICRON_dev, ref="+code=pci_">DEcode=PCI_DJMICRONDJMB3an>
PCcode=PCI_DJMICRONDJMB3an#L74, ref="+code=pci_ass="_jmicron_ata="L655"> 655smb);
DECLARE_PCI_JMICRON 722DECLARE_PCI_JMICRON_dev, ref="+code=pci_">DEcode=PCI_DJMICRONDJMB3a1 722DEcode=PCI_DJMICRONDJMB3a1#L74, ref="+code=pci_ass="_jmicron_ata="L655"> 655smb152c#L746" id="L684" class="line" name="LEARLY684DECLARE_PCI_JMICRON 722DECLARE_PCI_JMICRON_dev, ref="+code=pci_">DEcode=PCI_DJMICRONDJMB3a2="L655"> 655PCcode=PCI_DJMICRONDJMB3a2#L74, ref="+code=pci_ass="_jmicron_ata="L655"> 655smb}
DECLARE_PCI_JMICRON 722DECLARE_PCI_JMICRON_dev, ref="+code=pci_">DEcode=PCI_DJMICRONDJMB3a3="L655"> 655PCcode=PCI_DJMICRONDJMB3a3#L74, ref="+code=pci_ass="_jmicron_ata="L655"> 655smb,
DECLARE_PCI_JMICRON 722DECLARE_PCI_JMICRON_dev, ref="+code=pci_">DEcode=PCI_DJMICRONDJMB3a4="L655"> 655PCcode=PCI_DJMICRONDJMB3a4#L74, ref="+code=pci_ass="_jmicron_ata="L655"> 655smb);
DECLARE_PCI_JMICRON 722DECLARE_PCI_JMICRON_dev, ref="+code=pci_">DEcode=PCI_DJMICRONDJMB3a5 722DEcode=PCI_DJMICRONDJMB3a5#L74, ref="+code=pci_ass="_jmicron_ata="L655"> 655smb
DECLARE_PCI_JMICRON 722DECLARE_PCI_JMICRON_dev, ref="+code=pci_">DEcode=PCI_DJMICRONDJMB3a);
">DEcode=PCI_DJMICRONDJMB3a)#L74, ref="+code=pci_ass="_jmicron_ata="L655"> 655smb 
DECLARE_PCI_JMICRON 722DECLARE_PCI_JMICRON_dev, ref="+code=pci_">DEcode=PCI_DJMICRONDJMB3a8" class="sref">">DEcode=PCI_DJMICRONDJMB3a8#L74, ref="+code=pci_ass="_jmicron_ata="L655"> 655smb
DECLARE_PCI_JMICRON 722DECLARE_PCI_JMICRON_dev, ref="+code=pci_">DEcode=PCI_DJMICRONDJMB3a9="L655"> 655PCcode=PCI_DJMICRONDJMB3a9#L74, ref="+code=pci_ass="_jmicron_ata="L655"> 655smb152c#L766" id="L684" class="line" name="LRESUME_EARLY684DECLARE_PCI_JMICRON 722DECLARE_PCI_JMICRON_dev, ref="+code=pci_">DEcode=PCI_DJMICRONDJMB3an>
PCcode=PCI_DJMICRONDJMB3an#L74, ref="+code=pci_ass="_jmicron_ata="L655"> 655smb
DECLARE_PCI_JMICRON 722DECLARE_PCI_JMICRON_dev, ref="+code=pci_">DEcode=PCI_DJMICRONDJMB3a1 722DEcode=PCI_DJMICRONDJMB3a1#L74, ref="+code=pci_ass="_jmicron_ata="L655"> 655smb
DECLARE_PCI_JMICRON 722DECLARE_PCI_JMICRON_dev, ref="+code=pci_">DEcode=PCI_DJMICRONDJMB3a2="L655"> 655PCcode=PCI_DJMICRONDJMB3a2#L74, ref="+code=pci_ass="_jmicron_ata="L655"> 655smb
DECLARE_PCI_JMICRON 722DECLARE_PCI_JMICRON_dev, ref="+code=pci_">DEcode=PCI_DJMICRONDJMB3a3="L655"> 655PCcode=PCI_DJMICRONDJMB3a3#L74, ref="+code=pci_ass="_jmicron_ata="L655"> 655smb
DECLARE_PCI_JMICRON 722DECLARE_PCI_JMICRON_dev, ref="+code=pci_">DEcode=PCI_DJMICRONDJMB3a4="L655"> 655PCcode=PCI_DJMICRONDJMB3a4#L74, ref="+code=pci_ass="_jmicron_ata="L655"> 655smb
DECLARE_PCI_JMICRON 722DECLARE_PCI_JMICRON_dev, ref="+code=pci_">DEcode=PCI_DJMICRONDJMB3a5 722DEcode=PCI_DJMICRONDJMB3a5#L74, ref="+code=pci_ass="_jmicron_ata="L655"> 655smb
DECLARE_PCI_JMICRON 722DECLARE_PCI_JMICRON_dev, ref="+code=pci_">DEcode=PCI_DJMICRONDJMB3a);
">DEcode=PCI_DJMICRONDJMB3a)#L74, ref="+code=pci_ass="_jmicron_ata="L655"> 655smb
DECLARE_PCI_JMICRON 722DECLARE_PCI_JMICRON_dev, ref="+code=pci_">DEcode=PCI_DJMICRONDJMB3a8" class="sref">">DEcode=PCI_DJMICRONDJMB3a8#L74, ref="+code=pci_ass="_jmicron_ata="L655"> 655smb
DECLARE_PCI_JMICRON 722DECLARE_PCI_JMICRON_dev, ref="+code=pci_">DEcode=PCI_DJMICRONDJMB3a9="L655"> 655PCcode=PCI_DJMICRONDJMB3a9#L74, ref="+code=pci_ass="_jmicron_ata="L655"> 655smb)
smb{
smb;
smb154)#L71#ifde66; 655smb154c#L740" id="L760" class="line" nass="_alder_ioapicf="+code=quirk_ass="_alder_ioapic_HEADef">quirk_via_vt8237_bypass_apic_deassert(struct smb
BYPASS_APIC_DE1543">smb154c#L743" id="Linuirk_via_vt8237_bipic_deassertsmb
smb154c#L715" id="Li66"(ref="+code=pci_>s_apic_deassertpci_dev(&smb,
smb);
smb
 759smb
 759smb);
 759smb}
(stresource_0" rtpic_deassert(stresource_0" rt_HEADER" class="srefps_apic_deassertpci_dev, 0) &p&pL="+code=dev" cl>(stresource_lenpic_deassert(stresource_len_HEADER" class="srefps_apic_deassertpci_dev, 0)smb);
smb);
smb
 759smb
 759smb
BYPASS_APIC_DE1557">smb
smb
smb
smb
smb)
 684DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R_ref="+code=pci_">DEcode=PCI_DINTEL_EESSC="L655"> 655PCcode=PCI_DINTEL_EESSC_dev, R_ R_ref="+code=pci_ass="_alder_ioapicf="+code=quirk_ass="_alder_ioapic_HEAVIA 8237 APIC De-Assert Message\n&1562">smb{
smb;
smb 8
quirk_via_vt8237_bypass_apic_deassert(struct smb
BYPASS_APIC_DE1566">smb);
smb156c#L767" id="Lref="+code=pci_>s_apic_deassertpci_dev(&smb);
smb);
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DEcode=PCI_DINTEL_E7520_MCH="L655"> 655PCcode=PCI_DINTEL_E7520_MCH_dev, R class="line" nass="_erte_mchf="+code=quirk_ass="_erte_mch_HEAVIA 8237 APIC De-Assert Message\n&157f">smb157)#L716" id="L684" class="line" name="LFINAL 722DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DEcode=PCI_DINTEL_E7320_MCH="L655"> 655PCcode=PCI_DINTEL_E7320_MCH_dev, R class="line" nass="_erte_mchf="+code=quirk_ass="_erte_mch_HEAVIA 8237 APIC De-Assert Message\n&1571">smb}
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DEcode=PCI_DINTEL_E7525_MCH="L655"> 655PCcode=PCI_DINTEL_E7525_MCH_dev, R class="line" nass="_erte_mchf="+code=quirk_ass="_erte_mch_HEAVIA 8237 APIC De-Assert Message\n&1572">smbivers href="drref="dria15>iv>1572#L74A 8237 APIC De-Assert Message\n&1573">smb;
smb
 759smb);
 6 MSInto get =prruptedLi66shpc 30d acpi name="L759"> 759smb
 759smb);
 759smb;
);
 759smb;
);>1479#L767" id=5Lref=5+code=BYPASS_APIC_DE1566">smb);
smb;
smbivers href="drive5s/pci14>);>148c#L741" id=5Lswit5h6"="+code=devpic_deassertsmb;
smb);
(stread_config_byt 759s_apic_deassert(&pci_dev, 1" id="L731" ef"ing">"En707"dLonboard AC9nam  deteci n; SHPCng name=dLi6hrd ">P 8237 APIC De-Assert Message\n&1454">smb
smb);
DECLARE_PCI_JMICRON 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DEcode=PCI_DINTEL_E7525_MCH="L655"> 6namD_Ccode=PCI_DJMICRONDJMB3an#L74,55"> 6namD_Cde=pci_ass"_erte_pxxnass="_erte_pxxLb);
smb
DECLARE_PCI_JMICRON 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DEcode=PCI_DINTEL_E7525_MCH="L655"> 6namD_Ecode=PCI_DJMICRONDJMB3a1#L74,55"> 6namD_Ede=pci_ass"_erte_pxxnass="_erte_pxxLb);
smb
DECLARE_PCI_JMICRON 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DEcode=PCI_DINTEL_E7525_MCH="L655"> 6nam_Ccode=PCI_DJMICRONDJMB3an#L74,55"> 6nam_Cde=pci_asss"_erte_pxxnass="_erte_pxxLb);
smb
DECLARE_PCI_JMICRON 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DEcode=PCI_DINTEL_E7525_MCH="L655"> 6nam_Ecode=PCI_DJMICRONDJMB3a1#L74,55"> 6nam_Ede=pci_asss"_erte_pxxnass="_erte_pxxLb);
smb
DECLARE_PCI_JMICRON 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DEcode=PCI_DINTEL_E7525_MCH="L655"> 6namVcode=PCI_DJMICRONDJMB3a1#L74,55"> 6namVde=pci_assss"_erte_pxxnass="_erte_pxxLb);
smb
smb
smb);
 759r oSome Intel="L75Expres must sets haly brouget with down"dLeama>smb);
smb);
smb;
);
 759smb;
>1495#L741" id=5Lcas"59ref">BYPASS_APIC_DE1566">smb);
(stmsi_offpic_deassertpm_d39 759pm_d39smb
s_apic_deassertsmb;
smb);
smb);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DE0x25e2s="_jmicron_ata="L655">intelrs/pci1m15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DE0x25e3s="_jmicron_ata="L655">intelrs/pci1m15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DE0x25e4s="_jmicron_ata="L655">intelrs/pci1m15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DE0x25e5s="_jmicron_ata="L655">intelrs/pci1m15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DE0x25e6s="_jmicron_ata="L655">intelrs/pci1m15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DE0x25e7s="_jmicron_ata="L655">intelrs/pci1m15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DE0x25f7s="_jmicron_ata="L655">intelrs/pci1m15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DE0x25f8s="_jmicron_ata="L655">intelrs/pci1m15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DE0x25f9s="_jmicron_ata="L655">intelrs/pci1m15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DE0x25fas="_jmicron_ata="L655">intelrs/pci1m15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DE0x260ls="_jmicron_ata="L655">intelrs/pci1m15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DE0x260ls="_jmicron_ata="L655">intelrs/pci1m15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DE0x260ls="_jmicron_ata="L655">intelrs/pci1m15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DE0x260ls="_jmicron_ata="L655">intelrs/pci1m15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DE0x260ls="_jmicron_ata="L655">intelrs/pci1m15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DE0x260es="_jmicron_ata="L655">intelrs/pci1m15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DE0x260es="_jmicron_ata="L655">intelrs/pci1m15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DE0x260ls="_jmicron_ata="L655">intelrs/pci1m15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DE0x260ls="_jmicron_ata="L655">intelrs/pci1m15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DE0x260as="_jmicron_ata="L655">intelrs/pci1m15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DE0x260bs="_jmicron_ata="L655">intelrs/pci1m15>);
smb
smb>)
 655smb,>152c#L746" id=6L684"62lass="line      do thisnearsmb);
 759 * Boo trede acpisedLssome ust sets can it&be -Assed off. Fprruptse ust sets,a>smb);
smb);
 6 MSrede acpi handngleiMSrestalled onname=boo trede acpia>smb);
 759< AineSrestead/a>smb);
smb;
);
 759smb;
>153)#L716" id=6L684"6class=BYPASS_APIC_DE1566">smb);
(stresource_0" rtpnoAPIC Dcode=PCI_DJMICR/aAPIC Dcode=||3" id="L733" cla/aAPIC Dreroutecode=PCI_DJMICR/aAPIC Dreroutef="drivers/O 12-19, 22, 23ne" name="L76ref="drive6s/pci15an>>1532#L746" id=6L684"63LLrk_via_vt8237_binseDe-Assert Message\n&1547">smb);
smb
smb;
 6IRQ_REROUTE_VARIANTet_HEAD&p; 6IRQ_REROUTE_VARIANTC Deert Message\n&1547">smb);
smb;
15e>s_apic_deassert(&pci_dev, 1" id="L731" ef"ing">"En707"dLonboard AC9reroutonbtrede acpise=prr[6> 7;04x:6> 7;04x]8237 APIC De-As,rt Message\n&1547">smb);
smb;
(&pci_isource_dev[="+codci_iso);>1sert Message\n&1454">smb
smb);
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DECLARE_PCI_INTEL 722MB3a1#L74,55"> 680333_Ccode=PCI_DJMICRONDJMB3an#L74,55"> 680333_C=pci_">DECLARE_PCI_INTELode=qureroute_to_boo _rede acpisrintel15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DECLARE_PCI_INTEL 722MB3a1#L74,55"> 680333_Ecode=PCI_DJMICRONDJMB3a1#L74,55"> 680333_E=pci_">DECLARE_PCI_INTELode=qureroute_to_boo _rede acpisrintel15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DECLARE_PCI_INTEL 722MB3a1#L74,55"> 6ESB2_Ccode=PCI_DJMICRONDJMB3an#L74,55"> 6ESB2_C=pci_">DEECLARE_PCI_INTELode=qureroute_to_boo _rede acpisrintel15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DECLARE_PCI_INTEL 722MB3a1#L74,55"> 6nam_Ccode=PCI_DJMICRONDJMB3an#L74,55"> 6nam_Cde=pci_asss"_erte_pxxnass="_ertereroute_to_boo _rede acpisrintel15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DECLARE_PCI_INTEL 722MB3a1#L74,55"> 6nam_Ecode=PCI_DJMICRONDJMB3a1#L74,55"> 6nam_Ede=pci_asss"_erte_pxxnass="_ertereroute_to_boo _rede acpisrintel15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DECLARE_PCI_INTEL 722MB3a1#L74,55"> 6namVcode=PCI_DJMICRONDJMB3a1#L74,55"> 6namVde=pci_assss"_erte_pxxnass="_ertereroute_to_boo _rede acpisrintel15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DECLARE_PCI_INTEL 722MB3a1#L74,55"> 680332_Ccode=PCI_DJMICRONDJMB3an#L74,55"> 680332_C=pci_">DECLARE_PCI_INTELode=qureroute_to_boo _rede acpisrintel15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DECLARE_PCI_INTEL 722MB3a1#L74,55"> 680332_Ecode=PCI_DJMICRONDJMB3a1#L74,55"> 680332_E=pci_">DECLARE_PCI_INTELode=qureroute_to_boo _rede acpisrintel15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DCLARE_PCI_INTEL 722MB3a1#L74,55"> 680333_Ccode=PCI_DJMICRONDJMB3an#L74,55"> 680333_C=pci_">DECLARE_PCI_INTELode=qureroute_to_boo _rede acpisrintel15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DCLARE_PCI_INTEL 722MB3a1#L74,55"> 680333_Ecode=PCI_DJMICRONDJMB3a1#L74,55"> 680333_E=pci_">DECLARE_PCI_INTELode=qureroute_to_boo _rede acpisrintel15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DCLARE_PCI_INTEL 722MB3a1#L74,55"> 6ESB2_Ccode=PCI_DJMICRONDJMB3an#L74,55"> 6ESB2_C=pci_">DEECLARE_PCI_INTELode=qureroute_to_boo _rede acpisrintel15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DCLARE_PCI_INTEL 722MB3a1#L74,55"> 6nam_Ccode=PCI_DJMICRONDJMB3an#L74,55"> 6nam_Cde=pci_asss"_erte_pxxnass="_ertereroute_to_boo _rede acpisrintel15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DCLARE_PCI_INTEL 722MB3a1#L74,55"> 6nam_Ecode=PCI_DJMICRONDJMB3a1#L74,55"> 6nam_Ede=pci_asss"_erte_pxxnass="_ertereroute_to_boo _rede acpisrintel15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DCLARE_PCI_INTEL 722MB3a1#L74,55"> 6namVcode=PCI_DJMICRONDJMB3a1#L74,55"> 6namVde=pci_assss"_erte_pxxnass="_ertereroute_to_boo _rede acpisrintel15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DCLARE_PCI_INTEL 722MB3a1#L74,55"> 680332_Ccode=PCI_DJMICRONDJMB3an#L74,55"> 680332_C=pci_">DECLARE_PCI_INTELode=qureroute_to_boo _rede acpisrintel15>);
smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DCLARE_PCI_INTEL 722MB3a1#L74,55"> 680332_Ecode=PCI_DJMICRONDJMB3a1#L74,55"> 680332_E=pci_">DECLARE_PCI_INTELode=qureroute_to_boo _rede acpisrintel15>);
smb
smb>155c#L713" id=6L733"6class="linnnnnnnnn*L> 6m outsmb);
Pname=generC...we mulegacy 55"x=boo a>smb);
 759< rede acpis/a>smb);
smb;
smb
smb);
 759r oIO- De-1 onn6300ESB=generC.es=boo trede acpis,, sotredel order n/a>smb);
smb);
smb;
 66300_IO De-_ABAode=DECLARE_PCI_55"> 66300_IO De-_ABAoareturnIA 82370x40 class="comme1578">smb;
#defineSsipic_deassert<55"> 66300_DISABLE_BOOT6IRQde=DECLARE_PCI_55"> 66300_DISABLE_BOOT6IRQareturnIA(1" cl" cl14rivers/O 12-19, 22, 23ne" name="L76ref="drive6s/pci15>);>156c#L656" id=6LER" 6lass="ivers/O 12-19, 22, 23ne" name="L76ref="drive6s/pci15) {>156c#L767" id=6Lref=6+code="line" nass="_erte_mchf="+code=quhrd ">Printelrboo _rede acpi15>);
Printelrboo _rede acpi);>157c#L763" id="L733" class="li/e" name="L759"> 759smb;
);>1568#L762" id=6L702"6class=BYPASS_APIC_DE1566">smb);
);>>;
 759config_wordC Deert Message\n&1547">smb);
smb);
(stresource_0" rtpnoAPIC Dcode=PCI_DJMICR/aAPIC Dcoderivers/O 12-19, 22, 23ne" name="L76ref="drref6"dria15>iv>1572#L74A 82376APIC 67LLrk_via_vt8237_binseDe-Assert Message\n&1547">smb);
smb
 759" ad"config_wordf">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing"ipic_deassert<55"> 66300_IO De-_ABAode=DECLARE_PCI_55"> 66300_IO De-_ABAoaretode>s_apic_deasserts="config_worde" name="L759"> 759config_wordC Desert Message\n&1454">smb
s="config_worde" name="L759"> 759config_wordC De |Assipic_deassert<55"> 66300_DISABLE_BOOT6IRQde=DECLARE_PCI_55"> 66300_DISABLE_BOOT6IRQaretert Message\n&1454">smb
(stmsi_offpic_deassertwrite_config_worde" name="L759"> 759write_config_wordf">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing"ipic_deassert<55"> 66300_IO De-_ABAode=DECLARE_PCI_55"> 66300_IO De-_ABAoaretodpic_deasserts="config_worde" name="L759"> 759config_wordC Desert Message\n&1454">smb
smb
(stmsi_offpic_deas78"rinfo>smb;
15e>s_apic_deassert(&pci_dev, 1" id="L731" ef"ing">"En707"dLonboard AC9hrd ">P =boo trede acpis onng name=[6> 7;04x:6> 7;04x]8237 APIC De-As,rt Message\n&1547">smb);
smb;
(&pci_isource_dev[="+codci_iso);>1sert Message\n&1454">smb
smb)
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DCLARE_PCI_INTEL 722MB3a1#L74,55"> 6ESB_1Ccode=PCI_DJMICRONDJMB3an#L74,55"> 6ESB_1Cde=pci_asss"_erte_pxxnass="_ertehrd ">Printelrboo _rede acpi15>);
Printelrboo _rede acpi);>1sert Message\n&1454">smb
DECLARE_PCI_INTEL 722DECLARE_PCI_INTEL_dev, R__ref="+code=pci_">DCLARE_PCI_INTEL 722MB3a1#L74,55"> 6ESB_1Ccode=PCI_DJMICRONDJMB3an#L74,55"> 6ESB_1Cde=pci_ass"_erte_pxxnass="_ertehrd ">Printelrboo _rede acpi15>);
Printelrboo _rede acpi);>1sert Message\n&1454">smb
smb
 759smb);
Pnboo trede acpis onnHT-100lassmb);
smb;
);
smb;
>1489#L741" id=6Lcas"68-Asse#defineSsipic_deassert);
smb;
);
smb;
smb>)
PrbroaddLtrboo _rede acpi15>);
PrbroaddLtrboo _rede acpi);>157c#L763" id="L733" class="li/e" name="L759"> 759smb;
{>149c#L743" id=6LLLLL69lass=BYPASS_APIC_DE1566">smb);
s="config_dworde" name="L759"> 759config_dwordC Deert Message\n&1547">smb);
smb);
;>149c#L767" id=6L767"69code=pci_>s_a>(stresource_0" rtpnoAPIC Dcode=PCI_DJMICR/aAPIC Dcoderivers/O 12-19, 22, 23ne" name="L76ref="drive6s/pci14>);>1498#L767" id=6L6" i698Lrk_via_vt8237_binseDe-Assert Message\n&1547">smb);
smb
s_apic_deassertert" ad"config_dworde" name="L759"> 759" ad"config_dwordf">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing"ipic_deassert);
 759config_dwordC Desert Message\n&1454">smb
 759write_config_dwordf">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing"ipic_deassert);
 759config_dwordC De |rt Message\n&1454">smb
);
smb
smb
smb);
DECLARE_PCI_INTELirqcode=PCI_DJMICRirqC Deng"ipic_deassert);
smb
DE0x00ng"ipic_deassert);
smb
s_a"line" name="L1561">smb)
smb)
 759write_config_dwordf">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing"ipic_deassert);
 759config_dwordC Desert Message\n&1454">smb
smb);
smb;
15e>s_apic_deassert(&pci_dev, 1" id="L731" ef"ing">"En707"dLonboard AC9hrd ">P =boo trede acpis onng name=[6> 7;04x:6> 7;04x]8237 APIC De-As,rt Message\n&1547">smb);
smb;
(&pci_isource_dev[="+codci_iso);>1sert Message\n&1454">smb
smb);
DECLARE_PCI_INTEL 722DCLARE_PCI_INTEL 722MB3a1#L74,SERVERWORKS_HT100lSBcode=PCI_DJMICRONDJMB3an#L74,SERVERWORKS_HT100lSBde=pci_asssss"_erte_pxxnass="_ertehrd ">PrbroaddLtrboo _rede acpi15>);
PrbroaddLtrboo _rede acpi);>1sert Message\n&1454">smb
DECLARE_PCI_INTEL 722DCLARE_PCI_INTEL 722MB3a1#L74,SERVERWORKS_HT100lSBcode=PCI_DJMICRONDJMB3an#L74,SERVERWORKS_HT100lSBde=pci_assss"_erte_pxxnass="_ertehrd ">PrbroaddLtrboo _rede acpi15>);
PrbroaddLtrboo _rede acpi);>1sert Message\n&1454">smb
151c#L767" id=7Lref=71lass="li/e" name="L759"> 75smb);
Pnboo trede acpis onnAMD and ATI ust setsa>smb);
smb;
smb);
 759r oNOIOAMODE needse" nbe hrd ">P =" nhrd ">Pn37 APIboo trede acpis37 API. FprrAMD 813+cosmb);
P =anywaye" nfixoIO- De- masscosmb);
smb);
 759 */a>smb;
#defineSsipic_deassertsmb;
>152c#L76s152c#L766" id=7L684"72lass=#defineSsipic_deassert>152c#L716" id=7L684"72-Assert Message\n&156f">smb
Pramd_813xrboo _rede acpi15>);
Pramd_813xrboo _rede acpi);>157c#L763" id="L733" class="li/e" name="L759"> 759smb;
>153c#L746" id=7L684"73+codeBYPASS_APIC_DE1566">smb);
s="config_dworde" name="L759"> 759config_dwordC Deert Message\n&1547">smb);
smb
(stresource_0" rtpnoAPIC Dcode=PCI_DJMICR/aAPIC Dcoderivers/O 12-19, 22, 23ne" name="L77r5f="drive7s/pci15an>>153c#L716" id=7L684"735Lrk_via_vt8237_binseDe-Assert Message\n&1547">smb);
(stECLARE_PCI_INTELci_dev, 1" id="L731" ef"ie=de" class="sref">previsiondev, 1" id="L73revisionC De =Assipic_deassertsmb
previsiondev, 1" id="L73revisionC De =Assipic_deassert{>1538#L76#endif7 8237738Lrk_via_vt8237_binseDe-Assert Message\n&1547">smb);
smb
 759" ad"config_dwordf">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing"ipic_deasserts_apic_deasserts="config_dworde" name="L759"> 759config_dwordC Desert Message\n&1454">smb
 759config_dwordC De e>s_a= ~sipic_deassertsmb
 759write_config_dwordf">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing"ipic_deasserts="config_dworde" name="L759"> 759config_dwordC Desert Message\n&1454">smb
smb
smb;
15e>s_apic_deassert(&pci_dev, 1" id="L731" ef"ing">"En707"dLonboard AC9hrd ">P =boo trede acpis onng name=[6> 7;04x:6> 7;04x]8237 APIC De-As,rt Message\n&1547">smb);
smb;
(&pci_isource_dev[="+codci_iso);>1sert Message\n&1454">smb
smb);
DECLARE_PCI_INTEL 722Pramd_813xrboo _rede acpi15>);
Pramd_813xrboo _rede acpi);>1sert Message\n&1454">smb
DECLARE_PCI_INTEL 722Pramd_813xrboo _rede acpi15>);
Pramd_813xrboo _rede acpi);>1sert Message\n&1454">smb
DECLARE_PCI_INTEL 722Pramd_813xrboo _rede acpi15>);
Pramd_813xrboo _rede acpi);>1sert Message\n&1454">smb
DECLARE_PCI_INTEL 722Pramd_813xrboo _rede acpi15>);
Pramd_813xrboo _rede acpi);>1sert Message\n&1454">smb
smb>)
);
smb>)
smb
Pramd_8111Aboo _rede acpi15>);
Pramd_8111Aboo _rede acpi);>157c#L763" id="L733" class="li/e" name="L759"> 759smb;
>155c#L713" id=7L733"7class=BYPASS_APIC_DE1566">smb);
(stmsi_offpic_deasus/pci15>);>>;
 759config_wordC Deert Message\n&1547">smb);
smb
(stresource_0" rtpnoAPIC Dcode=PCI_DJMICR/aAPIC Dcoderivers/O 12-19, 22, 23ne" name="L77ref="drive7s/pci15an>>155c#L71A 82377APIC 759Lrk_via_vt8237_binseDe-Assert Message\n&1547">smb);
smb);
 759" ad"config_wordf">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing"ipic_deassert);
s_apic_deasserts="config_worde" name="L759"> 759config_wordC Desert Message\n&1454">smb
 759config_wordC Des BYPASS_APIC_DE1566">smb);
smb;
15e>s_apic_deassert(&pci_dev, 1" id="L731" ef"ing">"En707"dLonboard AC9boo trede acpis onng name=[6> 7;04x:6> 7;04x] 37 APIC De-AsYPASS_APIC_DE1566">smb);
"En707"dLonboard AC9al" ady hrd ">P 8237 APIC De-As,cpic_deassertsmb;
(&pci_isource_dev[="+codci_iso);>1sert Message\n&1454">smb
smb);
smb);
 759write_config_wordf">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing"ipic_deassert);
smb
(stmsi_offpic_deas78"rinfo>smb;
15e>s_apic_deassert(&pci_dev, 1" id="L731" ef"ing">"En707"dLonboard AC9hrd ">P =boo trede acpis onng name=[6> 7;04x:6> 7;04x]8237 APIC De-As,rt Message\n&1454">smb
smb;
(&pci_isource_dev[="+codci_iso);>1sert Message\n&1454">smb
smb)
DECLARE_PCI_INTEL 722Pramd_8111Aboo _rede acpi15>);
Pramd_8111Aboo _rede acpi);>1sert Message\n&1454">smb
iv>1572#L74A 82377APIC 77lass="line" name="LRESUME_EARLY684DECLARE_PCI_INTEL 722Pramd_8111Aboo _rede acpi15>);
Pramd_8111Aboo _rede acpi);>1sert Message\n&1454">smb
smb;
smb);>157c#L713" id=7L733"77lass="linnnnnnnnn*L> 6m outsmb);
smb);
 759< but ame=PIO transf575 won6> 9;t work2>(sBAR0 falls at ame=odd 8 bytes/a>smb);
(sneeded../a>smb);
smb;
157c#L763" id="L733" class="li/e" name="L759"> 759smb;
);>148c#L741" id=7Lswit78+codeBYPASS_APIC_DE1566">smb);
presoursource_dev[="+codresourso>smb
smb
(stresource_0" rtp#L65 &pL0x80p"liri15>);
s_a 0x8s BYPASS_APIC_DE1566">smb);
p"liri15>);
smb
pendL65 &pL0x80smb
s_a"line" name="L1561">smb)
smb)
DECLARE_PCI_INTEL 722smb)
smb)
1sert Message\n&1454">smb
smb
smb);
 759 * PLX  72 9050  72 Target bridge controllerehasnne e aatanamat prev> 7s amea>smb);
PnviasBAR0 (memory) orsBAR1 (i/o)a>smb);
(sbit 7e muame=base address is set/a>smb);
 759< The BAR0 orsBAR1 reg..wemaynbe hrd ">P =(sizs 0) orsen ">P =(sizs 128)/a>smb);
(snecessary/a>smb);
smb;
sm9050urce_dev[="+codode=quplx_>sm9050);>157c#L763" id="L733" class="li/e" name="L759"> 759smb;
n>>150c#L74A 82378APIC 80+codeBYPASS_APIC_DE1566">smb);
smb);
smb
smb;
(stresource_0" rtpci_dev, 1" id="L731" ef"ie=de" class="sref">previsiondev, 1" id="L73revisionC De =de"= 2rivers/O 12-19, 22, 23ne" name="L78r6f="drive8s/pci14>);>1496#L741" id=8L2" i80lareturnIA 8237 APIC De-Assert Message\n&1547">smb);
s_a=prrECLARE_PCI_INTELba#L65 &pL0x80);>1498#L767" id=8Lrk_v808Lrk_via_vt8237_binse>(stresource_0" rtp 759" sourso_lendev, 1" id="L73 759" sourso_lenf">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing"ipic_deasserts_ae>s_aivers/O 12-19, 22, 23ne" name="L78r9f="drive8s/pci14/a>>149c#L719" id=8Lref=809Lrk_via_vt8237_binsea _bECLARE_PCI_INTEL 759" sourso_"liri15>);
DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing"ipic_deasserts_a 0x80)s BYPASS_APIC_DE1566">smb);
presoursource_dev[="+codresourso>smb
smb;
15e>s_apic_deassert(&pci_dev, 1" id="L731" ef"inrt Message\n&1454">smb
"En707"dLonboard AC9Re-allocating PLX  72 9050 BAR 6> 7;ue" nlength 256e" nanass=bit 7ebug8237 APIC De-As,rt Message\n&1454">smb
smb
p"liri15>);
smb
pendL65 &pL0x80smb
smb)
smb)
DECLARE_PCI_INTEL 722smb
sm9050urce_dev[="+codode=quplx_>sm9050);>1)ert Message\n&1454">smb
smb);
 759r oThe following Meilhaus (vendo# IDc0x1402)ng name=IDs (amongst oth575)a>smb);
smb);
smb);
 759 *c0x168f,c0x2000,c0x2600,c0x3000,c0x810a,c0x810b/a>smb);
smb);
smb);
 759< _DE156/a>smb);
smb;
DE0x1402,c0x2000,cpic_deassertsm9050urce_dev[="+codode=quplx_>sm9050);>1)ert Message\n&1454">smb
DE0x1402,c0x2600,cpic_deassertsm9050urce_dev[="+codode=quplx_>sm9050);>1)ert Message\n&1454">smb
smb>)
157c#L763" id="L733" class="li/e" name="L759"> 759smb;
>153c#L746" id=8L684"83lass=BYPASS_APIC_DE1566">smb);
smb;
psubsystem_ci_isource_dev[="+codsubsystem_ci_isoC De e>s_a 0xf0) =de"=de" 4ert Message\n&1454">smb
smb;
psubsystem_ci_isource_dev[="+codsubsystem_ci_isoC De e>s_a 0xfert Message\n&1454">smb
)>153c#L76A 82378APIC 837Lrk_via_vt82"linnnnnnnnn*Lforciblysmb);
smb);
smb);
smb);
 759rllllllll owill namim amem.  To prev> 7 amis,nmark amem=asnnnnnn OTHER/a>smb);
smb);
smb);
 759 llllllll oThe subg name=ID is  muame=formc0x00PS, where " clP=de" is ame=numb57C smb);
smb);
smb;
pci_isource_dev[="+codci_iso);>1s BYPASS_APIC_DE1566">smb);
>="+cod 722MB3a1#L74,NETMOS_98s/Lrk_:YPASS_APIC_DE1566">smb);
 9;t holdn=prrthe following 98s/ng name= /a>smb;
(stresource_0" rtpci_dev, 1" id="L731" ef"ie=de" class="sref">psubsystem_vendo#L65 &pL0x80}>155c#L741" id=8Li66"85ELrk_via_vt8237_binsec37 APIC 7_binse"esource_0" rtpci_dev, 1" id="L731" ef"ie=de" class="sref">psubsystem_ci_isource_dev[="+codsubsystem_ci_isoC De =As0x0299rivers/O 12-19, 22, 23ne" name="L78ref="drive8s/pci15>);>1552#L741" id=8LLLLL85LLrk_via_vt8237_binsec37_binsDe-Assert Message\n&1547">smb);
>="+cod 722MB3a1#L74,NETMOS_97s/Lrk_:YPASS_APIC_DE1566">smb);
>="+cod 722MB3a1#L74,NETMOS_974/Lrk_:YPASS_APIC_DE1566">smb);
>="+cod 722MB3a1#L74,NETMOS_984/Lrk_:YPASS_APIC_DE1566">smb);
(stcase "ipic_deassert< 722MB3a1#L74,NETMOS_985/pci15an>>="+cod 722MB3a1#L74,NETMOS_985/Lrk_:YPASS_APIC_DE1566">smb);
(stresource_0" rtpnum_parallel>smb;
smb);
smb;
15e>s_apic_deassert(&pci_dev, 1" id="L731" ef"ing">"En707"dLonboard AC9Netmos 6> 7;04x (6> 7;ueparallel, 37 APIC De-AsYPASS_APIC_DE1566">smb);
"En707"dLonboard AC96> 7;ueserial); changing nnnnn SERIALe" nOTHER 37 APIC De-AsYPASS_APIC_DE1566">smb);
"En707"dLonboard AC9(use parpori_serial)8237 APIC De-As,rt Message\n&1454">smb
pci_isource_dev[="+codci_iso);>1,cpic_deassertsmb;
smb;
smb
pv, 1"dev, 1" id="L73v, 1"C De = tresource_0" rtp 722CLASS_COMMUNICATION_OTHERpci15an>>="+cod 722CLASS_COMMUNICATION_OTHERC De " cl" cln8) |rt Message\n&1454">smb
pv, 1"dev, 1" id="L73v, 1"C De e>s_a 0xff)ert Message\n&1454">smb
smb)
smb)
smb);
DECLARE_PCI_INTEL 722smb
>="+cod 722CLASS_COMMUNICATION_SERIALef"ing8,cpic_deassert1)ert Message\n&1454">smb
smb
);
 759smb;
}>157c#L746" id=8L684"87+codeBYPASS_APIC_DE1566">smb);
iv>1572#L74A 82378APIC 87LLrk_via_vt82pic_deassert);>>;
smb
);>>;
smb
);>>;
smb
n63" id="L733" clapmpci15>);>>;
smb
);>157c#L763" id=8L733"877Lrk_via_vt82switch tresource_0" rtpci_dev, 1" id="L731" ef"ie=de" class="sref">pci_isource_dev[="+codci_iso);>1s BYPASS_APIC_DE1566">smb);
(stmlinnnnnnnnn*Lforciblysmb;
smb);
smb);
smb);
smb);
smb);
smb);
smb);
(stcase 0x1209:YPASS_APIC_DE1566">smb);
s_acase 0x1229:YPASS_APIC_DE1566">smb);
smb);
smb);
smb);
smb);
smb
smb);
smb);
smb)
;>149c#L767" id=8L767"897Lrk_via_vt82"linnnnnnnnn*Lforciblysmb);
P ,a>smb);
smb);
smb);
 759rllllllll ohrd ">P all=e100 rede acpis here.  Tme=mme157 willa>smb);
P amem=when it6> 9;s " ady/a>smb);
smb;
 759" ad"config_wordf">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing"ipic_deassert< 722COMMANrcode=PCI_DJMICR 722COMMANref"inge>s_apic_deassertsmb
smb
(st!ECLARE_PCI_INTELLforandL65 &pL0x80s_a "ipic_deassert< 722COMMANr_MEMORYcode=PCI_DJMICR 722COMMANr_MEMORY);>1s || !pic_deasserts="" sourso_"liri15>);
DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing0)rivers/O 12-19, 22, 23ne" name="L79r7f="drive9s/pci14a>;>149c#L767" id=9APIC 907Lrk_via_vt8237_bPIC De-Assert Message\n&1547">smb);
smb);
smb);
 9;s not,a>smb);
 759rllllllll othere is no po>n63" nlook any further/a>smb);
smb;
);>>;
);
DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing"ipic_deassert< 722CAPL74,PMcode=PCI_DJMICR 722CAPL74,PMef"i)ert Message\n&1454">smb
(stresource_0" rtppmpci15>);>>;
smb);
 759" ad"config_wordf">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing"ipic_deassert);>>;
>="+cod 722PM_CTRLef"inge>s_apic_deassertsmb
(sttresource_0" rtppmcs#L65 &pL0x80s_a "ipic_deassert< 722PM_CTRL_STATE_MASKpci15an>>="+cod 722PM_CTRL_STATE_MASKef"is != resource_0" rtp_devD0urce_dev[="+cod 722M0f="drivers/O 12-19, 22, 23ne" name="L79r7f="drive9s/pci15) {>151c#L767" id=9Lref=917Lrk_via_vt8237_bPIC 37_bPIC De-Assert Message\n&1547">smb);
smb)
smb
smb;
DECLARE_PCI_INTEL>s="" sourso_"liri15>);
DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing0), 8)ert Message\n&1454">smb
(st!pic_deassertsmb);
15e>s_apic_deassert(&pci_dev, 1" id="L731" ef"ing">"En707"dLonboard AC9Can6> 9;t map=e100 reg.st5758237 APIC De-As)ert Message\n&1454">smb
smb);
smb)
>152c#L76sDECLARE_PCI_INTELcs#L65 &pL0x80smb
(stresource_0" rtpcmd_hiL65 &pL0x80smb);
15e>s_apic_deassert(&pci_dev, 1" id="L731" ef"ing">"En707"dLonboard AC9Firmware left=e100 rede acpis en ">P ; 37 APIC De-AsYPASS_APIC_DE1566">smb);
"En707"dLonboard AC9hrd ">onb8237 APIC De-As)ert Message\n&1454">smb
pwritebL65 &pL0x80151ng"ipic_deassertsmb
smb)
smb
DECLARE_PCI_INTELcs#L65 &pL0x80smb
smb)
DECLARE_PCI_INTEL 722>="+cod 722smb
>="+cod 722CLASS_NETWORK_ETHERNETef"ing8,cpic_deassert);
smb
smb);
smb);
smb);
 759r* outo muL0S.  To prev> 7 amis wesneede" nhrd ">P L0S onname=>sm-e linka>smb);
smb;
Praspm_l0surce_dev[="+codode=quhrd ">Praspm_l0sf">DE7c#L763" id="L733" class="li/e" name="L759"> 759smb;
>1544#L69" id="9702" 94lass=BYPASS_APIC_DE1566">smb);
smb;
15e>s_apic_deassert(&pci_dev, 1" id="L731" ef"ing">"En707"dLonboard AC9Drd ">onb L058237 APIC De-As)ert Message\n&1454">smb
Prlink_"linee" name="L759"> 759Prlink_"linef">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing"ipic_deassert< 72E_LINK_STATE_L0Spci15an>>="+cod 72E_LINK_STATE_L0S);>1)ert Message\n&1454">smb
smb)
DECLARE_PCI_INTEL 722>="+cod 722Praspm_l0surce_dev[="+codode=quhrd ">Praspm_l0sf">D)ert Message\n&1454">smb
DECLARE_PCI_INTEL 722>="+cod 722Praspm_l0surce_dev[="+codode=quhrd ">Praspm_l0sf">D)ert Message\n&1454">smb
DECLARE_PCI_INTEL 722>="+cod 722Praspm_l0surce_dev[="+codode=quhrd ">Praspm_l0sf">D)ert Message\n&1454">smb
DECLARE_PCI_INTEL 722>="+cod 722Praspm_l0surce_dev[="+codode=quhrd ">Praspm_l0sf">D)ert Message\n&1454">smb
DECLARE_PCI_INTEL 722>="+cod 722Praspm_l0surce_dev[="+codode=quhrd ">Praspm_l0sf">D)ert Message\n&1454">smb
DECLARE_PCI_INTEL 722>="+cod 722Praspm_l0surce_dev[="+codode=quhrd ">Praspm_l0sf">D)ert Message\n&1454">smb
DECLARE_PCI_INTEL 722>="+cod 722Praspm_l0surce_dev[="+codode=quhrd ">Praspm_l0sf">D)ert Message\n&1454">smb
DECLARE_PCI_INTEL 722>="+cod 722Praspm_l0surce_dev[="+codode=quhrd ">Praspm_l0sf">D)ert Message\n&1454">smb
DECLARE_PCI_INTEL 722>="+cod 722Praspm_l0surce_dev[="+codode=quhrd ">Praspm_l0sf">D)ert Message\n&1454">smb
DECLARE_PCI_INTEL 722>="+cod 722Praspm_l0surce_dev[="+codode=quhrd ">Praspm_l0sf">D)ert Message\n&1454">smb
DECLARE_PCI_INTEL 722>="+cod 722Praspm_l0surce_dev[="+codode=quhrd ">Praspm_l0sf">D)ert Message\n&1454">smb
DECLARE_PCI_INTEL 722>="+cod 722Praspm_l0surce_dev[="+codode=quhrd ">Praspm_l0sf">D)ert Message\n&1454">smb
DECLARE_PCI_INTEL 722>="+cod 722Praspm_l0surce_dev[="+codode=quhrd ">Praspm_l0sf">D)ert Message\n&1454">smb
DECLARE_PCI_INTEL 722>="+cod 722Praspm_l0surce_dev[="+codode=quhrd ">Praspm_l0sf">D)ert Message\n&1454">smb
smb
)>="+codfixup_rev1_53c8s/f">DE7c#L763" id="L733" class="li/e" name="L759"> 759smb;
 8>15a4#L740" id=9L760"96lass=BYPASS_APIC_DE1566">smb);
 9;t set ame=nnnnn at all=which meansa>smb;
smb;
 759llllllll /a>smb;
smb);
(stresource_0" rtpci_dev, 1" id="L731" ef"ie=de" class="sref">pv, 1"L65 &pL0x80smb);
smb;
15e>s_apic_deassert(&pci_dev, 1" id="L731" ef"ing">"En707"dLonboard AC9NCR 53c8s/ rev 1 detectP ; setting PCIot;En78237 APIC De-As)ert Message\n&1454">smb
pci_dev, 1" id="L731" ef"ie=de" class="sref">pv, 1"dev, 1" id="L73v, 1"C De = "ipic_deassert< 722CLASS_STORAGE_SCSIcode=PCI_DJMICR 722CLASS_STORAGE_SCSIC Deert Message\n&1454">smb
iv>1572#L74A 82379APIC 972Lrk_via_vt82"line" name="L1561">smb)
smb)
DECLARE_PCI_INTEL 722>="+cod 722)>="+cod 722MB3a1#L74,NCR_53C8s/ef"ing"ipic_deassert)>="+codfixup_rev1_53c8s/f">D)ert Message\n&1454">smb
smb
P 1k I/O linso granularity onname=Intel P64H2l /a>smb;
smb;
DE7c#L763" id="L733" class="li/e" name="L759"> 759smb;
;>15&15e1"0" id=9L760"978ss="BYPASS_APIC_DE1566">smb);
);>>;
);>>;
smb
smb
 759" ad"config_wordf">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing0x40,ce>s_apic_deassert);>>;
smb
smb
(stresource_0" rtpen1kpci15>);>>;
s_a 0x200) BYPASS_APIC_DE1566">smb);
smb;
15e>s_apic_deassert(&pci_dev, 1" id="L731" ef"ing">"En707"dLonboard AC9En ">P I/O Sinso to 1KB granularity8237 APIC De-As)ert Message\n&1454">smb
(&pio_window_1kpci15>);>>;
smb
(st"line" name="L1561">smb)
smb)
DECLARE_PCI_INTEL 722>="+cod 722smb;
D)ert Message\n&1454">smb
smb
smb);
 759r* Forso i63" nbe linked by setting ame=norresponding nontrol bi63in ameC smb);
smb);
smb;
sme_aer_ext"cap>smb;
sme_aer_ext"capf">DE7c#L763" id="L733" class="li/e" name="L759"> 759smb;
>1495#L741" id=9Lcas"995Lrk_BYPASS_APIC_DE1566">smb);
);
smb
(stresource_0" rtpp759" ad"config_bynee" name="L759"> 759" ad"config_bynef">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing0xf41,ce>s_apic_deassertsmb);
(st!ECLARE_PCI_INTELbL65 &pL0x80s_a 0x20)) BYPASS_APIC_DE1566">smb);
 759write"config_bynef">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing0xf41,cCLARE_PCI_INTELbL65 &pL0x80smb
>149c#L719" id2000f>2000Lrk_via_vt8237_binse37_binseresource_0" rtpci_rinfo>smb;
15e>s_apic_deassert(&pci_dev, 1" id="L731" ef"in
t Message\n&1454">smb >149c#L741" id200/p>200ELrk_via_vt8237_binsec37 APIC 7_bins">"En707"dLonboard AC9Linking AER extend5d capability8237 APIC De-As)ert Message\n&1454">smb )>1492#L741" id200/p>200LLrk_via_vt8237_binse"line" name="L1561">smb) {>149c#L743" id200/p>2003Lrk_via_vt82"line" name="L1561">smb) ;>1494#L741" id200/p>2004ass="line" name="L1561">smb) >1495#L741" id200/p>200/Lrk_"line" name="LRESUME_EARLY684fass="line" name="LFINAL_HEADER" class="sref">DECLARE_PCI_INTEL 722>="+cod 722)>="+cod 722MB3a1#L74,NVIDIA_CK804_ 72Eef"in smb) );>1496#L741" id200/p>200lareturnIA 8237 APIC 37_binseresource_0" rtpode=qunvidia_ck804_>sme_aer_ext"cap>smb; sme_aer_ext"capf">D)ert Message\n&1454">smb ;>149c#L767" id200/p>200eass="line" name="LEARLY684DECLARE_PCI_INTEL 722>="+cod 722)>="+cod 722MB3a1#L74,NVIDIA_CK804_ 72Eef"in smb) );>1498#L767" id200/p>2008Lrk_via_vt8237_binse 7_binse"esource_0" rtpode=qunvidia_ck804_>sme_aer_ext"cap>smb; sme_aer_ext"capf">D)ert Message\n&1454">smb >149c#L719" id200/p>200-Assert Message\n&156f">smb )>151)#L71A 82320s/p>20s/ass="line" nass="_erte_mchf="+code=quvia_cx700_>sm_parking"cachonbosmb; sm_parking"cachonbf">DE7c#L763" id="L733" class="li/e" name="L759"> 759smb; {>151c#L741" id20s/p>20s+codeBYPASS_APIC_DE1566">smb); ;>1512#L741" id20s/p>20sLLrk_via_vt82pline 3rs usedLtogethesmb); ;>151c#L743" id20s/p>20slass="line do thisnearsllllllll Drd ">P PCIoBus Parking and PCIoMast57 " ad cachonb onnCX700Lrsmb); >1514#L697" id20s/p>20slass="li/* name="L759"> 759 llllllll owhich cnuses unspecifiP =timonb errors with a VT6212L onname=PCILrsmb); >151c#L71A 82320s/p>20slass="line It's possi07"llllllll obusel ading ao USB2.0upackei loss.C smb); );>151c#L656" id20s/p>20slass="line 3rs usedLtogetherllllllll C smb); 151c#L767" id20s/p>20slass="li/e" name="L759"> 759llllllll Tmis is nly en ">P e>(sa second (onname=external 72 bus)C smb); );>1518#L762" id20s/p>20slass="line do thisnearlllllllll* VT6212L is found --name=CX700=noro i6sel(salso nontainssa USBC smb); )>151c#L716" id20s/p>20slass="line 3rs usedLtogetherllllllll* host nontroll57 with ame=s16" 72 ID as ame=VT6212L.C smb); );>152)#L716" id20s/p>20s/ass="li/e" name="L759"> 759llllllll /a>smb; 152c#L746" id20s/p>20s1Assert Message\n&156f">smb }>1522#L746" id20s/p>20sLLrk_via_vt82pline 3rs usedLtogethesmb; ,>152c#L746" id20s/p>20s3Lrk_via_vt827c#L763" id="L733" class="li/e" name="L759"> 759smb; DECLARE_PCI_INTEL 722>="+cod 722smb; );>1524#L696" id20s/p>20s4ass=ia_vt8237_binsecpic_deassert)>="+cod 722MB3a1#L74,VIA_8235_USB_2ef"ing"ipic_deassertD)ert Message\n&1454">smb >152c#L716" id20s/p>20s5"line" nps_apic_deassert); smb >152c#L65s20sass="ivers/O 12-19, 22, 23ne" name="L20s7f="driv20s/pci15/a>>152c#L76s20s7Lrk_via_vt82"linnnnnnnnn*Lforcibly(swe haveC smb); 152c#L766" id20s/p>20slass="line do thisnearlllllllll an=external one by searchonb again /a>smb; >152c#L716" id20s/p>20s9Lrk_via_vt82pic_deassertsmb; DECLARE_PCI_INTEL 722>="+cod 722)>="+cod 722MB3a1#L74,VIA_8235_USB_2ef"ing"ipic_deassert

smb; smb >153)#L716" id20s/p>20s/Lrk_via_vt82>(st!pic_deassert>smb; smb >153c#L746" id20s/p>20sELrk_via_vt8237_binseDe-Assert Message\n&1547">smb); >1532#L746" id20s/p>20sLLrk_via_vt82pic_deassert); DECLARE_PCI_INTELp>smb; smb >153c#L746" id20s/p>20s-Assert Message\n&1574">smb >1534#L696" id20s/p>20s="line" nps_a>(stresource_0" rtpp759" ad"config_bynee" name="L759"> 759" ad"config_bynef">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing0x76,ce>s_apic_deassertsmb); >153c#L716" id20s/p>20s5Lrk_via_vt8237_binse>(stresource_0" rtpbL65 &pL0x80s_a 0x40) BYPASS_APIC_DE1566">smb); >153c#L65s20slareturnIA 8237 APIC 37_binserlinnnnnnnnn*Lforciblysmb; )>153c#L76A 82320s/p>20s7Lrk_via_vt8237_bPIC 37_bPIC "ipic_deassert 759write"config_bynef">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing0x76,cpic_deassertsmb {>1538#L76#endi20s/p>20s8Lrk_rt Message\n&1547">smb); ;>153c#L71A 82320s/p>20s9Lrk_via_vt8237_binse37_binseresource_0" rtpci_rinfo>smb; 15e>s_apic_deassert(&pci_dev, 1" id="L731" ef"in < Message\n&1547">smb); 154)#L71#ifde20s/p>20s/Lrk_via_vt8237_binsec37 APIC 7_binsg">"En707"dLonboard AC9Drd ">onb VIA=CX700=PCIoparking8237 APIC De-As)ert Message\n&1454">smb 154c#L740" id20s/p>20sELrk_via_vt8237_binse"line" name="L1561">smb) >1542#L74SERT"20s/p>20s2Lrk_via_vt82"line" name="L1561">smb) 154c#L743" id20s/p>20s-Assert Message\n&1574">smb >1544#L69" id=20s/p>20s="line" nps_a>(stresource_0" rtpp759" ad"config_bynee" name="L759"> 759" ad"config_bynef">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing0x72,ce>s_apic_deassertsmb); 154c#L715" id20s/p>20s5Lrk_via_vt8237_binse>(stresource_0" rtpbL65 &pL0x80smb); ,>1546#L715" id20s/p>20slareturnIA 8237 APIC 37_binserlinnnnnnnnn*Lforciblysmb; );>154c#L76A 82320s/p>20s7Lrk_via_vt8237_bPIC 37_bPIC "ipic_deassert 759write"config_bynef">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing0x72ng0x0)ert Message\n&1454">smb >1548#L767" id20s/p>20s8Lrk_rt Message\n&1547">smb); >154c#L713" id20s/p>20s9Lrk_via_vt8237_binse37_binserlinnnnnnnnn*Lforciblysmb; );>155)#L713" id20s/p>20s/Lrk_via_vt8237_bPIC 37_bPIC "ipic_deassert 759write"config_bynef">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing0x75ng0x1)ert Message\n&1454">smb }>155c#L741" id20s/p>20s1Assert Message\n&156f">smb );>1552#L741" id20s/p>20sLLrk_via_vt8237_binse37_binserlinnnnnnnnn*LforciblyP 37 APIR ad FIFO Timer37 API /a>smb; );>155c#L74A 82320s/p>20slass=ia_vt8237_binsec37_bPIC "ipic_deassert 759write"config_bynef">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing0x77ng0x0)ert Message\n&1454">smb >1554#L697" id20s/p>20s4Assert Message\n&156f">smb >155c#L713" id20s/p>20s5Lrk_via_vt8237_binse37_bPIC "ipic_deassertsmb; 15e>s_apic_deassert(&pci_dev, 1" id="L731" ef"in < Message\n&1547">smb); >1556#L715" id20s/p>20slareturnIA 8237 APIC 37_binse37_binserlinnnnnnnnn*"dLonboard AC9Drd ">onb VIA=CX700=PCIocachonb8237 APIC De-As)ert Message\n&1454">smb >155c#L767" id20s/p>20s7Lrk_via_vt8237_bPIC "line" name="L1561">smb) >1558#L767" id20s/p>20s8Lrk_via_vt82"line" name="L1561">smb) >155c#L71A 82320s/p>20s9ass="line" name="L1561">smb) >15an#L742" id20s/p>20s/Lrk_"line" name="LRESUME_EARLY684fass="line" name="LFINAL_HEADER" class="sref">DECLARE_PCI_INTEL 722>="+cod 722sm_parking"cachonbosmb; sm_parking"cachonbf">D)ert Message\n&1454">smb )>156c#L746" id20s/p>20s1Assert Message\n&156f">smb {>15a2#L74#endi20s/p>20slass="lin* I66w ars usmb); ;>156c#L74A 82320s/p>20slass="line do thisnearsi For Broad th 5706, 5708, 5709 rev. A nics, any " ad beyond ameC smb); 8>15a4#L740" id20s/p>20slass="li/* name="L759"> 759 * VPD end aag will hangname=mi_iso. Tmis pro">Pm was initiallyC smb); >15a5#L74SERT"20s/p>20slass="line It's possi07"* obser15dnwhen a vpd entry was c" atP e>n sysfsa>smb; );>156c#L656" id20s/p>20slass="line 3rs usedLtogether* (6> 9;/sys/bu8">smbmi_isos/<id=de"/vpd6> 9;). A " ad " namis sysfs entrya>smb; 156c#L767" id20s/p>20slass="li/e" name="L759"> 759* will dump 32ko mudata. R ading a full 32kowill 3ause an acsossa>smb; );>1568#L762" id20s/p>20slass="line do thisnearl* beyond ame VPD end aag 3ausingname=mi_iso " nhang. Onso ame=mi_isoa>smb; );>156c#L716" id20s/p>20slass="line 3rs usedLtogether* is hung, ame=bnx2=mme157 will not be a">P a n" set ame=mi_iso.C smb); 157)#L716" id20s/p>20s/ass="line 3rs usedLtogether* We=believenamat i63isel gal a n" ad beyond ame end aag andefsmb); }>157c#L746" id20s/p>20slass="li/* name="L759"> 759r* thereforPname=solu...w is3" nlimit ame=" ad/writeel ngth.C smb); iv>1572#L74A 82320"dr>20slass="lin* I66w ars us /a>smb; ;>157c#L74A 82320s/p>20slass="line" nass="_erte_mchf="+code=qubrcm_570x_limit_vpdosmb; DE7c#L763" id="L733" class="li/e" name="L759"> 759smb; >1574#L693" id20s/p>20slass=BYPASS_APIC_DE1566">smb); );>157c#L713" id20s/p>20s5Lrk_via_vt82"linnnnnnnnn*Lforciblysmb; >157c#L653" id20s/p>20slass="line 3rs usedLtogetherllllllll Only hrd ">P ame VPD capability for 5706, 5706S, 5708,a>smb; );>157c#L763" id20s/p>20slass="li/e" name="L759"> 759llllllll 5708S and 5709 rev. Aa>smb; ;>15&15e1"0" id20s/p>20slass="line do thisnearlllllllll*/a>smb; );>1479#L767" id20s/p>20s9Lrk_via_vt82>(sttresource_0" rtpci_dev, 1" id="L731" ef"ie=de" class="sref">pci_isource_dev[="+codci_isof">D == "ipic_deassert< 722MB3a1#L74,NX2_570/pci15>);>>; smb; >148)#L71A 82320s/p>20s/Lrk_via_vt8237_btresource_0" rtpci_dev, 1" id="L731" ef"ie=de" class="sref">pci_isource_dev[="+codci_isof">D == "ipic_deassert< 722MB3a1#L74,NX2_570/Spci15an>>="+cod 722MB3a1#L74,NX2_570/SC De) || class="comme1578">smb; );>148c#L741" id20s/p>20sELrk_via_vt8237_btresource_0" rtpci_dev, 1" id="L731" ef"ie=de" class="sref">pci_isource_dev[="+codci_isof">D == "ipic_deassert< 722MB3a1#L74,NX2_5708pci15an>>="+cod 722MB3a1#L74,NX2_5708C De) || class="comme1578">smb; ;>1482#L741" id20s/p>20sLLrk_via_vt8237_btresource_0" rtpci_dev, 1" id="L731" ef"ie=de" class="sref">pci_isource_dev[="+codci_isof">D == "ipic_deassert< 722MB3a1#L74,NX2_5708Spci15an>>="+cod 722MB3a1#L74,NX2_5708SC De) || class="comme1578">smb; );>1483#L741" id20s/p>20slass=ia_vt8237_bittresource_0" rtpci_dev, 1" id="L731" ef"ie=de" class="sref">pci_isource_dev[="+codci_isof">D == "ipic_deassert< 722MB3a1#L74,NX2_5709pci15an>>="+cod 722MB3a1#L74,NX2_5709C De) e>s_ae>s_a class="comme1578">smb; }>1484#L741" id20s/p>20s4ass=ia_vt8237_bintresource_0" rtpci_dev, 1" id="L731" ef"ie=de" class="sref">previs..wdev, 1" id="L73revis..wC De e>s_a 0xf0) == 0x0)) BYPASS_APIC_DE1566">smb); );>148c#L715" id20s/p>20s5Lrk_via_vt8237_binse>(stresource_0" rtpci_dev, 1" id="L731" ef"ie=de" class="sref">pvpdosmb; Drivers/O 12-19, 22, 23ne" name="L2086f="driv20s/pci14/a>>1486#L715" id20s/p>20slareturnIA 8237 APIC 37_binseresource_0" rtpci_dev, 1" id="L731" ef"ie=de" class="sref">pvpdosmb; De=de" class="sref">pl nosmb; smb; >148c#L767" id20s/p>20s7Lrk_via_vt82"line" name="L1561">smb) >1488#L76A 82320s/p>20s8ass="line" name="L1561">smb) >1489#L741" id20s/p>20s-Assert Message\n&156f">smb >1490#L741" id20s/p>20s/Lrk_"line" name="LRESUME_EARLY684fass="line" name="LFINAL_HEADER" class="sref">DECLARE_PCI_INTEL 722>="+cod 722smb); >149c#L741" id20s/p>20sELrk_via_vt8237_binsec37 APIC"ipic_deassert< 722MB3a1#L74,NX2_570/pci15>);>>; smb); )>1492#L741" id20s/p>20sLLrk_via_vt8237_binse37_binser_erte_mchf="+code=qubrcm_570x_limit_vpdosmb; D)ert Message\n&1454">smb {>149c#L743" id20s/p>20s3Lrk_"line" name="LRESUME_EARLY684fass="line" name="LFINAL_HEADER" class="sref">DECLARE_PCI_INTEL 722>="+cod 722smb); ;>1494#L741" id20s/p>20s4ass=ia_vt8237_binsecc37 APIC"ipic_deassert< 722MB3a1#L74,NX2_570/Spci15an>>="+cod 722MB3a1#L74,NX2_570/SC Den < Message\n&1547">smb); >1495#L741" id20s/p>20s5Lrk_via_vt8237_binse37_bPIC "ipic_deassert; D)ert Message\n&1454">smb );>1496#L741" id20s/p>20sass=""line" name="LEARLY684DECLARE_PCI_INTEL 722>="+cod 722smb); ;>149c#L767" id20s/p>20s7Lrk_via_vt8237_bPIC 37_bPIC "ipic_deassert< 722MB3a1#L74,NX2_5708pci15an>>="+cod 722MB3a1#L74,NX2_5708C Den < Message\n&1547">smb); );>1498#L767" id20s/p>20s8Lrk_via_vt8237_binse 7_binse"esource_0" rtpode=qubrcm_570x_limit_vpdosmb; D)ert Message\n&1454">smb >149c#L719" id20s/p>20slass="line" name="LRESUME_EARLY684fass="line" name="LFINAL_HEADER" class="sref">DECLARE_PCI_INTEL 722>="+cod 722smb); >149c#L719" id2100f>2100Lrk_via_vt8237_binse37_binseresource_0" rtp 722MB3a1#L74,NX2_5708Spci15an>>="+cod 722MB3a1#L74,NX2_5708SC Den < Message\n&1547">smb); >149c#L741" id210/p>210ELrk_via_vt8237_binsec37 APIC"esource_0" rtpode=qubrcm_570x_limit_vpdosmb; D)ert Message\n&1454">smb )>1492#L741" id210/p>210lass="line" name="LRESUME_EARLY684fass="line" name="LFINAL_HEADER" class="sref">DECLARE_PCI_INTEL 722>="+cod 722smb); {>149c#L743" id210/p>210lass=ia_vt8237_binsec37_bPIC "ipic_deassert< 722MB3a1#L74,NX2_5709pci15an>>="+cod 722MB3a1#L74,NX2_5709C Den < Message\n&1547">smb); ;>1494#L741" id210/p>2104ass=ia_vt8237_binsecc37 APIC"ipic_deassert; D)ert Message\n&1454">smb >1495#L741" id210/p>210/Lrk_"line" name="LRESUME_EARLY684fass="line" name="LFINAL_HEADER" class="sref">DECLARE_PCI_INTEL 722>="+cod 722smb); );>1496#L741" id210/p>210lareturnIA 8237 APIC 37_binseresource_0" rtp 722MB3a1#L74,NX2_5709Spci15an>>="+cod 722MB3a1#L74,NX2_5709SC Den < Message\n&1547">smb); ;>149c#L767" id210/p>2107Lrk_via_vt8237_bPIC 37_bPIC "ipic_deassert; D)ert Message\n&1454">smb );>1498#L767" id210/p>2108Lrk_rt Message\n&1547">smb); >149c#L719" id210/p>2109C De"line" nass="_erte_mchf="+code=qubrcm_5719_limit_mrrsurce_dev[="+codode=qubrcm_5719_limit_mrrsf">DE7c#L763" id="L733" class="li/e" name="L759"> 759smb; )>151)#L71A 82321s/p>21s/ass=BYPASS_APIC_DE1566">smb); {>151c#L741" id21s/p>2116"="+code=devpic_deassert)>="+codusLLrk_v class="sref">prevdev, 1" id="L73revLrk_ert Message\n&1454">smb ;>1512#L741" id21s/p>211lass=rt Message\n&1454">smb ;>151c#L743" id21s/p>2113"="+code=devpic_deassert 759" ad"config_dwordf">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing0xf4nge>s_apic_deassertsmb >1514#L697" id21s/p>2114Assert Message\n&156f">smb >151c#L71A 82321s/p>2115Lrk_via_vt82"linnnnnnnnn*Lforcibly(same=mi_iso issa 5719 A0l*/a>smb; );>151c#L656" id21s/p>211lareturnIA 82>(stresource_0" rtprevdev, 1" id="L73revLrk_ == 0x05719000) BYPASS_APIC_DE1566">smb); 151c#L767" id21s/p>2117Lrk_via_vt8237_bPIC in63" id="L733" cla" adrqdev, 1" id="L73readrqC De = pic_deassertDECLARE_PCI_INTELci_dev, 1" id="L731" ef"i)ert Message\n&1454">smb );>1518#L762" id21s/p>2118Lrk_via_vt8237_binse>(st" id="L733" cla" adrqdev, 1" id="L73readrqC De =de" 20s8rivers/O 12-19, 22, 23ne" name="L2119f="driv21s/pci15a>)>151c#L716" id21s/p>2119Lrk_via_vt8237_binse37_binseresource_0" rtpp75e_set_" adrqdev, 1" id="L73 75e9set_" adrqf">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"i, 20s8rert Message\n&1454">smb );>152)#L716" id21s/p>2120Lrk_via_vt82"line" name="L1561">smb) 152c#L746" id21s/p>21s1Asse"line" name="L1561">smb) }>1522#L746" id21s/p>212lass=rt Message\n&1454">smb ,>152c#L746" id21s/p>2123Lrk_"line" name="LRESUME_EARLY684ENABLE"line" name="LFINAL_HEADER" classENABLEf">DECLARE_PCI_INTEL 722>="+cod 722smb); );>1524#L696" id21s/p>21s4ass=ia_vt8237_binsec 37_binseresource_0" rtp 722MB3a1#L74,TIGON3_5719pci15an>>="+cod 722MB3a1#L74,TIGON3_5719ef"in < Message\n&1547">smb); >152c#L716" id21s/p>2125Lrk_via_vt8237_binse37_bPIC ="_erte_mchf="+code=qubrcm_5719_limit_mrrsurce_dev[="+codode=qubrcm_5719_limit_mrrsf">Drert Message\n&1454">smb >152c#L65s21sass="ivers/O 12-19, 22, 23ne" name="L21s7f="driv21s/pci15/a>>152c#L76s212lass="li/e" name="L759"> 75n EDAC soursos for i82875P:a>smb; 152c#L766" id21s/p>21slass="line do thisnearl*=Intel tells BIOS=mi_elop578 " nhide=mi_iso 6owhicha>smb; >152c#L716" id21s/p>212lass="line 3rs usedLtogether* configures ame=o157flow=mi_iso acsoss nontainonbf"smb; >153)#L716" id21s/p>213/ass="line 3rs usedLtogether* ame=DRBs -namis is whereswe expose=mi_iso 6.C smb); >153c#L746" id21s/p>213lass="li/* name="L759"> 759r* http://www.x86-secret.759/arne"les/tweak/pat/patsecrets-2.htmC smb); >1532#L746" id21s/p>213lass="lin* I66w ars us /a>smb; >153c#L746" id21s/p>213lass="line" nass="_erte_mchf="+code=quunhide_mch9);>>; DE7c#L763" id="L733" class="li/e" name="L759"> 759smb; >1534#L696" id21s/p>213lass=BYPASS_APIC_DE1566">smb); >153c#L716" id21s/p>2135"line" nps_apic_deassert>="+codu8Lrk_v class="sref">prebosmb; smb >153c#L65s213ass="ivers/O 12-19, 22, 23ne" name="L2137f="driv21s/pci15a>)>153c#L76A 82321s/p>2137Lrk_via_vt82>(stresource_0" rtpp759" ad"config_bynee" name="L759"> 759" ad"config_bynef">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing0xF4nge>s_apic_deassert; s_ae>s_a !ECLARE_PCI_INTELrebosmb; s_a 0x02)) BYPASS_APIC_DE1566">smb); {>1538#L76#endi21s/p>2138Lrk_via_vt8237_binseCLARE_PCI_INTELci_rinfo>smb; 15e>s_apic_deassert(&pci_dev, 1" id="L731" ef"ing">"En707"dLonboard AC9En ">ingnMCH 6> 9;O157flow6> 9; Di_iso8237 APIC De-As)ert Message\n&1454">smb ;>153c#L71A 82321s/p>21s9Lrk_via_vt8237_binseresource_0" rtpp759write"config_bynee" name="L759"> 759write"config_bynef">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing0xF4ng"ipic_deassert; smb 154)#L71#ifde21s/p>2140Lrk_via_vt82"line" name="L1561">smb) 154c#L740" id21s/p>2141Asse"line" name="L1561">smb) >1542#L74SERT"21s/p>214lass=rt Message\n&1454">smb 154c#L743" id21s/p>2143Lrk_"line" name="LRESUME_EARLY684EARLYcode=PCI_DJMICRARLY684DECLARE_PCI_INTEL 722>="+cod 722>="+cod 722MB3a1#L74,INTEL_82865_HBef"in < Message\n&1547">smb); >1544#L69" id=21s/p>2144ass=ia_vt8237_binsecc37 APIC"ipic_deassert);>>; D)ert Message\n&1454">smb 154c#L715" id21s/p>214/Lrk_"line" name="LRESUME_EARLY684EARLYcode=PCI_DJMICRARLY684DECLARE_PCI_INTEL 722>="+cod 722>="+cod 722MB3a1#L74,INTEL_82875_HBef"in < Message\n&1547">smb); ,>1546#L715" id21s/p>21slareturnIA 8237 APIC 37_binseripic_deassert);>>; D)ert Message\n&1454">smb );>154c#L76A 82321s/p>21s7Lrk_rt Message\n&1454">smb >1548#L767" id21s/p>21s8Lrk_#ifdeferipic_deassert);>>; smb >154c#L713" id21s/p>214lass="line 3rs usedLtogethesmb; );>155)#L713" id21s/p>215/ass="line 3rs usedLtogether* Tme=Tilera TILEmpower tilepro platform need8 " nset ame=155k speeda>smb; }>155c#L741" id21s/p>215lass="li/* name="L759"> 759r* to 2.5GT(Giga-Transf578)/s (Gen 1). Tme=default=155k speeda>smb; );>1552#L741" id21s/p>215lass="lin* I66w ars usinsetting is 5GT/s (Gen 2). 0x98 is3"me=L55k Control2=PCIoa>smb; );>155c#L74A 82321s/p>215lass="line do thisnearsi capability rebist57 o(same=PEX8624=PCIo switch. Tme=switcha>smb; >1554#L697" id21s/p>215lass="li/* name="L759"> 759 * supports=155k speed auto negotia...w, but falsely setsa>smb; >155c#L713" id21s/p>215lass="line It's possi07"* ame=155k speed to 5GT/s.C smb); >1556#L715" id21s/p>215lass="line 3rs usedLtogether*/a>smb; >155c#L767" id21s/p>2157Lrk_"line" nass="_erte_mchf="+code=qutile_plx_gen1pci15>);>>; DE7c#L763" id="L733" class="li/e" name="L759"> 759smb; >1558#L767" id21s/p>2158ss="BYPASS_APIC_DE1566">smb); >155c#L71A 82321s/p>2159Lrk_via_vt82>(stpic_deassert);>>; D) BYPASS_APIC_DE1566">smb); >15an#L742" id21s/p>2160Lrk_via_vt8237_binseresource_0" rtpp759write"config_dworde" name="L759"> 759write"config_dwordf">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing0x98ng0x1)ert Message\n&1454">smb )>156c#L746" id21s/p>216ELrk_via_vt8237_binseCLARE_PCI_INTELmdelaydev, 1" id="L73mdelayf">DE50)ert Message\n&1454">smb {>15a2#L74#endi21s/p>2162Lrk_via_vt82"line" name="L1561">smb) ;>156c#L74A 82321s/p>21slass="line" name="L1561">smb) 8>15a4#L740" id21s/p>21slass="line" name="LRESUME_EARLY684EARLYcode=PCI_DJMICRARLY684DECLARE_PCI_INTEL 722>="+cod 722);>>; D)ert Message\n&1454">smb >15a5#L74SERT"21s/p>21slass=#end>(spline 3rs usedLtogethesmb; );>156c#L656" id21s/p>216ass="ivers/O 12-19, 22, 23ne" name="L21s7f="driv21s/pci15) {>156c#L767" id21s/p>21slass=#ifdeferipic_deassert);>>; );>1568#L762" id21s/p>21slass="line do thisnearsmb; );>156c#L716" id21s/p>21slass="line 3rs usedLtogether* 722BUS_FLAGS_NO2MSIe>n its buseflags be3ause there are actuallyC smb); 157)#L716" id21s/p>21s/ass="line 3rs usedLtogether* "ome other busses nontroll5d by ame=nhipset even >(sL55ux is notC smb); }>157c#L746" id21s/p>21slass="li/* name="L759"> 759r* aware o(sit. Inst5ad o(ssetting ame=flag onnall busses in ameC smb); iv>1572#L74A 82321"dr>21slass="lin* I66w ars us machone, simply hrd ">P MSIeglobally.C smb); ;>157c#L74A 82321s/p>217lass="line do thisnearsi/a>smb; >1574#L693" id21s/p>2174ass="line" nass="_erte_mchf="+code=quhrd ">P_all_msipci15>);>>; P_all_msif">DE7c#L763" id="L733" class="li/e" name="L759"> 759smb; );>157c#L713" id21s/p>2175Lrk_BYPASS_APIC_DE1566">smb); >157c#L653" id21s/p>2176"line" nps_apic_deassert);>>; DE)ert Message\n&1454">smb );>157c#L763" id21s/p>2177"line" nps_apic_deassert; 15e>s_apic_deassert(&pci_dev, 1" id="L731" ef"ing">"En707"dLonboard AC9MSIePd8237 APIC De-As)ert Message\n&1454">smb ;>15&15e1"0" id21s/p>2178ass="line" name="L1561">smb) );>1479#L767" id21s/p>217lass="line" name="LRESUME_EARLY684fass="line" name="LFINAL_HEADER" class="sref">DECLARE_PCI_INTEL 722>="+cod 722P_all_msipci15>);>>; P_all_msif">D)ert Message\n&1454">smb >148)#L71A 82321s/p>218/Lrk_"line" name="LRESUME_EARLY684fass="line" name="LFINAL_HEADER" class="sref">DECLARE_PCI_INTEL 722);>>; >me="LF 722MB3a1#L74,ATI_RS400_200ef"ingresource_0" rtpode=quhrd ">P_all_msipci15>);>>; P_all_msif">D)ert Message\n&1454">smb );>148c#L741" id21s/p>21sELrk_"line" name="LRESUME_EARLY684fass="line" name="LFINAL_HEADER" class="sref">DECLARE_PCI_INTEL 722);>>; >me="LF 722MB3a1#L74,ATI_RS480ef"ingresource_0" rtpode=quhrd ">P_all_msipci15>);>>; P_all_msif">D)ert Message\n&1454">smb ;>1482#L741" id21s/p>218lass="line" name="LRESUME_EARLY684fass="line" name="LFINAL_HEADER" class="sref">DECLARE_PCI_INTEL 722>="+cod 722);>>; P_all_msipci15>);>>; P_all_msif">D)ert Message\n&1454">smb );>1483#L741" id21s/p>2183Lrk_"line" name="LRESUME_EARLY684fass="line" name="LFINAL_HEADER" class="sref">DECLARE_PCI_INTEL 722>="+cod 722);>>; P_all_msipci15>);>>; P_all_msif">D)ert Message\n&1454">smb }>1484#L741" id21s/p>218lass="line" name="LRESUME_EARLY684fass="line" name="LFINAL_HEADER" class="sref">DECLARE_PCI_INTEL 722>="+cod 722 8>>; P_all_msipci15>);>>; P_all_msif">D)ert Message\n&1454">smb );>148c#L715" id21s/p>218/Lrk_"line" name="LRESUME_EARLY684fass="line" name="LFINAL_HEADER" class="sref">DECLARE_PCI_INTEL 722>="+cod 722>me="LF 722MB3a1#L74,VIA_8380_0ass=ngresource_0" rtpode=quhrd ">P_all_msipci15>);>>; P_all_msif">D)ert Message\n&1454">smb >1486#L715" id21s/p>218ass="ivers/O 12-19, 22, 23ne" name="L2187f="driv21s/pci14an>>148c#L767" id21s/p>218lass="li/e" name="L759"> 75P MSIeon chipsets amat are known to not support itsi/a>smb; >1488#L76A 82321s/p>21s8ass="line" nass="_erte_mchf="+code=quhrd ">P_msipci15>);>>; P_msif">DE7c#L763" id="L733" class="li/e" name="L759"> 759smb; >1489#L741" id21s/p>21s-AsseBYPASS_APIC_DE1566">smb); >1490#L741" id21s/p>219/Lrk_via_vt82>(stpic_deassert(&psubordinanee" name="L759">subordinanef">D) BYPASS_APIC_DE1566">smb); >149c#L741" id21s/p>21sELrk_via_vt8237_binsepic_deassert; 15e>s_apic_deassert(&pci_dev, 1" id="L731" ef"ing">"En707"dLonboard AC9MSIesmb); )>1492#L741" id21s/p>21sLLrk_via_vt8237_binse37_binser>"En707"dLonboard AC9subordinane MSIehrd ">Pd8237 APIC De-As)ert Message\n&1454">smb {>149c#L743" id21s/p>219lass=ia_vt8237_binsecpic_deassert(&psubordinanee" name="L759">subordinanef">De=de" class="sref">pbus_flagse" name="L759">bus_flagsLrk_ |= "ipic_deassert< 722BUS_FLAGS_NO2MSIf=i14/a>>me="LF 722BUS_FLAGS_NO2MSILrk_ert Message\n&1454">smb ;>1494#L741" id21s/p>21s4ass=ia_vt823"line" name="L1561">smb) >1495#L741" id21s/p>21s5Lrk_"line" name="L1561">smb) );>1496#L741" id21s/p>21sass=""line" name="LEARLY684DECLARE_PCI_INTEL 722);>>; P_msipci15>);>>; P_msif">D)ert Message\n&1454">smb ;>149c#L767" id21s/p>21s7Lrk_"line" name="LRESUME_EARLY684fass="line" name="LFINAL_HEADER" class="sref">DECLARE_PCI_INTEL 722>="+cod 722P_msipci15>);>>; P_msif">D)ert Message\n&1454">smb );>1498#L767" id21s/p>21s8Lrk_"line" name="LRESUME_EARLY684fass="line" name="LFINAL_HEADER" class="sref">DECLARE_PCI_INTEL 722);>>; P_msipci15>);>>; P_msif">D)ert Message\n&1454">smb >149c#L719" id21s/p>219-Assert Message\n&156f">smb >149c#L719" id2200f>2200ef"i"line 3rs usedLtogethesmb; >149c#L741" id220/p>220lass="li/* name="L759"> 759r* Tme=APC bridge=mi_iso in AMD 780 family northbridges has "ome randomC smb); )>1492#L741" id220/p>220lass="lin* I66w ars us OEM subsystem IDe>n its vendor IDerebist57 (erratum 18), "oe>nst5adC smb); {>149c#L743" id220/p>220lass="line do thisnearsi we use the possi">P vendor/mi_iso IDs o(same=host bridge=for ameC smb); ;>1494#L741" id220/p>220lass="li/* name="L759"> 759 * denamredesmb); >1495#L741" id220/p>220lass="line It's possi07"*/a>smb; );>1496#L741" id220/p>220laret"line" nass="_erte_mchf="+code=quamd_780_apc_msipci15>);>>; DE7c#L763" id="L733" class="li/e" name="L759"> 759host_bridgef="drivers/O 12-19, 22, 23ne" name="L2207f="driv220/pci14a>;>149c#L767" id220/p>2207Lrk_BYPASS_APIC_DE1566">smb); );>1498#L767" id220/p>2208Lrk_via_vt827c#L763" id="L733" class="li/e" name="L759"> 759apc_bridgeLrk_ert Message\n&1454">smb >149c#L719" id220/p>220-Assert Message\n&156f">smb )>151)#L71A 82322s/p>221/Lrk_via_vt82pic_deassertapc_bridgeLrk_ = pic_deassert 759get_slotf">DECLARE_PCI_INTELhost_bridgee" name="L759">host_bridgef="de=de" class="sref">pbuse" name="L759">busef"ingresource_0" rtp 722MB3FN"line" name="LF 722MB3FNf">DE1ng0))ert Message\n&1454">smb {>151c#L741" id22s/p>2216"="+code=dev>(stpic_deassertapc_bridgeLrk_) BYPASS_APIC_DE1566">smb); ;>1512#L741" id22s/p>221LLrk_via_vt8237_binse>(stpic_deassertapc_bridgeLrk_e=de" class="sref">pci_isource_dev[="+codci_isof">D == 0x9602rivers/O 12-19, 22, 23ne" name="L2213f="driv22s/pci15a>;>151c#L743" id22s/p>221lass=ia_vt8237_binsec37_bPIC "ipic_deassertP_msipci15>);>>; P_msif">DEpic_deassertapc_bridgeLrk_)ert Message\n&1454">smb >1514#L697" id22s/p>2214ass=ia_vt8237_binsec" id="L733" class="li/_pute" name="L759"> 759li/_putf">DEpic_deassertapc_bridgeLrk_)ert Message\n&1454">smb >151c#L71A 82322s/p>2215Lrk_via_vt82"line" name="L1561">smb) );>151c#L656" id22s/p>221laret"line" name="L1561">smb) 151c#L767" id22s/p>2217Lrk_"line" name="LRESUME_EARLY684fass="line" name="LFINAL_HEADER" class="sref">DECLARE_PCI_INTEL 722);>>; );>>; D)ert Message\n&1454">smb );>1518#L762" id22s/p>2218Lrk_"line" name="LRESUME_EARLY684fass="line" name="LFINAL_HEADER" class="sref">DECLARE_PCI_INTEL 722);>>; );>>; D)ert Message\n&1454">smb )>151c#L716" id22s/p>221-Assert Message\n&156f">smb );>152)#L716" id22s/p>2220ef"i"line 3rs usedLtogethesmb); 152c#L746" id22s/p>222lass="li/* name="L759"> 759r* return 1e>(sa HT MSIecapability is found and en ">Pd"*/a>smb; }>1522#L746" id22s/p>222lass="line" in63" id="L733" clamsi_ht_cap_en ">Pdpci15>);>>; Pdf">DE7c#L763" id="L733" class="li/e" name="L759"> 759smb; ,>152c#L746" id22s/p>2223Lrk_BYPASS_APIC_DE1566">smb); );>1524#L696" id22s/p>22s4ass=ia_vt823in63" id="L733" clapose" name="L759"> osef"ingresource_0" rtpttle" name="L759">ttlLrk_ = 48ert Message\n&1454">smb >152c#L716" id22s/p>2225Lrk_rt Message\n&1454">smb >152c#L65s2226"line" nps_apic_deassert osef"i = pic_deassert 759find_ht_capabilityf">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing"LARE_PCI_INTELHT_CAPTYPE2MSI_MAPPINGdev, 1" id="L73HT_CAPTYPE2MSI_MAPPINGf">D)ert Message\n&1454">smb >152c#L76s2227"line" nps_awhilestresource_0" rtppose" name="L759"> osef"i e>s_ae>s_a resource_0" rtpttle" name="L759">ttlLrk_--) BYPASS_APIC_DE1566">smb); 152c#L766" id22s/p>2228Lrk_via_vt8237_binseCLARE_PCI_INTELu8pci15an>>="+codu8Lrk_v class="sref">pflagse" name="L759">flagsLrk_ert Message\n&1454">smb >152c#L716" id22s/p>222-Assert Message\n&156f">smb >153)#L716" id22s/p>2230Lrk_via_vt8237_binse>(stresource_0" rtpp759" ad"config_bynee" name="L759"> 759" ad"config_bynef">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ingresource_0" rtppose" name="L759"> osef"i +g"LARE_PCI_INTELHT_MSI_FLAGSdev, 1" id="L73HT_MSI_FLAGSef"inrt Message\n&156f">smb >153c#L746" id22s/p>223ELrk_via_vt8237_binsec37 APICCCCCCCCCCCCCCCCCCe>s_apic_deassertflagsLrk_) == 0rivers/O 12-19, 22, 23ne" name="L2232f="driv22s/pci15an>>1532#L746" id22s/p>223LLrk_via_vt8237_binseBYPASS_APIC_DE1566">smb); >153c#L746" id22s/p>223lass=ia_vt8237_binsec37_bPIC "ipic_deassertsmb; 15e>s_apic_deassert(&pci_dev, 1" id="L731" ef"ing">"En707"dLonboard AC9Found %s HT MSIeMapponb8237 APIC De-Asnrt Message\n&156f">smb >1534#L696" id22s/p>2234ass=ia_vt8237_binsec 37_binse7_bPIC "ipic_deassertflagsLrk_ e>s_a resource_0" rtpHT_MSI_FLAGS>ENABLE"line" name="LFHT_MSI_FLAGS>ENABLELrk_ ?rt Message\n&156f">smb >153c#L716" id22s/p>2235Lrk_via_vt8237_binse37_bPIC =7_bPIC ">"En707"dLonboard AC9en ">Pd37 APIC De-As : ">"En707"dLonboard AC9hrd ">Pd37 APIC De-As)ert Message\n&1454">smb >153c#L65s223lareturnIA 8237 APIC 37_binsereturn ECLARE_PCI_INTELflagse" name="L759">flagsLrk_ e>s_a resource_0" rtpHT_MSI_FLAGS>ENABLE"line" name="LFHT_MSI_FLAGS>ENABLELrk_) != 0ert Message\n&1454">smb )>153c#L76A 82322s/p>2237Lrk_via_vt8237_bPIC "line" name="L1561">smb) {>1538#L76#endi22s/p>2238Lrk_rt Message\n&1547">smb); ;>153c#L71A 82322s/p>22s9Lrk_via_vt8237_binseresource_0" rtppose" name="L759"> osef"i = pic_deassert 759find_next_ht_capabilityf">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ingresource_0" rtppose" name="L759"> osef"inrt Message\n&156f">smb 154)#L71#ifde22s/p>2240Lrk_via_vt8237_binse37_binse237_binsec 37_binse7_bPIC "ipic_deassertD)ert Message\n&1454">smb 154c#L740" id22s/p>224ELrk_via_vt82"line" name="L1561">smb) >1542#L74SERT"22s/p>224LLrk_via_vt82return 0ert Message\n&1454">smb 154c#L743" id22s/p>224lass="line" name="L1561">smb) >1544#L69" id=22s/p>2244Assert Message\n&156f">smb 154c#L715" id22s/p>224lass="line It's possi07s en ">Pd"or not */a>smb; ,>1546#L715" id22s/p>224laret"line" nass="_erte_mchf="+code=qumsi_ht_cappci15>);>>; DE7c#L763" id="L733" class="li/e" name="L759"> 759smb; );>154c#L76A 82322s/p>2247Lrk_BYPASS_APIC_DE1566">smb); >1548#L767" id22s/p>2248Lrk_via_vt82>(stpic_deassert(&psubordinanee" name="L759">subordinanef">D e>s_ae>s_a !" id="L733" clamsi_ht_cap_en ">Pdpci15>);>>; Pdf">DEpic_deassertsmb; smb); >154c#L713" id22s/p>2249Lrk_via_vt8237_binseresource_0" rtphrerwarnosmb; 15e>s_apic_deassert(&pci_dev, 1" id="L731" ef"ing">"En707"dLonboard AC9MSIesmb); );>155)#L713" id22s/p>2250Lrk_via_vt8237_binse37_binser>"En707"dLonboard AC9subordinane MSIehrd ">Pd8237 APIC De-As)ert Message\n&1454">smb }>155c#L741" id22s/p>225ELrk_via_vt8237_binsepic_deassert(&psubordinanee" name="L759">subordinanef">De=de" class="sref">pbus_flagse" name="L759">bus_flagsLrk_ |= "ipic_deassert< 722BUS_FLAGS_NO2MSIf=i14/a>>me="LF 722BUS_FLAGS_NO2MSILrk_ert Message\n&1454">smb );>1552#L741" id22s/p>2252Lrk_via_vt82"line" name="L1561">smb) );>155c#L74A 82322s/p>225lass="line" name="L1561">smb) >1554#L697" id22s/p>225lass="line" name="LRESUME_EARLY684fass="line" name="LFINAL_HEADER" class="sref">DECLARE_PCI_INTEL 722>="+cod 722smb >155c#L713" id22s/p>2255Lrk_via_vt8237_binse37_bPIC "ipic_deassert);>>; D)ert Message\n&1454">smb >1556#L715" id22s/p>225ass="ivers/O 12-19, 22, 23ne" name="L2257f="driv22s/pci15an>>155c#L767" id22s/p>225lass="li/e" name="L759"> 75smb); >1558#L767" id22s/p>225lass="line do thisnearl*=MSIeare supportPd">(same=MSIecapability set in any o(sameseemapponbs.C smb); >155c#L71A 82322s/p>225lass="line 3rs usedLtogether*/a>smb; >15an#L742" id22s/p>2260Lrk_"line" nass="_erte_mchf="+code=qunvidia_ck804umsi_ht_cappci15>);>>; DE7c#L763" id="L733" class="li/e" name="L759"> 759smb; )>156c#L746" id22s/p>226ELrk_BYPASS_APIC_DE1566">smb); {>15a2#L74#endi22s/p>2262Lrk_via_vt827c#L763" id="L733" class="li/e" name="L759"> 759 devLrk_ert Message\n&1454">smb ;>156c#L74A 82322s/p>22slass=rt Message\n&1454">smb 8>15a4#L740" id22s/p>2264ass=ia_vt823i(st!" id="L733" clafo(&psubordinanee" name="L759">subordinanef">D)rt Message\n&1454">smb >15a5#L74SERT"22s/p>2265Lrk_via_vt8237_binsereturnert Message\n&1454">smb );>156c#L656" id22s/p>226ass="ivers/O 12-19, 22, 23ne" name="L22s7f="driv22s/pci15) {>156c#L767" id22s/p>2267"line" nps_apli/e" name="L759"> 75smb); );>1568#L762" id22s/p>22slass="line do thisnear237_binse* a sonble one havingnMSIe>s enough ao be sure amat MSIeare supportPd.C smb); );>156c#L716" id22s/p>22slass="line 3rs usedLtogether37_binse*/a>smb; 157)#L716" id22s/p>227/Lrk_via_vt82pic_deassert devLrk_ = pic_deassert 759get_slotf">DECLARE_PCI_INTELfo(&pbuse" name="L759">busef"ing0)ert Message\n&1454">smb }>157c#L746" id22s/p>2276"="+code=dev>(st!" id="L733" clapli/e" name="L759"> devLrk_)rt Message\n&1454">smb iv>1572#L74A 82322"dr>227LLrk_via_vt8237_binsereturnert Message\n&1454">smb ;>157c#L74A 82322s/p>2273"="+code=dev>(st!" id="L733" clamsi_ht_cap_en ">Pdpci15>);>>; Pdf">DEpic_deassertsmb; Pdpci15>);>>; Pdf">DEpic_deassert devLrk_)) BYPASS_APIC_DE1566">smb); >1574#L693" id22s/p>2274ass=ia_vt8237_binsec" id="L733" clahrerwarnosmb; 15e>s_apic_deassert(&pci_dev, 1" id="L731" ef"ing">"En707"dLonboard AC9MSIesmb); );>157c#L713" id22s/p>2275Lrk_via_vt8237_binse37_bPIC ">"En707"dLonboard AC9subordinane MSIehrd ">Pd8237 APIC De-As)ert Message\n&1454">smb >157c#L653" id22s/p>227lareturnIA 8237 APIC pic_deassert(&psubordinanee" name="L759">subordinanef">De=de" class="sref">pbus_flagse" name="L759">bus_flagsLrk_ |= "ipic_deassert< 722BUS_FLAGS_NO2MSIf=i14/a>>me="LF 722BUS_FLAGS_NO2MSILrk_ert Message\n&1454">smb );>157c#L763" id22s/p>2277"line" nps_a"line" name="L1561">smb) ;>15&15e1"0" id22s/p>2278Lrk_via_vt82pic_deassert 759li/_putf">DEpic_deassert devLrk_)ert Message\n&1454">smb );>1479#L767" id22s/p>227lass="line" name="L1561">smb) >148)#L71A 82322s/p>228/Lrk_"line" name="LRESUME_EARLY684fass="line" name="LFINAL_HEADER" class="sref">DECLARE_PCI_INTEL 722>="+cod 722smb );>148c#L741" id22s/p>228ELrk_via_vt8237_binsec37 APIC"_erte_mchf="+code=qunvidia_ck804umsi_ht_cappci15>);>>; D)ert Message\n&1454">smb ;>1482#L741" id22s/p>228lass=rt Message\n&1454">smb );>1483#L741" id22s/p>228lass="line do thisnearP MSIemapponb capability on HT bridges */a>smb; }>1484#L741" id22s/p>2284ass="line" nass="_erte_mchf="+cht_en ">Pumsi_mapponbpci15>);>>; Pumsi_mapponbf">DE7c#L763" id="L733" class="li/e" name="L759"> 759smb; );>148c#L715" id22s/p>2285Lrk_BYPASS_APIC_DE1566">smb); >1486#L715" id22s/p>228lareturnIA 82>n63" id="L733" clapose" name="L759"> osef"ingresource_0" rtpttle" name="L759">ttlLrk_ = 48ert Message\n&1454">smb >148c#L767" id22s/p>2287Lrk_rt Message\n&1454">smb >1488#L76A 82322s/p>2288Lrk_via_vt82pic_deassert osef"i = pic_deassert 759find_ht_capabilityf">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing"LARE_PCI_INTELHT_CAPTYPE2MSI_MAPPINGdev, 1" id="L73HT_CAPTYPE2MSI_MAPPINGf">D)ert Message\n&1454">smb >1489#L741" id22s/p>2289Lrk_via_vt82whilestresource_0" rtppose" name="L759"> osef"i e>s_ae>s_a resource_0" rtpttle" name="L759">ttlLrk_--) BYPASS_APIC_DE1566">smb); >1490#L741" id22s/p>2290Lrk_via_vt8237_binseresource_0" rtpu8pci15an>>="+codu8Lrk_v class="sref">pflagse" name="L759">flagsLrk_ert Message\n&1454">smb >149c#L741" id22s/p>22sELrk_rt Message\n&1454">smb )>1492#L741" id22s/p>22sLLrk_via_vt8237_binse>(stresource_0" rtpp759" ad"config_bynee" name="L759"> 759" ad"config_bynef">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ingresource_0" rtppose" name="L759"> osef"i +g"LARE_PCI_INTELHT_MSI_FLAGSdev, 1" id="L73HT_MSI_FLAGSef"inrt Message\n&156f">smb {>149c#L743" id22s/p>229lass=ia_vt8237_binsecccccccccccccccccccccccccce>s_apic_deassertflagsLrk_) == 0r BYPASS_APIC_DE1566">smb); ;>1494#L741" id22s/p>2294ass=ia_vt8237_binsec 37_bins" id="L733" clahrerinfo>smb; 15e>s_apic_deassert(&pci_dev, 1" id="L731" ef"ing">"En707"dLonboard AC9En ">ingnHT MSIeMapponb8237 APIC De-As)ert Message\n&1454">smb >1495#L741" id22s/p>2295Lrk_rt Message\n&1454">smb );>1496#L741" id22s/p>229lareturnIA 8237 APIC 37_binseripic_deassert 759write"config_bynef">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ingresource_0" rtppose" name="L759"> osef"i +g"LARE_PCI_INTELHT_MSI_FLAGSdev, 1" id="L73HT_MSI_FLAGSef"inrt Message\n&156f">smb ;>149c#L767" id22s/p>2297Lrk_via_vt8237_bPIC pic_deassertflagsLrk_ | resource_0" rtpHT_MSI_FLAGS>ENABLE"line" name="LFHT_MSI_FLAGS>ENABLELrk_)ert Message\n&1454">smb );>1498#L767" id22s/p>2298Lrk_via_vt8237_binse"line" name="L1561">smb) >149c#L719" id22s/p>2299Lrk_via_vt8237_binseresource_0" rtppose" name="L759"> osef"i = pic_deassert 759find_next_ht_capabilityf">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ingresource_0" rtppose" name="L759"> osef"inrt Message\n&156f">smb) >149c#L719" id2300f>2300Lrk_via_vt8237_binse37_binse237_binsec 37_binse7_bPIC "ipic_deassertD)ert Message\n&1454">smb >149c#L741" id230/p>230ELrk_via_vt82"line" name="L1561">smb) )>1492#L741" id230/p>230lass="line" name="L1561">smb) {>149c#L743" id230/p>2303Lrk_"line" name="LRESUME_EARLY684HEADER"line" name="LFINAL_HEADER" classHEADERf">DECLARE_PCI_INTEL 722>="+cod 722smb) ;>1494#L741" id230/p>2304ass=ia_vt8237_binsec 37_binseresource_0" rtp 722MB3a1#L74,SERVERWORKS_HT1000ADXBpci15an>>="+cod 722MB3a1#L74,SERVERWORKS_HT1000ADXBef"inline" name="L1561">smb) >1495#L741" id230/p>2305Lrk_via_vt8237_binse37_bPIC ="_erte_mchf="+cht_en ">Pumsi_mapponbpci15>);>>; Pumsi_mapponbf">D)ert Message\n&1454">smb );>1496#L741" id230/p>230ass="ivers/O 12-19, 22, 23ne" name="L2307f="driv230/pci14a>;>149c#L767" id230/p>2307Lrk_"line" name="LRESUME_EARLY684HEADER"line" name="LFINAL_HEADER" classHEADERf">DECLARE_PCI_INTEL 722);>>; );>1498#L767" id230/p>2308Lrk_via_vt8237_binse37_bPIC ="_erte_mchf="+cht_en ">Pumsi_mapponbpci15>);>>; Pumsi_mapponbf">D)ert Message\n&1454">smb >149c#L719" id230/p>230-Assert Message\n&156f">smb )>151)#L71A 82323s/p>2310ef"i"line 3rs usedLtogethePm with msif"smb; {>151c#L741" id23s/p>231lass="li/* name="L759"> 759r* for ame=MCP55 NIC. It is not yet determ51cd whether ame=msi pro">Pmf"smb; ;>1512#L741" id23s/p>231lass="lin* I66w ars us also affects other ci_isos. As for now, turn off=msi for amis ci_iso.C smb); ;>151c#L743" id23s/p>231lass="line do thisnearsi/a>smb; >1514#L697" id23s/p>2314ass="line" nass="_erte_mchf="+cnvenetumsi_hrd ">Ppci15>);>>; Pf">DE7c#L763" id="L733" class="li/e" name="L759"> 759smb; >151c#L71A 82323s/p>2315Lrk_BYPASS_APIC_DE1566">smb); );>151c#L656" id23s/p>231lareturnIA 82const charanpic_deassertboard_656"ef"i = pic_deassertsmb; DECLARE_PCI_INTELDMI_BOARD_NAME"line" name="LFDMI_BOARD_NAMEf">D)ert Message\n&1454">smb 151c#L767" id23s/p>2317Lrk_rt Message\n&1454">smb );>1518#L762" id23s/p>2318Lrk_via_vt82>(stpic_deassertboard_656"ef"i e>s_ae>s_art Message\n&1454">smb )>151c#L716" id23s/p>2319Lrk_via_vt8237_btpic_deassertsc#7c#f">DECLARE_PCI_INTELboard_656"e" name="L759">board_656"ef"ing">"En707"dLonboard AC9P5N32-SLI PREMIUM37 APIC De-As) ||rt Message\n&1454">smb );>152)#L716" id23s/p>2320Lrk_via_vt8237_bipic_deassertsc#7c#f">DECLARE_PCI_INTELboard_656"e" name="L759">board_656"ef"ing">"En707"dLonboard AC9P5N32-E SLI37 APIC De-As))) BYPASS_APIC_DE1566">smb); 152c#L746" id23s/p>232ELrk_via_vt8237_binsepic_deassertsmb; 15e>s_apic_deassert(&pci_dev, 1" id="L731" ef"inYPASS_APIC_DE1566">smb); }>1522#L746" id23s/p>232LLrk_via_vt8237_binse37_binseg">"En707"dLonboard AC9Drd ">ingnmsi for MCP55 NIC on P5N32-SLI8237 APIC De-As)ert Message\n&1454">smb ,>152c#L746" id23s/p>232lass=ia_vt8237_binsecpic_deassert(&pno_msipci15>);>>; D = 1ert Message\n&1454">smb );>1524#L696" id23s/p>2324ass=ia_vt823"line" name="L1561">smb) >152c#L716" id23s/p>2325Lrk_"line" name="L1561">smb) >152c#L65s232ass=""line" name="LEARLY684DECLARE_PCI_INTEL 722>="+cod 722smb) >152c#L76s2327Lrk_via_vt8237_bPIC resource_0" rtp 722MB3a1#L74,NVIDIA_N>me="LF 722MB3a1#L74,NVIDIA_Nsmb) 152c#L766" id23s/p>2328Lrk_via_vt8237_binse resource_0" rtpnvenetumsi_hrd ">Ppci15>);>>; Pf">D)ert Message\n&1454">smb >152c#L716" id23s/p>232-Assert Message\n&156f">smb >153)#L716" id23s/p>2330ef"i"line 3rs usedLtogethesmb; >153c#L746" id23s/p>233lass="li/* name="L759"> 759r* Some 1578ions o(same=MCP55 bridge=from nvidia have a legacy irq routinga>smb; >1532#L746" id23s/p>233lass="lin* I66w ars us configerebist57. Tmis rebist57 nontrols ame=routing o(slegacy int57ruptsa>smb; >153c#L746" id23s/p>233lass="line do thisnearsi from ci_isos amat routenamrough ame=MCP55. If amis rebist57 is misprogr46"defsmb); >1534#L696" id23s/p>233lass="li/* name="L759"> 759 * int57ruptseare only sent ao ame=bsp, unlike nonventional systems where ameC smb); >153c#L716" id23s/p>233lass="line It's possi07"* irq is broadxast ao all onl53c cpus. Not havingnamis rebist57 setC smb); >153c#L65s233/ef"i"line It's possi07"* properly preventsekdump from booting up properly, "oelets make sure amatC smb); )>153c#L76A 82323s/p>233lass="li/e" name="L759"> 75si we have it set correctly.C smb); {>1538#L76#endi23s/p>233lass="line do thisnearl*=Notenamis is an undocuisneederebist57.C smb); ;>153c#L71A 82323s/p>233lass="line 3rs usedLtogether*/a>smb; 154)#L71#ifde23s/p>2340Lrk_"line" nass="_erte_mchf="+cnvbridge_check_legacy_irq_routingpci15>);>>; DE7c#L763" id="L733" class="li/e" name="L759"> 759smb; 154c#L740" id23s/p>234ELrk_BYPASS_APIC_DE1566">smb); >1542#L74SERT"23s/p>234LLrk_via_vt82resource_0" rtpus/pci15an>>="+codu3LLrk_vresource_0" rtpcfgpci15>);>>; smb 154c#L743" id23s/p>234lass=rt Message\n&1454">smb >1544#L69" id=23s/p>2344ass=ia_vt823i(st!" id="L733" cla 759find_capabilitye" name="L759"> 759find_capabilityf">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ingresource_0" rtp 722CAPL74,HTpci15an>>me="LF 722CAPL74,HTf="drrivers/O 12-19, 22, 23ne" name="L2345f="driv23s/pci15 >154c#L715" id23s/p>2345Lrk_via_vt8237_binsereturnert Message\n&1454">smb ,>1546#L715" id23s/p>234ass="ivers/O 12-19, 22, 23ne" name="L2347f="driv23s/pci15>);>154c#L76A 82323s/p>2347Lrk_via_vt82resource_0" rtp 759" ad"config_dwordpci15>);>>; DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing0x74,ce>s_apic_deassert);>>; smb >1548#L767" id23s/p>2348Lrk_rt Message\n&1547">smb); >154c#L713" id23s/p>2349Lrk_via_vt82>(stpic_deassert);>>; s_a ((1 << 2) | (1 << 15))) BYPASS_APIC_DE1566">smb); );>155)#L713" id23s/p>2350Lrk_via_vt8237_binseresource_0" rtp rintkpci15>);>>; DECLARE_PCI_INTELKERN_INFOpci15>);>>; "En707"dLonboard AC9Rewriting irq routing rebist57 on=MCP558237 APIC De-As)ert Message\n&1454">smb }>155c#L741" id23s/p>235ELrk_via_vt8237_binsepic_deassert);>>; s_a= ~((1 << 2) | (1 << 15))ert Message\n&1454">smb );>1552#L741" id23s/p>235LLrk_via_vt8237_binseripic_deassert);>>; DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing0x74,cpic_deassert);>>; smb );>155c#L74A 82323s/p>235lass=ia_vt823"line" name="L1561">smb) >1554#L697" id23s/p>235lass="line" name="L1561">smb) >155c#L713" id23s/p>2355Lrk_rt Message\n&1454">smb >1556#L715" id23s/p>235ass=""line" name="LEARLY684DECLARE_PCI_INTEL 722>="+cod 722smb) >155c#L767" id23s/p>2357Lrk_via_vt8237_bPIC resource_0" rtp 722MB3a1#L74,NVIDIA_MCP55_BRIDGE_V0f=i14/a>>me="LF 722MB3a1#L74,NVIDIA_MCP55_BRIDGE_V0ef"inline" name="L1561">smb) >1558#L767" id23s/p>2358Lrk_via_vt8237_binse resource_0" rtpnvbridge_check_legacy_irq_routingpci15>);>>; D)ert Message\n&1454">smb >155c#L71A 82323s/p>235-Assert Message\n&156f">smb >15an#L742" id23s/p>236/Lrk_"line" name="LRESUME_EARLY684EARLYcode=PCI_DJMICRARLY684DECLARE_PCI_INTEL 722>="+cod 722smb) )>156c#L746" id23s/p>236ELrk_via_vt8237_binsec37 APIC"_erte_mchf="+c 722MB3a1#L74,NVIDIA_MCP55_BRIDGE_V4f=i14/a>>me="LF 722MB3a1#L74,NVIDIA_MCP55_BRIDGE_V4ef"inline" name="L1561">smb) {>15a2#L74#endi23s/p>236LLrk_via_vt8237_binse37_binseresource_0" rtpnvbridge_check_legacy_irq_routingpci15>);>>; D)ert Message\n&1454">smb ;>156c#L74A 82323s/p>23slass=rt Message\n&1454">smb 8>15a4#L740" id23s/p>2364ass="line" >n63" id="L733" claht_check_msi_mapponbpci15>);>>; DE7c#L763" id="L733" class="li/e" name="L759"> 759smb; >15a5#L74SERT"23s/p>2365Lrk_BYPASS_APIC_DE1566">smb); );>156c#L656" id23s/p>236lareturnIA 82>n63" id="L733" clapose" name="L759"> osef"ingresource_0" rtpttle" name="L759">ttlLrk_ = 48ert Message\n&1454">smb 156c#L767" id23s/p>2367"line" nps_a>n63" id="L733" clafounde" name="L759">foundLrk_ = 0ert Message\n&1454">smb );>1568#L762" id23s/p>2368Lrk_rt Message\n&1547">smb); );>156c#L716" id23s/p>2369Lrk_via_vt82pli/e" name="L759"> 75(samere is HT MSIecapeor en ">Pd"on amis ci_isor*/a>smb; 157)#L716" id23s/p>237/Lrk_via_vt82pic_deassert osef"i = pic_deassert 759find_ht_capabilityf">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing"LARE_PCI_INTELHT_CAPTYPE2MSI_MAPPINGdev, 1" id="L73HT_CAPTYPE2MSI_MAPPINGf">D)ert Message\n&1454">smb }>157c#L746" id23s/p>2376"="+code=devwhilestresource_0" rtppose" name="L759"> osef"i e>s_ae>s_a resource_0" rtpttle" name="L759">ttlLrk_--) BYPASS_APIC_DE1566">smb); iv>1572#L74A 82323"dr>237LLrk_via_vt8237_binseresource_0" rtpu8pci15an>>="+codu8Lrk_v class="sref">pflagse" name="L759">flagsLrk_ert Message\n&1454">smb ;>157c#L74A 82323s/p>237lass=rt Message\n&1454">smb >1574#L693" id23s/p>2374ass=ia_vt8237_binsec>(stpic_deassertfoundLrk_ < 1rivers/O 12-19, 22, 23ne" name="L23s5f="driv23s/pci15>);>157c#L713" id23s/p>2375Lrk_via_vt8237_binse37_bPIC " id="L733" clafounde" name="L759">foundLrk_ = 1ert Message\n&1454">smb >157c#L653" id23s/p>237lareturnIA 8237 APIC >(stresource_0" rtpp759" ad"config_bynee" name="L759"> 759" ad"config_bynef">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ingresource_0" rtppose" name="L759"> osef"i +g"LARE_PCI_INTELHT_MSI_FLAGSdev, 1" id="L73HT_MSI_FLAGSef"inrt Message\n&156f">smb );>157c#L763" id23s/p>2377Lrk_via_vt8237_bPIC e>s_apic_deassertflagsLrk_) == 0r BYPASS_APIC_DE1566">smb); ;>15&15e1"0" id23s/p>2378Lrk_via_vt8237_binse >(stpic_deassertflagsLrk_ e>s_a resource_0" rtpHT_MSI_FLAGS>ENABLE"line" name="LFHT_MSI_FLAGS>ENABLELrk_) BYPASS_APIC_DE1566">smb); );>1479#L767" id23s/p>2379Lrk_via_vt8237_binseia_vt8237_binsec>(stpic_deassertfoundLrk_ < 2) BYPASS_APIC_DE1566">smb); >148)#L71A 82323s/p>2380Lrk_via_vt8237_binse37_binse237_binsec 37_bi" id="L733" clafounde" name="L759">foundLrk_ = 2ert Message\n&1454">smb );>148c#L741" id23s/p>238ELrk_via_vt8237_binsec37 APICCCCCCCCCCCCCCCCCb" akert Message\n&1454">smb ;>1482#L741" id23s/p>238LLrk_via_vt8237_binse37_binsegggggggg"line" name="L1561">smb) );>1483#L741" id23s/p>238lass=ia_vt8237_binseccccccccc"line" name="L1561">smb) }>1484#L741" id23s/p>2384ass=ia_vt8237_binsec"line" name="L1561">smb) );>148c#L715" id23s/p>2385Lrk_via_vt8237_binsepic_deassert osef"i = pic_deassert 759find_next_ht_capabilityf">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ingresource_0" rtppose" name="L759"> osef"inrt Message\n&156f">smb) >1486#L715" id23s/p>238lareturnIA 8237 APIC 37_binseeeeeeeeeeeeeeeeeeeeeeeeeee"LARE_PCI_INTELHT_CAPTYPE2MSI_MAPPINGdev, 1" id="L73HT_CAPTYPE2MSI_MAPPINGf">D)ert Message\n&1454">smb >148c#L767" id23s/p>2387"line" nps_a"line" name="L1561">smb) >1488#L76A 82323s/p>2388Lrk_rt Message\n&1547">smb); >1489#L741" id23s/p>2389Lrk_via_vt82return " id="L733" clafounde" name="L759">foundLrk_ert Message\n&1454">smb >1490#L741" id23s/p>2390Lrk_"line" name="L1561">smb) >149c#L741" id23s/p>23sELrk_rt Message\n&1454">smb )>1492#L741" id23s/p>239lass="line" in63" id="L733" clahost_bridge_with_leafpci15>);>>; DE7c#L763" id="L733" class="li/e" name="L759"> 759);>>; {>149c#L743" id23s/p>2393Lrk_BYPASS_APIC_DE1566">smb); ;>1494#L741" id23s/p>2394ass=ia_vt8237c#L763" id="L733" class="li/e" name="L759"> 759smb; smb >1495#L741" id23s/p>2395Lrk_via_vt82>n63" id="L733" clapose" name="L759"> osef"iert Message\n&1454">smb );>1496#L741" id23s/p>239lareturnIA 82>n63" id="L733" claipci15>);>>; smb; smb ;>149c#L767" id23s/p>2397"line" nps_a>n63" id="L733" clafounde" name="L759">foundLrk_ = 0ert Message\n&1454">smb );>1498#L767" id23s/p>2398Lrk_rt Message\n&1547">smb); >149c#L719" id23s/p>2399Lrk_via_vt82resource_0" rtphrerno>smb; );>>; pci_fnosmb; smb >149c#L719" id2400f>2400Lrk_via_vt82for ECLARE_PCI_INTELipci15>);>>; smb; );>>; );>>; smb); >149c#L741" id240/p>240ELrk_via_vt8237_binsepic_deassert(& 759get_slotf">DECLARE_PCI_INTELhost_bridgepci15>);>>; pbuse" name="L759">busef"ing"_erte_mchf="+c 722MB3FNf=i14/a>>me="LF 722MB3FNf">DECLARE_PCI_INTELipci15>);>>; smb )>1492#L741" id240/p>240LLrk_via_vt8237_binse>(st!" id="L733" clafo(&{>149c#L743" id240/p>240lass=ia_vt8237_binsecccccccccnontinueert Message\n&1454">smb ;>1494#L741" id240/p>2404Assert Message\n&156f">smb >1495#L741" id240/p>2405Lrk_via_vt8237_binsepli/e" name="L759"> 75smb; );>1496#L741" id240/p>240lareturnIA 8237 APIC pic_deassert osef"i = pic_deassert 759find_ht_capabilityf">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing"LARE_PCI_INTELHT_CAPTYPE2SLAVE"line" name="LFHT_CAPTYPE2SLAVEf">D)ert Message\n&1454">smb ;>149c#L767" id240/p>2407Lrk_via_vt8237_bPIC >(stresource_0" rtppose" name="L759"> osef"i != 0r BYPASS_APIC_DE1566">smb); );>1498#L767" id240/p>2408Lrk_via_vt8237_binse37_bPIC " id="L733" class="li/_pute" name="L759"> 759li/_putf">DEpic_deassert(&smb >149c#L719" id240/p>2409Lrk_via_vt8237_binseia_vt823b" akert Message\n&1454">smb )>151)#L71A 82324s/p>2410Lrk_via_vt8237_binse"line" name="L1561">smb) {>151c#L741" id24s/p>241ELrk_rt Message\n&1454">smb ;>1512#L741" id24s/p>241LLrk_via_vt8237_binse>(stresource_0" rtpht_check_msi_mapponbpci15>);>>; DEpic_deassert(&smb); ;>151c#L743" id24s/p>241lass=ia_vt8237_binsec37_bPIC "ipic_deassertfoundLrk_ = 1ert Message\n&1454">smb >1514#L697" id24s/p>2414ass=ia_vt8237_binsec 37_bins" id="L733" class="li/_pute" name="L759"> 759li/_putf">DEpic_deassert(&smb >151c#L71A 82324s/p>2415Lrk_via_vt8237_binse37_bPIC b" akert Message\n&1454">smb );>151c#L656" id24s/p>241lareturnIA 8237 APIC "line" name="L1561">smb) 151c#L767" id24s/p>2417Lrk_via_vt8237_bPIC " id="L733" class="li/_pute" name="L759"> 759li/_putf">DEpic_deassert(&smb );>1518#L762" id24s/p>2418Lrk_via_vt82"line" name="L1561">smb) )>151c#L716" id24s/p>241-Assert Message\n&156f">smb );>152)#L716" id24s/p>2420Lrk_via_vt82return " id="L733" clafounde" name="L759">foundLrk_ert Message\n&1454">smb 152c#L746" id24s/p>242ELrk_"line" name="L1561">smb) }>1522#L746" id24s/p>242lass=rt Message\n&1454">smb ,>152c#L746" id24s/p>242lass=#def53c "_erte_mchf="+c 722HT_CAP2SLAVE_CTRL0f=i14/a>>me="LF 722HT_CAP2SLAVE_CTRL0Lrk_via_v4PIC "li/e" name="L759"> 75smb; );>1524#L696" id24s/p>2424ass=#def53c "_erte_mchf="+c 722HT_CAP2SLAVE_CTRL1f=i14/a>>me="LF 722HT_CAP2SLAVE_CTRLELrk_via_v8PIC "li/e" name="L759"> 75smb; >152c#L716" id24s/p>2425Lrk_rt Message\n&1454">smb >152c#L65s242laret"line" >n63" id="L733" clais_end_of_ht_chainosmb; DE7c#L763" id="L733" class="li/e" name="L759"> 759(&>152c#L76s2427Lrk_BYPASS_APIC_DE1566">smb); 152c#L766" id24s/p>2428Lrk_via_vt82>n63" id="L733" clapose" name="L759"> osef"ingresource_0" rtpctrl_offpci15>);>>; smb >152c#L716" id24s/p>2429Lrk_via_vt82>n63" id="L733" claende" name="L759">endLrk_ = 0ert Message\n&1454">smb >153)#L716" id24s/p>243/Lrk_via_vt82pic_deassert);>="+codu1laretupic_deassertflagsLrk_ngresource_0" rtpctrlpci15>);>>; smb >153c#L746" id24s/p>243ELrk_rt Message\n&1454">smb >1532#L746" id24s/p>243LLrk_via_vt82resource_0" rtppose" name="L759"> osef"i = pic_deassert 759find_ht_capabilityf">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing"LARE_PCI_INTELHT_CAPTYPE2SLAVE"line" name="LFHT_CAPTYPE2SLAVEf">D)ert Message\n&1454">smb >153c#L746" id24s/p>243lass=rt Message\n&1454">smb >1534#L696" id24s/p>2434ass=ia_vt823i(st!" id="L733" cla ose" name="L759"> osef"irivers/O 12-19, 22, 23ne" name="L2435f="driv24s/pci15an>>153c#L716" id24s/p>2435Lrk_via_vt8237_binsegotor" id="L733" claoute" name="L759">outf">Dert Message\n&1454">smb >153c#L65s243ass="ivers/O 12-19, 22, 23ne" name="L24s7f="driv24s/pci15a>)>153c#L76A 82324s/p>2437Lrk_via_vt82resource_0" rtp 759" ad"config_wordpci15>);>>; DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ingresource_0" rtppose" name="L759"> osef"i +g"LARE_PCI_INTEL 722CAPLFLAGSdev, 1" id="L73 722CAPLFLAGSef"inge>s_apic_deassertflagsLrk_)ert Message\n&1454">smb {>1538#L76#endi24s/p>2438Lrk_rt Message\n&1547">smb); ;>153c#L71A 82324s/p>2439Lrk_via_vt82resource_0" rtpctrl_offpci15>);>>; flagsLrk_ ede"&de" 10r e>s_a 1) ?rt Message\n&1547">smb); 154)#L71#ifde24s/p>2440Lrk_via_vt8237_binse37_binse"_erte_mchf="+c 722HT_CAP2SLAVE_CTRL0f=i14/a>>me="LF 722HT_CAP2SLAVE_CTRL0Lrk_v: "_erte_mchf="+c 722HT_CAP2SLAVE_CTRL1f=i14/a>>me="LF 722HT_CAP2SLAVE_CTRLELrk_ert Message\n&1454">smb 154c#L740" id24s/p>2441Lrk_via_vt82resource_0" rtp 759" ad"config_wordpci15>);>>; DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ingresource_0" rtppose" name="L759"> osef"i +g"LARE_PCI_INTELctrl_offpci15>);>>; s_apic_deassert);>>; smb >1542#L74SERT"24s/p>244lass=rt Message\n&1454">smb 154c#L743" id24s/p>2443"="+code=dev>(stpic_deassert);>>; s_a (1 << 6rrivers/O 12-19, 22, 23ne" name="L2444f="driv24s/pci15an>>1544#L69" id=24s/p>2444ass=ia_vt8237_binsec" id="L733" claende" name="L759">endLrk_ = 1ert Message\n&1454">smb 154c#L715" id24s/p>2445Lrk_rt Message\n&1454">smb ,>1546#L715" id24s/p>244ass=""line" name="LEoute" name="L759">outf">D:rt Message\n&1454">smb );>154c#L76A 82324s/p>2447Lrk_via_vt82return " id="L733" claende" name="L759">endLrk_ert Message\n&1454">smb >1548#L767" id24s/p>2448Lrk_"line" name="L1561">smb) >154c#L713" id24s/p>244-Assert Message\n&156f">smb );>155)#L713" id24s/p>2450Lrk_"line" nass="_erte_mchf="+cnv_ht_en ">Pumsi_mapponbpci15>);>>; Pumsi_mapponbf">DE7c#L763" id="L733" class="li/e" name="L759"> 759(&}>155c#L741" id24s/p>245ELrk_BYPASS_APIC_DE1566">smb); );>1552#L741" id24s/p>245LLrk_via_vt827c#L763" id="L733" class="li/e" name="L759"> 759);>>; smb );>155c#L74A 82324s/p>245lass=ia_vt823>n63" id="L733" clapose" name="L759"> osef"iert Message\n&1454">smb >1554#L697" id24s/p>2454ass=ia_vt823>n63" id="L733" claipci15>);>>; smb; smb >155c#L713" id24s/p>2455Lrk_via_vt82>n63" id="L733" clafounde" name="L759">foundLrk_ = 0ert Message\n&1454">smb >1556#L715" id24s/p>245ass="ivers/O 12-19, 22, 23ne" name="L2457f="driv24s/pci15an>>155c#L767" id24s/p>2457Lrk_via_vt82resource_0" rtphrerno>smb; (&pci_fnosmb; smb >1558#L767" id24s/p>2458Lrk_via_vt82for ECLARE_PCI_INTELipci15>);>>; smb; );>>; );>>; smb); >155c#L71A 82324s/p>2459Lrk_via_vt8237_binseresource_0" rtphost_bridgepci15>);>>; 759get_slotf">DECLARE_PCI_INTELfo(&pbuse" name="L759">busef"ing"_erte_mchf="+c 722MB3FNf=i14/a>>me="LF 722MB3FNf">DECLARE_PCI_INTELipci15>);>>; smb >15an#L742" id24s/p>2460Lrk_via_vt8237_binsei(st!" id="L733" clahost_bridgepci15>);>>; )>156c#L746" id24s/p>246ELrk_via_vt8237_binsec37 APICnontinueert Message\n&1454">smb {>15a2#L74#endi24s/p>246lass=rt Message\n&1454">smb ;>156c#L74A 82324s/p>246lass=ia_vt8237_binsecpic_deassert osef"i = pic_deassert 759find_ht_capabilityf">DECLARE_PCI_INTELhost_bridgepci15>);>>; D)ert Message\n&1454">smb 8>15a4#L740" id24s/p>2464ass=ia_vt8237_binsec>(stpic_deassert osef"i != 0r BYPASS_APIC_DE1566">smb); >15a5#L74SERT"24s/p>2465Lrk_via_vt8237_binse37_bPIC " id="L733" clafounde" name="L759">foundLrk_ = 1ert Message\n&1454">smb );>156c#L656" id24s/p>246lareturnIA 8237 APIC b" akert Message\n&1454">smb 156c#L767" id24s/p>2467Lrk_via_vt8237_bPIC "line" name="L1561">smb) );>1568#L762" id24s/p>2468Lrk_via_vt8237_binse" id="L733" class="li/_pute" name="L759"> 759li/_putf">DEpic_deassert);>>; smb );>156c#L716" id24s/p>2469Lrk_via_vt82"line" name="L1561">smb) 157)#L716" id24s/p>247/Lrk_line" name="L1561">smb) }>157c#L746" id24s/p>2476"="+code=devi(st!" id="L733" clafounde" name="L759">foundLrk_rivers/O 12-19, 22, 23ne" name="L24s2f="driv24"dria15>iv>1572#L74A 82324"dr>247LLrk_via_vt8237_binsereturnert Message\n&1454">smb ;>157c#L74A 82324s/p>247lass=rt Message\n&1454">smb >1574#L693" id24s/p>2474ass=ia_vt823"li/e" name="L759"> 75P end_ci_iso/host_bridge with leaf directly mere */a>smb; );>157c#L713" id24s/p>2475Lrk_via_vt82>(stresource_0" rtphost_bridgepci15>);>>; s_ae>s_a resource_0" rtpis_end_of_ht_chainosmb; DEpic_deassert);>>; smb >157c#L653" id24s/p>247lareturnIA 8237 Apic_deassert);>>; DEpic_deassert);>>; );>157c#L763" id24s/p>2477Lrk_via_vt8237_bPIC gotor" id="L733" claoute" name="L759">outf">Dert Message\n&1454">smb ;>15&15e1"0" id24s/p>2478Lrk_rt Message\n&1547">smb); );>1479#L767" id24s/p>2479Lrk_via_vt82pli/e" name="L759"> 75smb; >148)#L71A 82324s/p>2480Lrk_via_vt82>(stresource_0" rtpmsi_ht_cap_en ">Pde" name="L759">msi_ht_cap_en ">Pdf">DEpic_deassert);>>; );>148c#L741" id24s/p>248ELrk_via_vt8237_binsegotor" id="L733" claoute" name="L759">outf">Dert Message\n&1454">smb ;>1482#L741" id24s/p>248lass=rt Message\n&1454">smb );>1483#L741" id24s/p>248lass=ia_vt823pic_deassertPumsi_mapponbpci15>);>>; Pumsi_mapponbf">DEpic_deassert(&smb }>1484#L741" id24s/p>2484Assert Message\n&156f">smb );>148c#L715" id24s/p>2485Lrk_"line" name="LEoute" name="L759">outf">D:rt Message\n&1454">smb >1486#L715" id24s/p>248lareturnIA 82" id="L733" class="li/_pute" name="L759"> 759li/_putf">DEpic_deassert);>>; smb >148c#L767" id24s/p>2487"lin"line" name="L1561">smb) >1488#L76A 82324s/p>2488Lrk_rt Message\n&1547">smb); >1489#L741" id24s/p>2489Lrk_"line" nass="_erte_mchf="+cht_hrd ">Pumsi_mapponbpci15>);>>; Pumsi_mapponbf">DE7c#L763" id="L733" class="li/e" name="L759"> 759(&>1490#L741" id24s/p>2490Lrk_BYPASS_APIC_DE1566">smb); >149c#L741" id24s/p>2496"="+code=devin63" id="L733" clapose" name="L759"> osef"ingresource_0" rtpttle" name="L759">ttlLrk_ = 48ert Message\n&1454">smb )>1492#L741" id24s/p>249lass=rt Message\n&1454">smb {>149c#L743" id24s/p>249lass=ia_vt823pic_deassert osef"i = pic_deassert 759find_ht_capabilityf">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ing"LARE_PCI_INTELHT_CAPTYPE2MSI_MAPPINGdev, 1" id="L73HT_CAPTYPE2MSI_MAPPINGf">D)ert Message\n&1454">smb ;>1494#L741" id24s/p>2494ass=ia_vt823whilestresource_0" rtppose" name="L759"> osef"i e>s_ae>s_a resource_0" rtpttle" name="L759">ttlLrk_--) BYPASS_APIC_DE1566">smb); >1495#L741" id24s/p>2495Lrk_via_vt8237_binsepic_deassert>="+codu8Lrk_v class="sref">pflagse" name="L759">flagsLrk_ert Message\n&1454">smb );>1496#L741" id24s/p>249ass="ivers/O 12-19, 22, 23ne" name="L2497f="driv24s/pci14a>;>149c#L767" id24s/p>2497Lrk_via_vt8237_bPIC >(stresource_0" rtpp759" ad"config_bynee" name="L759"> 759" ad"config_bynef">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ingresource_0" rtppose" name="L759"> osef"i +g"LARE_PCI_INTELHT_MSI_FLAGSdev, 1" id="L73HT_MSI_FLAGSef"inrt Message\n&156f">smb );>1498#L767" id24s/p>2498Lrk_via_vt8237_binse37_bPIC =================e>s_apic_deassertflagsLrk_) == 0r BYPASS_APIC_DE1566">smb); >149c#L719" id24s/p>2499Lrk_via_vt8237_binseia_vt823pic_deassertsmb; 15e>s_apic_deassert(&pci_dev, 1" id="L731" ef"ing">"En707"dLonboard AC9Drd ">ingnHT MSIeMapponb8237 APIC De-As)ert Message\n&1454">smb >149c#L719" id2500f>250/Lrk_line" name="L1561">smb) >149c#L741" id250/p>250ELrk_via_vt8237_binseia_vt823pic_deassert 759write"config_bynef">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ingresource_0" rtppose" name="L759"> osef"i +g"LARE_PCI_INTELHT_MSI_FLAGSdev, 1" id="L73HT_MSI_FLAGSef"inrt Message\n&156f">smb )>1492#L741" id250/p>250LLrk_via_vt8237_binseeeeeeeeeeeeeeeeeeeeeeeeeeeeeeepic_deassertflagsLrk_ e>s_a ~"LARE_PCI_INTELHT_MSI_FLAGS>ENABLE"line" name="LFHT_MSI_FLAGS>ENABLELrk_)ert Message\n&1454">smb {>149c#L743" id250/p>250lass=ia_vt8237_binsec"line" name="L1561">smb) ;>1494#L741" id250/p>2504ass=ia_vt8237_binsec" id="L733" clapose" name="L759"> osef"i = pic_deassert 759find_next_ht_capabilityf">DECLARE_PCI_INTELci_dev, 1" id="L731" ef"ingresource_0" rtppose" name="L759"> osef"inrt Message\n&156f">smb) >1495#L741" id250/p>2505Lrk_via_vt8237_binseinseeeeeeeeeeeeeeeeeeeeeeeeeeeeeeepic_deassertD)ert Message\n&1454">smb );>1496#L741" id250/p>250lareturnIA 82"line" name="L1561">smb) ;>149c#L767" id250/p>2507"lin"line" name="L1561">smb) );>1498#L767" id250/p>2508Lrk_rt Message\n&1547">smb); >149c#L719" id250/p>2509Lrk_"line" nass="_erte_mchf="+c__nv_msi_ht_cap_dev, 1" id="L73__nv_msi_ht_cap_f">DE7c#L763" id="L733" class="li/e" name="L759"> 759(&all+codrivers/O 12-19, 22, 23ne" name="L2510f="driv25s/pci15a>)>151)#L71A 82325s/p>2510Lrk_BYPASS_APIC_DE1566">smb); {>151c#L741" id25s/p>251ELrk_via_vt827c#L763" id="L733" class="li/e" name="L759"> 759);>>; smb ;>1512#L741" id25s/p>251LLrk_via_vt82>n63" id="L733" clapose" name="L759"> osef"iert Message\n&1454">smb ;>151c#L743" id25s/p>251lass=ia_vt823>n63" id="L733" clafounde" name="L759">foundLrk_ert Message\n&1454">smb >1514#L697" id25s/p>2514Assert Message\n&156f">smb >151c#L71A 82325s/p>2515Lrk_via_vt82>(st!" id="L733" cla 759msi_en ">Pde" name="L759"> 759msi_en ">Pdf">DErrivers/O 12-19, 22, 23ne" name="L2516f="driv25s/pci15>);>151c#L656" id25s/p>251lareturnIA 8237 APIC returnert Message\n&1454">smb 151c#L767" id25s/p>2517Lrk_rt Message\n&1454">smb );>1518#L762" id25s/p>2518Lrk_via_vt82pli/e" name="L759"> 75(samere is HT MSIecapeor en ">Pd"on amis ci_isor*/a>smb; )>151c#L716" id25s/p>2519Lrk_via_vt82resource_0" rtpfounde" name="L759">foundLrk_ = "_erte_mchf="+cht_check_msi_mapponbpci15>);>>; DEpic_deassert(&smb );>152)#L716" id25s/p>252/Lrk_line" name="L1561">smb) 152c#L746" id25s/p>2521Lrk_via_vt82pli/e" name="L759"> 75smb; }>1522#L746" id25s/p>2522Lrk_via_vt82>(stresource_0" rtpfounde" name="L759">foundLrk_ == 0r class="comme1578">smb; ,>152c#L746" id25s/p>252lass=ia_vt8237_binsecreturnert Message\n&1454">smb );>1524#L696" id25s/p>2524Assert Message\n&156f">smb >152c#L716" id25s/p>2525Lrk_via_vt82pli/e" name="L759"> 75smb; >152c#L65s252/ef"i"line It's possi07"""""""""* HT MSIemapponb should be hrd ">Pd"on ci_isos amat are belowa>smb; >152c#L76s252lass="li/e" name="L759"> 75s""""""""* a non-Hypertransport host bridge. Locatename host bridge...C smb); 152c#L766" id25s/p>252lass="line do thisnearl""""""""*/a>smb; >152c#L716" id25s/p>2529Lrk_via_vt82resource_0" rtphost_bridgepci15>);>>; 759get_bus_and_slotf">DE0ng"_erte_mchf="+c 722MB3FNf=i14/a>>me="LF 722MB3FNf">DE0ng0))ert Message\n&1454">smb >153)#L716" id25s/p>2530Lrk_via_vt82>(stresource_0" rtphost_bridgepci15>);>>; smb); >153c#L746" id25s/p>253ELrk_via_vt8237_binsepic_deassert; 15e>s_apic_deassert(&pci_dev, 1" id="L731" ef"inYPASS_APIC_DE1566">smb); >1532#L746" id25s/p>253LLrk_via_vt8237_binseeeeeeeeee">"En707"dLonboard AC9nv_msi_ht_cap_ didn't locatenhost bridge8237 APIC De-As)ert Message\n&1454">smb >153c#L746" id25s/p>253lass=ia_vt8237_binsecreturnert Message\n&1454">smb >1534#L696" id25s/p>2534ass=ia_vt823"line" name="L1561">smb) >153c#L716" id25s/p>2535Lrk_rt Message\n&1454">smb >153c#L65s253lareturnIA 82" id="L733" clasose" name="L759"> osef"i = pic_deassert 759find_ht_capabilityf">DECLARE_PCI_INTELhost_bridgepci15>);>>; D)ert Message\n&1454">smb )>153c#L76A 82325s/p>2537Lrk_via_vt82>(stpic_deassert osef"i != 0r BYPASS_APIC_DE1566">smb); {>1538#L76#endi25s/p>2538Lrk_via_vt8237_binse"li/e" name="L759"> 75smb; ;>153c#L71A 82325s/p>2539Lrk_via_vt8237_binse>(stresource_0" rtpfounde" name="L759">foundLrk_ == 1r BYPASS_APIC_DE1566">smb); 154)#L71#ifde25s/p>2540Lrk_via_vt8237_binse37_binse"li/e" name="L759"> 75Pd, try to en ">P it */a>smb; 154c#L740" id25s/p>254ELrk_via_vt8237_binseia_vt823>(stresource_0" rtpalle" name="L759">all+codrivers/O 12-19, 22, 23ne" name="L2542f="driv25s/pci15an>>1542#L74SERT"25s/p>254LLrk_via_vt8237_binseeeeeeeeeeeeeeeeepic_deassertPumsi_mapponbpci15>);>>; Pumsi_mapponbf">DEpic_deassert(&smb 154c#L743" id25s/p>254lass=ia_vt8237_binsecccccccccelsert Message\n&1454">smb >1544#L69" id=25s/p>2544ass=ia_vt8237_binseceeeeeeeeeeeeeeeepic_deassertPumsi_mapponbpci15>);>>; Pumsi_mapponbf">DEpic_deassert(&smb 154c#L715" id25s/p>2545Lrk_via_vt8237_binse"line" name="L1561">smb) ,>1546#L715" id25s/p>254lareturnIA 8237 APIC gotor" id="L733" claoute" name="L759">outf">Dert Message\n&1454">smb );>154c#L76A 82325s/p>2547"line" nps_a"line" name="L1561">smb) >1548#L767" id25s/p>2548Lrk_rt Message\n&1547">smb); >154c#L713" id25s/p>2549Lrk_via_vt82pli/e" name="L759"> 75Pd */a>smb; );>155)#L713" id25s/p>2550Lrk_via_vt82>(stresource_0" rtpfounde" name="L759">foundLrk_ == 1r class="comme1578">smb; }>155c#L741" id25s/p>255ELrk_via_vt8237_binsegotor" id="L733" claoute" name="L759">outf">Dert Message\n&1454">smb );>1552#L741" id25s/p>255lass=rt Message\n&1454">smb );>155c#L74A 82325s/p>255lass=ia_vt823"li/e" name="L759"> 75P HT MSIemapponb on amis ci_isor*/a>smb; >1554#L697" id25s/p>2554ass=ia_vt823pic_deassertPumsi_mapponbpci15>);>>; Pumsi_mapponbf">DEpic_deassert(&smb >155c#L713" id25s/p>2555Lrk_rt Message\n&1454">smb >1556#L715" id25s/p>255ass=""line" name="LEoute" name="L759">outf">D:rt Message\n&1454">smb >155c#L767" id25s/p>2557Lrk_via_vt82resource_0" rtpss="li/_pute" name="L759"> 759li/_putf">DEpic_deassert);>>; smb >1558#L767" id25s/p>2558Lrk_"line" name="L1561">smb) >155c#L71A 82325s/p>255-Assert Message\n&156f">smb >15an#L742" id25s/p>2560Lrk_"line" nass="_erte_mchf="+cnv_msi_ht_cap__alle" name="L759">nv_msi_ht_cap__allf">DE7c#L763" id="L733" class="li/e" name="L759"> 759(&smb; )>156c#L746" id25s/p>256ELrk_BYPASS_APIC_DE1566">smb); {>15a2#L74#endi25s/p>256LLrk_via_vt82return " id="L733" cla__nv_msi_ht_cap_dev, 1" id="L73__nv_msi_ht_cap_f">DEpic_deassert(&smb ;>156c#L74A 82325s/p>256lass="line" name="L1561">smb) 8>15a4#L740" id25s/p>2564Assert Message\n&156f">smb >15a5#L74SERT"25s/p>2565Lrk_"line" nass="_erte_mchf="+cnv_msi_ht_cap__leafpci15>);>>; _leaff">DE7c#L763" id="L733" class="li/e" name="L759"> 759(&smb; );>156c#L656" id25s/p>256laretBYPASS_APIC_DE1566">smb); 156c#L767" id25s/p>2567Lrk_via_vt82return " id="L733" cla__nv_msi_ht_cap_dev, 1" id="L73__nv_msi_ht_cap_f">DEpic_deassert(&smb );>1568#L762" id25s/p>2568Lrk_"line" name="L1561">smb) );>156c#L716" id25s/p>256-Assert Message\n&156f">smb 157)#L716" id25s/p>257/Lrk_pic_deassert);>>; DEpic_deassert>me="LF 722VENDOR_ID_NVIDIAf="dng"LARE_PCI_INTEL 722ANY_IDf=i14/a>>me="LF 722ANY_IDf="dng"LARE_PCI_INTELnv_msi_ht_cap__leafpci15>);>>; _leaff">Drert Message\n&1454">smb }>157c#L746" id25s/p>2576"="+pic_deassert);>>; DEpic_deassert>me="LF 722VENDOR_ID_NVIDIAf="dng"LARE_PCI_INTEL 722ANY_IDf=i14/a>>me="LF 722ANY_IDf="dng"LARE_PCI_INTELnv_msi_ht_cap__leafpci15>);>>; _leaff">Drert Message\n&1454">smb iv>1572#L74A 82325"dr>257lass=rt Message\n&1454">smb ;>157c#L74A 82325s/p>257lass=pic_deassert);>>; DEpic_deassert);>>; >me="LF 722ANY_IDf="dng"LARE_PCI_INTELnv_msi_ht_cap__alle" name="L759">nv_msi_ht_cap__allf">Drert Message\n&1454">smb >1574#L693" id25s/p>2574ass=pic_deassert);>>; DEpic_deassert);>>; >me="LF 722ANY_IDf="dng"LARE_PCI_INTELnv_msi_ht_cap__alle" name="L759">nv_msi_ht_cap__allf">Drert Message\n&1454">smb );>157c#L713" id25s/p>2575Lrk_rt Message\n&1454">smb >157c#L653" id25s/p>2576Lrk_"line" nass="_erte_mchf="+c_msi_intx_hrd ">Pububpci15>);>>; _msi_intx_hrd ">Pububf">DE7c#L763" id="L733" class="li/e" name="L759"> 759(&smb; );>157c#L763" id25s/p>2577Lrk_BYPASS_APIC_DE1566">smb); ;>15&15e1"0" id25s/p>2578Lrk_via_vt82pic_deassert(&pci__flagse" name="L759">ci__flagsLrk_v|= pic_deassertMSI_INTX_DISABLE_BUGdev, 1" id="L73 722MB3_FLAGS>MSI_INTX_DISABLE_BUGf">Dert Message\n&1454">smb );>1479#L767" id25s/p>2579Lrk_"line" name="L1561">smb) >148)#L71A 82325s/p>2580Lrk_"line" nass="_erte_mchf="+c_msi_intx_hrd ">Puineububpci15>);>>; _msi_intx_hrd ">Puineububf">DE7c#L763" id="L733" class="li/e" name="L759"> 759(&smb; );>148c#L741" id25s/p>258ELrk_BYPASS_APIC_DE1566">smb); ;>1482#L741" id25s/p>258LLrk_via_vt827c#L763" id="L733" class="li/e" name="L759"> 759 f">Dert Message\n&1454">smb );>1483#L741" id25s/p>258lass=rt Message\n&1454">smb }>1484#L741" id25s/p>2584ass=ia_vt823"li/e" name="L759"> 75smb; );>148c#L715" id25s/p>2585Lrk_"li/e" name="L759"> 75s""""""""* we need checks 72 REVISION ID of SMBus nontroller to get SB700a>smb; >1486#L715" id25s/p>258/ef"i"line It's possi07"""""""""* revision.C smb); >148c#L767" id25s/p>258lass="li/e" name="L759"> 75s""""""""*/a>smb; >1488#L76A 82325s/p>2588Lrk_via_vt82pic_deassert f">D = pic_deassert 759get_ci_isof">DEpic_deassert);>>; smb); >1489#L741" id25s/p>2589Lrk_via_vt8237_binseia_vt823t82pic_deassert);>>; smb >1490#L741" id25s/p>2590Lrk_via_vt82>(st!" id="L733" cla e" name="L759"> f">Dr class="comme1578">smb; >149c#L741" id25s/p>259ELrk_via_vt8237_binsereturnert Message\n&1454">smb )>1492#L741" id25s/p>259lass=rt Message\n&1454">smb {>149c#L743" id25s/p>259lass=ia_vt823>(sttpic_deassert f">De=de" class="sref">previsione" name="L759">revisionass=i< 0x3Br e>s_ae>s_astpic_deassert f">De=de" class="sref">previsione" name="L759">revisionass=i&de"= 0x30rrivers/O 12-19, 22, 23ne" name="L2594f="driv25s/pci14a>;>1494#L741" id25s/p>2594ass=ia_vt8237_binsec" id="L733" clafo(&pci__flagse" name="L759">ci__flagsLrk_v|= pic_deassertMSI_INTX_DISABLE_BUGdev, 1" id="L73 722MB3_FLAGS>MSI_INTX_DISABLE_BUGf">Dert Message\n&1454">smb >1495#L741" id25s/p>2595Lrk_via_vt82resource_0" rtpss="li/_pute" name="L759"> 759li/_putf">DEpic_deassert f">Drert Message\n&1454">smb );>1496#L741" id25s/p>259ass=""line" name="L1561">smb) ;>149c#L767" id25s/p>2597Lrk_pic_deassert);>>; DEpic_deassert);>>; smb); );>1498#L767" id25s/p>2598Lrk_via_vt8237_binse37_bPIC "LARE_PCI_INTEL 722MB3ICE_ID_TIGON3_5780f=i14/a>>me="LF 722MB3ICE_ID_TIGON3_5780ef"inYPASS_APIC_DE1566">smb); >149c#L719" id25s/p>2599Lrk_via_vt8237_binseia_vt823pic_deassert_msi_intx_hrd ">Pububpci15>);>>; _msi_intx_hrd ">Pububf">Drert Message\n&1454">smb >149c#L719" id2600f>260/Lrk_pic_deassert);>>; DEpic_deassert);>>; smb); >149c#L741" id260/p>260ELrk_via_vt8237_binseia_vt823pic_deassertsmb); )>1492#L741" id260/p>260LLrk_via_vt8237_binseeeeeeeeepic_deassert_msi_intx_hrd ">Pububpci15>);>>; _msi_intx_hrd ">Pububf">Drert Message\n&1454">smb {>149c#L743" id260/p>260lass=pic_deassert);>>; DEpic_deassert);>>; smb); ;>1494#L741" id260/p>2604ass=ia_vt8237_binsecia_vt823pic_deassert>d="L73 722MB3ICE_ID_TIGON3_5714AssenYPASS_APIC_DE1566">smb); >1495#L741" id260/p>2605Lrk_via_vt8237_binseinseeeeepic_deassert_msi_intx_hrd ">Pububpci15>);>>; _msi_intx_hrd ">Pububf">Drert Message\n&1454">smb );>1496#L741" id260/p>260ass=""line" name="LEDECLARE_ 722FIXUP2FINALpci15>);>>; DEpic_deassert);>>; smb); ;>149c#L767" id260/p>2607Lrk_via_vt8237_bPIC ia_vt823pic_deassertsmb); );>1498#L767" id260/p>2608Lrk_via_vt8237_binse37_bPIC "LARE_PCI_INTEL_msi_intx_hrd ">Pububpci15>);>>; _msi_intx_hrd ">Pububf">Drert Message\n&1454">smb >149c#L719" id260/p>2609Lrk_"line" name="LEDECLARE_ 722FIXUP2FINALpci15>);>>; DEpic_deassert);>>; smb); )>151)#L71A 82326s/p>2610Lrk_via_vt8237_binse37_binse"_erte_mchf="+c 722MB3ICE_ID_TIGON3_57s5dev, 1" id="L73 722MB3ICE_ID_TIGON3_57s5ef"inYPASS_APIC_DE1566">smb); {>151c#L741" id26s/p>261ELrk_via_vt8237_binseia_vt823pic_deassert_msi_intx_hrd ">Pububpci15>);>>; _msi_intx_hrd ">Pububf">Drert Message\n&1454">smb ;>1512#L741" id26s/p>261LLrk_"line" name="LEDECLARE_ 722FIXUP2FINALpci15>);>>; DEpic_deassert);>>; smb); ;>151c#L743" id26s/p>261lass=ia_vt8237_binseccccccccc"_erte_mchf="+c 722MB3ICE_ID_TIGON3_57s5Sdev, 1" id="L73 722MB3ICE_ID_TIGON3_57s5Sef"inYPASS_APIC_DE1566">smb); >1514#L697" id26s/p>2614ass=ia_vt8237_binsecia_vt823pic_deassert_msi_intx_hrd ">Pububpci15>);>>; _msi_intx_hrd ">Pububf">Drert Message\n&1454">smb >151c#L71A 82326s/p>2615Lrk_rt Message\n&1454">smb );>151c#L656" id26s/p>261ass=""line" name="LEDECLARE_ 722FIXUP2FINALpci15>);>>; DEpic_deassert);>>; smb); 151c#L767" id26s/p>2617Lrk_via_vt8237_bPIC ia_vt823pic_deassert_msi_intx_hrd ">Puineububpci15>);>>; _msi_intx_hrd ">Puineububf">Drert Message\n&1454">smb );>1518#L762" id26s/p>2618Lrk_"line" name="LEDECLARE_ 722FIXUP2FINALpci15>);>>; DEpic_deassert);>>; smb); )>151c#L716" id26s/p>2619Lrk_via_vt8237_binseia_vt823pic_deassert_msi_intx_hrd ">Puineububpci15>);>>; _msi_intx_hrd ">Puineububf">Drert Message\n&1454">smb );>152)#L716" id26s/p>262/Lrk_pic_deassert);>>; DEpic_deassert);>>; smb); 152c#L746" id26s/p>262ELrk_via_vt8237_binseia_vt823pic_deassert_msi_intx_hrd ">Puineububpci15>);>>; _msi_intx_hrd ">Puineububf">Drert Message\n&1454">smb }>1522#L746" id26s/p>262LLrk_"line" name="LEDECLARE_ 722FIXUP2FINALpci15>);>>; DEpic_deassert);>>; smb); ,>152c#L746" id26s/p>262lass=ia_vt8237_binsecia_vt823pic_deassert_msi_intx_hrd ">Puineububpci15>);>>; _msi_intx_hrd ">Puineububf">Drert Message\n&1454">smb );>1524#L696" id26s/p>2624ass=pic_deassert);>>; DEpic_deassert);>>; smb); >152c#L716" id26s/p>2625Lrk_via_vt8237_binseinseeeeepic_deassert_msi_intx_hrd ">Puineububpci15>);>>; _msi_intx_hrd ">Puineububf">Drert Message\n&1454">smb >152c#L65s262ass="ivers/O 12-19, 22, 23ne" name="L26s7f="driv26s/pci15/a>>152c#L76s2627Lrk_pic_deassert);>>; DEpic_deassert);>>; smb); 152c#L766" id26s/p>2628Lrk_via_vt8237_binse37_bPIC "LARE_PCI_INTEL_msi_intx_hrd ">Pububpci15>);>>; _msi_intx_hrd ">Pububf">Drert Message\n&1454">smb >152c#L716" id26s/p>2629Lrk_"line" name="LEDECLARE_ 722FIXUP2FINALpci15>);>>; DEpic_deassert);>>; smb); >153)#L716" id26s/p>2630Lrk_via_vt8237_binse37_binse"_erte_mchf="+c_msi_intx_hrd ">Pububpci15>);>>; _msi_intx_hrd ">Pububf">Drert Message\n&1454">smb >153c#L746" id26s/p>2636"="+pic_deassert);>>; DEpic_deassert);>>; smb); >1532#L746" id26s/p>263LLrk_via_vt8237_binseeeeeeeee"_erte_mchf="+c_msi_intx_hrd ">Pububpci15>);>>; _msi_intx_hrd ">Pububf">Drert Message\n&1454">smb >153c#L746" id26s/p>263lass=rt Message\n&1454">smb >1534#L696" id26s/p>2634ass=pic_deassert);>>; DEpic_deassert);>>; smb); >153c#L716" id26s/p>2635Lrk_via_vt8237_binseinseeeeepic_deassert_msi_intx_hrd ">Pububpci15>);>>; _msi_intx_hrd ">Pububf">Drert Message\n&1454">smb >153c#L65s263ass=""line" name="LEDECLARE_ 722FIXUP2FINALpci15>);>>; DEpic_deassert);>>; smb); )>153c#L76A 82326s/p>2637Lrk_via_vt8237_bPIC ia_vt823pic_deassert_msi_intx_hrd ">Pububpci15>);>>; _msi_intx_hrd ">Pububf">Drert Message\n&1454">smb {>1538#L76#endi26s/p>2638Lrk_"line" name="LEDECLARE_ 722FIXUP2FINALpci15>);>>; DEpic_deassert);>>; smb); ;>153c#L71A 82326s/p>2639Lrk_via_vt8237_binseia_vt823pic_deassert_msi_intx_hrd ">Pububpci15>);>>; _msi_intx_hrd ">Pububf">Drert Message\n&1454">smb 154)#L71#ifde26s/p>264/Lrk_pic_deassert);>>; DEpic_deassert);>>; smb); 154c#L740" id26s/p>264ELrk_via_vt8237_binseia_vt823pic_deassert_msi_intx_hrd ">Pububpci15>);>>; _msi_intx_hrd ">Pububf">Drert Message\n&1454">smb >1542#L74SERT"26s/p>264LLrk_"line" name="LEDECLARE_ 722FIXUP2FINALpci15>);>>; DEpic_deassert);>>; smb); 154c#L743" id26s/p>264lass=ia_vt8237_binsecccccccccpic_deassert_msi_intx_hrd ">Pububpci15>);>>; _msi_intx_hrd ">Pububf">Drert Message\n&1454">smb >1544#L69" id=26s/p>2644ass=pic_deassert);>>; DEpic_deassert);>>; smb); 154c#L715" id26s/p>2645Lrk_via_vt8237_binseccccccccpic_deassert_msi_intx_hrd ">Pububpci15>);>>; _msi_intx_hrd ">Pububf">Drert Message\n&1454">smb ,>1546#L715" id26s/p>264laret#endif3"li/e" name="L759"> 75smb; );>154c#L76A 82326s/p>2647Lrk_rt Message\n&1454">smb >1548#L767" id26s/p>264lass="line do thisnearsmb; >154c#L713" id26s/p>2649Lrk_"li/e" name="L759"> 75s* via >sm=hpmemsize=nnM and >sm=hpiosize=nnM par13"t578. Fora>smb; );>155)#L713" id26s/p>2650Lrk_"li/e" name="L759"> 75s* somes 72- 72 hotplug bridges, likes LX 6254 (former HINT HB6),a>smb; }>155c#L741" id26s/p>265ELrk_"li/e" name="L759"> 75s* kernel fails to allocate resources when hotplug ci_isoris a>smb; );>1552#L741" id26s/p>265lass="li/e" name="L759"> 75s* inserted and 72 busris rescanned.C smb); );>155c#L74A 82326s/p>265lass="li/e" name="L759"> 75s*/a>smb; >1554#L697" id26s/p>2654ass="line" nass="_erte_mchf="+c_hotplug_bridgepci15>);>>; _hotplug_bridgef">DE7c#L763" id="L733" class="li/e" name="L759"> 759(&smb; >155c#L713" id26s/p>2655Lrk_BYPASS_APIC_DE1566">smb); >1556#L715" id26s/p>265lareturnIA 82" id="L733" clafo(&pis_hotplug_bridgepci15>);>>; smb >155c#L767" id26s/p>2657"lin"line" name="L1561">smb) >1558#L767" id26s/p>2658Lrk_rt Message\n&1547">smb); >155c#L71A 82326s/p>2659Lrk_"line" name="LEDECLARE_ 722FIXUP2HEADERpci15>);>>; DEpic_deassert);>>; Drert Message\n&1454">smb >15an#L742" id26s/p>266/Lrk_line" name="L1561">smb) )>156c#L746" id26s/p>266ELrk_"li/e" name="L759"> 75smb; {>15a2#L74#endi26s/p>266lass="li/e" name="L759"> 75s* Tmis is a smb; ;>156c#L74A 82326s/p>266lass="li/e" name="L759"> 75s* somesmulifunction chips.C smb); 8>15a4#L740" id26s/p>2664Assert Message\n&156f">smb >15a5#L74SERT"26s/p>2665Lrk_"li/e" name="L759"> 75s* Tmis is 156y similar and basPd"on ame ricoh_mmc \n&156 written byC smb); );>156c#L656" id26s/p>266/ef"i"line It's possi07"* Philip Langdale. Tmank you forsamesesmage" sequences.C smb); 156c#L767" id26s/p>266lass="li/e" name="L759"> 75s/a>smb; );>1568#L762" id26s/p>266lass="line do thisnearl* Tmeseschips impleisne ame foursmain memo6y card nontrollers (SD, MMC, MS, xD)a>smb; );>156c#L716" id26s/p>2669Lrk_"li/e" name="L759"> 75s* and oneeor both of cardbusror firewire.C smb); 157)#L716" id26s/p>2670Lrk_"li/e" name="L759"> 75s*C smb); }>157c#L746" id26s/p>267ELrk_"li/e" name="L759"> 75s* It happens amat amey impleisne SD and MMCC smb); iv>1572#L74A 82326"dr>267lass="li/e" name="L759"> 75s* support as separ1te nontrollers (and 72 functions). Tme linux SDHCIC smb); ;>157c#L74A 82326s/p>267lass="li/e" name="L759"> 75s* \n&156 supports MMC nards bue ame chip citects MMC nards in hardwareC smb); >1574#L693" id26s/p>2674ass=pli/e" name="L759"> 75s* and directs amem to ame MMC nontroller - so ame SDHCI \n&156 ne156 seesa>smb; );>157c#L713" id26s/p>2675Lrk_"li/e" name="L759"> 75s* amem.C smb); >157c#L653" id26s/p>267/ef"i"line It's possi07"*C smb); );>157c#L763" id26s/p>267lass="li/e" name="L759"> 75s/ To get around amis, we must hrd ">P ame useless MMC nontroller.C smb); ;>15&15e1"0" id26s/p>267lass="line do thisnearl* At amat point, ame SDHCI nontroller will "lirt seeonb amemC smb); );>1479#L767" id26s/p>2679Lrk_"li/e" name="L759"> 75s* It seems to bP ame casP amat ame relevane 72 regist578 to deactivatenameC smb); >148)#L71A 82326s/p>2680Lrk_"li/e" name="L759"> 75s* MMC nontroller le15"on 72 function 0ngwhich might bP ame cardbusrnontrollerC smb); );>148c#L741" id26s/p>268ELrk_"li/e" name="L759"> 75s* orsame firewirernontroller, dependinb on ame particular chip in questionassmb); ;>1482#L741" id26s/p>268lass="li/e" name="L759"> 75s*assmb); );>1483#L741" id26s/p>268lass="li/e" name="L759"> 75s* Tmis has to bP doneeearly, bPcause as soon as we hrd ">P ame MMC nontrollerassmb); }>1484#L741" id26s/p>2684ass=pli/e" name="L759"> 75s* oamer >sm functions shift up oneelevel, e.g. function #2 bPcomes functionassmb); );>148c#L715" id26s/p>2685Lrk_"li/e" name="L759"> 75s* #1, and amis will confusP ame >sm core.C smb); >1486#L715" id26s/p>268/ef"i"line It's possi07"*/a>smb; >148c#L767" id26s/p>2687Lrk_rt Message\n&1454">smb >1488#L76A 82326s/p>2688Lrk_#ifdefg"_erte_mchf="+cCONFIG_MMC_RICOH_MMCpci15>);>>; smb >1489#L741" id26s/p>2689Lrk_"line" nass="_erte_mchf="+cricoh_mmc_fixup_rl5c4s/pci15/a>>L759">ricoh_mmc_fixup_rl5c4s/f">DE7c#L763" id="L733" class="li/e" name="L759"> 759(&smb; >1490#L741" id26s/p>2690Lrk_BYPASS_APIC_DE1566">smb); >149c#L741" id26s/p>2691Lrk_via_vt82pli/e" name="L759"> 75P via cardbusrinterfasor*/a>smb; )>1492#L741" id26s/p>269LLrk_via_vt82pic_deassert(&P/a>(&PLrk_ert Message\n&1454">smb {>149c#L743" id26s/p>269lass=ia_vt823pic_deassert(&(&smb ;>1494#L741" id26s/p>2694ass=ia_vt823pic_deassert(&P/a>(&PLrk_ert Message\n&1454">smb >1495#L741" id26s/p>2695Lrk_rt Message\n&1454">smb );>1496#L741" id26s/p>2696Lrk_via_vt82pli/e" name="L759"> 75P must bP doneevia function #0r*/a>smb; ;>149c#L767" id26s/p>2697Lrk_via_vt82>(stpic_deassert);>>; DEpic_deassert(&pci_fnosmb; );>1498#L767" id26s/p>2698Lrk_via_vt8237_binsereturnert Message\n&1454">smb >149c#L719" id26s/p>269-Assert Message\n&156f">smb >149c#L719" id2700f>2700ass=ia_vt823pic_deassert(&DEpic_deassert(&P/a>(&PLrk_rert Message\n&1454">smb >149c#L741" id270/p>270ELrk_via_vt82>(stpic_deassertP/a>(&PLrk_ e>s_ag0x02rivers/O 12-19, 22, 23ne" name="L2702f="driv270/pci14a>)>1492#L741" id270/p>270LLrk_via_vt8237_binsereturnert Message\n&1454">smb {>149c#L743" id270/p>270lass=rt Message\n&1454">smb ;>1494#L741" id270/p>2704ass=ia_vt823pic_deassert(&DEpic_deassert(&P/a>(&PLrk_rert Message\n&1454">smb >1495#L741" id270/p>2705Lrk_via_vt82resource_0" rtpss="write_config_bytP/a>(&DEpic_deassert(&smb );>1496#L741" id270/p>270lareturnIA 82" id="L733" clas759read_config_bytP/a>(&DEpic_deassert(&smb ;>149c#L767" id270/p>2707Lrk_via_vt82resource_0" rtpss="write_config_bytP/a>(&DEpic_deassert(&smb );>1498#L767" id270/p>2708Lrk_via_vt82pic_deassert(&DEpic_deassert(&P/a>(&PLrk_ |g0x02rert Message\n&1454">smb >149c#L719" id270/p>2709Lrk_via_vt82resource_0" rtpss="write_config_bytP/a>(&DEpic_deassert(&P/a>(&PLrk_rert Message\n&1454">smb )>151)#L71A 82327s/p>2710ass=ia_vt823pic_deassert(&DEpic_deassert(&smb {>151c#L741" id27s/p>271ELrk_rt Message\n&1454">smb ;>1512#L741" id27s/p>271LLrk_via_vt82pic_deassertli/_notisof">DEe>s_apic_deassert(&pci_dev, 1" id="L731" ef"ine">"En707"dLonboard AC9proprieliry Ricoh MMC nontroller frd ">Pd (via cardbusrfunction)8237 APIC De-As)ert Message\n&1454">smb ;>151c#L743" id27s/p>271lass=ia_vt823pic_deassertli/_notisof">DEe>s_apic_deassert(&pci_dev, 1" id="L731" ef"ine">"En707"dLonboard AC9MMC nards are now supportPd by "lindard SDHCI nontroller8237 APIC De-As)ert Message\n&1454">smb >1514#L697" id27s/p>2714Asse"line" name="L1561">smb) >151c#L71A 82327s/p>27s5ef"i"line" name="LEDECLARE_ 722FIXUP2EARLYpci15>);>>; DEpic_deassert);>>; >L759"> 722MB3ICE_ID_RICOH_RL5C4s/ef"ine"ic_deassert>L759">ricoh_mmc_fixup_rl5c4s/f">D)ert Message\n&1454">smb );>151c#L656" id27s/p>271ass=""line" name="LEDECLARE_ 722FIXUP2RESUME_EARLYpci15>);>>; DEpic_deassert);>>; >L759"> 722MB3ICE_ID_RICOH_RL5C4s/ef"ine"ic_deassert>L759">ricoh_mmc_fixup_rl5c4s/f">D)ert Message\n&1454">smb 151c#L767" id27s/p>2717Lrk_rt Message\n&1454">smb );>1518#L762" id27s/p>2718Lrk_"line" nass="_erte_mchf="+cricoh_mmc_fixup_r5c8s/pci15an>>L759">ricoh_mmc_fixup_r5c8s/f">DE7c#L763" id="L733" class="li/e" name="L759"> 759(&smb; )>151c#L716" id27s/p>2719Lrk_BYPASS_APIC_DE1566">smb); );>152)#L716" id27s/p>2720ass=ia_vt823pli/e" name="L759"> 75P via firewirerinterfasor*/a>smb; 152c#L746" id27s/p>272ELrk_via_vt82pic_deassert(&P/a>(&PLrk_ert Message\n&1454">smb }>1522#L746" id27s/p>272LLrk_via_vt82pic_deassert(&P/a>(&PLrk_ert Message\n&1454">smb ,>152c#L746" id27s/p>272lass=rt Message\n&1454">smb );>1524#L696" id27s/p>2724ass=ia_vt823"li/e" name="L759"> 75P must bP doneevia function #0r*/a>smb; >152c#L716" id27s/p>2725Lrk_via_vt82>(stpic_deassert);>>; DEpic_deassert(&pci_fnosmb; >152c#L65s272lareturnIA 8237_binsereturnert Message\n&1454">smb >152c#L76s2727ass=ia_vt823"li/e" name="L759"> 75smb; 152c#L766" id27s/p>272lass="line do thisnearlllllllll* RICOHg0xe822 and 0xe823 SD/MMC nard read578 fail to recognizeC smb); >152c#L716" id27s/p>2729Lrk_"li/e" name="L759"> 75sllllllll* certain types of SD/MMC nards. Loweronb ame SD basPC smb); >153)#L716" id27s/p>2730Lrk_"li/e" name="L759"> 75sllllllll* clock frequency from2200Mhz to 50Mhz fixes amis issue.C smb); >153c#L746" id27s/p>273ELrk_"li/e" name="L759"> 75sllllllll*C smb); >1532#L746" id27s/p>273lass="li/e" name="L759"> 75sllllllll* 0x150 - SD2.0 mf"> en ">P forschangonb basP clockC smb); >153c#L746" id27s/p>273lass="li/e" name="L759"> 75sllllllll* frequency to 50MhzC smb); >1534#L696" id27s/p>2734ass=pli/e" name="L759"> 75sllllllll* 0xe1 - BasP clock frequencyC smb); >153c#L716" id27s/p>2735Lrk_"li/e" name="L759"> 75s""""""""* 0x32 - 50Mhz new clock frequencyC smb); >153c#L65s273/ef"i"line It's possi07"""""""""* 0xf9 - Key regist57 fors0x150C smb); )>153c#L76A 82327s/p>273lass="li/e" name="L759"> 75s""""""""* 0xfc - key regist57 fors0xe1C smb); {>1538#L76#endi27s/p>273lass="line do thisnearlllllllll*/a>smb; ;>153c#L71A 82327s/p>2739Lrk_via_vt82>(stpic_deassert(&pci_isoe" name="L759">li/isof">D == pic_deassert>L759"> 722MB3ICE_ID_RICOH_R5CE82/Lrk_ || class="comme1578">smb; 154)#L71#ifde27s/p>2740Lrk_via_vt8237_bpic_deassert(&pci_isoe" name="L759">li/isof">D == pic_deassert>L759"> 722MB3ICE_ID_RICOH_R5CE82lass=) BYPASS_APIC_DE1566">smb); 154c#L740" id27s/p>274ELrk_via_vt8237_binsepic_deassert(&DEpic_deassert(&smb >1542#L74SERT"27s/p>274LLrk_via_vt8237_binsepic_deassert(&DEpic_deassert(&smb 154c#L743" id27s/p>274lass=ia_vt8237_binsecpic_deassert(&DEpic_deassert(&smb >1544#L69" id=27s/p>2744ass=ia_vt8237_binsec" id="L733" cla 759write_config_bytP/a>(&DEpic_deassert(&smb 154c#L715" id27s/p>2745Lrk_via_vt8237_binse" id="L733" cla 759write_config_bytP/a>(&DEpic_deassert(&smb ,>1546#L715" id27s/p>274lareturnIA 8237_binse" id="L733" cla 759write_config_bytP/a>(&DEpic_deassert(&smb );>154c#L76A 82327s/p>2747Lrk_rt Message\n&1454">smb >1548#L767" id27s/p>2748Lrk_via_vt8237_binsepic_deassertli/_notisof">DEe>s_apic_deassert(&pci_dev, 1" id="L731" ef"ine">"En707"dLonboard AC9MMC nontroller basP frequency changed to 50Mhz.8237 APIC De-As)ert Message\n&1454">smb >154c#L713" id27s/p>2749Lrk_via_vt82"line" name="L1561">smb) );>155)#L713" id27s/p>275/Lrk_line" name="L1561">smb) }>155c#L741" id27s/p>275ELrk_via_vt82pic_deassert(&DEpic_deassert(&P/a>(&PLrk_rert Message\n&1454">smb );>1552#L741" id27s/p>275lass=rt Message\n&1454">smb );>155c#L74A 82327s/p>275lass=ia_vt823>(stpic_deassertP/a>(&PLrk_ e>s_ag0x02rivers/O 12-19, 22, 23ne" name="L2754f="driv27s/pci15/a>>1554#L697" id27s/p>2754ass=ia_vt8237_binsecreturnert Message\n&1454">smb >155c#L713" id27s/p>2755Lrk_rt Message\n&1454">smb >1556#L715" id27s/p>275lareturnIA 82" id="L733" clas759read_config_bytP/a>(&DEpic_deassert(&P/a>(&PLrk_rert Message\n&1454">smb >155c#L767" id27s/p>2757Lrk_via_vt82resource_0" rtpss="write_config_bytP/a>(&DEpic_deassert(&smb >1558#L767" id27s/p>2758Lrk_via_vt82pic_deassert(&DEpic_deassert(&P/a>(&PLrk_ |g0x02rert Message\n&1454">smb >155c#L71A 82327s/p>2759Lrk_via_vt82resource_0" rtpss="write_config_bytP/a>(&DEpic_deassert(&P/a>(&PLrk_rert Message\n&1454">smb >15an#L742" id27s/p>276/Lrk_line" name="L1561">smb) )>156c#L746" id27s/p>276ELrk_via_vt82pic_deassertli/_notisof">DEe>s_apic_deassert(&pci_dev, 1" id="L731" ef"ine">"En707"dLonboard AC9proprieliry Ricoh MMC nontroller frd ">Pd (via firewirerfunction)8237 APIC De-As)ert Message\n&1454">smb {>15a2#L74#endi27s/p>276LLrk_via_vt82pic_deassertli/_notisof">DEe>s_apic_deassert(&pci_dev, 1" id="L731" ef"ine">"En707"dLonboard AC9MMC nards are now supportPd by "lindard SDHCI nontroller8237 APIC De-As)ert Message\n&1454">smb ;>156c#L74A 82327s/p>276lass=rt Message\n&1454">smb 8>15a4#L740" id27s/p>2764Asse"line" name="L1561">smb) >15a5#L74SERT"27s/p>2765ef"i"line" name="LEDECLARE_ 722FIXUP2EARLYpci15>);>>; DEpic_deassert);>>; >L759"> 722MB3ICE_ID_RICOH_R5C8s/ef"ine"ic_deassert>L759">ricoh_mmc_fixup_r5c8s/f">D)ert Message\n&1454">smb );>156c#L656" id27s/p>276ass=""line" name="LEDECLARE_ 722FIXUP2RESUME_EARLYpci15>);>>; DEpic_deassert);>>; >L759"> 722MB3ICE_ID_RICOH_R5C8s/ef"ine"ic_deassert>L759">ricoh_mmc_fixup_r5c8s/f">D)ert Message\n&1454">smb 156c#L767" id27s/p>2767Lrk_pic_deassert);>>; DEpic_deassert);>>; >L759"> 722MB3ICE_ID_RICOH_R5CE82/Lrk_ne"ic_deassert>L759">ricoh_mmc_fixup_r5c8s/f">D)ert Message\n&1454">smb );>1568#L762" id27s/p>2768Lrk_"line" name="LEDECLARE_ 722FIXUP2RESUME_EARLYpci15>);>>; DEpic_deassert);>>; >L759"> 722MB3ICE_ID_RICOH_R5CE82/Lrk_ne"ic_deassert>L759">ricoh_mmc_fixup_r5c8s/f">D)ert Message\n&1454">smb );>156c#L716" id27s/p>2769Lrk_"line" name="LEDECLARE_ 722FIXUP2EARLYpci15>);>>; DEpic_deassert);>>; >L759"> 722MB3ICE_ID_RICOH_R5CE82lass=ne"ic_deassert>L759">ricoh_mmc_fixup_r5c8s/f">D)ert Message\n&1454">smb 157)#L716" id27s/p>277/Lrk_pic_deassert);>>; DEpic_deassert);>>; >L759"> 722MB3ICE_ID_RICOH_R5CE82lass=ne"ic_deassert>L759">ricoh_mmc_fixup_r5c8s/f">D)ert Message\n&1454">smb }>157c#L746" id27s/p>277ELrk_#endif3"li/e" name="L759"> 75smb; iv>1572#L74A 82327"dr>277lass=rt Message\n&1454">smb ;>157c#L74A 82327s/p>277lass=#ifdefg"_erte_mchf="+cCONFIG_DMAR_TABLEpci15an>>L759">CONFIG_DMAR_TABLEass=rt Message\n&1454">smb >1574#L693" id27s/p>2774ass=#def574g"_erte_mchf="+cVTUNCERRMSK2REGpci15an>>L759">VTUNCERRMSK2REGLrk_v0x1acrt Message\n&1454">smb );>157c#L713" id27s/p>2775Lrk_#def574g"_erte_mchf="+cVTD_MSK2SPEC_ERRORSdev, 1" id="L73VTD_MSK2SPEC_ERRORSLrk_via_v(1 << 31rivers/O 12-19, 22, 23ne" name="L2776f="driv27s/pci15/a>>157c#L653" id27s/p>277/ef"i"line It's possi07smb; );>157c#L763" id27s/p>277lass="li/e" name="L759"> 75s/ Tmis is a smb; ;>15&15e1"0" id27s/p>277lass="line do thisnearl* hindlonb logic. With oue amis, platforms usonb Intel 7500, 5500schipsetsa>smb; );>1479#L767" id27s/p>2779Lrk_"li/e" name="L759"> 75s* (and ame derivate15"chipsets likesX58 etc) seem to gener1te NMI/SMI (basPda>smb; >148)#L71A 82327s/p>2780Lrk_"li/e" name="L759"> 75s* on ame RAS config settonbs of ame >latform) when a vt-d fault happens.C smb); );>148c#L741" id27s/p>278ELrk_"li/e" name="L759"> 75s* Tme resultonb SMI caused ame system to hang.C smb); ;>1482#L741" id27s/p>278lass="li/e" name="L759"> 75s*assmb); );>1483#L741" id27s/p>278lass="li/e" name="L759"> 75s* VT-d spec relat4d erro78 are already hindlPd by ame VT-d OS code, so noassmb); }>1484#L741" id27s/p>2784ass=pli/e" name="L759"> 75s* need to report ame s41" erro7 amrough oamer channels.C smb); );>148c#L715" id27s/p>2785Lrk_"li/e" name="L759"> 75s*/a>smb; >1486#L715" id27s/p>278/ef"i"line" nass="_erte_mchf="+cvtd_mask_spec_erro78dev, 1" id="L73vtd_mask_spec_erro78f">DE7c#L763" id="L733" class="li/e" name="L759"> 759(&smb; >148c#L767" id27s/p>2787Lrk_BYPASS_APIC_DE1566">smb); >1488#L76A 82327s/p>2788Lrk_via_vt82pic_deassert>L759">u3LLrk_vpic_deassert(&smb >1489#L741" id27s/p>278-Assert Message\n&156f">smb >1490#L741" id27s/p>2790ass=ia_vt823pic_deassert(&DEpic_deassert(&VTUNCERRMSK2REGLrk_, e>s_apic_deassert(&smb >149c#L741" id27s/p>279ELrk_via_vt82pic_deassert(&DEpic_deassert(&VTUNCERRMSK2REGLrk_, pic_deassert(&smb )>1492#L741" id27s/p>279LLrk_"line" name="L1561">smb) {>149c#L743" id27s/p>279lass="line" name="LEDECLARE_ 722FIXUP2EARLYpci15>);>>; DEpic_deassert);>>; D)ert Message\n&1454">smb ;>1494#L741" id27s/p>2794ass=pic_deassert);>>; DEpic_deassert);>>; D)ert Message\n&1454">smb >1495#L741" id27s/p>2795Lrk_#endifrt Message\n&1454">smb );>1496#L741" id27s/p>279ass="ivers/O 12-19, 22, 23ne" name="L2797f="driv27s/pci14a>;>149c#L767" id27s/p>2797Lrk_"line" nass="_erte_mchf="+cfixup_ti816x_i14a>dev, 1" id="L73fixup_ti816x_i14a>f">DE7c#L763" id="L733" class="li/e" name="L759"> 759(&smb; );>1498#L767" id27s/p>2798Lrk_BYPASS_APIC_DE1566">smb); >149c#L719" id27s/p>2799Lrk_via_vt82rli/e" name="L759"> 75 */a>smb; >149c#L719" id2800f>2800ass=ia_vt823pic_deassertli/_infof">DEe>s_apic_deassert(&pci_dev, 1" id="L731" ef"ine">"En707"dLonboard AC9Settonb 72 cname fors816x 72e ci_iso8237 APIC De-As)ert Message\n&1454">smb >149c#L741" id280/p>280ELrk_via_vt82pic_deassert(&pi14a>dev, 1" id="L73i14a>f">D = pic_deassert);>>; smb )>1492#L741" id280/p>280LLrk_"line" name="L1561">smb) {>149c#L743" id280/p>280lass="line" name="LEDECLARE_ 722FIXUP2CLASS_EARLYpci15>);>>; DEpic_deassert);>>; smb); ;>1494#L741" id280/p>2804ass=ia_vt8237_binseccccccccccccccccccpic_deassert);>>; dev, 1" id="L73fixup_ti816x_i14a>f">D)ert Message\n&1454">smb >1495#L741" id280/p>2805Lrk_rt Message\n&1454">smb );>1496#L741" id280/p>280/ef"i"line It's possi07smb); ;>149c#L767" id280/p>280lass="li/e" name="L759"> 75s/ payload size supportPd.C smb); );>1498#L767" id280/p>280lass="line do thisnearl*/a>smb; >149c#L719" id280/p>2809Lrk_"line" nass="_erte_mchf="+cfixup_mpss_2s/pci15an>>d="L73fixup_mpss_2s/f">DE7c#L763" id="L733" class="li/e" name="L759"> 759(&smb; )>151)#L71A 82328s/p>2810Lrk_BYPASS_APIC_DE1566">smb); {>151c#L741" id28s/p>281ELrk_via_vt82pic_deassert(&p>sme_mpsse" name="L759"> 75e_mpssf">D = 1;2rli/e" name="L759"> 75smb; ;>1512#L741" id28s/p>281LLrk_"line" name="L1561">smb) ;>151c#L743" id28s/p>281lass="line" name="LEDECLARE_ 722FIXUP2HEADERpci15>);>>; DEpic_deassert);>>; smb) >1514#L697" id28s/p>2814ass=ia_vt8237_binsecccccccccc"ic_deassert);>>; >d="L73fixup_mpss_2s/f">D)ert Message\n&1454">smb >151c#L71A 82328s/p>28s5ef"i"line" name="LEDECLARE_ 722FIXUP2HEADERpci15>);>>; DEpic_deassert);>>; smb) );>151c#L656" id28s/p>281lareturnIA 8237_binseccccccccc"ic_deassert);>>; >d="L73fixup_mpss_2s/f">D)ert Message\n&1454">smb 151c#L767" id28s/p>2817Lrk_pic_deassert);>>; DEpic_deassert);>>; smb) );>1518#L762" id28s/p>2818Lrk_via_vt8237_binseccccccccc"ic_deassert);>>; >d="L73fixup_mpss_2s/f">D)ert Message\n&1454">smb )>151c#L716" id28s/p>281-Assert Message\n&156f">smb );>152)#L716" id28s/p>2820Lrk_"li/e" name="L759"> 75smb); 152c#L746" id28s/p>282ELrk_"li/e" name="L759"> 75s* coalesconb (which is en ">Pd by default on somesBIOSes) and MPS of 2s/B.C smb); }>1522#L746" id28s/p>282/Lrk_"li/e" name="L759"> 75s* SincP ameroris no way of knowonb wmat ame 72E MPS oe"each fabre" will bPC smb); ,>152c#L746" id28s/p>282lass="li/e" name="L759"> 75s* until all of ame ci_isos are disco157ed and busos walked, read completionassmb); );>1524#L696" id28s/p>2824ass=pli/e" name="L759"> 75s* coalesconb must bP drd ">Pd. Unfortunately, it cannot be re-en ">Pd bPcauseassmb); >152c#L716" id28s/p>2825Lrk_"li/e" name="L759"> 75s* it is possi">P ao hotplug a ci_iso with MPS of 2s/B.C smb); >152c#L65s282/ef"i"line It's possi07"*/a>smb; >152c#L76s2827Lrk_"line" nass="_erte_mchf="+c>d="L73DE7c#L763" id="L733" class="li/e" name="L759"> 759(&smb; 152c#L766" id28s/p>2828Lrk_BYPASS_APIC_DE1566">smb); >152c#L716" id28s/p>2829Lrk_via_vt82>n63" id="L733" claerr/a>(&smb >153)#L716" id28s/p>2830ass=ia_vt823pic_deassert>d="L73u1laretu"ic_deassert>L759">rccLrk_ert Message\n&1454">smb >153c#L746" id28s/p>283ELrk_rt Message\n&1454">smb >1532#L746" id28s/p>28s/f">Dvia_vt82>(stpic_deassert 75e_bus_configf">D == pic_deassert);>>; smb; >153c#L746" id28s/p>283lass=ia_vt8237_binsecreturnert Message\n&1454">smb >1534#L696" id28s/p>2834Assert Message\n&156f">smb >153c#L716" id28s/p>2835Lrk_via_vt82rli/e" name="L759"> 75smb); >153c#L65s283/ef"i"line It's possi07"""""""""* Keeponb amemsmage"al until such time as ame regist578 and values canC smb); )>153c#L76A 82328s/p>283lass="li/e" name="L759"> 75s""""""""* be expla574d.C smb); {>1538#L76#endi28s/p>283lass="line do thisnearlllllllll*/a>smb; ;>153c#L71A 82328s/p>2839Lrk_via_vt82resource_0" rtperr/a>(&(&DEpic_deassert(&rccLrk_)ert Message\n&1454">smb 154)#L71#ifde28s/p>2840Lrk_via_vt82>(stpic_deassert(&smb); 154c#L740" id28s/p>284ELrk_via_vt8237_binsepic_deassert(&DEe>s_apic_deassert(&pci_dev, 1" id="L731" ef"ine">"En707"dLonboard AC9Erro7 attemptonb to read ame read 37 APIC De-AsYPASS_APIC_DE1566">smb); >1542#L74SERT"28s/p>284LLrk_via_vt8237_binsevia_vt82rli/e" name=""dLonboard AC9completion coalesconb regist57.8237 APIC De-As)ert Message\n&1454">smb 154c#L743" id28s/p>284lass=ia_vt8237_binsecreturnert Message\n&1454">smb >1544#L69" id=28s/p>2844ass=ia_vt823"line" name="L1561">smb) 154c#L715" id28s/p>2845Lrk_rt Message\n&1454">smb ,>1546#L715" id28s/p>284lareturnIA 82>(st!tpic_deassert>L759">rccLrk_ e>s_ag(1 << 10)rrivers/O 12-19, 22, 23ne" name="L2847f="driv28s/pci15>);>154c#L76A 82328s/p>2847ass=ia_vt8237_binsecreturnert Message\n&1454">smb >1548#L767" id28s/p>2848Lrk_rt Message\n&1454">smb >154c#L713" id28s/p>2849Lrk_via_vt82resource_0" rtprccpci15an>>L759">rccLrk_ e>s_a= ~(1 << 10)ert Message\n&1454">smb );>155)#L713" id28s/p>285/Lrk_line" name="L1561">smb) }>155c#L741" id28s/p>285ELrk_via_vt82pic_deassert(&(&DEpic_deassert(&rccLrk_)ert Message\n&1454">smb );>1552#L741" id28s/p>285/f">Dvia_vt82>(stpic_deassert(&smb); );>155c#L74A 82328s/p>285lass=ia_vt8237_binsecpic_deassert(&DEe>s_apic_deassert(&pci_dev, 1" id="L731" ef"ine">"En707"dLonboard AC9Erro7 attemptonb to write ame read 37 APIC De-AsYPASS_APIC_DE1566">smb); >1554#L697" id28s/p>2854ass=ia_vt8237_binsecvia_vt82rli/e" name=""dLonboard AC9completion coalesconb regist57.8237 APIC De-As)ert Message\n&1454">smb >155c#L713" id28s/p>2855Lrk_via_vt8237_binsereturnert Message\n&1454">smb >1556#L715" id28s/p>285lareturnIA 82"line" name="L1561">smb) >155c#L767" id28s/p>2857Lrk_rt Message\n&1454">smb >1558#L767" id28s/p>2858Lrk_via_vt82pic_deassertpr_info_onsof">DEpli/e" name=""dLonboard AC9Read completion coalesconb frd ">Pd duP ao hardware 37 APIC De-AsYPASS_APIC_DE1566">smb); >155c#L71A 82328s/p>2859Lrk_via_vt82insecvia_vt82rli/e" name=""dLonboard AC9errata relatonb to 2s/B MPS.8237 APIC De-As)ert Message\n&1454">smb >15an#L742" id28s/p>286/Lrk_"line" name="L1561">smb) )>156c#L746" id28s/p>286ELrk_"li/e" name="L759"> 75smb; {>15a2#L74#endi28s/p>286LLrk_pic_deassert);>>; DEpic_deassert);>>; >d="L73D)ert Message\n&1454">smb ;>156c#L74A 82328s/p>286lass="line" name="LEDECLARE_ 722FIXUP2HEADERpci15>);>>; DEpic_deassert);>>; >d="L73D)ert Message\n&1454">smb 8>15a4#L740" id28s/p>2864ass=pic_deassert);>>; DEpic_deassert);>>; >d="L73D)ert Message\n&1454">smb >15a5#L74SERT"28s/p>2865ef"i"line" name="LEDECLARE_ 722FIXUP2HEADERpci15>);>>; DEpic_deassert);>>; >d="L73D)ert Message\n&1454">smb );>156c#L656" id28s/p>286ass=""line" name="LEDECLARE_ 722FIXUP2HEADERpci15>);>>; DEpic_deassert);>>; >d="L73D)ert Message\n&1454">smb 156c#L767" id28s/p>2867Lrk_pic_deassert);>>; DEpic_deassert);>>; >d="L73D)ert Message\n&1454">smb );>1568#L762" id28s/p>2868Lrk_"line" name="LEDECLARE_ 722FIXUP2HEADERpci15>);>>; DEpic_deassert);>>; >d="L73D)ert Message\n&1454">smb );>156c#L716" id28s/p>2869Lrk_"line" name="LEDECLARE_ 722FIXUP2HEADERpci15>);>>; DEpic_deassert);>>; >d="L73D)ert Message\n&1454">smb 157)#L716" id28s/p>287/Lrk_pic_deassert);>>; DEpic_deassert);>>; >d="L73D)ert Message\n&1454">smb }>157c#L746" id28s/p>287ELrk_pic_deassert);>>; DEpic_deassert);>>; >d="L73D)ert Message\n&1454">smb iv>1572#L74A 82328"dr>287LLrk_pic_deassert);>>; DEpic_deassert);>>; >d="L73D)ert Message\n&1454">smb ;>157c#L74A 82328s/p>287lass="line" name="LEDECLARE_ 722FIXUP2HEADERpci15>);>>; DEpic_deassert);>>; >d="L73D)ert Message\n&1454">smb >1574#L693" id28s/p>2874ass=pic_deassert);>>; DEpic_deassert);>>; >d="L73D)ert Message\n&1454">smb );>157c#L713" id28s/p>2875ef"i"line" name="LEDECLARE_ 722FIXUP2HEADERpci15>);>>; DEpic_deassert);>>; >d="L73D)ert Message\n&1454">smb >157c#L653" id28s/p>287/ef"i"line It's possi07smb; );>157c#L763" id28s/p>2877Lrk_pic_deassert);>>; DEpic_deassert);>>; >d="L73D)ert Message\n&1454">smb ;>15&15e1"0" id28s/p>2878Lrk_"line" name="LEDECLARE_ 722FIXUP2HEADERpci15>);>>; DEpic_deassert);>>; >d="L73D)ert Message\n&1454">smb );>1479#L767" id28s/p>2879Lrk_"line" name="LEDECLARE_ 722FIXUP2HEADERpci15>);>>; DEpic_deassert);>>; >d="L73D)ert Message\n&1454">smb >148)#L71A 82328s/p>288/Lrk_pic_deassert);>>; DEpic_deassert);>>; >d="L73D)ert Message\n&1454">smb );>148c#L741" id28s/p>288ELrk_pic_deassert);>>; DEpic_deassert);>>; >d="L73D)ert Message\n&1454">smb ;>1482#L741" id28s/p>288LLrk_pic_deassert);>>; DEpic_deassert);>>; >d="L73D)ert Message\n&1454">smb );>1483#L741" id28s/p>288lass="line" name="LEDECLARE_ 722FIXUP2HEADERpci15>);>>; DEpic_deassert);>>; >d="L73D)ert Message\n&1454">smb }>1484#L741" id28s/p>2884ass=pic_deassert);>>; DEpic_deassert);>>; >d="L73D)ert Message\n&1454">smb );>148c#L715" id28s/p>2885ef"i"line" name="LEDECLARE_ 722FIXUP2HEADERpci15>);>>; DEpic_deassert);>>; >d="L73D)ert Message\n&1454">smb >1486#L715" id28s/p>288ass=""line" name="LEDECLARE_ 722FIXUP2HEADERpci15>);>>; DEpic_deassert);>>; >d="L73D)ert Message\n&1454">smb >148c#L767" id28s/p>2887Lrk_pic_deassert);>>; DEpic_deassert);>>; >d="L73D)ert Message\n&1454">smb >1488#L76A 82328s/p>2888Lrk_rt Message\n&1454">smb >1489#L741" id28s/p>288-Assert Message\n&156f">smb >1490#L741" id28s/p>2890ass="line" pic_deassert>d="L73ktime_tLrk_vpic_deassert>d="L73fixup_debug_"lirtf">DE7c#L763" id="L733" class="li/e" name="L759"> 759(&smb) >149c#L741" id28s/p>289ELrk_via_vt8237_binseeeeeeeeeeeeeeeeeenass=(npic_deassert>d="L73fnf">D)E7c#L763" id="L733" class="li/e" name="L759"> 759(&)>1492#L741" id28s/p>289LLrk_BYPASS_APIC_DE1566">smb); {>149c#L743" id28s/p>289lass=ia_vt823pic_deassert>d="L73ktime_tLrk_vpic_deassert>d="L73calltimeLrk_v= pic_deassert>d="L73ktime_setf">DE0ng0)ert Message\n&1454">smb ;>1494#L741" id28s/p>2894Assert Message\n&156f">smb >1495#L741" id28s/p>2895ass=ia_vt823pic_deassertli/_dbgf">DEe>s_apic_deassert(&pci_dev, 1" id="L731" ef"ine">"En707"dLonboard AC9callonb %pF8237 APIC De-As, pic_deassert>d="L73fnf">D)ert Message\n&1454">smb );>1496#L741" id28s/p>289lareturnIA 82>(stpic_deassert>d="L73initcall_debugf">D) BYPASS_APIC_DE1566">smb); ;>149c#L767" id28s/p>2897ass=ia_vt8237_binsec" id="L733" clasr_debugpci15an>>d="L73sr_debugf">DEp>"En707"dLonboard AC9callonb %pF @ %i fors%s8237 APIC De-As,YPASS_APIC_DE1566">smb); );>1498#L767" id28s/p>2898Lrk_via_vt8237_binseccccccccc"ic_deassert>d="L73fnf">D, pic_deassert(&DEpic_deassert>d="L73currssif">D), pic_deassert>d="L73fi/_namef">DEe>s_apic_deassert(&pci_dev, 1" id="L731" ef"i))ert Message\n&1454">smb >149c#L719" id28s/p>2899Lrk_via_vt82insecviapic_deassert>d="L73calltimeLrk_v= pic_deassert>d="L73ktime_getf">DE)ert Message\n&1454">smb >149c#L719" id2900f>2900ass=ia_vt823"line" name="L1561">smb) >149c#L741" id290/p>290ELrk_rt Message\n&1454">smb )>1492#L741" id290/p>290/f">Dvia_vt82returnapic_deassert>d="L73calltimeLrk_ert Message\n&1454">smb {>149c#L743" id290/p>290lass="line" name="L1561">smb) ;>1494#L741" id290/p>2904Assert Message\n&156f">smb >1495#L741" id290/p>2905Lrk_"line" nass="_erte_mchf="+cfixup_debug_reportpci15an>>d="L73fixup_debug_reportf">DE7c#L763" id="L733" class="li/e" name="L759"> 759(&>d="L73calltimeLrk_,YPASS_APIC_DE1566">smb); );>1496#L741" id290/p>290lareturnIA 8237_binseccccccccceeeeeenass=(npic_deassert>d="L73fnf">D)E7c#L763" id="L733" class="li/e" name="L759"> 759(&;>149c#L767" id290/p>2907Lrk_BYPASS_APIC_DE1566">smb); );>1498#L767" id290/p>2908Lrk_via_vt82pic_deassert>d="L73ktime_tLrk_vpic_deassert>d="L73delta+codn3pic_deassert>d="L73rettomeLrk_ert Message\n&1454">smb >149c#L719" id290/p>2909Lrk_via_vt82unsig74d lonb lonb pic_deassert>d="L73durationLrk_ert Message\n&1454">smb )>151)#L71A 82329s/p>291/Lrk_line" name="L1561">smb) {>151c#L741" id29s/p>291ELrk_via_vt82>(stpic_deassert>d="L73initcall_debugf">D) BYPASS_APIC_DE1566">smb); ;>1512#L741" id29s/p>291LLrk_via_vt8237_binsepic_deassert>d="L73rettomeLrk_v= pic_deassert>d="L73ktime_getf">DE)ert Message\n&1454">smb ;>151c#L743" id29s/p>291lass=ia_vt8237_binsecpic_deassert>d="L73delta+codv= pic_deassert>d="L73ktime_subf">DEpic_deassert>d="L73rettomeLrk_n3pic_deassert>d="L73calltimeLrk_)ert Message\n&1454">smb >1514#L697" id29s/p>2914ass=ia_vt8237_binsecpic_deassert>d="L73durationLrk_v= (unsig74d lonb lonb)2pic_deassertktime_to_nsf">DEpic_deassert>d="L73delta+cod) =de"=de" 10ert Message\n&1454">smb >151c#L71A 82329s/p>2915Lrk_via_vt8237_binse" id="L733" clasr_debugpci15an>>d="L73sr_debugf">DEp>"En707"dLonboard AC9>sm fixup %pF returned afters%lld usecs fors%s8237 APIC De-As,YPASS_APIC_DE1566">smb); );>151c#L656" id29s/p>291lareturnIA 8237_binseccccccccc"ic_deassert>d="L73fnf">D, pic_deassert>d="L73durationLrk_, pic_deassert>d="L73fi/_namef">DEe>s_apic_deassert(&pci_dev, 1" id="L731" ef"i))ert Message\n&1454">smb 151c#L767" id29s/p>2917ass=ia_vt823"line" name="L1561">smb) );>1518#L762" id29s/p>2918Lrk_"line" name="L1561">smb) )>151c#L716" id29s/p>291-Assert Message\n&156f">smb );>152)#L716" id29s/p>2920Lrk_"li/e" name="L759"> 75smb; 152c#L746" id29s/p>292ELrk_"li/e" name="L759"> 75s* SomesBIOS imple9"> ations lea15"ame Intel GPU2>n6errupts en ">Pd,a>smb; }>1522#L746" id29s/p>292/Lrk_"li/e" name="L759"> 75s* even amough no onoris hindlonb amems(f.e. i915 mme157ris ne157rloaded).C smb); ,>152c#L746" id29s/p>292lass="li/e" name="L759"> 75s* Additionally ame >n6errupt destinationris not set up properlyC smb); );>1524#L696" id29s/p>2924ass=pli/e" name="L759"> 75s* and ame >n6errupt ends up -somewmero-.C smb); >152c#L716" id29s/p>2925Lrk_"li/e" name="L759"> 75s*C smb); >152c#L65s292/ef"i"line It's possi07"* Tmese spurious2>n6errupts are 37 APIsticky37 API and ame kernel frd ">Psa>smb; >152c#L76s292lass="li/e" name="L759"> 75s/ ame (shared) >n6errupt 152c afters100.000+ gener1ted2>n6errupts.C smb); 152c#L766" id29s/p>292lass="line do thisnearl*C smb); >152c#L716" id29s/p>2929Lrk_"li/e" name="L759"> 75s* Fix it by drd ">onb ame still en ">Pd >n6errupts.C smb); >153)#L716" id29s/p>2930Lrk_"li/e" name="L759"> 75s* Tmis resolves crasmes often seen oe"monitorsunplug.C smb); >153c#L746" id29s/p>293ELrk_"li/e" name="L759"> 75s*/a>smb; >1532#L746" id29s/p>29s/f">D#def574g"_erte_mchf="+cI915_DEIER2REGpci15an>>L759">I915_DEIER2REGass=i0x4400crt Message\n&1454">smb >153c#L746" id29s/p>293lass="line" nass="_erte_mchf="+cfrd ">P_igfx_irqdev, 1" id="L731rd ">P_igfx_irqf">DE7c#L763" id="L733" class="li/e" name="L759"> 759(&>1534#L696" id29s/p>2934AsseBYPASS_APIC_DE1566">smb); >153c#L716" id29s/p>2935Lrk_via_vt82nass="_erte_mchf="+c__iomem/a>(&regs+codv= pic_deassert 759iomapf">DEpic_deassert(&smb >153c#L65s293lareturnIA 82>(stpic_deassertregs+codv== pic_deassert);>>; D) BYPASS_APIC_DE1566">smb); )>153c#L76A 82329s/p>2937ass=ia_vt8237_binsec" id="L733" clafi/_warnpci15an>>d="L73di/_warnf">DEe>s_apic_deassert(&pci_dev, 1" id="L731" ef"ine">"En707"dLonboard AC9igfx smb {>1538#L76#endi29s/p>2938Lrk_via_vt8237_binsereturnert Message\n&1454">smb ;>153c#L71A 82329s/p>2939Lrk_via_vt82"line" name="L1561">smb) 154)#L71#ifde29s/p>294/Lrk_line" name="L1561">smb) 154c#L740" id29s/p>294ELrk_via_vt82"line It's possi07(sany >n6errupt 152c is still en ">Pd */a>smb; >1542#L74SERT"29s/p>294LLrk_via_vt82>(stpic_deassertreadlf">DEpic_deassertregs+codv+g"_erte_mchf="+cI915_DEIER2REGpci15an>>L759">I915_DEIER2REGass=) !=g0) BYPASS_APIC_DE1566">smb); 154c#L743" id29s/p>294lass=ia_vt8237_binsec" id="L733" clafi/_warnpci15an>>d="L73di/_warnf">DEe>s_apic_deassert(&pci_dev, 1" id="L731" ef"ine">"En707"dLonboard AC9BIOS left Intel GPU2>n6errupts en ">Pd; 37 APIC De-AsYPASS_APIC_DE1566">smb); >1544#L69" id=29s/p>2944ass=ia_vt8237_binsecvia_vt82rli/e" name=""dLonboard AC9drd ">onb8237 APIC De-As)ert Message\n&1454">smb 154c#L715" id29s/p>2945Lrk_rt Message\n&1454">smb ,>1546#L715" id29s/p>294lareturnIA 8237_binse class="sref">pwritele" name="L759">writelf">DE0ngpic_deassertregs+codv+g"_erte_mchf="+cI915_DEIER2REGpci15an>>L759">I915_DEIER2REGass=)ert Message\n&1454">smb );>154c#L76A 82329s/p>2947ass=ia_vt823"line" name="L1561">smb) >1548#L767" id29s/p>2948Lrk_rt Message\n&1454">smb >154c#L713" id29s/p>2949Lrk_via_vt82resource_0" rtp 759iounmape" name="L759"> 759iounmapf">DEpic_deassert(&regs+cod)ert Message\n&1454">smb );>155)#L713" id29s/p>295/Lrk_"line" name="L1561">smb) }>155c#L741" id29s/p>295ELrk_pic_deassert);>>; DEpic_deassert);>>; P_igfx_irqdev, 1" id="L731rd ">P_igfx_irqf">D)ert Message\n&1454">smb );>1552#L741" id29s/p>295LLrk_pic_deassert);>>; DEpic_deassert);>>; P_igfx_irqdev, 1" id="L731rd ">P_igfx_irqf">D)ert Message\n&1454">smb );>155c#L74A 82329s/p>295lass=rt Message\n&1454">smb >1554#L697" id29s/p>2954ass=pli/e" name="L759"> 75smb; >155c#L713" id29s/p>2955Lrk_"li/e" name="L759"> 75s* Somesci_isos may pame our check2>n 759intx_mask_supportPd2>(a>smb; >1556#L715" id29s/p>295/ef"i"line It's possi07"* 722COMMAND_INTX_DISABLE works amough amey actually do not properlyC smb); >155c#L767" id29s/p>295lass="li/e" name="L759"> 75s/ support amis feature.C smb); >1558#L767" id29s/p>295lass="line do thisnearl*/a>smb; >155c#L71A 82329s/p>2959Lrk_"line" nass="_erte_mchf="+cDE7c#L763" id="L733" class="li/e" name="L759"> 759(&>15an#L742" id29s/p>2960Lrk_BYPASS_APIC_DE1566">smb); )>156c#L746" id29s/p>296ELrk_via_vt82pic_deassert(&pbroken9intx_maskonboev, 1" id="L73broken9intx_maskonbf">D = 1;YPASS_APIC_DE1566">smb); {>15a2#L74#endi29s/p>296LLrk_"line" name="L1561">smb) ;>156c#L74A 82329s/p>296lass="line" name="LEDECLARE_ 722FIXUP2HEADERpci15>);>>; DEpic_deassert);>>; smb); 8>15a4#L740" id29s/p>2964ass=ia_vt8237_binsecccccccccc"ic_deassertD)ert Message\n&1454">smb >15a5#L74SERT"29s/p>2965ef"i"line" name="LEDECLARE_ 722FIXUP2HEADERpci15>);>>; DE0x1814ng0x0601,2"line It's possi07smb; );>156c#L656" id29s/p>296lareturnIA 8237_binseccccccccc"ic_deassertD)ert Message\n&1454">smb 156c#L767" id29s/p>2967Lrk_rt Message\n&1454">smb );>1568#L762" id29s/p>2968Lrk_"line" nass="_erte_mchf="+c 759 759DE7c#L763" id="L733" class="li/e" name="L759"> 759(& 759fixup>>d="L73f+cod,rt Message\n&1454">smb );>156c#L716" id29s/p>2969Lrk_via_vt82insecvia_vt82222227c#L763" id="L733" class="fixupe" name="L759"> 759fixup>(&157)#L716" id29s/p>2970Lrk_BYPASS_APIC_DE1566">smb); }>157c#L746" id29s/p>297ELrk_via_vt82pic_deassert>d="L73ktime_tLrk_vpic_deassert>d="L73calltimeLrk_ert Message\n&1454">smb iv>1572#L74A 82329"dr>297LLrk_rt Message\n&1454">smb ;>157c#L74A 82329s/p>297lass=ia_vt823fors(;c"ic_deassert>d="L73f+cod <2pic_deassert(&>d="L73f+cod++rivers/O 12-19, 22, 23ne" name="L2974f="driv29s/pci15/a>>1574#L693" id29s/p>2974ass=ia_vt8237_binsec>(stEpic_deassert>d="L73f+code=de" class="sref">pi15anpci15an>>d="L73c15an+codv== Epic_deassert>d="L73us/f">D) Epic_deassert(&pi15anpci15an>>d="L73c15an+codv=de"=de" pic_deassert>d="L73f+code=de" class="sref">pi15an_shifi0ci15an>>d="L73c15an_shifif">D) ||ivers/O 12-19, 22, 23ne" name="L2975f="driv29s/pci15>);>157c#L713" id29s/p>2975Lrk_via_vt8237_binse_vt82pic_deassert>d="L73f+code=de" class="sref">pi15anpci15an>>d="L73c15an+codv== Epic_deassert>d="L73us/f">D) pic_deassert);>>; D) e>s_ae>s_aivers/O 12-19, 22, 23ne" name="L2976f="driv29s/pci15/a>>157c#L653" id29s/p>297lareturnIA 8237_binseccccEpic_deassert>d="L73f+code=de" class="sref">pvendor/a>(&(&pvendor/a>(&);>157c#L763" id29s/p>2977ass=ia_vt8237_binsec_vt82pic_deassert>d="L73f+code=de" class="sref">pvendor/a>(&>d="L73u1laret) pic_deassert);>>; D) e>s_ae>s_aivers/O 12-19, 22, 23ne" name="L2978f="driv29s/pci15a>;>15&15e1"0" id29s/p>2978Lrk_via_vt8237_binseccccEpic_deassert>d="L73f+code=de" class="sref">pci_iso/a>(&pci_iso/a>(&);>1479#L767" id29s/p>2979Lrk_via_vt82insecvia_vt82ric_deassert>d="L73f+code=de" class="sref">pci_iso/a>(&);>>; D)) BYPASS_APIC_DE1566">smb); >148)#L71A 82329s/p>2980Lrk_via_vt82insecvia_vt82t82ric_deassert>d="L73calltimeLrk_v= pic_deassert>d="L73fixup_debug_"lirtf">DEpic_deassert(&phookpci15an>>d="L73hookf">D)ert Message\n&1454">smb );>148c#L741" id29s/p>298ELrk_via_vt8237_binseeeeeeeeepic_deassert>d="L73f+code=de" class="sref">phookpci15an>>d="L73hookf">DEpic_deassert(&smb ;>1482#L741" id29s/p>298LLrk_via_vt8237_binsevia_vt82ric_deassert>d="L73fixup_debug_reportf">DEpic_deassert(&>d="L73f+code=de" class="sref">phookpci15an>>d="L73hookf">D)ert Message\n&1454">smb );>1483#L741" id29s/p>298lass=ia_vt8237_binsec"line" name="L1561">smb) }>1484#L741" id29s/p>2984ass="line" name="L1561">smb) );>148c#L715" id29s/p>2985Lrk_rt Message\n&1454">smb >1486#L715" id29s/p>298ass="extern27c#L763" id="L733" class="fixupe" name="L759"> 759fixup>__"lirt_ 759fixups_early>smb >148c#L767" id29s/p>2987Lrk_extern27c#L763" id="L733" class="fixupe" name="L759"> 759fixup>__end_ 759fixups_early>smb >1488#L76A 82329s/p>2988Lrk_extern27c#L763" id="L733" class="fixupe" name="L759"> 759fixup>(&smb >1489#L741" id29s/p>298-Asseextern27c#L763" id="L733" class="fixupe" name="L759"> 759fixup>(&smb >1490#L741" id29s/p>2990ass=extern27c#L763" id="L733" class="fixupe" name="L759"> 759fixup>__"lirt_ 759fixups_final>smb >149c#L741" id29s/p>299ELrk_extern27c#L763" id="L733" class="fixupe" name="L759"> 759fixup>__end_ 759fixups_final>smb )>1492#L741" id29s/p>299LLrk_extern27c#L763" id="L733" class="fixupe" name="L759"> 759fixup>Pe" name="L759">__"lirt_ 759fixups_en ">P>smb {>149c#L743" id29s/p>299lass=extern27c#L763" id="L733" class="fixupe" name="L759"> 759fixup>Pe" name="L759">__end_ 759fixups_en ">P>smb ;>1494#L741" id29s/p>2994Asseextern27c#L763" id="L733" class="fixupe" name="L759"> 759fixup>>d="L73__"lirt_ 759fixups_resume>smb >1495#L741" id29s/p>2995ass=extern27c#L763" id="L733" class="fixupe" name="L759"> 759fixup>>d="L73__end_ 759fixups_resume>smb );>1496#L741" id29s/p>299ass="extern27c#L763" id="L733" class="fixupe" name="L759"> 759fixup>__"lirt_ 759fixups_resume_early>smb ;>149c#L767" id29s/p>2997Lrk_extern27c#L763" id="L733" class="fixupe" name="L759"> 759fixup>__end_ 759fixups_resume_early>smb );>1498#L767" id29s/p>2998Lrk_extern27c#L763" id="L733" class="fixupe" name="L759"> 759fixup>(&smb >149c#L719" id29s/p>299-Asseextern27c#L763" id="L733" class="fixupe" name="L759"> 759fixup>(&smb >149c#L719" id3000f>3000Lrk_rt/pre>>do9c#L"dri8b/27/5ec2adea0f45e81c4e5a01a724741a6b05c7_3/3000f>t Message\n&1454">smb >149c#L741" id300/p>3001Lrk_"line" class="sref">pboole" name="L759">bool> 759apply9fixup_final_smb )>1492#L741" id300/p>300LLrk_rt Message\n&1454">smb {>149c#L743" id300/p>300lass=nass="_erte_mchf="+c 759fixup_de_iso/a>(&DEenum="_erte_mchf="+c 759fixup_p5anpci15an>>d="L73 759fixup_p5an>>d="L73 5an> 759(&;>1494#L741" id300/p>3004AsseBYPASS_APIC_DE1566">smb); >1495#L741" id300/p>3005Lrk_via_vt827c#L763" id="L733" class="fixupe" name="L759"> 759fixup>>d="L73"lirtf">D,anpic_deassert(&smb );>1496#L741" id300/p>3006Lrk_rt Message\n&1454">smb ;>149c#L767" id300/p>3007ass=ia_vt823switchEpic_deassert>d="L73 5an>smb); );>1498#L767" id300/p>3008Lrk_via_vt82cas4g"_erte_mchf="+c 759fixup_earlye" name="L759"> 759fixup_earlyLrk_:YPASS_APIC_DE1566">smb); >149c#L719" id300/p>3009Lrk_via_vt82insecviapic_deassert>d="L73"lirtf">Dv= pic_deassert__"lirt_ 759fixups_early>smb )>151)#L71A 82330s/p>30s/Lrk_via_vt82insecviapic_deassert(&__end_ 759fixups_early>smb {>151c#L741" id30s/p>30sELrk_via_vt8237_binsebreakert Message\n&1454">smb ;>1512#L741" id30s/p>30sLLrk_rt Message\n&1454">smb ;>151c#L743" id30s/p>30s3Lrk_via_vt82cas4g"_erte_mchf="+c 759fixup_header/a>(&smb); >1514#L697" id30s/p>30s4ass=ia_vt8237_binsecpic_deassert>d="L73"lirtf">Dv= pic_deassert(&smb >151c#L71A 82330s/p>30s5Lrk_via_vt8237_binse" id="L733" claend/a>(&(&smb );>151c#L656" id30s/p>30slareturnIA 8237_binsebreakert Message\n&1454">smb 151c#L767" id30s/p>30s7Lrk_rt Message\n&1454">smb );>1518#L762" id30s/p>30s8Lrk_via_vt82cas4g"_erte_mchf="+c 759fixup_finale" name="L759"> 759fixup_finalLrk_:YPASS_APIC_DE1566">smb); )>151c#L716" id30s/p>30s9Lrk_via_vt82insecvia>(st!" id="L733" cla 759apply9fixup_final_ 759apply9fixup_final_);>152)#L716" id30s/p>30s/Lrk_via_vt8237_binsevia_vt82returnert Message\n&1454">smb 152c#L746" id30s/p>30sELrk_via_vt8237_binsepic_deassert>d="L73"lirtf">Dv= pic_deassert__"lirt_ 759fixups_final>smb }>1522#L746" id30s/p>30sLLrk_via_vt8237_binsepic_deassert(&__end_ 759fixups_final>smb ,>152c#L746" id30s/p>30slass=ia_vt8237_binsecbreakert Message\n&1454">smb );>1524#L696" id30s/p>30s4Assert Message\n&156f">smb >152c#L716" id30s/p>30s5Lrk_via_vt82cas4g"_erte_mchf="+c 759fixup_en ">Pe" name="L759"> 759fixup_en ">PLrk_:YPASS_APIC_DE1566">smb); >152c#L65s30slareturnIA 8237_binse class="sref">p"lirtpci15an>>d="L73"lirtf">Dv= pic_deassertPe" name="L759">__"lirt_ 759fixups_en ">P>smb >152c#L76s30s7ass=ia_vt8237_binsec" id="L733" claend/a>(&Pe" name="L759">__end_ 759fixups_en ">P>smb 152c#L766" id30s/p>30s8Lrk_via_vt8237_binsebreakert Message\n&1454">smb >152c#L716" id30s/p>30s-Assert Message\n&156f">smb >153)#L716" id30s/p>30s/Lrk_via_vt82cas4g"_erte_mchf="+c 759fixup_resumepci15an>>d="L73 759fixup_resumeLrk_:YPASS_APIC_DE1566">smb); >153c#L746" id30s/p>30sELrk_via_vt8237_binsepic_deassert>d="L73"lirtf">Dv= pic_deassert>d="L73__"lirt_ 759fixups_resume>smb >1532#L746" id30s/p>30sLLrk_via_vt8237_binsepic_deassert(&>d="L73__end_ 759fixups_resume>smb >153c#L746" id30s/p>30slass=ia_vt8237_binsecbreakert Message\n&1454">smb >1534#L696" id30s/p>30s4Assert Message\n&156f">smb >153c#L716" id30s/p>30s5Lrk_via_vt82cas4g"_erte_mchf="+c 759fixup_resume_earlye" name="L759"> 759fixup_resume_earlyLrk_:YPASS_APIC_DE1566">smb); >153c#L65s30slareturnIA 8237_binse class="sref">p"lirtpci15an>>d="L73"lirtf">Dv= pic_deassert__"lirt_ 759fixups_resume_early>smb )>153c#L76A 82330s/p>30s7ass=ia_vt8237_binsec" id="L733" claend/a>(&__end_ 759fixups_resume_early>smb {>1538#L76#endi30s/p>30s8Lrk_via_vt8237_binsebreakert Message\n&1454">smb ;>153c#L71A 82330s/p>30s-Assert Message\n&156f">smb 154)#L71#ifde30s/p>30s/Lrk_via_vt82cas4g"_erte_mchf="+c 759fixup_suspend/a>(&smb); 154c#L740" id30s/p>30sELrk_via_vt8237_binsepic_deassert>d="L73"lirtf">Dv= pic_deassert(&smb >1542#L74SERT"30s/p>30sLLrk_via_vt8237_binsepic_deassert(&(&smb 154c#L743" id30s/p>30slass=ia_vt8237_binsecbreakert Message\n&1454">smb >1544#L69" id=30s/p>30s4Assert Message\n&156f">smb 154c#L715" id30s/p>30s5Lrk_via_vt82default:YPASS_APIC_DE1566">smb); ,>1546#L715" id30s/p>30slareturnIA 8237_binse line It's possi07smb; );>154c#L76A 82330s/p>30s7ass=ia_vt8237_binsecreturnert Message\n&1454">smb >1548#L767" id30s/p>30s8Lrk_via_vt82"line" name="L1561">smb) >154c#L713" id30s/p>30s9Lrk_via_vt82resource_0" rtp 759 759DEpic_deassert(&>d="L73"lirtf">D,apic_deassert(&smb );>155)#L713" id30s/p>30s/+cod"line" name="L1561">smb) }>155c#L741" id30s/p>30sELrk_pic_deassert);>>; DEpic_deassert(&D)ert Message\n&1454">smb );>1552#L741" id30s/p>30sLLrk_rt Message\n&1454">smb );>155c#L74A 82330s/p>30slass=rt Message\n&1454">smb >1554#L697" id30s/p>30s4Lrk_"line" in63" id="L733" cla__init/a>(& 759apply9final_>155c#L713" id30s/p>30s5AsseBYPASS_APIC_DE1566">smb); >1556#L715" id30s/p>30slareturnIA 827c#L763" id="L733" class="li/e" name="L759"> 759(&Dert Message\n&1454">smb >155c#L767" id30s/p>30s7Lrk_via_vt82resource_0" rtpu8pci15>);>>; >d="L73c1s+codv= 0ert Message\n&1454">smb >1558#L767" id30s/p>30s8Lrk_via_vt82pic_deassert);>>; tmpf">Dert Message\n&1454">smb >155c#L71A 82330s/p>30s-Assert Message\n&156f">smb >15an#L742" id30s/p>30s/Lrk_via_vt82>(stpic_deassert(&)>156c#L746" id30s/p>30sELrk_via_vt8237_binsepic_deassert>d="L73prin6kf">DEpic_deassert>L759">KERN_DEBUG>smb); {>15a2#L74#endi30s/p>30sLLrk_via_vt8237_binsevia_vt8pic_deassert(&smb ;>156c#L74A 82330s/p>30slass=rt Message\n&1454">smb 8>15a4#L740" id30s/p>30s4Lrk_via_vt82pic_deassert 759apply9fixup_final_(&Dert Message\n&1454">smb >15a5#L74SERT"30s/p>30s5ass=ia_vt823pic_deassertfor_each_ss="li/f">DEpic_deassert(&smb); );>156c#L656" id30s/p>30slareturnIA 8237_binse class="sref">p 759fixup_de_iso/a>(&DEpic_deassert 759fixup_finalLrk_, pic_deassert(&smb 156c#L767" id30s/p>30s7ass=ia_vt8237_binsec"li/e" name="L759"> 75smb; );>1568#L762" id30s/p>30slass="line do thisnearlllllllllllllllll* If arch hasn't set it explicitly yet, use ame CLSa>smb; );>156c#L716" id30s/p>30s9Lrk_"li/e" name="L759"> 75sllllllllllllllll* value shared by all 72 ci_isos. If tmero's aa>smb; 157)#L716" id30s/p>30s/Lrk_"li/e" name="L759"> 75sllllllllllllllll* mismatch, fall back to ame default value.C smb); }>157c#L746" id30s/p>30sELrk_"li/e" name="L759"> 75sllllllllllllllll*/a>smb; iv>1572#L74A 82330"dr>30sLLrk_via_vt8237_binse>(st!" id="L733" cla 759cache_15an_sizo/a>(&smb); ;>157c#L74A 82330s/p>30slass=ia_vt8237_binsec37_binse class="sref">p 759read_config_byte/a>(&DEpic_deassert(&tmpf">D)ert Message\n&1454">smb >1574#L693" id30s/p>30s4ass=ia_vt8237_binseccccccccc>(st!" id="L733" claclnpci15an>>d="L73c1s+codrivers/O 12-19, 22, 23ne" name="L3075f="driv30s/pci15>);>157c#L713" id30s/p>30s5Lrk_via_vt8237_binse_vt82sec37_binse class="sref">pclnpci15an>>d="L73c1s+codv= " id="L733" clatmpe" name="L759">tmpf">Dert Message\n&1454">smb >157c#L653" id30s/p>30slareturnIA 8237_binsecccccccc>(st!" id="L733" clatmpe" name="L759">tmpf">D ||e class="sref">pclnpci15an>>d="L73c1s+codv== " id="L733" clatmpe" name="L759">tmpf">Drivers/O 12-19, 22, 23ne" name="L3077f="driv30s/pci15>);>157c#L763" id30s/p>30s7ass=ia_vt8237_binsec_vt8222222222222continueert Message\n&1454">smb ;>15&15e1"0" id30s/p>30s8Lrk_rt Message\n&1454">smb );>1479#L767" id30s/p>30s9Lrk_via_vt82insecvia_vt82222pic_deassert>d="L73prin6kf">DEpic_deassert>L759">KERN_DEBUG>smb); >148)#L71A 82330s/p>30s/ass=ia_vt8237_binsec_vt822222222222"li/e" name=""dLonboard AC9usonb %u bytes8237 APIC De-As,e class="sref">pclnpci15an>>d="L73c1s+codv<<22,e class="sref">ptmpe" name="L759">tmpf">D <<22,YPASS_APIC_DE1566">smb); );>148c#L741" id30s/p>30sELrk_via_vt8237_binseeeeeeeeevt82222pic_deassert(&smb ;>1482#L741" id30s/p>30sLLrk_via_vt8237_binsevia_vt82ric_deassert(&(&smb );>1483#L741" id30s/p>30slass=ia_vt8237_binsec"line" name="L1561">smb) }>1484#L741" id30s/p>30s4ass=ia_vt823"line" name="L1561">smb) );>148c#L715" id30s/p>30s5Lrk_rt Message\n&1454">smb >1486#L715" id30s/p>30slareturnIA 82>(st!" id="L733" cla 759cache_15an_sizo/a>(&smb); >148c#L767" id30s/p>30s7ass=ia_vt8237_binsec" id="L733" claprin6kpci15an>>d="L73prin6kf">DEpic_deassert>L759">KERN_DEBUG>smb); >1488#L76A 82330s/p>30s8Lrk_via_vt8237_binseccccsec" id="L733" claclnpci15an>>d="L73c1s+codv<<22,e class="sref">pps="lfl9cache_15an_sizo/a>(&smb >1489#L741" id30s/p>30s9Lrk_via_vt82insecviapic_deassert(&>d="L73c1s+codv? pic_deassert>d="L73c1s+codv: pic_deassert(&smb >1490#L741" id30s/p>30s/ass=ia_vt823"line" name="L1561">smb) >149c#L741" id30s/p>30s1Lrk_rt Message\n&1454">smb )>1492#L741" id30s/p>30sLLrk_via_vt82return 0ert Message\n&1454">smb {>149c#L743" id30s/p>30s3+cod"line" name="L1561">smb) ;>1494#L741" id30s/p>30s4Assert Message\n&156f">smb >1495#L741" id30s/p>30s5ef"i"line" name="LEfs_initcall_synce" name="L759">fs_initcall_syncf">DEpic_deassert 759apply9final_smb );>1496#L741" id30s/p>30s6Lrk_rt Message\n&1454">smb ;>149c#L767" id30s/p>30slass="li/e" name="L759"> 75smb; );>1498#L767" id30s/p>30slass="line do thisnearl* Followonbs are ci_iso-specific reset methods which cne be used toa>smb; >149c#L719" id30s/p>30s9Lrk_"li/e" name="L759"> 75s* reset a sonble functionrif otmer methods (e.g. FLR, PM D0e=de"D3) area>smb; >149c#L719" id3100f>3100Lrk_"li/e" name="L759"> 75s* not avail ">P.C smb); >149c#L741" id310/p>310ELrk_"li/e" name="L759"> 75s*/a>smb; )>1492#L741" id310/p>310LLrk_"line" in63" id="L733" clareset9intel_generic"li/e" name="L759">reset9intel_generic"li/f">DE7c#L763" id="L733" class="li/e" name="L759"> 759(&(&Drivers/O 12-19, 22, 23ne" name="L3103f="driv310/pci14a>{>149c#L743" id310/p>310lass=BYPASS_APIC_DE1566">smb); ;>1494#L741" id310/p>3104ass=ia_vt823in63" id="L733" clapoae" name="L759"> oaLrk_ert Message\n&1454">smb >1495#L741" id310/p>3105Lrk_rt Message\n&1454">smb );>1496#L741" id310/p>310lareturnIA 82 line It's possi07smb; ;>149c#L767" id310/p>3107ass=ia_vt823>(stpic_deassert(&pi15anpci15an>>d="L73c15an+codv== " id="L733" cla 722CLASS_SERIAL_USB/a>(&smb); );>1498#L767" id310/p>3108Lrk_via_vt8237_binse" id="L733" clapoae" name="L759"> oaLrk_ = pic_deassert 759find9capabilityf">DEpic_deassert(&smb >149c#L719" id310/p>3109Lrk_via_vt82insecvia>(st!" id="L733" cla oae" name="L759"> oaLrk_rivers/O 12-19, 22, 23ne" name="L3110f="driv31s/pci15a>)>151)#L71A 82331s/p>31s/Lrk_via_vt82insecviavia_vt82return -pic_deassert);>>; smb {>151c#L741" id31s/p>3111Lrk_rt Message\n&1454">smb ;>1512#L741" id31s/p>311LLrk_via_vt8237_binse>(st" id="L733" claprobo/a>(&Drivers/O 12-19, 22, 23ne" name="L3113f="driv31s/pci15a>;>151c#L743" id31s/p>311lass=ia_vt8237_binsec37_binsereturn 0ert Message\n&1454">smb >1514#L697" id31s/p>3114Assert Message\n&156f">smb >151c#L71A 82331s/p>31s5Lrk_via_vt8237_binse" id="L733" cla 759write_config_byte/a>(&DEpic_deassert(& oaLrk_ + 0x4, 1)ert Message\n&1454">smb );>151c#L656" id31s/p>31slareturnIA 8237_binsepic_deassertmsleepf">DE100)ert Message\n&1454">smb 151c#L767" id31s/p>31s7Lrk_rt Message\n&1454">smb );>1518#L762" id31s/p>3118Lrk_via_vt8237_binsereturn 0ert Message\n&1454">smb )>151c#L716" id31s/p>31s9Lrk_via_vt82} else BYPASS_APIC_DE1566">smb); );>152)#L716" id31s/p>31s/Lrk_via_vt8237_binsereturn -pic_deassert);>>; smb 152c#L746" id31s/p>31sELrk_via_vt82"line" name="L1561">smb) }>1522#L746" id31s/p>312LLrk_"line" name="L1561">smb) ,>152c#L746" id31s/p>312lass=rt Message\n&1454">smb );>1524#L696" id31s/p>3124Lrk_"line" in63" id="L733" clareset9intel_82599_sfp_virtfnpci15an>>d="L73reset9intel_82599_sfp_virtfnf">DE7c#L763" id="L733" class="li/e" name="L759"> 759(&(&Drivers/O 12-19, 22, 23ne" name="L31s5f="driv31s/pci15/a>>152c#L716" id31s/p>3125AsseBYPASS_APIC_DE1566">smb); >152c#L65s31slareturnIA 82in63" id="L733" clai/a>(&smb >152c#L76s3127Lrk_via_vt82resource_0" rtpu1/pci15an>>d="L73u1laretgpic_deassert"lituaLrk_ert Message\n&1454">smb 152c#L766" id31s/p>3128Lrk_rt Message\n&1454">smb >152c#L716" id31s/p>3129Lrk_via_vt82rli/e" name="L759"> 75smb; >153)#L716" id31s/p>313/Lrk_"li/e" name="L759"> 75sllllllll* http://www.intel.L75/cont"> /dam/doc/datasheet/82599-10-gbe-controller-datasheet.pd(a>smb; >153c#L746" id31s/p>313ELrk_"li/e" name="L759"> 75sllllllll/a>smb; >1532#L746" id31s/p>31sLLrk_"li/e" name="L759"> 75sllllllll* The 82599 supports FLR on VFs, but FLR support is reported onlya>smb; >153c#L746" id31s/p>31slass="li/e" name="L759"> 75sllllllll* in ame PF DEVCAP (sec 9.3.10.4), not in ame VF DEVCAP (sec 9.5).C smb); >1534#L696" id31s/p>3134ass=pli/e" name="L759"> 75sllllllll* Thes="ore, we cne't use >sme_flr(), which checks ame VF DEVCAP.C smb); >153c#L716" id31s/p>3135Lrk_"li/e" name="L759"> 75sllllllll*/a>smb; >153c#L65s3136Lrk_rt Message\n&1454">smb )>153c#L76A 82331s/p>3137ass=ia_vt823>(stpic_deassert(&Drivers/O 12-19, 22, 23ne" name="L3138f="driv31s/pci15a>{>1538#L76#endi31s/p>31s8Lrk_via_vt8237_binsereturn 0ert Message\n&1454">smb ;>153c#L71A 82331s/p>31s-Assert Message\n&156f">smb 154)#L71#ifde31s/p>31s/Lrk_via_vt82 line It's possi07smb; 154c#L740" id31s/p>31sELrk_via_vt82fors(" id="L733" clai/a>(&(&(&smb); >1542#L74SERT"31s/p>31sLLrk_via_vt8237_binse>(stpic_deassert(&154c#L743" id31s/p>31slass=ia_vt8237_binsecvia_vt82resource_0" rtpmsleepe" name="L759">msleepf">DE(1 <<2(" id="L733" clai/a>(&smb >1544#L69" id=31s/p>31s4Assert Message\n&156f">smb 154c#L715" id31s/p>3145Lrk_via_vt8237_binse" id="L733" cla 75e9capability9read_word/a>(&DEpic_deassert(&"lituaLrk_)ert Message\n&1454">smb ,>1546#L715" id31s/p>31slareturnIA 8237_binse>(st!Epic_deassert"lituaLrk_ge>s_agpic_deassert);>>; );>154c#L76A 82331s/p>31s7ass=ia_vt8237_binsecccccccccgoto pic_deassert(&smb >1548#L767" id31s/p>31s8Lrk_via_vt82"line" name="L1561">smb) >154c#L713" id31s/p>314-Assert Message\n&156f">smb );>155)#L713" id31s/p>315/Lrk_via_vt82 ic_deassert(&DEe>s_apic_deassert(&pci_/a>(&smb); }>155c#L741" id31s/p>315ELrk_via_vt8237_binseeeeeeeeepli/e" name=""dLonboard AC9 roceedonb with reset anyway8237 APIC De-As)ert Message\n&1454">smb );>1552#L741" id31s/p>31sLLrk_rt Message\n&1454">smb );>155c#L74A 82331s/p>31slass=pic_deassert(&smb); >1554#L697" id31s/p>3154Lrk_via_vt82pic_deassert(&DEpic_deassert(&smb >155c#L713" id31s/p>3155Lrk_rt Message\n&1454">smb >1556#L715" id31s/p>31slareturnIA 82pic_deassertmsleepf">DE100)ert Message\n&1454">smb >155c#L767" id31s/p>3157Lrk_rt Message\n&1454">smb >1558#L767" id31s/p>31s8Lrk_via_vt82return 0ert Message\n&1454">smb >155c#L71A 82331s/p>31s-Asse"line" name="L1561">smb) >15an#L742" id31s/p>3160Lrk_rt Message\n&1454">smb )>156c#L746" id31s/p>31sELrk_#include 37 APIC Message\n&1454"gpu/drm/i915/i9159reg.hpci15a>)>f759">.."gpu/drm/i915/i9159reg.hLrk_37 APIrt Message\n&1454">smb {>15a2#L74#endi31s/p>31sLLrk_#def5a22pic_deassert);>>; smb ;>156c#L74A 82331s/p>31slass=#def5a22pic_deassert(&smb 8>15a4#L740" id31s/p>31s4Lrk_#def5a22pic_deassert(&smb; >15a5#L74SERT"31s/p>3165Lrk_rt Message\n&1454">smb );>156c#L656" id31s/p>31slaret"line" in63" id="L733" clareset9ivb_igd/a>(&DE7c#L763" id="L733" class="li/e" name="L759"> 759(&(&Drivers/O 12-19, 22, 23ne" name="L3167f="driv31s/pci15) {>156c#L767" id31s/p>31s7ass=BYPASS_APIC_DE1566">smb); );>1568#L762" id31s/p>3168Lrk_via_vt82nass="_erte_mchf="+c__iomem/a>(&(&smb );>156c#L716" id31s/p>3169Lrk_via_vt82unsigned lonb pic_deassert(&smb 157)#L716" id31s/p>317/Lrk_via_vt82 ic_deassert>d="L73usLLrk_v ic_deassertval>smb }>157c#L746" id31s/p>3171Lrk_rt Message\n&1454">smb iv>1572#L74A 82331"dr>31sLLrk_via_vt82>(stpic_deassert(&Drivers/O 12-19, 22, 23ne" name="L3173f="driv31s/pci15a>;>157c#L74A 82331s/p>31slass=ia_vt8237_binsecreturn 0ert Message\n&1454">smb >1574#L693" id31s/p>3174Assert Message\n&156f">smb );>157c#L713" id31s/p>3175ass=ia_vt823pic_deassert(& 759iomapf">DEpic_deassert(&smb >157c#L653" id31s/p>317lareturnIA 82>(st!" id="L733" clammio_baso/a>(&);>157c#L763" id31s/p>31s7ass=ia_vt8237_binsecreturn -pic_deassert);>>; smb ;>15&15e1"0" id31s/p>31s8Lrk_rt Message\n&1454">smb );>1479#L767" id31s/p>3179Lrk_via_vt82resource_0" rtpiowrites/pci15an>>d="L73iowrites/f">DE0x00000002,e class="sref">pmmio_baso/a>(&);>>; smb >148)#L71A 82331s/p>3180Lrk_rt Message\n&1454">smb );>148c#L741" id31s/p>31sELrk_via_vt82rli/e" name="L759"> 75smb; ;>1482#L741" id31s/p>318LLrk_"li/e" name="L759"> 75sllllllll* ClobbeLonb SOUTH_CHICKEN2cregisterris f5a22only if tme nexta>smb; );>1483#L741" id31s/p>318lass="li/e" name="L759"> 75sllllllll* mme157 loaded sets ame right bits. Howe157, am5s's a reset anda>smb; }>1484#L741" id31s/p>3184ass=pli/e" name="L759"> 75sllllllll* ame bits have been set by i915 previously, so we clobbeLa>smb; );>148c#L715" id31s/p>3185Lrk_"li/e" name="L759"> 75sllllllll* SOUTH_CHICKEN2cregisterrdirectly hes=.C smb); >1486#L715" id31s/p>31slaret"li/e" name="L759"> 75sllllllll*/a>smb; >148c#L767" id31s/p>3187Lrk_via_vt82resource_0" rtpiowrites/pci15an>>d="L73iowrites/f">DE0x00000005,e class="sref">pmmio_baso/a>(&(&smb >1488#L76A 82331s/p>3188Lrk_rt Message\n&1454">smb >1489#L741" id31s/p>3189Lrk_via_vt82resource_0" rtpvale" name="L759">val>>d="L73ioreads/f">DEpic_deassert(&);>>; s_ag0xfffffffeert Message\n&1454">smb >1490#L741" id31s/p>319/Lrk_via_vt82 ic_deassert>d="L73iowrites/f">DEresource_0" rtpvale" name="L759">val>pmmio_baso/a>(&);>>; smb >149c#L741" id31s/p>31s1Lrk_rt Message\n&1454">smb )>1492#L741" id31s/p>31sLLrk_via_vt82pic_deassert(&jiffieaLrk_ +2pic_deassertmsecs_to_jiffieaf">DEresource_0" rtpIGD_OPERATION_TIMEOUT/a>(&smb {>149c#L743" id31s/p>319lass=ia_vt823do BYPASS_APIC_DE1566">smb); ;>1494#L741" id31s/p>3194ass=ia_vt8237_binsecpic_deassertval>>d="L73ioreads/f">DEpic_deassert(&);>>; smb >1495#L741" id31s/p>3195Lrk_via_vt8237_binse>(stEresource_0" rtpvale" name="L759">val>s_ag0xb0000000)v== 0rivers/O 12-19, 22, 23ne" name="L3196f="driv31s/pci14>);>1496#L741" id31s/p>319lareturnIA 8237_binseccccccccgoto pic_deassert(&smb ;>149c#L767" id31s/p>3197ass=ia_vt8237_binsec" id="L733" clamsleepe" name="L759">msleepf">DE10)ert Message\n&1454">smb );>1498#L767" id31s/p>3198Lrk_via_vt82" whilestpic_deassert(&DEpic_deassertjiffieaLrk_,e class="sref">ptimeout/a>(&smb >149c#L719" id31s/p>3199Lrk_via_vt82resource_0" rtpfo<_warn/a>(&DEe>s_apic_deassert(&pci_/a>(&smb >149c#L719" id3200f>3200Lrk_rt Message\n&1454">smb >149c#L741" id320/p>320ELrk_pic_deassert(&smb); )>1492#L741" id320/p>320LLrk_via_vt82pic_deassert>d="L73iowrites/f">DE0x00000002,e class="sref">pmmio_baso/a>(&(&smb {>149c#L743" id320/p>320lass=rt Message\n&1454">smb ;>1494#L741" id320/p>3204Lrk_via_vt82pic_deassert 759iounmapf">DEpic_deassert(&smb >1495#L741" id320/p>3205Lrk_via_vt82return 0ert Message\n&1454">smb );>1496#L741" id320/p>320laret"line" name="L1561">smb) ;>149c#L767" id320/p>3207Lrk_rt Message\n&1454">smb );>1498#L767" id320/p>3208Lrk_#def5a22pic_deassert);>>; smb >149c#L719" id320/p>3209Lrk_#def5a22pic_deassert);>>; smb )>151)#L71A 82332s/p>32s/Lrk_#def5a22pic_deassert);>>; smb {>151c#L741" id32s/p>3211Lrk_rt Message\n&1454">smb ;>1512#L741" id32s/p>321LLrk_"line" const27c#L763" id="L733" class="li/_reset9methodse" name="L759"> 759 759smb); ;>151c#L743" id32s/p>321lass=ia_vt823{2pic_deassert);>>; );>>; smb); >1514#L697" id32s/p>3214ass=ia_vt8237_binsecc" id="L733" clareset9intel_82599_sfp_virtfnpci15an>>d="L73reset9intel_82599_sfp_virtfnf">D },YPASS_APIC_DE1566">smb); >151c#L71A 82332s/p>32s5Lrk_via_vt82{2pic_deassert);>>; );>>; smb); );>151c#L656" id32s/p>32slareturnIA 8237_binsepic_deassert(&D },YPASS_APIC_DE1566">smb); 151c#L767" id32s/p>3217Lrk_via_vt82{2pic_deassert);>>; );>>; smb); );>1518#L762" id32s/p>3218Lrk_via_vt8237_binsepic_deassert(&D },YPASS_APIC_DE1566">smb); )>151c#L716" id32s/p>32s9Lrk_via_vt82{2pic_deassert);>>; );>>; smb); );>152)#L716" id32s/p>32s/Lrk_via_vt8237_binse" id="L733" clareset9intel_generic"li/e" name="L759">reset9intel_generic"li/f">D },YPASS_APIC_DE1566">smb); 152c#L746" id32s/p>32sELrk_via_vt82{ 02"line" name="L1561">smb) }>1522#L746" id32s/p>322LLrk_"ert Message\n&1454">smb ,>152c#L746" id32s/p>322lass=rt Message\n&1454">smb );>1524#L696" id32s/p>3224ass=pli/e" name="L759"> 75smb; >152c#L716" id32s/p>3225Lrk_"li/e" name="L759"> 75s* These ci_iso-specific reset methods are hes= ratmer th/e"in a mme157a>smb; >152c#L65s322laret"li/e" name="L759"> 75s* because when a host2ameigns a ci_iso to a guest2VM, ame host2may needa>smb; >152c#L76s322lass="li/e" name="L759"> 75l* ao reset ame de_iso but robably doesn't have a mme1572forsit.C smb); 152c#L766" id32s/p>322lass="line do thisnearl*/a>smb; >152c#L716" id32s/p>3229Lrk_in63" id="L733" clap759 759DE7c#L763" id="L733" class="li/e" name="L759"> 759(&(&Drivers/O 12-19, 22, 23ne" name="L3230f="driv32s/pci15an>>153)#L716" id32s/p>323/Lrk_BYPASS_APIC_DE1566">smb); >153c#L746" id32s/p>323ELrk_via_vt82const27c#L763" id="L733" class="li/_reset9methodse" name="L759"> 759(&smb >1532#L746" id32s/p>323LLrk_rt Message\n&1454">smb >153c#L746" id32s/p>323lass=ia_vt823fors(" id="L733" clai/a>(& 759(&presete" name="L759">resetf">De3" id="L733" clai/a>(&smb); >1534#L696" id32s/p>3234ass=ia_vt8237_binsec>(stEresource_0" rtpi/a>(&pvendor/a>(&(&pvendor/a>(&smb); >153c#L716" id32s/p>3235Lrk_via_vt8237_binse_vt82resource_0" rtpi/a>(&pvendor/a>(&>d="L73u1laret)pic_deassert);>>; s_ae>s_aYPASS_APIC_DE1566">smb); >153c#L65s323lareturnIA 8237_binseccccEresource_0" rtpi/a>(&pde_iso/a>(&Dv== " id="L733" clali//a>(&pde_iso/a>(&Dv||YPASS_APIC_DE1566">smb); )>153c#L76A 82332s/p>3237ass=ia_vt8237_binseccccccresource_0" rtpi/a>(&pde_iso/a>(&Dv== Eresource_0" rtpu1/pci15an>>d="L73u1laret)pic_deassert);>>; {>1538#L76#endi32s/p>32s8Lrk_via_vt8237_binseeeeeeeeereturn " id="L733" clai/a>(&presete" name="L759">resetf">DEpic_deassert(&DraYPASS_APIC_DE1566">smb); ;>153c#L71A 82332s/p>3239Lrk_via_vt82}YPASS_APIC_DE1566">smb); 154)#L71#ifde32s/p>3240Lrk_rt Message\n&1454">smb 154c#L740" id32s/p>32sELrk_via_vt82return -pic_deassert);>>; smb >1542#L74SERT"32s/p>324LLrk_"line" name="L1561">smb) 154c#L743" id32s/p>324lass=rt Message\n&1454">smb >1544#L69" id=32s/p>3244Lrk_"line" 7c#L763" id="L733" class="li/e" name="L759"> 759(&DE7c#L763" id="L733" class="li/e" name="L759"> 759(&154c#L715" id32s/p>3245AsseBYPASS_APIC_DE1566">smb); ,>1546#L715" id32s/p>324lareturnIA 82>(st!" id="L733" cla 722FUNCpci15>);>>; DEpic_deassert(&pde_fnpci15an>>d="L73de_fnLrk_)rivers/O 12-19, 22, 23ne" name="L3247f="driv32s/pci15>);>154c#L76A 82332s/p>32s7ass=ia_vt8237_binsecreturn " id="L733" cla 759 759DEpic_deassert(&smb); >1548#L767" id32s/p>3248Lrk_rt Message\n&1454">smb >154c#L713" id32s/p>3249Lrk_via_vt82return " id="L733" cla 759get_slote" name="L759"> 759get_slotf">DEpic_deassert(&pbuae" name="L759">buaLrk_,e class="sref">p 722DEVFNpci15>);>>; DEpic_deassert(&DEpic_deassert(&pde_fnpci15an>>d="L73de_fnLrk_),g0)raYPASS_APIC_DE1566">smb); );>155)#L713" id32s/p>325/Lrk_"line" name="L1561">smb) }>155c#L741" id32s/p>3251Lrk_rt Message\n&1454">smb );>1552#L741" id32s/p>325LLrk_"line" const27c#L763" id="L733" class="li/_dma_sourso/a>(&smb); );>155c#L74A 82332s/p>325lass=ia_vt823resource_0" rtpu1/pci15an>>d="L73u1laretcpic_deassert(&smb); >1554#L697" id32s/p>3254Lrk_via_vt82pic_deassert>d="L73u1laretcpic_deassert(&DaYPASS_APIC_DE1566">smb); >155c#L713" id32s/p>3255Lrk_via_vt827c#L763" id="L733" class="li/e" name="L759"> 759(& 759(&smb); >1556#L715" id32s/p>32slaret}3" id="L733" class="li/_dma_sourso/a>(&smb); >155c#L767" id32s/p>3257Lrk_via_vt82rli/e" name="L759"> 75smb; >1558#L767" id32s/p>325lass="line do thisnearlllllllll* https://bugzilla.redhat.L75/show_bug.cgi?"dr605888Lrsmb; >155c#L71A 82332s/p>3259Lrk_"li/e" name="L759"> 75sllllllll/a>smb; >15an#L742" id32s/p>326/Lrk_"li/e" name="L759"> 75sllllllll* Some Ricoh ci_isos use ame functionr0 sourso ID3forsDMA ona>smb; )>156c#L746" id32s/p>326ELrk_"li/e" name="L759"> 75sllllllll/ otmer functions of a multifunctionrci_iso. The DMA ci_isosa>smb; {>15a2#L74#endi32s/p>326LLrk_"li/e" name="L759"> 75sllllllll* is amer="ore functionr0, which will have implications of amea>smb; ;>156c#L74A 82332s/p>326lass="li/e" name="L759"> 75sllllllll* i759u grouponb of amese ci_isos.C smb); 8>15a4#L740" id32s/p>3264ass=pli/e" name="L759"> 75sllllllll*/a>smb; >15a5#L74SERT"32s/p>3265Lrk_via_vt82{2pic_deassert);>>; pps="func_0_dma_sourso/a>(&D },YPASS_APIC_DE1566">smb); );>156c#L656" id32s/p>3266Lrk_via_vt82{2pic_deassert);>>; pps="func_0_dma_sourso/a>(&D },YPASS_APIC_DE1566">smb); 156c#L767" id32s/p>3267Lrk_via_vt82{2pic_deassert);>>; pps="func_0_dma_sourso/a>(&D },YPASS_APIC_DE1566">smb); );>1568#L762" id32s/p>3268Lrk_via_vt82{2pic_deassert);>>; pps="func_0_dma_sourso/a>(&D },YPASS_APIC_DE1566">smb); );>156c#L716" id32s/p>3269Lrk_via_vt82{202"line" name="L1561">smb) 157)#L716" id32s/p>327/Lrk_"ert Message\n&1454">smb }>157c#L746" id32s/p>3271Lrk_rt Message\n&1454">smb iv>1572#L74A 82332"dr>327LLrk_"li/e" name="L759"> 75smb; ;>157c#L74A 82332s/p>327lass="li/e" name="L759"> 75s* IOMMUs with isolation capabilitios need ao be rogra59"d with amea>smb; >1574#L693" id32s/p>3274ass=pli/e" name="L759"> 75s* correct sourso ID3of a ci_iso. In most2cases, ame sourso ID3matchosa>smb; );>157c#L713" id32s/p>3275Lrk_"li/e" name="L759"> 75s* ame de_iso doonb the DMA, but sometimes hardware is broken and willa>smb; >157c#L653" id32s/p>327laret"li/e" name="L759"> 75s* tab the DMA as beonb soursod from a ciffer=ntrci_iso. This functiona>smb; );>157c#L763" id32s/p>327lass="li/e" name="L759"> 75l* allows amat translation. Note amat tme refer=nso countrof amea>smb; ;>15&15e1"0" id32s/p>327lass="line do thisnearl* returnod de_iso is increossied on all paths.C smb); );>1479#L767" id32s/p>3279Lrk_"li/e" name="L759"> 75s*/a>smb; >148)#L71A 82332s/p>3280Lrk_7c#L763" id="L733" class="li/e" name="L759"> 759(&DE7c#L763" id="L733" class="li/e" name="L759"> 759(&);>148c#L741" id32s/p>32sELrk_BYPASS_APIC_DE1566">smb); ;>1482#L741" id32s/p>328LLrk_via_vt82const27c#L763" id="L733" class="li/_dma_sourso/a>(&(&smb );>1483#L741" id32s/p>328lass=rt Message\n&1454">smb }>1484#L741" id32s/p>3284Lrk_via_vt82fors(" id="L733" clai/a>(&(&pfma_sourso/a>(&(&smb); );>148c#L715" id32s/p>3285Lrk_via_vt8237_binse>(stEresource_0" rtpi/a>(&pvendor/a>(&(&pvendor/a>(&smb); >1486#L715" id32s/p>328lareturnIA 8237_binsecccccresource_0" rtpi/a>(&pvendor/a>(&>d="L73u1laret)pic_deassert);>>; s_ae>s_aYPASS_APIC_DE1566">smb); >148c#L767" id32s/p>3287ass=ia_vt8237_binsecccccEresource_0" rtpi/a>(&pde_iso/a>(&Dv== " id="L733" clali//a>(&pde_iso/a>(&Dv||YPASS_APIC_DE1566">smb); >1488#L76A 82332s/p>3288Lrk_via_vt8237_binseeeeeeresource_0" rtpi/a>(&pde_iso/a>(&Dv== Eresource_0" rtpu1/pci15an>>d="L73u1laret)pic_deassert);>>; >1489#L741" id32s/p>3289Lrk_via_vt822222222222222222return " id="L733" clai/a>(&pfma_sourso/a>(&(&smb); >1490#L741" id32s/p>329/Lrk_via_vt82"line" name="L1561">smb) >149c#L741" id32s/p>32s1Lrk_rt Message\n&1454">smb )>1492#L741" id32s/p>32sLLrk_via_vt82return " id="L733" cla 759 759DEpic_deassert(&smb); {>149c#L743" id32s/p>329lass="line" name="L1561">smb) ;>1494#L741" id32s/p>3294Assert Message\n&156f">smb >1495#L741" id32s/p>3295Lrk_"line" const27c#L763" id="L733" class="li/_acs_enabled/a>(&smb); );>1496#L741" id32s/p>329lareturnIA 82resource_0" rtpu1/pci15an>>d="L73u1laretcpic_deassert(&smb); ;>149c#L767" id32s/p>3297Lrk_via_vt82resource_0" rtpu1/pci15an>>d="L73u1laretgpic_deassert(&DaYPASS_APIC_DE1566">smb); );>1498#L767" id32s/p>3298Lrk_via_vt82in63(npic_deassert(& 759(&pu1/pci15an>>d="L73u1laretgpic_deassertacs_flaga+codraYPASS_APIC_DE1566">smb); >149c#L719" id32s/p>3299Lrk_}3" id="L733" class="li/_acs_enabled/a>(&smb); >149c#L719" id3300f>330/Lrk_via_vt82{202"line" name="L1561">smb) >149c#L741" id330/p>330ELrk_"ert Message\n&1454">smb )>1492#L741" id330/p>330LLrk_rt Message\n&1454">smb {>149c#L743" id330/p>330lass=in63" id="L733" clap759(&DE7c#L763" id="L733" class="li/e" name="L759"> 759(&pu1/pci15an>>d="L73u1laretgpic_deassertacs_flaga+codrrt Message\n&1454">smb ;>1494#L741" id330/p>3304Lrk_BYPASS_APIC_DE1566">smb); >1495#L741" id330/p>3305Lrk_via_vt82const27c#L763" id="L733" class="li/_acs_enabled/a>(&(&smb );>1496#L741" id330/p>330lareturnIA 82in63" id="L733" clarete" name="L759">retLrk_ert Message\n&1454">smb ;>149c#L767" id330/p>3307Lrk_rt Message\n&1454">smb );>1498#L767" id330/p>3308Lrk_via_vt82"li/e" name="L759"> 75smb; >149c#L719" id330/p>3309Lrk_"li/e" name="L759"> 75sllllllll/ Allow ci_isos amat do not expose27candard 72e ACS capabilitiosa>smb; )>151)#L71A 82333s/p>331/Lrk_"li/e" name="L759"> 75sllllllll* or control ao indicate ameir support hes=. Multi-functionrexpressa>smb; {>151c#L741" id33s/p>331ELrk_"li/e" name="L759"> 75sllllllll/ ci_isos which do not allow2in6ernal peer-to-peer between functions,a>smb; ;>1512#L741" id33s/p>331LLrk_"li/e" name="L759"> 75sllllllll* but do not impleossi 72e ACS may wish ao return c#Le hes=.C smb); ;>151c#L743" id33s/p>331lass="li/e" name="L759"> 75sllllllll*/a>smb; >1514#L697" id33s/p>3314Lrk_via_vt82fors(" id="L733" clai/a>(&(&pacs_enabled/a>(&(&smb); >151c#L71A 82333s/p>3315Lrk_via_vt8237_binse>(stEresource_0" rtpi/a>(&pvendor/a>(&(&pvendor/a>(&smb); );>151c#L656" id33s/p>33slareturnIA 8237_binse_vt82resource_0" rtpi/a>(&pvendor/a>(&>d="L73u1laret)pic_deassert);>>; s_ae>s_aYPASS_APIC_DE1566">smb); 151c#L767" id33s/p>3317ass=ia_vt8237_binsecccccEresource_0" rtpi/a>(&pde_iso/a>(&Dv== " id="L733" clali//a>(&pde_iso/a>(&Dv||YPASS_APIC_DE1566">smb); );>1518#L762" id33s/p>3318Lrk_via_vt8237_binse_vt82resource_0" rtpi/a>(&pde_iso/a>(&Dv== Eresource_0" rtpu1/pci15an>>d="L73u1laret)pic_deassert);>>; smb); )>151c#L716" id33s/p>3319Lrk_via_vt822222222222222222" id="L733" clarete" name="L759">retLrk_ = pic_deassert(&pacs_enabled/a>(&(&acs_flaga+codraYPASS_APIC_DE1566">smb); );>152)#L716" id33s/p>33s/Lrk_via_vt8237_binse37_binse>(st" id="L733" clarete" name="L759">retLrk_ =de"= 0rivers/O 12-19, 22, 23ne" name="L33s1f="driv33s/pci15 }>152c#L746" id33s/p>332ELrk_via_vt8237_binseeeeeeeeeeeeeeeeereturn " id="L733" clarete" name="L759">retLrk_ert Message\n&1454">smb }>1522#L746" id33s/p>332LLrk_via_vt8237_binse"line" name="L1561">smb) ,>152c#L746" id33s/p>332lass=ia_vt823"line" name="L1561">smb) );>1524#L696" id33s/p>3324Assert Message\n&156f">smb >152c#L716" id33s/p>3325Lrk_via_vt82return -pic_deassert);>>; smb >152c#L65s332laret"line" name="L1561">smb) >152c#L76s332lass="/pre="/div> "/div> >foo6er"> The original LXR software by tme ine" namehttp://soursoforge.net/projects/lxr">LXR L759unity+cod,gam5srexperi9"> al 1561ionrby ine" namemailto:lxr@152ux.no">lxr@152ux.no+cod. "/div> >subfoo6er"> lxr.152ux.no kindly hosied by ine" namehttp://www.redpill-152pro.no">Redpill L52pro AS+cod,gprovider of L52ux2consulting and operations ser_isos sinso 1995. "/div>