linux/drivers/gpio/gpio-tegra.c
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   1/*
   2 * arch/arm/mach-tegra/gpio.c
   3 *
   4 * Copyright (c) 2010 Google, Inc
   5 *
   6 * Author:
   7 *      Erik Gilling <konkers@google.com>
   8 *
   9 * This software is licensed under the terms of the GNU General Public
  10 * License version 2, as published by the Free Software Foundation, and
  11 * may be copied, distributed, and modified under those terms.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 */
  19
  20#include <linux/init.h>
  21#include <linux/irq.h>
  22#include <linux/interrupt.h>
  23#include <linux/io.h>
  24#include <linux/gpio.h>
  25#include <linux/of_device.h>
  26#include <linux/platform_device.h>
  27#include <linux/module.h>
  28#include <linux/irqdomain.h>
  29#include <linux/pinctrl/consumer.h>
  30#include <linux/pm.h>
  31
  32#include <asm/mach/irq.h>
  33
  34#define GPIO_BANK(x)            ((x) >> 5)
  35#define GPIO_PORT(x)            (((x) >> 3) & 0x3)
  36#define GPIO_BIT(x)             ((x) & 0x7)
  37
  38#define GPIO_REG(x)             (GPIO_BANK(x) * tegra_gpio_bank_stride + \
  39                                        GPIO_PORT(x) * 4)
  40
  41#define GPIO_CNF(x)             (GPIO_REG(x) + 0x00)
  42#define GPIO_OE(x)              (GPIO_REG(x) + 0x10)
  43#define GPIO_OUT(x)             (GPIO_REG(x) + 0X20)
  44#define GPIO_IN(x)              (GPIO_REG(x) + 0x30)
  45#define GPIO_INT_STA(x)         (GPIO_REG(x) + 0x40)
  46#define GPIO_INT_ENB(x)         (GPIO_REG(x) + 0x50)
  47#define GPIO_INT_LVL(x)         (GPIO_REG(x) + 0x60)
  48#define GPIO_INT_CLR(x)         (GPIO_REG(x) + 0x70)
  49
  50#define GPIO_MSK_CNF(x)         (GPIO_REG(x) + tegra_gpio_upper_offset + 0x00)
  51#define GPIO_MSK_OE(x)          (GPIO_REG(x) + tegra_gpio_upper_offset + 0x10)
  52#define GPIO_MSK_OUT(x)         (GPIO_REG(x) + tegra_gpio_upper_offset + 0X20)
  53#define GPIO_MSK_INT_STA(x)     (GPIO_REG(x) + tegra_gpio_upper_offset + 0x40)
  54#define GPIO_MSK_INT_ENB(x)     (GPIO_REG(x) + tegra_gpio_upper_offset + 0x50)
  55#define GPIO_MSK_INT_LVL(x)     (GPIO_REG(x) + tegra_gpio_upper_offset + 0x60)
  56
  57#define GPIO_INT_LVL_MASK               0x010101
  58#define GPIO_INT_LVL_EDGE_RISING        0x000101
  59#define GPIO_INT_LVL_EDGE_FALLING       0x000100
  60#define GPIO_INT_LVL_EDGE_BOTH          0x010100
  61#define GPIO_INT_LVL_LEVEL_HIGH         0x000001
  62#define GPIO_INT_LVL_LEVEL_LOW          0x000000
  63
  64struct tegra_gpio_bank {
  65        int bank;
  66        int irq;
  67        spinlock_t lvl_lock[4];
  68#ifdef CONFIG_PM_SLEEP
  69        u32 cnf[4];
  70        u32 out[4];
  71        u32 oe[4];
  72        u32 int_enb[4];
  73        u32 int_lvl[4];
  74#endif
  75};
  76
  77static struct irq_domain *irq_domain;
  78static void __iomem *regs;
  79static u32 tegra_gpio_bank_count;
  80static u32 tegra_gpio_bank_stride;
  81static u32 tegra_gpio_upper_offset;
  82static struct tegra_gpio_bank *tegra_gpio_banks;
  83
  84static inline void tegra_gpio_writel(u32 val, u32 reg)
  85{
  86        __raw_writel(val, regs + reg);
  87}
  88
  89static inline u32 tegra_gpio_readl(u32 reg)
  90{
  91        return __raw_readl(regs + reg);
  92}
  93
  94static int tegra_gpio_compose(int bank, int port, int bit)
  95{
  96        return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
  97}
  98
  99static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
 100{
 101        u32 val;
 102
 103        val = 0x100 << GPIO_BIT(gpio);
 104        if (value)
 105                val |= 1 << GPIO_BIT(gpio);
 106        tegra_gpio_writel(val, reg);
 107}
 108
 109static void tegra_gpio_enable(int gpio)
 110{
 111        tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
 112}
 113
 114static void tegra_gpio_disable(int gpio)
 115{
 116        tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
 117}
 118
 119static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
 120{
 121        return pinctrl_request_gpio(offset);
 122}
 123
 124static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
 125{
 126        pinctrl_free_gpio(offset);
 127        tegra_gpio_disable(offset);
 128}
 129
 130static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 131{
 132        tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
 133}
 134
 135static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
 136{
 137        /* If gpio is in output mode then read from the out value */
 138        if ((tegra_gpio_readl(GPIO_OE(offset)) >> GPIO_BIT(offset)) & 1)
 139                return (tegra_gpio_readl(GPIO_OUT(offset)) >>
 140                                GPIO_BIT(offset)) & 0x1;
 141
 142        return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
 143}
 144
 145static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 146{
 147        tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
 148        tegra_gpio_enable(offset);
 149        return 0;
 150}
 151
 152static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 153                                        int value)
 154{
 155        tegra_gpio_set(chip, offset, value);
 156        tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
 157        tegra_gpio_enable(offset);
 158        return 0;
 159}
 160
 161static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 162{
 163        return irq_find_mapping(irq_domain, offset);
 164}
 165
 166static struct gpio_chip tegra_gpio_chip = {
 167        .label                  = "tegra-gpio",
 168        .request                = tegra_gpio_request,
 169        .free                   = tegra_gpio_free,
 170        .direction_input        = tegra_gpio_direction_input,
 171        .get                    = tegra_gpio_get,
 172        .direction_output       = tegra_gpio_direction_output,
 173        .set                    = tegra_gpio_set,
 174        .to_irq                 = tegra_gpio_to_irq,
 175        .base                   = 0,
 176};
 177
 178static void tegra_gpio_irq_ack(struct irq_data *d)
 179{
 180        int gpio = d->hwirq;
 181
 182        tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
 183}
 184
 185static void tegra_gpio_irq_mask(struct irq_data *d)
 186{
 187        int gpio = d->hwirq;
 188
 189        tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
 190}
 191
 192static void tegra_gpio_irq_unmask(struct irq_data *d)
 193{
 194        int gpio = d->hwirq;
 195
 196        tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
 197}
 198
 199static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 200{
 201        int gpio = d->hwirq;
 202        struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
 203        int port = GPIO_PORT(gpio);
 204        int lvl_type;
 205        int val;
 206        unsigned long flags;
 207
 208        switch (type & IRQ_TYPE_SENSE_MASK) {
 209        case IRQ_TYPE_EDGE_RISING:
 210                lvl_type = GPIO_INT_LVL_EDGE_RISING;
 211                break;
 212
 213        case IRQ_TYPE_EDGE_FALLING:
 214                lvl_type = GPIO_INT_LVL_EDGE_FALLING;
 215                break;
 216
 217        case IRQ_TYPE_EDGE_BOTH:
 218                lvl_type = GPIO_INT_LVL_EDGE_BOTH;
 219                break;
 220
 221        case IRQ_TYPE_LEVEL_HIGH:
 222                lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
 223                break;
 224
 225        case IRQ_TYPE_LEVEL_LOW:
 226                lvl_type = GPIO_INT_LVL_LEVEL_LOW;
 227                break;
 228
 229        default:
 230                return -EINVAL;
 231        }
 232
 233        spin_lock_irqsave(&bank->lvl_lock[port], flags);
 234
 235        val = tegra_gpio_readl(GPIO_INT_LVL(gpio));
 236        val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
 237        val |= lvl_type << GPIO_BIT(gpio);
 238        tegra_gpio_writel(val, GPIO_INT_LVL(gpio));
 239
 240        spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
 241
 242        tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
 243        tegra_gpio_enable(gpio);
 244
 245        if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 246                __irq_set_handler_locked(d->irq, handle_level_irq);
 247        else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 248                __irq_set_handler_locked(d->irq, handle_edge_irq);
 249
 250        return 0;
 251}
 252
 253static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 254{
 255        struct tegra_gpio_bank *bank;
 256        int port;
 257        int pin;
 258        int unmasked = 0;
 259        struct irq_chip *chip = irq_desc_get_chip(desc);
 260
 261        chained_irq_enter(chip, desc);
 262
 263        bank = irq_get_handler_data(irq);
 264
 265        for (port = 0; port < 4; port++) {
 266                int gpio = tegra_gpio_compose(bank->bank, port, 0);
 267                unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) &
 268                        tegra_gpio_readl(GPIO_INT_ENB(gpio));
 269                u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio));
 270
 271                for_each_set_bit(pin, &sta, 8) {
 272                        tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio));
 273
 274                        /* if gpio is edge triggered, clear condition
 275                         * before executing the hander so that we don't
 276                         * miss edges
 277                         */
 278                        if (lvl & (0x100 << pin)) {
 279                                unmasked = 1;
 280                                chained_irq_exit(chip, desc);
 281                        }
 282
 283                        generic_handle_irq(gpio_to_irq(gpio + pin));
 284                }
 285        }
 286
 287        if (!unmasked)
 288                chained_irq_exit(chip, desc);
 289
 290}
 291
 292#ifdef CONFIG_PM_SLEEP
 293static int tegra_gpio_resume(struct device *dev)
 294{
 295        unsigned long flags;
 296        int b;
 297        int p;
 298
 299        local_irq_save(flags);
 300
 301        for (b = 0; b < tegra_gpio_bank_count; b++) {
 302                struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
 303
 304                for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
 305                        unsigned int gpio = (b<<5) | (p<<3);
 306                        tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio));
 307                        tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio));
 308                        tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio));
 309                        tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
 310                        tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
 311                }
 312        }
 313
 314        local_irq_restore(flags);
 315        return 0;
 316}
 317
 318static int tegra_gpio_suspend(struct device *dev)
 319{
 320        unsigned long flags;
 321        int b;
 322        int p;
 323
 324        local_irq_save(flags);
 325        for (b = 0; b < tegra_gpio_bank_count; b++) {
 326                struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
 327
 328                for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
 329                        unsigned int gpio = (b<<5) | (p<<3);
 330                        bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio));
 331                        bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio));
 332                        bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
 333                        bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
 334                        bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
 335                }
 336        }
 337        local_irq_restore(flags);
 338        return 0;
 339}
 340
 341static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
 342{
 343        struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
 344        return irq_set_irq_wake(bank->irq, enable);
 345}
 346#endif
 347
 348static struct irq_chip tegra_gpio_irq_chip = {
 349        .name           = "GPIO",
 350        .irq_ack        = tegra_gpio_irq_ack,
 351        .irq_mask       = tegra_gpio_irq_mask,
 352        .irq_unmask     = tegra_gpio_irq_unmask,
 353        .irq_set_type   = tegra_gpio_irq_set_type,
 354#ifdef CONFIG_PM_SLEEP
 355        .irq_set_wake   = tegra_gpio_wake_enable,
 356#endif
 357};
 358
 359static const struct dev_pm_ops tegra_gpio_pm_ops = {
 360        SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
 361};
 362
 363struct tegra_gpio_soc_config {
 364        u32 bank_stride;
 365        u32 upper_offset;
 366};
 367
 368static struct tegra_gpio_soc_config tegra20_gpio_config = {
 369        .bank_stride = 0x80,
 370        .upper_offset = 0x800,
 371};
 372
 373static struct tegra_gpio_soc_config tegra30_gpio_config = {
 374        .bank_stride = 0x100,
 375        .upper_offset = 0x80,
 376};
 377
 378static struct of_device_id tegra_gpio_of_match[] = {
 379        { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
 380        { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
 381        { },
 382};
 383
 384/* This lock class tells lockdep that GPIO irqs are in a different
 385 * category than their parents, so it won't report false recursion.
 386 */
 387static struct lock_class_key gpio_lock_class;
 388
 389static int tegra_gpio_probe(struct platform_device *pdev)
 390{
 391        const struct of_device_id *match;
 392        struct tegra_gpio_soc_config *config;
 393        struct resource *res;
 394        struct tegra_gpio_bank *bank;
 395        int gpio;
 396        int i;
 397        int j;
 398
 399        match = of_match_device(tegra_gpio_of_match, &pdev->dev);
 400        if (match)
 401                config = (struct tegra_gpio_soc_config *)match->data;
 402        else
 403                config = &tegra20_gpio_config;
 404
 405        tegra_gpio_bank_stride = config->bank_stride;
 406        tegra_gpio_upper_offset = config->upper_offset;
 407
 408        for (;;) {
 409                res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count);
 410                if (!res)
 411                        break;
 412                tegra_gpio_bank_count++;
 413        }
 414        if (!tegra_gpio_bank_count) {
 415                dev_err(&pdev->dev, "Missing IRQ resource\n");
 416                return -ENODEV;
 417        }
 418
 419        tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32;
 420
 421        tegra_gpio_banks = devm_kzalloc(&pdev->dev,
 422                        tegra_gpio_bank_count * sizeof(*tegra_gpio_banks),
 423                        GFP_KERNEL);
 424        if (!tegra_gpio_banks) {
 425                dev_err(&pdev->dev, "Couldn't allocate bank structure\n");
 426                return -ENODEV;
 427        }
 428
 429        irq_domain = irq_domain_add_linear(pdev->dev.of_node,
 430                                           tegra_gpio_chip.ngpio,
 431                                           &irq_domain_simple_ops, NULL);
 432        if (!irq_domain)
 433                return -ENODEV;
 434
 435        for (i = 0; i < tegra_gpio_bank_count; i++) {
 436                res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
 437                if (!res) {
 438                        dev_err(&pdev->dev, "Missing IRQ resource\n");
 439                        return -ENODEV;
 440                }
 441
 442                bank = &tegra_gpio_banks[i];
 443                bank->bank = i;
 444                bank->irq = res->start;
 445        }
 446
 447        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 448        if (!res) {
 449                dev_err(&pdev->dev, "Missing MEM resource\n");
 450                return -ENODEV;
 451        }
 452
 453        regs = devm_request_and_ioremap(&pdev->dev, res);
 454        if (!regs) {
 455                dev_err(&pdev->dev, "Couldn't ioremap regs\n");
 456                return -ENODEV;
 457        }
 458
 459        for (i = 0; i < tegra_gpio_bank_count; i++) {
 460                for (j = 0; j < 4; j++) {
 461                        int gpio = tegra_gpio_compose(i, j, 0);
 462                        tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
 463                }
 464        }
 465
 466#ifdef CONFIG_OF_GPIO
 467        tegra_gpio_chip.of_node = pdev->dev.of_node;
 468#endif
 469
 470        gpiochip_add(&tegra_gpio_chip);
 471
 472        for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) {
 473                int irq = irq_create_mapping(irq_domain, gpio);
 474                /* No validity check; all Tegra GPIOs are valid IRQs */
 475
 476                bank = &tegra_gpio_banks[GPIO_BANK(gpio)];
 477
 478                irq_set_lockdep_class(irq, &gpio_lock_class);
 479                irq_set_chip_data(irq, bank);
 480                irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
 481                                         handle_simple_irq);
 482                set_irq_flags(irq, IRQF_VALID);
 483        }
 484
 485        for (i = 0; i < tegra_gpio_bank_count; i++) {
 486                bank = &tegra_gpio_banks[i];
 487
 488                irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
 489                irq_set_handler_data(bank->irq, bank);
 490
 491                for (j = 0; j < 4; j++)
 492                        spin_lock_init(&bank->lvl_lock[j]);
 493        }
 494
 495        return 0;
 496}
 497
 498static struct platform_driver tegra_gpio_driver = {
 499        .driver         = {
 500                .name   = "tegra-gpio",
 501                .owner  = THIS_MODULE,
 502                .pm     = &tegra_gpio_pm_ops,
 503                .of_match_table = tegra_gpio_of_match,
 504        },
 505        .probe          = tegra_gpio_probe,
 506};
 507
 508static int __init tegra_gpio_init(void)
 509{
 510        return platform_driver_register(&tegra_gpio_driver);
 511}
 512postcore_initcall(tegra_gpio_init);
 513
 514#ifdef  CONFIG_DEBUG_FS
 515
 516#include <linux/debugfs.h>
 517#include <linux/seq_file.h>
 518
 519static int dbg_gpio_show(struct seq_file *s, void *unused)
 520{
 521        int i;
 522        int j;
 523
 524        for (i = 0; i < tegra_gpio_bank_count; i++) {
 525                for (j = 0; j < 4; j++) {
 526                        int gpio = tegra_gpio_compose(i, j, 0);
 527                        seq_printf(s,
 528                                "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
 529                                i, j,
 530                                tegra_gpio_readl(GPIO_CNF(gpio)),
 531                                tegra_gpio_readl(GPIO_OE(gpio)),
 532                                tegra_gpio_readl(GPIO_OUT(gpio)),
 533                                tegra_gpio_readl(GPIO_IN(gpio)),
 534                                tegra_gpio_readl(GPIO_INT_STA(gpio)),
 535                                tegra_gpio_readl(GPIO_INT_ENB(gpio)),
 536                                tegra_gpio_readl(GPIO_INT_LVL(gpio)));
 537                }
 538        }
 539        return 0;
 540}
 541
 542static int dbg_gpio_open(struct inode *inode, struct file *file)
 543{
 544        return single_open(file, dbg_gpio_show, &inode->i_private);
 545}
 546
 547static const struct file_operations debug_fops = {
 548        .open           = dbg_gpio_open,
 549        .read           = seq_read,
 550        .llseek         = seq_lseek,
 551        .release        = single_release,
 552};
 553
 554static int __init tegra_gpio_debuginit(void)
 555{
 556        (void) debugfs_create_file("tegra_gpio", S_IRUGO,
 557                                        NULL, NULL, &debug_fops);
 558        return 0;
 559}
 560late_initcall(tegra_gpio_debuginit);
 561#endif
 562
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