linux/drivers/gpio/gpio-lpc32xx.c
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   1/*
   2 * GPIO driver for LPC32xx SoC
   3 *
   4 * Author: Kevin Wells <kevin.wells@nxp.com>
   5 *
   6 * Copyright (C) 2010 NXP Semiconductors
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License as published by
  10 * the Free Software Foundation; either version 2 of the License, or
  11 * (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 */
  18
  19#include <linux/kernel.h>
  20#include <linux/init.h>
  21#include <linux/io.h>
  22#include <linux/errno.h>
  23#include <linux/gpio.h>
  24#include <linux/of_gpio.h>
  25#include <linux/platform_device.h>
  26#include <linux/module.h>
  27
  28#include <mach/hardware.h>
  29#include <mach/platform.h>
  30#include <mach/gpio-lpc32xx.h>
  31#include <mach/irqs.h>
  32
  33#define LPC32XX_GPIO_P3_INP_STATE               _GPREG(0x000)
  34#define LPC32XX_GPIO_P3_OUTP_SET                _GPREG(0x004)
  35#define LPC32XX_GPIO_P3_OUTP_CLR                _GPREG(0x008)
  36#define LPC32XX_GPIO_P3_OUTP_STATE              _GPREG(0x00C)
  37#define LPC32XX_GPIO_P2_DIR_SET                 _GPREG(0x010)
  38#define LPC32XX_GPIO_P2_DIR_CLR                 _GPREG(0x014)
  39#define LPC32XX_GPIO_P2_DIR_STATE               _GPREG(0x018)
  40#define LPC32XX_GPIO_P2_INP_STATE               _GPREG(0x01C)
  41#define LPC32XX_GPIO_P2_OUTP_SET                _GPREG(0x020)
  42#define LPC32XX_GPIO_P2_OUTP_CLR                _GPREG(0x024)
  43#define LPC32XX_GPIO_P2_MUX_SET                 _GPREG(0x028)
  44#define LPC32XX_GPIO_P2_MUX_CLR                 _GPREG(0x02C)
  45#define LPC32XX_GPIO_P2_MUX_STATE               _GPREG(0x030)
  46#define LPC32XX_GPIO_P0_INP_STATE               _GPREG(0x040)
  47#define LPC32XX_GPIO_P0_OUTP_SET                _GPREG(0x044)
  48#define LPC32XX_GPIO_P0_OUTP_CLR                _GPREG(0x048)
  49#define LPC32XX_GPIO_P0_OUTP_STATE              _GPREG(0x04C)
  50#define LPC32XX_GPIO_P0_DIR_SET                 _GPREG(0x050)
  51#define LPC32XX_GPIO_P0_DIR_CLR                 _GPREG(0x054)
  52#define LPC32XX_GPIO_P0_DIR_STATE               _GPREG(0x058)
  53#define LPC32XX_GPIO_P1_INP_STATE               _GPREG(0x060)
  54#define LPC32XX_GPIO_P1_OUTP_SET                _GPREG(0x064)
  55#define LPC32XX_GPIO_P1_OUTP_CLR                _GPREG(0x068)
  56#define LPC32XX_GPIO_P1_OUTP_STATE              _GPREG(0x06C)
  57#define LPC32XX_GPIO_P1_DIR_SET                 _GPREG(0x070)
  58#define LPC32XX_GPIO_P1_DIR_CLR                 _GPREG(0x074)
  59#define LPC32XX_GPIO_P1_DIR_STATE               _GPREG(0x078)
  60
  61#define GPIO012_PIN_TO_BIT(x)                   (1 << (x))
  62#define GPIO3_PIN_TO_BIT(x)                     (1 << ((x) + 25))
  63#define GPO3_PIN_TO_BIT(x)                      (1 << (x))
  64#define GPIO012_PIN_IN_SEL(x, y)                (((x) >> (y)) & 1)
  65#define GPIO3_PIN_IN_SHIFT(x)                   ((x) == 5 ? 24 : 10 + (x))
  66#define GPIO3_PIN_IN_SEL(x, y)                  (((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1)
  67#define GPIO3_PIN5_IN_SEL(x)                    (((x) >> 24) & 1)
  68#define GPI3_PIN_IN_SEL(x, y)                   (((x) >> (y)) & 1)
  69#define GPO3_PIN_IN_SEL(x, y)                   (((x) >> (y)) & 1)
  70
  71struct gpio_regs {
  72        void __iomem *inp_state;
  73        void __iomem *outp_state;
  74        void __iomem *outp_set;
  75        void __iomem *outp_clr;
  76        void __iomem *dir_set;
  77        void __iomem *dir_clr;
  78};
  79
  80/*
  81 * GPIO names
  82 */
  83static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = {
  84        "p0.0", "p0.1", "p0.2", "p0.3",
  85        "p0.4", "p0.5", "p0.6", "p0.7"
  86};
  87
  88static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = {
  89        "p1.0", "p1.1", "p1.2", "p1.3",
  90        "p1.4", "p1.5", "p1.6", "p1.7",
  91        "p1.8", "p1.9", "p1.10", "p1.11",
  92        "p1.12", "p1.13", "p1.14", "p1.15",
  93        "p1.16", "p1.17", "p1.18", "p1.19",
  94        "p1.20", "p1.21", "p1.22", "p1.23",
  95};
  96
  97static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = {
  98        "p2.0", "p2.1", "p2.2", "p2.3",
  99        "p2.4", "p2.5", "p2.6", "p2.7",
 100        "p2.8", "p2.9", "p2.10", "p2.11",
 101        "p2.12"
 102};
 103
 104static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = {
 105        "gpio00", "gpio01", "gpio02", "gpio03",
 106        "gpio04", "gpio05"
 107};
 108
 109static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = {
 110        "gpi00", "gpi01", "gpi02", "gpi03",
 111        "gpi04", "gpi05", "gpi06", "gpi07",
 112        "gpi08", "gpi09",  NULL,    NULL,
 113         NULL,    NULL,    NULL,   "gpi15",
 114        "gpi16", "gpi17", "gpi18", "gpi19",
 115        "gpi20", "gpi21", "gpi22", "gpi23",
 116        "gpi24", "gpi25", "gpi26", "gpi27",
 117        "gpi28"
 118};
 119
 120static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = {
 121        "gpo00", "gpo01", "gpo02", "gpo03",
 122        "gpo04", "gpo05", "gpo06", "gpo07",
 123        "gpo08", "gpo09", "gpo10", "gpo11",
 124        "gpo12", "gpo13", "gpo14", "gpo15",
 125        "gpo16", "gpo17", "gpo18", "gpo19",
 126        "gpo20", "gpo21", "gpo22", "gpo23"
 127};
 128
 129static struct gpio_regs gpio_grp_regs_p0 = {
 130        .inp_state      = LPC32XX_GPIO_P0_INP_STATE,
 131        .outp_set       = LPC32XX_GPIO_P0_OUTP_SET,
 132        .outp_clr       = LPC32XX_GPIO_P0_OUTP_CLR,
 133        .dir_set        = LPC32XX_GPIO_P0_DIR_SET,
 134        .dir_clr        = LPC32XX_GPIO_P0_DIR_CLR,
 135};
 136
 137static struct gpio_regs gpio_grp_regs_p1 = {
 138        .inp_state      = LPC32XX_GPIO_P1_INP_STATE,
 139        .outp_set       = LPC32XX_GPIO_P1_OUTP_SET,
 140        .outp_clr       = LPC32XX_GPIO_P1_OUTP_CLR,
 141        .dir_set        = LPC32XX_GPIO_P1_DIR_SET,
 142        .dir_clr        = LPC32XX_GPIO_P1_DIR_CLR,
 143};
 144
 145static struct gpio_regs gpio_grp_regs_p2 = {
 146        .inp_state      = LPC32XX_GPIO_P2_INP_STATE,
 147        .outp_set       = LPC32XX_GPIO_P2_OUTP_SET,
 148        .outp_clr       = LPC32XX_GPIO_P2_OUTP_CLR,
 149        .dir_set        = LPC32XX_GPIO_P2_DIR_SET,
 150        .dir_clr        = LPC32XX_GPIO_P2_DIR_CLR,
 151};
 152
 153static struct gpio_regs gpio_grp_regs_p3 = {
 154        .inp_state      = LPC32XX_GPIO_P3_INP_STATE,
 155        .outp_state     = LPC32XX_GPIO_P3_OUTP_STATE,
 156        .outp_set       = LPC32XX_GPIO_P3_OUTP_SET,
 157        .outp_clr       = LPC32XX_GPIO_P3_OUTP_CLR,
 158        .dir_set        = LPC32XX_GPIO_P2_DIR_SET,
 159        .dir_clr        = LPC32XX_GPIO_P2_DIR_CLR,
 160};
 161
 162struct lpc32xx_gpio_chip {
 163        struct gpio_chip        chip;
 164        struct gpio_regs        *gpio_grp;
 165};
 166
 167static inline struct lpc32xx_gpio_chip *to_lpc32xx_gpio(
 168        struct gpio_chip *gpc)
 169{
 170        return container_of(gpc, struct lpc32xx_gpio_chip, chip);
 171}
 172
 173static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
 174        unsigned pin, int input)
 175{
 176        if (input)
 177                __raw_writel(GPIO012_PIN_TO_BIT(pin),
 178                        group->gpio_grp->dir_clr);
 179        else
 180                __raw_writel(GPIO012_PIN_TO_BIT(pin),
 181                        group->gpio_grp->dir_set);
 182}
 183
 184static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
 185        unsigned pin, int input)
 186{
 187        u32 u = GPIO3_PIN_TO_BIT(pin);
 188
 189        if (input)
 190                __raw_writel(u, group->gpio_grp->dir_clr);
 191        else
 192                __raw_writel(u, group->gpio_grp->dir_set);
 193}
 194
 195static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
 196        unsigned pin, int high)
 197{
 198        if (high)
 199                __raw_writel(GPIO012_PIN_TO_BIT(pin),
 200                        group->gpio_grp->outp_set);
 201        else
 202                __raw_writel(GPIO012_PIN_TO_BIT(pin),
 203                        group->gpio_grp->outp_clr);
 204}
 205
 206static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
 207        unsigned pin, int high)
 208{
 209        u32 u = GPIO3_PIN_TO_BIT(pin);
 210
 211        if (high)
 212                __raw_writel(u, group->gpio_grp->outp_set);
 213        else
 214                __raw_writel(u, group->gpio_grp->outp_clr);
 215}
 216
 217static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
 218        unsigned pin, int high)
 219{
 220        if (high)
 221                __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
 222        else
 223                __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
 224}
 225
 226static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
 227        unsigned pin)
 228{
 229        return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
 230                pin);
 231}
 232
 233static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
 234        unsigned pin)
 235{
 236        int state = __raw_readl(group->gpio_grp->inp_state);
 237
 238        /*
 239         * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
 240         * to bits 10..14, while GPIOP3-5 is mapped to bit 24.
 241         */
 242        return GPIO3_PIN_IN_SEL(state, pin);
 243}
 244
 245static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
 246        unsigned pin)
 247{
 248        return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
 249}
 250
 251static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
 252        unsigned pin)
 253{
 254        return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin);
 255}
 256
 257/*
 258 * GENERIC_GPIO primitives.
 259 */
 260static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip,
 261        unsigned pin)
 262{
 263        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
 264
 265        __set_gpio_dir_p012(group, pin, 1);
 266
 267        return 0;
 268}
 269
 270static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip,
 271        unsigned pin)
 272{
 273        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
 274
 275        __set_gpio_dir_p3(group, pin, 1);
 276
 277        return 0;
 278}
 279
 280static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip,
 281        unsigned pin)
 282{
 283        return 0;
 284}
 285
 286static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin)
 287{
 288        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
 289
 290        return __get_gpio_state_p012(group, pin);
 291}
 292
 293static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin)
 294{
 295        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
 296
 297        return __get_gpio_state_p3(group, pin);
 298}
 299
 300static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin)
 301{
 302        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
 303
 304        return __get_gpi_state_p3(group, pin);
 305}
 306
 307static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin,
 308        int value)
 309{
 310        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
 311
 312        __set_gpio_level_p012(group, pin, value);
 313        __set_gpio_dir_p012(group, pin, 0);
 314
 315        return 0;
 316}
 317
 318static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin,
 319        int value)
 320{
 321        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
 322
 323        __set_gpio_level_p3(group, pin, value);
 324        __set_gpio_dir_p3(group, pin, 0);
 325
 326        return 0;
 327}
 328
 329static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin,
 330        int value)
 331{
 332        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
 333
 334        __set_gpo_level_p3(group, pin, value);
 335        return 0;
 336}
 337
 338static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin,
 339        int value)
 340{
 341        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
 342
 343        __set_gpio_level_p012(group, pin, value);
 344}
 345
 346static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin,
 347        int value)
 348{
 349        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
 350
 351        __set_gpio_level_p3(group, pin, value);
 352}
 353
 354static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin,
 355        int value)
 356{
 357        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
 358
 359        __set_gpo_level_p3(group, pin, value);
 360}
 361
 362static int lpc32xx_gpo_get_value(struct gpio_chip *chip, unsigned pin)
 363{
 364        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
 365
 366        return __get_gpo_state_p3(group, pin);
 367}
 368
 369static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin)
 370{
 371        if (pin < chip->ngpio)
 372                return 0;
 373
 374        return -EINVAL;
 375}
 376
 377static int lpc32xx_gpio_to_irq_p01(struct gpio_chip *chip, unsigned offset)
 378{
 379        return IRQ_LPC32XX_P0_P1_IRQ;
 380}
 381
 382static const char lpc32xx_gpio_to_irq_gpio_p3_table[] = {
 383        IRQ_LPC32XX_GPIO_00,
 384        IRQ_LPC32XX_GPIO_01,
 385        IRQ_LPC32XX_GPIO_02,
 386        IRQ_LPC32XX_GPIO_03,
 387        IRQ_LPC32XX_GPIO_04,
 388        IRQ_LPC32XX_GPIO_05,
 389};
 390
 391static int lpc32xx_gpio_to_irq_gpio_p3(struct gpio_chip *chip, unsigned offset)
 392{
 393        if (offset < ARRAY_SIZE(lpc32xx_gpio_to_irq_gpio_p3_table))
 394                return lpc32xx_gpio_to_irq_gpio_p3_table[offset];
 395        return -ENXIO;
 396}
 397
 398static const char lpc32xx_gpio_to_irq_gpi_p3_table[] = {
 399        IRQ_LPC32XX_GPI_00,
 400        IRQ_LPC32XX_GPI_01,
 401        IRQ_LPC32XX_GPI_02,
 402        IRQ_LPC32XX_GPI_03,
 403        IRQ_LPC32XX_GPI_04,
 404        IRQ_LPC32XX_GPI_05,
 405        IRQ_LPC32XX_GPI_06,
 406        IRQ_LPC32XX_GPI_07,
 407        IRQ_LPC32XX_GPI_08,
 408        IRQ_LPC32XX_GPI_09,
 409        -ENXIO, /* 10 */
 410        -ENXIO, /* 11 */
 411        -ENXIO, /* 12 */
 412        -ENXIO, /* 13 */
 413        -ENXIO, /* 14 */
 414        -ENXIO, /* 15 */
 415        -ENXIO, /* 16 */
 416        -ENXIO, /* 17 */
 417        -ENXIO, /* 18 */
 418        IRQ_LPC32XX_GPI_19,
 419        -ENXIO, /* 20 */
 420        -ENXIO, /* 21 */
 421        -ENXIO, /* 22 */
 422        -ENXIO, /* 23 */
 423        -ENXIO, /* 24 */
 424        -ENXIO, /* 25 */
 425        -ENXIO, /* 26 */
 426        -ENXIO, /* 27 */
 427        IRQ_LPC32XX_GPI_28,
 428};
 429
 430static int lpc32xx_gpio_to_irq_gpi_p3(struct gpio_chip *chip, unsigned offset)
 431{
 432        if (offset < ARRAY_SIZE(lpc32xx_gpio_to_irq_gpi_p3_table))
 433                return lpc32xx_gpio_to_irq_gpi_p3_table[offset];
 434        return -ENXIO;
 435}
 436
 437static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
 438        {
 439                .chip = {
 440                        .label                  = "gpio_p0",
 441                        .direction_input        = lpc32xx_gpio_dir_input_p012,
 442                        .get                    = lpc32xx_gpio_get_value_p012,
 443                        .direction_output       = lpc32xx_gpio_dir_output_p012,
 444                        .set                    = lpc32xx_gpio_set_value_p012,
 445                        .request                = lpc32xx_gpio_request,
 446                        .to_irq                 = lpc32xx_gpio_to_irq_p01,
 447                        .base                   = LPC32XX_GPIO_P0_GRP,
 448                        .ngpio                  = LPC32XX_GPIO_P0_MAX,
 449                        .names                  = gpio_p0_names,
 450                        .can_sleep              = 0,
 451                },
 452                .gpio_grp = &gpio_grp_regs_p0,
 453        },
 454        {
 455                .chip = {
 456                        .label                  = "gpio_p1",
 457                        .direction_input        = lpc32xx_gpio_dir_input_p012,
 458                        .get                    = lpc32xx_gpio_get_value_p012,
 459                        .direction_output       = lpc32xx_gpio_dir_output_p012,
 460                        .set                    = lpc32xx_gpio_set_value_p012,
 461                        .request                = lpc32xx_gpio_request,
 462                        .to_irq                 = lpc32xx_gpio_to_irq_p01,
 463                        .base                   = LPC32XX_GPIO_P1_GRP,
 464                        .ngpio                  = LPC32XX_GPIO_P1_MAX,
 465                        .names                  = gpio_p1_names,
 466                        .can_sleep              = 0,
 467                },
 468                .gpio_grp = &gpio_grp_regs_p1,
 469        },
 470        {
 471                .chip = {
 472                        .label                  = "gpio_p2",
 473                        .direction_input        = lpc32xx_gpio_dir_input_p012,
 474                        .get                    = lpc32xx_gpio_get_value_p012,
 475                        .direction_output       = lpc32xx_gpio_dir_output_p012,
 476                        .set                    = lpc32xx_gpio_set_value_p012,
 477                        .request                = lpc32xx_gpio_request,
 478                        .base                   = LPC32XX_GPIO_P2_GRP,
 479                        .ngpio                  = LPC32XX_GPIO_P2_MAX,
 480                        .names                  = gpio_p2_names,
 481                        .can_sleep              = 0,
 482                },
 483                .gpio_grp = &gpio_grp_regs_p2,
 484        },
 485        {
 486                .chip = {
 487                        .label                  = "gpio_p3",
 488                        .direction_input        = lpc32xx_gpio_dir_input_p3,
 489                        .get                    = lpc32xx_gpio_get_value_p3,
 490                        .direction_output       = lpc32xx_gpio_dir_output_p3,
 491                        .set                    = lpc32xx_gpio_set_value_p3,
 492                        .request                = lpc32xx_gpio_request,
 493                        .to_irq                 = lpc32xx_gpio_to_irq_gpio_p3,
 494                        .base                   = LPC32XX_GPIO_P3_GRP,
 495                        .ngpio                  = LPC32XX_GPIO_P3_MAX,
 496                        .names                  = gpio_p3_names,
 497                        .can_sleep              = 0,
 498                },
 499                .gpio_grp = &gpio_grp_regs_p3,
 500        },
 501        {
 502                .chip = {
 503                        .label                  = "gpi_p3",
 504                        .direction_input        = lpc32xx_gpio_dir_in_always,
 505                        .get                    = lpc32xx_gpi_get_value,
 506                        .request                = lpc32xx_gpio_request,
 507                        .to_irq                 = lpc32xx_gpio_to_irq_gpi_p3,
 508                        .base                   = LPC32XX_GPI_P3_GRP,
 509                        .ngpio                  = LPC32XX_GPI_P3_MAX,
 510                        .names                  = gpi_p3_names,
 511                        .can_sleep              = 0,
 512                },
 513                .gpio_grp = &gpio_grp_regs_p3,
 514        },
 515        {
 516                .chip = {
 517                        .label                  = "gpo_p3",
 518                        .direction_output       = lpc32xx_gpio_dir_out_always,
 519                        .set                    = lpc32xx_gpo_set_value,
 520                        .get                    = lpc32xx_gpo_get_value,
 521                        .request                = lpc32xx_gpio_request,
 522                        .base                   = LPC32XX_GPO_P3_GRP,
 523                        .ngpio                  = LPC32XX_GPO_P3_MAX,
 524                        .names                  = gpo_p3_names,
 525                        .can_sleep              = 0,
 526                },
 527                .gpio_grp = &gpio_grp_regs_p3,
 528        },
 529};
 530
 531static int lpc32xx_of_xlate(struct gpio_chip *gc,
 532                            const struct of_phandle_args *gpiospec, u32 *flags)
 533{
 534        /* Is this the correct bank? */
 535        u32 bank = gpiospec->args[0];
 536        if ((bank > ARRAY_SIZE(lpc32xx_gpiochip) ||
 537            (gc != &lpc32xx_gpiochip[bank].chip)))
 538                return -EINVAL;
 539
 540        if (flags)
 541                *flags = gpiospec->args[2];
 542        return gpiospec->args[1];
 543}
 544
 545static int lpc32xx_gpio_probe(struct platform_device *pdev)
 546{
 547        int i;
 548
 549        for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) {
 550                if (pdev->dev.of_node) {
 551                        lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate;
 552                        lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3;
 553                        lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node;
 554                }
 555                gpiochip_add(&lpc32xx_gpiochip[i].chip);
 556        }
 557
 558        return 0;
 559}
 560
 561#ifdef CONFIG_OF
 562static struct of_device_id lpc32xx_gpio_of_match[] = {
 563        { .compatible = "nxp,lpc3220-gpio", },
 564        { },
 565};
 566#endif
 567
 568static struct platform_driver lpc32xx_gpio_driver = {
 569        .driver         = {
 570                .name   = "lpc32xx-gpio",
 571                .owner  = THIS_MODULE,
 572                .of_match_table = of_match_ptr(lpc32xx_gpio_of_match),
 573        },
 574        .probe          = lpc32xx_gpio_probe,
 575};
 576
 577module_platform_driver(lpc32xx_gpio_driver);
 578
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