linux/drivers/edac/i5100_edac.c
<<
>>
Prefs
   1/*
   2 * Intel 5100 Memory Controllers kernel module
   3 *
   4 * This file may be distributed under the terms of the
   5 * GNU General Public License.
   6 *
   7 * This module is based on the following document:
   8 *
   9 * Intel 5100X Chipset Memory Controller Hub (MCH) - Datasheet
  10 *      http://download.intel.com/design/chipsets/datashts/318378.pdf
  11 *
  12 * The intel 5100 has two independent channels. EDAC core currently
  13 * can not reflect this configuration so instead the chip-select
  14 * rows for each respective channel are laid out one after another,
  15 * the first half belonging to channel 0, the second half belonging
  16 * to channel 1.
  17 *
  18 * This driver is for DDR2 DIMMs, and it uses chip select to select among the
  19 * several ranks. However, instead of showing memories as ranks, it outputs
  20 * them as DIMM's. An internal table creates the association between ranks
  21 * and DIMM's.
  22 */
  23#include <linux/module.h>
  24#include <linux/init.h>
  25#include <linux/pci.h>
  26#include <linux/pci_ids.h>
  27#include <linux/edac.h>
  28#include <linux/delay.h>
  29#include <linux/mmzone.h>
  30
  31#include "edac_core.h"
  32
  33/* register addresses */
  34
  35/* device 16, func 1 */
  36#define I5100_MC                0x40    /* Memory Control Register */
  37#define         I5100_MC_SCRBEN_MASK    (1 << 7)
  38#define         I5100_MC_SCRBDONE_MASK  (1 << 4)
  39#define I5100_MS                0x44    /* Memory Status Register */
  40#define I5100_SPDDATA           0x48    /* Serial Presence Detect Status Reg */
  41#define I5100_SPDCMD            0x4c    /* Serial Presence Detect Command Reg */
  42#define I5100_TOLM              0x6c    /* Top of Low Memory */
  43#define I5100_MIR0              0x80    /* Memory Interleave Range 0 */
  44#define I5100_MIR1              0x84    /* Memory Interleave Range 1 */
  45#define I5100_AMIR_0            0x8c    /* Adjusted Memory Interleave Range 0 */
  46#define I5100_AMIR_1            0x90    /* Adjusted Memory Interleave Range 1 */
  47#define I5100_FERR_NF_MEM       0xa0    /* MC First Non Fatal Errors */
  48#define         I5100_FERR_NF_MEM_M16ERR_MASK   (1 << 16)
  49#define         I5100_FERR_NF_MEM_M15ERR_MASK   (1 << 15)
  50#define         I5100_FERR_NF_MEM_M14ERR_MASK   (1 << 14)
  51#define         I5100_FERR_NF_MEM_M12ERR_MASK   (1 << 12)
  52#define         I5100_FERR_NF_MEM_M11ERR_MASK   (1 << 11)
  53#define         I5100_FERR_NF_MEM_M10ERR_MASK   (1 << 10)
  54#define         I5100_FERR_NF_MEM_M6ERR_MASK    (1 << 6)
  55#define         I5100_FERR_NF_MEM_M5ERR_MASK    (1 << 5)
  56#define         I5100_FERR_NF_MEM_M4ERR_MASK    (1 << 4)
  57#define         I5100_FERR_NF_MEM_M1ERR_MASK    (1 << 1)
  58#define         I5100_FERR_NF_MEM_ANY_MASK      \
  59                        (I5100_FERR_NF_MEM_M16ERR_MASK | \
  60                        I5100_FERR_NF_MEM_M15ERR_MASK | \
  61                        I5100_FERR_NF_MEM_M14ERR_MASK | \
  62                        I5100_FERR_NF_MEM_M12ERR_MASK | \
  63                        I5100_FERR_NF_MEM_M11ERR_MASK | \
  64                        I5100_FERR_NF_MEM_M10ERR_MASK | \
  65                        I5100_FERR_NF_MEM_M6ERR_MASK | \
  66                        I5100_FERR_NF_MEM_M5ERR_MASK | \
  67                        I5100_FERR_NF_MEM_M4ERR_MASK | \
  68                        I5100_FERR_NF_MEM_M1ERR_MASK)
  69#define I5100_NERR_NF_MEM       0xa4    /* MC Next Non-Fatal Errors */
  70#define I5100_EMASK_MEM         0xa8    /* MC Error Mask Register */
  71
  72/* device 21 and 22, func 0 */
  73#define I5100_MTR_0     0x154   /* Memory Technology Registers 0-3 */
  74#define I5100_DMIR      0x15c   /* DIMM Interleave Range */
  75#define I5100_VALIDLOG  0x18c   /* Valid Log Markers */
  76#define I5100_NRECMEMA  0x190   /* Non-Recoverable Memory Error Log Reg A */
  77#define I5100_NRECMEMB  0x194   /* Non-Recoverable Memory Error Log Reg B */
  78#define I5100_REDMEMA   0x198   /* Recoverable Memory Data Error Log Reg A */
  79#define I5100_REDMEMB   0x19c   /* Recoverable Memory Data Error Log Reg B */
  80#define I5100_RECMEMA   0x1a0   /* Recoverable Memory Error Log Reg A */
  81#define I5100_RECMEMB   0x1a4   /* Recoverable Memory Error Log Reg B */
  82#define I5100_MTR_4     0x1b0   /* Memory Technology Registers 4,5 */
  83
  84/* bit field accessors */
  85
  86static inline u32 i5100_mc_scrben(u32 mc)
  87{
  88        return mc >> 7 & 1;
  89}
  90
  91static inline u32 i5100_mc_errdeten(u32 mc)
  92{
  93        return mc >> 5 & 1;
  94}
  95
  96static inline u32 i5100_mc_scrbdone(u32 mc)
  97{
  98        return mc >> 4 & 1;
  99}
 100
 101static inline u16 i5100_spddata_rdo(u16 a)
 102{
 103        return a >> 15 & 1;
 104}
 105
 106static inline u16 i5100_spddata_sbe(u16 a)
 107{
 108        return a >> 13 & 1;
 109}
 110
 111static inline u16 i5100_spddata_busy(u16 a)
 112{
 113        return a >> 12 & 1;
 114}
 115
 116static inline u16 i5100_spddata_data(u16 a)
 117{
 118        return a & ((1 << 8) - 1);
 119}
 120
 121static inline u32 i5100_spdcmd_create(u32 dti, u32 ckovrd, u32 sa, u32 ba,
 122                                      u32 data, u32 cmd)
 123{
 124        return  ((dti & ((1 << 4) - 1))  << 28) |
 125                ((ckovrd & 1)            << 27) |
 126                ((sa & ((1 << 3) - 1))   << 24) |
 127                ((ba & ((1 << 8) - 1))   << 16) |
 128                ((data & ((1 << 8) - 1)) <<  8) |
 129                (cmd & 1);
 130}
 131
 132static inline u16 i5100_tolm_tolm(u16 a)
 133{
 134        return a >> 12 & ((1 << 4) - 1);
 135}
 136
 137static inline u16 i5100_mir_limit(u16 a)
 138{
 139        return a >> 4 & ((1 << 12) - 1);
 140}
 141
 142static inline u16 i5100_mir_way1(u16 a)
 143{
 144        return a >> 1 & 1;
 145}
 146
 147static inline u16 i5100_mir_way0(u16 a)
 148{
 149        return a & 1;
 150}
 151
 152static inline u32 i5100_ferr_nf_mem_chan_indx(u32 a)
 153{
 154        return a >> 28 & 1;
 155}
 156
 157static inline u32 i5100_ferr_nf_mem_any(u32 a)
 158{
 159        return a & I5100_FERR_NF_MEM_ANY_MASK;
 160}
 161
 162static inline u32 i5100_nerr_nf_mem_any(u32 a)
 163{
 164        return i5100_ferr_nf_mem_any(a);
 165}
 166
 167static inline u32 i5100_dmir_limit(u32 a)
 168{
 169        return a >> 16 & ((1 << 11) - 1);
 170}
 171
 172static inline u32 i5100_dmir_rank(u32 a, u32 i)
 173{
 174        return a >> (4 * i) & ((1 << 2) - 1);
 175}
 176
 177static inline u16 i5100_mtr_present(u16 a)
 178{
 179        return a >> 10 & 1;
 180}
 181
 182static inline u16 i5100_mtr_ethrottle(u16 a)
 183{
 184        return a >> 9 & 1;
 185}
 186
 187static inline u16 i5100_mtr_width(u16 a)
 188{
 189        return a >> 8 & 1;
 190}
 191
 192static inline u16 i5100_mtr_numbank(u16 a)
 193{
 194        return a >> 6 & 1;
 195}
 196
 197static inline u16 i5100_mtr_numrow(u16 a)
 198{
 199        return a >> 2 & ((1 << 2) - 1);
 200}
 201
 202static inline u16 i5100_mtr_numcol(u16 a)
 203{
 204        return a & ((1 << 2) - 1);
 205}
 206
 207
 208static inline u32 i5100_validlog_redmemvalid(u32 a)
 209{
 210        return a >> 2 & 1;
 211}
 212
 213static inline u32 i5100_validlog_recmemvalid(u32 a)
 214{
 215        return a >> 1 & 1;
 216}
 217
 218static inline u32 i5100_validlog_nrecmemvalid(u32 a)
 219{
 220        return a & 1;
 221}
 222
 223static inline u32 i5100_nrecmema_merr(u32 a)
 224{
 225        return a >> 15 & ((1 << 5) - 1);
 226}
 227
 228static inline u32 i5100_nrecmema_bank(u32 a)
 229{
 230        return a >> 12 & ((1 << 3) - 1);
 231}
 232
 233static inline u32 i5100_nrecmema_rank(u32 a)
 234{
 235        return a >>  8 & ((1 << 3) - 1);
 236}
 237
 238static inline u32 i5100_nrecmema_dm_buf_id(u32 a)
 239{
 240        return a & ((1 << 8) - 1);
 241}
 242
 243static inline u32 i5100_nrecmemb_cas(u32 a)
 244{
 245        return a >> 16 & ((1 << 13) - 1);
 246}
 247
 248static inline u32 i5100_nrecmemb_ras(u32 a)
 249{
 250        return a & ((1 << 16) - 1);
 251}
 252
 253static inline u32 i5100_redmemb_ecc_locator(u32 a)
 254{
 255        return a & ((1 << 18) - 1);
 256}
 257
 258static inline u32 i5100_recmema_merr(u32 a)
 259{
 260        return i5100_nrecmema_merr(a);
 261}
 262
 263static inline u32 i5100_recmema_bank(u32 a)
 264{
 265        return i5100_nrecmema_bank(a);
 266}
 267
 268static inline u32 i5100_recmema_rank(u32 a)
 269{
 270        return i5100_nrecmema_rank(a);
 271}
 272
 273static inline u32 i5100_recmema_dm_buf_id(u32 a)
 274{
 275        return i5100_nrecmema_dm_buf_id(a);
 276}
 277
 278static inline u32 i5100_recmemb_cas(u32 a)
 279{
 280        return i5100_nrecmemb_cas(a);
 281}
 282
 283static inline u32 i5100_recmemb_ras(u32 a)
 284{
 285        return i5100_nrecmemb_ras(a);
 286}
 287
 288/* some generic limits */
 289#define I5100_MAX_RANKS_PER_CHAN        6
 290#define I5100_CHANNELS                      2
 291#define I5100_MAX_RANKS_PER_DIMM        4
 292#define I5100_DIMM_ADDR_LINES           (6 - 3) /* 64 bits / 8 bits per byte */
 293#define I5100_MAX_DIMM_SLOTS_PER_CHAN   4
 294#define I5100_MAX_RANK_INTERLEAVE       4
 295#define I5100_MAX_DMIRS                 5
 296#define I5100_SCRUB_REFRESH_RATE        (5 * 60 * HZ)
 297
 298struct i5100_priv {
 299        /* ranks on each dimm -- 0 maps to not present -- obtained via SPD */
 300        int dimm_numrank[I5100_CHANNELS][I5100_MAX_DIMM_SLOTS_PER_CHAN];
 301
 302        /*
 303         * mainboard chip select map -- maps i5100 chip selects to
 304         * DIMM slot chip selects.  In the case of only 4 ranks per
 305         * channel, the mapping is fairly obvious but not unique.
 306         * we map -1 -> NC and assume both channels use the same
 307         * map...
 308         *
 309         */
 310        int dimm_csmap[I5100_MAX_DIMM_SLOTS_PER_CHAN][I5100_MAX_RANKS_PER_DIMM];
 311
 312        /* memory interleave range */
 313        struct {
 314                u64      limit;
 315                unsigned way[2];
 316        } mir[I5100_CHANNELS];
 317
 318        /* adjusted memory interleave range register */
 319        unsigned amir[I5100_CHANNELS];
 320
 321        /* dimm interleave range */
 322        struct {
 323                unsigned rank[I5100_MAX_RANK_INTERLEAVE];
 324                u64      limit;
 325        } dmir[I5100_CHANNELS][I5100_MAX_DMIRS];
 326
 327        /* memory technology registers... */
 328        struct {
 329                unsigned present;       /* 0 or 1 */
 330                unsigned ethrottle;     /* 0 or 1 */
 331                unsigned width;         /* 4 or 8 bits  */
 332                unsigned numbank;       /* 2 or 3 lines */
 333                unsigned numrow;        /* 13 .. 16 lines */
 334                unsigned numcol;        /* 11 .. 12 lines */
 335        } mtr[I5100_CHANNELS][I5100_MAX_RANKS_PER_CHAN];
 336
 337        u64 tolm;               /* top of low memory in bytes */
 338        unsigned ranksperchan;  /* number of ranks per channel */
 339
 340        struct pci_dev *mc;     /* device 16 func 1 */
 341        struct pci_dev *ch0mm;  /* device 21 func 0 */
 342        struct pci_dev *ch1mm;  /* device 22 func 0 */
 343
 344        struct delayed_work i5100_scrubbing;
 345        int scrub_enable;
 346};
 347
 348/* map a rank/chan to a slot number on the mainboard */
 349static int i5100_rank_to_slot(const struct mem_ctl_info *mci,
 350                              int chan, int rank)
 351{
 352        const struct i5100_priv *priv = mci->pvt_info;
 353        int i;
 354
 355        for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) {
 356                int j;
 357                const int numrank = priv->dimm_numrank[chan][i];
 358
 359                for (j = 0; j < numrank; j++)
 360                        if (priv->dimm_csmap[i][j] == rank)
 361                                return i * 2 + chan;
 362        }
 363
 364        return -1;
 365}
 366
 367static const char *i5100_err_msg(unsigned err)
 368{
 369        static const char *merrs[] = {
 370                "unknown", /* 0 */
 371                "uncorrectable data ECC on replay", /* 1 */
 372                "unknown", /* 2 */
 373                "unknown", /* 3 */
 374                "aliased uncorrectable demand data ECC", /* 4 */
 375                "aliased uncorrectable spare-copy data ECC", /* 5 */
 376                "aliased uncorrectable patrol data ECC", /* 6 */
 377                "unknown", /* 7 */
 378                "unknown", /* 8 */
 379                "unknown", /* 9 */
 380                "non-aliased uncorrectable demand data ECC", /* 10 */
 381                "non-aliased uncorrectable spare-copy data ECC", /* 11 */
 382                "non-aliased uncorrectable patrol data ECC", /* 12 */
 383                "unknown", /* 13 */
 384                "correctable demand data ECC", /* 14 */
 385                "correctable spare-copy data ECC", /* 15 */
 386                "correctable patrol data ECC", /* 16 */
 387                "unknown", /* 17 */
 388                "SPD protocol error", /* 18 */
 389                "unknown", /* 19 */
 390                "spare copy initiated", /* 20 */
 391                "spare copy completed", /* 21 */
 392        };
 393        unsigned i;
 394
 395        for (i = 0; i < ARRAY_SIZE(merrs); i++)
 396                if (1 << i & err)
 397                        return merrs[i];
 398
 399        return "none";
 400}
 401
 402/* convert csrow index into a rank (per channel -- 0..5) */
 403static int i5100_csrow_to_rank(const struct mem_ctl_info *mci, int csrow)
 404{
 405        const struct i5100_priv *priv = mci->pvt_info;
 406
 407        return csrow % priv->ranksperchan;
 408}
 409
 410/* convert csrow index into a channel (0..1) */
 411static int i5100_csrow_to_chan(const struct mem_ctl_info *mci, int csrow)
 412{
 413        const struct i5100_priv *priv = mci->pvt_info;
 414
 415        return csrow / priv->ranksperchan;
 416}
 417
 418static void i5100_handle_ce(struct mem_ctl_info *mci,
 419                            int chan,
 420                            unsigned bank,
 421                            unsigned rank,
 422                            unsigned long syndrome,
 423                            unsigned cas,
 424                            unsigned ras,
 425                            const char *msg)
 426{
 427        char detail[80];
 428
 429        /* Form out message */
 430        snprintf(detail, sizeof(detail),
 431                 "bank %u, cas %u, ras %u\n",
 432                 bank, cas, ras);
 433
 434        edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
 435                             0, 0, syndrome,
 436                             chan, rank, -1,
 437                             msg, detail);
 438}
 439
 440static void i5100_handle_ue(struct mem_ctl_info *mci,
 441                            int chan,
 442                            unsigned bank,
 443                            unsigned rank,
 444                            unsigned long syndrome,
 445                            unsigned cas,
 446                            unsigned ras,
 447                            const char *msg)
 448{
 449        char detail[80];
 450
 451        /* Form out message */
 452        snprintf(detail, sizeof(detail),
 453                 "bank %u, cas %u, ras %u\n",
 454                 bank, cas, ras);
 455
 456        edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
 457                             0, 0, syndrome,
 458                             chan, rank, -1,
 459                             msg, detail);
 460}
 461
 462static void i5100_read_log(struct mem_ctl_info *mci, int chan,
 463                           u32 ferr, u32 nerr)
 464{
 465        struct i5100_priv *priv = mci->pvt_info;
 466        struct pci_dev *pdev = (chan) ? priv->ch1mm : priv->ch0mm;
 467        u32 dw;
 468        u32 dw2;
 469        unsigned syndrome = 0;
 470        unsigned ecc_loc = 0;
 471        unsigned merr;
 472        unsigned bank;
 473        unsigned rank;
 474        unsigned cas;
 475        unsigned ras;
 476
 477        pci_read_config_dword(pdev, I5100_VALIDLOG, &dw);
 478
 479        if (i5100_validlog_redmemvalid(dw)) {
 480                pci_read_config_dword(pdev, I5100_REDMEMA, &dw2);
 481                syndrome = dw2;
 482                pci_read_config_dword(pdev, I5100_REDMEMB, &dw2);
 483                ecc_loc = i5100_redmemb_ecc_locator(dw2);
 484        }
 485
 486        if (i5100_validlog_recmemvalid(dw)) {
 487                const char *msg;
 488
 489                pci_read_config_dword(pdev, I5100_RECMEMA, &dw2);
 490                merr = i5100_recmema_merr(dw2);
 491                bank = i5100_recmema_bank(dw2);
 492                rank = i5100_recmema_rank(dw2);
 493
 494                pci_read_config_dword(pdev, I5100_RECMEMB, &dw2);
 495                cas = i5100_recmemb_cas(dw2);
 496                ras = i5100_recmemb_ras(dw2);
 497
 498                /* FIXME:  not really sure if this is what merr is...
 499                 */
 500                if (!merr)
 501                        msg = i5100_err_msg(ferr);
 502                else
 503                        msg = i5100_err_msg(nerr);
 504
 505                i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg);
 506        }
 507
 508        if (i5100_validlog_nrecmemvalid(dw)) {
 509                const char *msg;
 510
 511                pci_read_config_dword(pdev, I5100_NRECMEMA, &dw2);
 512                merr = i5100_nrecmema_merr(dw2);
 513                bank = i5100_nrecmema_bank(dw2);
 514                rank = i5100_nrecmema_rank(dw2);
 515
 516                pci_read_config_dword(pdev, I5100_NRECMEMB, &dw2);
 517                cas = i5100_nrecmemb_cas(dw2);
 518                ras = i5100_nrecmemb_ras(dw2);
 519
 520                /* FIXME:  not really sure if this is what merr is...
 521                 */
 522                if (!merr)
 523                        msg = i5100_err_msg(ferr);
 524                else
 525                        msg = i5100_err_msg(nerr);
 526
 527                i5100_handle_ue(mci, chan, bank, rank, syndrome, cas, ras, msg);
 528        }
 529
 530        pci_write_config_dword(pdev, I5100_VALIDLOG, dw);
 531}
 532
 533static void i5100_check_error(struct mem_ctl_info *mci)
 534{
 535        struct i5100_priv *priv = mci->pvt_info;
 536        u32 dw, dw2;
 537
 538        pci_read_config_dword(priv->mc, I5100_FERR_NF_MEM, &dw);
 539        if (i5100_ferr_nf_mem_any(dw)) {
 540
 541                pci_read_config_dword(priv->mc, I5100_NERR_NF_MEM, &dw2);
 542
 543                i5100_read_log(mci, i5100_ferr_nf_mem_chan_indx(dw),
 544                               i5100_ferr_nf_mem_any(dw),
 545                               i5100_nerr_nf_mem_any(dw2));
 546
 547                pci_write_config_dword(priv->mc, I5100_NERR_NF_MEM, dw2);
 548        }
 549        pci_write_config_dword(priv->mc, I5100_FERR_NF_MEM, dw);
 550}
 551
 552/* The i5100 chipset will scrub the entire memory once, then
 553 * set a done bit. Continuous scrubbing is achieved by enqueing
 554 * delayed work to a workqueue, checking every few minutes if
 555 * the scrubbing has completed and if so reinitiating it.
 556 */
 557
 558static void i5100_refresh_scrubbing(struct work_struct *work)
 559{
 560        struct delayed_work *i5100_scrubbing = container_of(work,
 561                                                            struct delayed_work,
 562                                                            work);
 563        struct i5100_priv *priv = container_of(i5100_scrubbing,
 564                                               struct i5100_priv,
 565                                               i5100_scrubbing);
 566        u32 dw;
 567
 568        pci_read_config_dword(priv->mc, I5100_MC, &dw);
 569
 570        if (priv->scrub_enable) {
 571
 572                pci_read_config_dword(priv->mc, I5100_MC, &dw);
 573
 574                if (i5100_mc_scrbdone(dw)) {
 575                        dw |= I5100_MC_SCRBEN_MASK;
 576                        pci_write_config_dword(priv->mc, I5100_MC, dw);
 577                        pci_read_config_dword(priv->mc, I5100_MC, &dw);
 578                }
 579
 580                schedule_delayed_work(&(priv->i5100_scrubbing),
 581                                      I5100_SCRUB_REFRESH_RATE);
 582        }
 583}
 584/*
 585 * The bandwidth is based on experimentation, feel free to refine it.
 586 */
 587static int i5100_set_scrub_rate(struct mem_ctl_info *mci, u32 bandwidth)
 588{
 589        struct i5100_priv *priv = mci->pvt_info;
 590        u32 dw;
 591
 592        pci_read_config_dword(priv->mc, I5100_MC, &dw);
 593        if (bandwidth) {
 594                priv->scrub_enable = 1;
 595                dw |= I5100_MC_SCRBEN_MASK;
 596                schedule_delayed_work(&(priv->i5100_scrubbing),
 597                                      I5100_SCRUB_REFRESH_RATE);
 598        } else {
 599                priv->scrub_enable = 0;
 600                dw &= ~I5100_MC_SCRBEN_MASK;
 601                cancel_delayed_work(&(priv->i5100_scrubbing));
 602        }
 603        pci_write_config_dword(priv->mc, I5100_MC, dw);
 604
 605        pci_read_config_dword(priv->mc, I5100_MC, &dw);
 606
 607        bandwidth = 5900000 * i5100_mc_scrben(dw);
 608
 609        return bandwidth;
 610}
 611
 612static int i5100_get_scrub_rate(struct mem_ctl_info *mci)
 613{
 614        struct i5100_priv *priv = mci->pvt_info;
 615        u32 dw;
 616
 617        pci_read_config_dword(priv->mc, I5100_MC, &dw);
 618
 619        return 5900000 * i5100_mc_scrben(dw);
 620}
 621
 622static struct pci_dev *pci_get_device_func(unsigned vendor,
 623                                           unsigned device,
 624                                           unsigned func)
 625{
 626        struct pci_dev *ret = NULL;
 627
 628        while (1) {
 629                ret = pci_get_device(vendor, device, ret);
 630
 631                if (!ret)
 632                        break;
 633
 634                if (PCI_FUNC(ret->devfn) == func)
 635                        break;
 636        }
 637
 638        return ret;
 639}
 640
 641static unsigned long i5100_npages(struct mem_ctl_info *mci, int csrow)
 642{
 643        struct i5100_priv *priv = mci->pvt_info;
 644        const unsigned chan_rank = i5100_csrow_to_rank(mci, csrow);
 645        const unsigned chan = i5100_csrow_to_chan(mci, csrow);
 646        unsigned addr_lines;
 647
 648        /* dimm present? */
 649        if (!priv->mtr[chan][chan_rank].present)
 650                return 0ULL;
 651
 652        addr_lines =
 653                I5100_DIMM_ADDR_LINES +
 654                priv->mtr[chan][chan_rank].numcol +
 655                priv->mtr[chan][chan_rank].numrow +
 656                priv->mtr[chan][chan_rank].numbank;
 657
 658        return (unsigned long)
 659                ((unsigned long long) (1ULL << addr_lines) / PAGE_SIZE);
 660}
 661
 662static void i5100_init_mtr(struct mem_ctl_info *mci)
 663{
 664        struct i5100_priv *priv = mci->pvt_info;
 665        struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm };
 666        int i;
 667
 668        for (i = 0; i < I5100_CHANNELS; i++) {
 669                int j;
 670                struct pci_dev *pdev = mms[i];
 671
 672                for (j = 0; j < I5100_MAX_RANKS_PER_CHAN; j++) {
 673                        const unsigned addr =
 674                                (j < 4) ? I5100_MTR_0 + j * 2 :
 675                                          I5100_MTR_4 + (j - 4) * 2;
 676                        u16 w;
 677
 678                        pci_read_config_word(pdev, addr, &w);
 679
 680                        priv->mtr[i][j].present = i5100_mtr_present(w);
 681                        priv->mtr[i][j].ethrottle = i5100_mtr_ethrottle(w);
 682                        priv->mtr[i][j].width = 4 + 4 * i5100_mtr_width(w);
 683                        priv->mtr[i][j].numbank = 2 + i5100_mtr_numbank(w);
 684                        priv->mtr[i][j].numrow = 13 + i5100_mtr_numrow(w);
 685                        priv->mtr[i][j].numcol = 10 + i5100_mtr_numcol(w);
 686                }
 687        }
 688}
 689
 690/*
 691 * FIXME: make this into a real i2c adapter (so that dimm-decode
 692 * will work)?
 693 */
 694static int i5100_read_spd_byte(const struct mem_ctl_info *mci,
 695                               u8 ch, u8 slot, u8 addr, u8 *byte)
 696{
 697        struct i5100_priv *priv = mci->pvt_info;
 698        u16 w;
 699        unsigned long et;
 700
 701        pci_read_config_word(priv->mc, I5100_SPDDATA, &w);
 702        if (i5100_spddata_busy(w))
 703                return -1;
 704
 705        pci_write_config_dword(priv->mc, I5100_SPDCMD,
 706                               i5100_spdcmd_create(0xa, 1, ch * 4 + slot, addr,
 707                                                   0, 0));
 708
 709        /* wait up to 100ms */
 710        et = jiffies + HZ / 10;
 711        udelay(100);
 712        while (1) {
 713                pci_read_config_word(priv->mc, I5100_SPDDATA, &w);
 714                if (!i5100_spddata_busy(w))
 715                        break;
 716                udelay(100);
 717        }
 718
 719        if (!i5100_spddata_rdo(w) || i5100_spddata_sbe(w))
 720                return -1;
 721
 722        *byte = i5100_spddata_data(w);
 723
 724        return 0;
 725}
 726
 727/*
 728 * fill dimm chip select map
 729 *
 730 * FIXME:
 731 *   o not the only way to may chip selects to dimm slots
 732 *   o investigate if there is some way to obtain this map from the bios
 733 */
 734static void i5100_init_dimm_csmap(struct mem_ctl_info *mci)
 735{
 736        struct i5100_priv *priv = mci->pvt_info;
 737        int i;
 738
 739        for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) {
 740                int j;
 741
 742                for (j = 0; j < I5100_MAX_RANKS_PER_DIMM; j++)
 743                        priv->dimm_csmap[i][j] = -1; /* default NC */
 744        }
 745
 746        /* only 2 chip selects per slot... */
 747        if (priv->ranksperchan == 4) {
 748                priv->dimm_csmap[0][0] = 0;
 749                priv->dimm_csmap[0][1] = 3;
 750                priv->dimm_csmap[1][0] = 1;
 751                priv->dimm_csmap[1][1] = 2;
 752                priv->dimm_csmap[2][0] = 2;
 753                priv->dimm_csmap[3][0] = 3;
 754        } else {
 755                priv->dimm_csmap[0][0] = 0;
 756                priv->dimm_csmap[0][1] = 1;
 757                priv->dimm_csmap[1][0] = 2;
 758                priv->dimm_csmap[1][1] = 3;
 759                priv->dimm_csmap[2][0] = 4;
 760                priv->dimm_csmap[2][1] = 5;
 761        }
 762}
 763
 764static void i5100_init_dimm_layout(struct pci_dev *pdev,
 765                                   struct mem_ctl_info *mci)
 766{
 767        struct i5100_priv *priv = mci->pvt_info;
 768        int i;
 769
 770        for (i = 0; i < I5100_CHANNELS; i++) {
 771                int j;
 772
 773                for (j = 0; j < I5100_MAX_DIMM_SLOTS_PER_CHAN; j++) {
 774                        u8 rank;
 775
 776                        if (i5100_read_spd_byte(mci, i, j, 5, &rank) < 0)
 777                                priv->dimm_numrank[i][j] = 0;
 778                        else
 779                                priv->dimm_numrank[i][j] = (rank & 3) + 1;
 780                }
 781        }
 782
 783        i5100_init_dimm_csmap(mci);
 784}
 785
 786static void i5100_init_interleaving(struct pci_dev *pdev,
 787                                    struct mem_ctl_info *mci)
 788{
 789        u16 w;
 790        u32 dw;
 791        struct i5100_priv *priv = mci->pvt_info;
 792        struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm };
 793        int i;
 794
 795        pci_read_config_word(pdev, I5100_TOLM, &w);
 796        priv->tolm = (u64) i5100_tolm_tolm(w) * 256 * 1024 * 1024;
 797
 798        pci_read_config_word(pdev, I5100_MIR0, &w);
 799        priv->mir[0].limit = (u64) i5100_mir_limit(w) << 28;
 800        priv->mir[0].way[1] = i5100_mir_way1(w);
 801        priv->mir[0].way[0] = i5100_mir_way0(w);
 802
 803        pci_read_config_word(pdev, I5100_MIR1, &w);
 804        priv->mir[1].limit = (u64) i5100_mir_limit(w) << 28;
 805        priv->mir[1].way[1] = i5100_mir_way1(w);
 806        priv->mir[1].way[0] = i5100_mir_way0(w);
 807
 808        pci_read_config_word(pdev, I5100_AMIR_0, &w);
 809        priv->amir[0] = w;
 810        pci_read_config_word(pdev, I5100_AMIR_1, &w);
 811        priv->amir[1] = w;
 812
 813        for (i = 0; i < I5100_CHANNELS; i++) {
 814                int j;
 815
 816                for (j = 0; j < 5; j++) {
 817                        int k;
 818
 819                        pci_read_config_dword(mms[i], I5100_DMIR + j * 4, &dw);
 820
 821                        priv->dmir[i][j].limit =
 822                                (u64) i5100_dmir_limit(dw) << 28;
 823                        for (k = 0; k < I5100_MAX_RANKS_PER_DIMM; k++)
 824                                priv->dmir[i][j].rank[k] =
 825                                        i5100_dmir_rank(dw, k);
 826                }
 827        }
 828
 829        i5100_init_mtr(mci);
 830}
 831
 832static void i5100_init_csrows(struct mem_ctl_info *mci)
 833{
 834        int i;
 835        struct i5100_priv *priv = mci->pvt_info;
 836
 837        for (i = 0; i < mci->tot_dimms; i++) {
 838                struct dimm_info *dimm;
 839                const unsigned long npages = i5100_npages(mci, i);
 840                const unsigned chan = i5100_csrow_to_chan(mci, i);
 841                const unsigned rank = i5100_csrow_to_rank(mci, i);
 842
 843                if (!npages)
 844                        continue;
 845
 846                dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
 847                               chan, rank, 0);
 848
 849                dimm->nr_pages = npages;
 850                if (npages) {
 851                        dimm->grain = 32;
 852                        dimm->dtype = (priv->mtr[chan][rank].width == 4) ?
 853                                        DEV_X4 : DEV_X8;
 854                        dimm->mtype = MEM_RDDR2;
 855                        dimm->edac_mode = EDAC_SECDED;
 856                        snprintf(dimm->label, sizeof(dimm->label),
 857                                "DIMM%u",
 858                                i5100_rank_to_slot(mci, chan, rank));
 859                }
 860
 861                edac_dbg(2, "dimm channel %d, rank %d, size %ld\n",
 862                         chan, rank, (long)PAGES_TO_MiB(npages));
 863        }
 864}
 865
 866static int i5100_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
 867{
 868        int rc;
 869        struct mem_ctl_info *mci;
 870        struct edac_mc_layer layers[2];
 871        struct i5100_priv *priv;
 872        struct pci_dev *ch0mm, *ch1mm;
 873        int ret = 0;
 874        u32 dw;
 875        int ranksperch;
 876
 877        if (PCI_FUNC(pdev->devfn) != 1)
 878                return -ENODEV;
 879
 880        rc = pci_enable_device(pdev);
 881        if (rc < 0) {
 882                ret = rc;
 883                goto bail;
 884        }
 885
 886        /* ECC enabled? */
 887        pci_read_config_dword(pdev, I5100_MC, &dw);
 888        if (!i5100_mc_errdeten(dw)) {
 889                printk(KERN_INFO "i5100_edac: ECC not enabled.\n");
 890                ret = -ENODEV;
 891                goto bail_pdev;
 892        }
 893
 894        /* figure out how many ranks, from strapped state of 48GB_Mode input */
 895        pci_read_config_dword(pdev, I5100_MS, &dw);
 896        ranksperch = !!(dw & (1 << 8)) * 2 + 4;
 897
 898        /* enable error reporting... */
 899        pci_read_config_dword(pdev, I5100_EMASK_MEM, &dw);
 900        dw &= ~I5100_FERR_NF_MEM_ANY_MASK;
 901        pci_write_config_dword(pdev, I5100_EMASK_MEM, dw);
 902
 903        /* device 21, func 0, Channel 0 Memory Map, Error Flag/Mask, etc... */
 904        ch0mm = pci_get_device_func(PCI_VENDOR_ID_INTEL,
 905                                    PCI_DEVICE_ID_INTEL_5100_21, 0);
 906        if (!ch0mm) {
 907                ret = -ENODEV;
 908                goto bail_pdev;
 909        }
 910
 911        rc = pci_enable_device(ch0mm);
 912        if (rc < 0) {
 913                ret = rc;
 914                goto bail_ch0;
 915        }
 916
 917        /* device 22, func 0, Channel 1 Memory Map, Error Flag/Mask, etc... */
 918        ch1mm = pci_get_device_func(PCI_VENDOR_ID_INTEL,
 919                                    PCI_DEVICE_ID_INTEL_5100_22, 0);
 920        if (!ch1mm) {
 921                ret = -ENODEV;
 922                goto bail_disable_ch0;
 923        }
 924
 925        rc = pci_enable_device(ch1mm);
 926        if (rc < 0) {
 927                ret = rc;
 928                goto bail_ch1;
 929        }
 930
 931        layers[0].type = EDAC_MC_LAYER_CHANNEL;
 932        layers[0].size = 2;
 933        layers[0].is_virt_csrow = false;
 934        layers[1].type = EDAC_MC_LAYER_SLOT;
 935        layers[1].size = ranksperch;
 936        layers[1].is_virt_csrow = true;
 937        mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
 938                            sizeof(*priv));
 939        if (!mci) {
 940                ret = -ENOMEM;
 941                goto bail_disable_ch1;
 942        }
 943
 944        mci->pdev = &pdev->dev;
 945
 946        priv = mci->pvt_info;
 947        priv->ranksperchan = ranksperch;
 948        priv->mc = pdev;
 949        priv->ch0mm = ch0mm;
 950        priv->ch1mm = ch1mm;
 951
 952        INIT_DELAYED_WORK(&(priv->i5100_scrubbing), i5100_refresh_scrubbing);
 953
 954        /* If scrubbing was already enabled by the bios, start maintaining it */
 955        pci_read_config_dword(pdev, I5100_MC, &dw);
 956        if (i5100_mc_scrben(dw)) {
 957                priv->scrub_enable = 1;
 958                schedule_delayed_work(&(priv->i5100_scrubbing),
 959                                      I5100_SCRUB_REFRESH_RATE);
 960        }
 961
 962        i5100_init_dimm_layout(pdev, mci);
 963        i5100_init_interleaving(pdev, mci);
 964
 965        mci->mtype_cap = MEM_FLAG_FB_DDR2;
 966        mci->edac_ctl_cap = EDAC_FLAG_SECDED;
 967        mci->edac_cap = EDAC_FLAG_SECDED;
 968        mci->mod_name = "i5100_edac.c";
 969        mci->mod_ver = "not versioned";
 970        mci->ctl_name = "i5100";
 971        mci->dev_name = pci_name(pdev);
 972        mci->ctl_page_to_phys = NULL;
 973
 974        mci->edac_check = i5100_check_error;
 975        mci->set_sdram_scrub_rate = i5100_set_scrub_rate;
 976        mci->get_sdram_scrub_rate = i5100_get_scrub_rate;
 977
 978        i5100_init_csrows(mci);
 979
 980        /* this strange construction seems to be in every driver, dunno why */
 981        switch (edac_op_state) {
 982        case EDAC_OPSTATE_POLL:
 983        case EDAC_OPSTATE_NMI:
 984                break;
 985        default:
 986                edac_op_state = EDAC_OPSTATE_POLL;
 987                break;
 988        }
 989
 990        if (edac_mc_add_mc(mci)) {
 991                ret = -ENODEV;
 992                goto bail_scrub;
 993        }
 994
 995        return ret;
 996
 997bail_scrub:
 998        priv->scrub_enable = 0;
 999        cancel_delayed_work_sync(&(priv->i5100_scrubbing));
1000        edac_mc_free(mci);
1001
1002bail_disable_ch1:
1003        pci_disable_device(ch1mm);
1004
1005bail_ch1:
1006        pci_dev_put(ch1mm);
1007
1008bail_disable_ch0:
1009        pci_disable_device(ch0mm);
1010
1011bail_ch0:
1012        pci_dev_put(ch0mm);
1013
1014bail_pdev:
1015        pci_disable_device(pdev);
1016
1017bail:
1018        return ret;
1019}
1020
1021static void i5100_remove_one(struct pci_dev *pdev)
1022{
1023        struct mem_ctl_info *mci;
1024        struct i5100_priv *priv;
1025
1026        mci = edac_mc_del_mc(&pdev->dev);
1027
1028        if (!mci)
1029                return;
1030
1031        priv = mci->pvt_info;
1032
1033        priv->scrub_enable = 0;
1034        cancel_delayed_work_sync(&(priv->i5100_scrubbing));
1035
1036        pci_disable_device(pdev);
1037        pci_disable_device(priv->ch0mm);
1038        pci_disable_device(priv->ch1mm);
1039        pci_dev_put(priv->ch0mm);
1040        pci_dev_put(priv->ch1mm);
1041
1042        edac_mc_free(mci);
1043}
1044
1045static DEFINE_PCI_DEVICE_TABLE(i5100_pci_tbl) = {
1046        /* Device 16, Function 0, Channel 0 Memory Map, Error Flag/Mask, ... */
1047        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5100_16) },
1048        { 0, }
1049};
1050MODULE_DEVICE_TABLE(pci, i5100_pci_tbl);
1051
1052static struct pci_driver i5100_driver = {
1053        .name = KBUILD_BASENAME,
1054        .probe = i5100_init_one,
1055        .remove = i5100_remove_one,
1056        .id_table = i5100_pci_tbl,
1057};
1058
1059static int __init i5100_init(void)
1060{
1061        int pci_rc;
1062
1063        pci_rc = pci_register_driver(&i5100_driver);
1064
1065        return (pci_rc < 0) ? pci_rc : 0;
1066}
1067
1068static void __exit i5100_exit(void)
1069{
1070        pci_unregister_driver(&i5100_driver);
1071}
1072
1073module_init(i5100_init);
1074module_exit(i5100_exit);
1075
1076MODULE_LICENSE("GPL");
1077MODULE_AUTHOR
1078    ("Arthur Jones <ajones@riverbed.com>");
1079MODULE_DESCRIPTION("MC Driver for Intel I5100 memory controllers");
1080
lxr.linux.no kindly hosted by Redpill Linpro AS, provider of Linux consulting and operations services since 1995.