linux/drivers/edac/cell_edac.c
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   1/*
   2 * Cell MIC driver for ECC counting
   3 *
   4 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
   5 *                <benh@kernel.crashing.org>
   6 *
   7 * This file may be distributed under the terms of the
   8 * GNU General Public License.
   9 */
  10#undef DEBUG
  11
  12#include <linux/edac.h>
  13#include <linux/module.h>
  14#include <linux/init.h>
  15#include <linux/platform_device.h>
  16#include <linux/stop_machine.h>
  17#include <linux/io.h>
  18#include <asm/machdep.h>
  19#include <asm/cell-regs.h>
  20
  21#include "edac_core.h"
  22
  23struct cell_edac_priv
  24{
  25        struct cbe_mic_tm_regs __iomem  *regs;
  26        int                             node;
  27        int                             chanmask;
  28#ifdef DEBUG
  29        u64                             prev_fir;
  30#endif
  31};
  32
  33static void cell_edac_count_ce(struct mem_ctl_info *mci, int chan, u64 ar)
  34{
  35        struct cell_edac_priv           *priv = mci->pvt_info;
  36        struct csrow_info               *csrow = mci->csrows[0];
  37        unsigned long                   address, pfn, offset, syndrome;
  38
  39        dev_dbg(mci->pdev, "ECC CE err on node %d, channel %d, ar = 0x%016llx\n",
  40                priv->node, chan, ar);
  41
  42        /* Address decoding is likely a bit bogus, to dbl check */
  43        address = (ar & 0xffffffffe0000000ul) >> 29;
  44        if (priv->chanmask == 0x3)
  45                address = (address << 1) | chan;
  46        pfn = address >> PAGE_SHIFT;
  47        offset = address & ~PAGE_MASK;
  48        syndrome = (ar & 0x000000001fe00000ul) >> 21;
  49
  50        /* TODO: Decoding of the error address */
  51        edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
  52                             csrow->first_page + pfn, offset, syndrome,
  53                             0, chan, -1, "", "");
  54}
  55
  56static void cell_edac_count_ue(struct mem_ctl_info *mci, int chan, u64 ar)
  57{
  58        struct cell_edac_priv           *priv = mci->pvt_info;
  59        struct csrow_info               *csrow = mci->csrows[0];
  60        unsigned long                   address, pfn, offset;
  61
  62        dev_dbg(mci->pdev, "ECC UE err on node %d, channel %d, ar = 0x%016llx\n",
  63                priv->node, chan, ar);
  64
  65        /* Address decoding is likely a bit bogus, to dbl check */
  66        address = (ar & 0xffffffffe0000000ul) >> 29;
  67        if (priv->chanmask == 0x3)
  68                address = (address << 1) | chan;
  69        pfn = address >> PAGE_SHIFT;
  70        offset = address & ~PAGE_MASK;
  71
  72        /* TODO: Decoding of the error address */
  73        edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
  74                             csrow->first_page + pfn, offset, 0,
  75                             0, chan, -1, "", "");
  76}
  77
  78static void cell_edac_check(struct mem_ctl_info *mci)
  79{
  80        struct cell_edac_priv           *priv = mci->pvt_info;
  81        u64                             fir, addreg, clear = 0;
  82
  83        fir = in_be64(&priv->regs->mic_fir);
  84#ifdef DEBUG
  85        if (fir != priv->prev_fir) {
  86                dev_dbg(mci->pdev, "fir change : 0x%016lx\n", fir);
  87                priv->prev_fir = fir;
  88        }
  89#endif
  90        if ((priv->chanmask & 0x1) && (fir & CBE_MIC_FIR_ECC_SINGLE_0_ERR)) {
  91                addreg = in_be64(&priv->regs->mic_df_ecc_address_0);
  92                clear |= CBE_MIC_FIR_ECC_SINGLE_0_RESET;
  93                cell_edac_count_ce(mci, 0, addreg);
  94        }
  95        if ((priv->chanmask & 0x2) && (fir & CBE_MIC_FIR_ECC_SINGLE_1_ERR)) {
  96                addreg = in_be64(&priv->regs->mic_df_ecc_address_1);
  97                clear |= CBE_MIC_FIR_ECC_SINGLE_1_RESET;
  98                cell_edac_count_ce(mci, 1, addreg);
  99        }
 100        if ((priv->chanmask & 0x1) && (fir & CBE_MIC_FIR_ECC_MULTI_0_ERR)) {
 101                addreg = in_be64(&priv->regs->mic_df_ecc_address_0);
 102                clear |= CBE_MIC_FIR_ECC_MULTI_0_RESET;
 103                cell_edac_count_ue(mci, 0, addreg);
 104        }
 105        if ((priv->chanmask & 0x2) && (fir & CBE_MIC_FIR_ECC_MULTI_1_ERR)) {
 106                addreg = in_be64(&priv->regs->mic_df_ecc_address_1);
 107                clear |= CBE_MIC_FIR_ECC_MULTI_1_RESET;
 108                cell_edac_count_ue(mci, 1, addreg);
 109        }
 110
 111        /* The procedure for clearing FIR bits is a bit ... weird */
 112        if (clear) {
 113                fir &= ~(CBE_MIC_FIR_ECC_ERR_MASK | CBE_MIC_FIR_ECC_SET_MASK);
 114                fir |= CBE_MIC_FIR_ECC_RESET_MASK;
 115                fir &= ~clear;
 116                out_be64(&priv->regs->mic_fir, fir);
 117                (void)in_be64(&priv->regs->mic_fir);
 118
 119                mb();   /* sync up */
 120#ifdef DEBUG
 121                fir = in_be64(&priv->regs->mic_fir);
 122                dev_dbg(mci->pdev, "fir clear  : 0x%016lx\n", fir);
 123#endif
 124        }
 125}
 126
 127static void cell_edac_init_csrows(struct mem_ctl_info *mci)
 128{
 129        struct csrow_info               *csrow = mci->csrows[0];
 130        struct dimm_info                *dimm;
 131        struct cell_edac_priv           *priv = mci->pvt_info;
 132        struct device_node              *np;
 133        int                             j;
 134        u32                             nr_pages;
 135
 136        for (np = NULL;
 137             (np = of_find_node_by_name(np, "memory")) != NULL;) {
 138                struct resource r;
 139
 140                /* We "know" that the Cell firmware only creates one entry
 141                 * in the "memory" nodes. If that changes, this code will
 142                 * need to be adapted.
 143                 */
 144                if (of_address_to_resource(np, 0, &r))
 145                        continue;
 146                if (of_node_to_nid(np) != priv->node)
 147                        continue;
 148                csrow->first_page = r.start >> PAGE_SHIFT;
 149                nr_pages = resource_size(&r) >> PAGE_SHIFT;
 150                csrow->last_page = csrow->first_page + nr_pages - 1;
 151
 152                for (j = 0; j < csrow->nr_channels; j++) {
 153                        dimm = csrow->channels[j]->dimm;
 154                        dimm->mtype = MEM_XDR;
 155                        dimm->edac_mode = EDAC_SECDED;
 156                        dimm->nr_pages = nr_pages / csrow->nr_channels;
 157                }
 158                dev_dbg(mci->pdev,
 159                        "Initialized on node %d, chanmask=0x%x,"
 160                        " first_page=0x%lx, nr_pages=0x%x\n",
 161                        priv->node, priv->chanmask,
 162                        csrow->first_page, nr_pages);
 163                break;
 164        }
 165}
 166
 167static int cell_edac_probe(struct platform_device *pdev)
 168{
 169        struct cbe_mic_tm_regs __iomem  *regs;
 170        struct mem_ctl_info             *mci;
 171        struct edac_mc_layer            layers[2];
 172        struct cell_edac_priv           *priv;
 173        u64                             reg;
 174        int                             rc, chanmask, num_chans;
 175
 176        regs = cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(pdev->id));
 177        if (regs == NULL)
 178                return -ENODEV;
 179
 180        edac_op_state = EDAC_OPSTATE_POLL;
 181
 182        /* Get channel population */
 183        reg = in_be64(&regs->mic_mnt_cfg);
 184        dev_dbg(&pdev->dev, "MIC_MNT_CFG = 0x%016llx\n", reg);
 185        chanmask = 0;
 186        if (reg & CBE_MIC_MNT_CFG_CHAN_0_POP)
 187                chanmask |= 0x1;
 188        if (reg & CBE_MIC_MNT_CFG_CHAN_1_POP)
 189                chanmask |= 0x2;
 190        if (chanmask == 0) {
 191                dev_warn(&pdev->dev,
 192                         "Yuck ! No channel populated ? Aborting !\n");
 193                return -ENODEV;
 194        }
 195        dev_dbg(&pdev->dev, "Initial FIR = 0x%016llx\n",
 196                in_be64(&regs->mic_fir));
 197
 198        /* Allocate & init EDAC MC data structure */
 199        num_chans = chanmask == 3 ? 2 : 1;
 200
 201        layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
 202        layers[0].size = 1;
 203        layers[0].is_virt_csrow = true;
 204        layers[1].type = EDAC_MC_LAYER_CHANNEL;
 205        layers[1].size = num_chans;
 206        layers[1].is_virt_csrow = false;
 207        mci = edac_mc_alloc(pdev->id, ARRAY_SIZE(layers), layers,
 208                            sizeof(struct cell_edac_priv));
 209        if (mci == NULL)
 210                return -ENOMEM;
 211        priv = mci->pvt_info;
 212        priv->regs = regs;
 213        priv->node = pdev->id;
 214        priv->chanmask = chanmask;
 215        mci->pdev = &pdev->dev;
 216        mci->mtype_cap = MEM_FLAG_XDR;
 217        mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
 218        mci->edac_cap = EDAC_FLAG_EC | EDAC_FLAG_SECDED;
 219        mci->mod_name = "cell_edac";
 220        mci->ctl_name = "MIC";
 221        mci->dev_name = dev_name(&pdev->dev);
 222        mci->edac_check = cell_edac_check;
 223        cell_edac_init_csrows(mci);
 224
 225        /* Register with EDAC core */
 226        rc = edac_mc_add_mc(mci);
 227        if (rc) {
 228                dev_err(&pdev->dev, "failed to register with EDAC core\n");
 229                edac_mc_free(mci);
 230                return rc;
 231        }
 232
 233        return 0;
 234}
 235
 236static int cell_edac_remove(struct platform_device *pdev)
 237{
 238        struct mem_ctl_info *mci = edac_mc_del_mc(&pdev->dev);
 239        if (mci)
 240                edac_mc_free(mci);
 241        return 0;
 242}
 243
 244static struct platform_driver cell_edac_driver = {
 245        .driver         = {
 246                .name   = "cbe-mic",
 247                .owner  = THIS_MODULE,
 248        },
 249        .probe          = cell_edac_probe,
 250        .remove         = cell_edac_remove,
 251};
 252
 253static int __init cell_edac_init(void)
 254{
 255        /* Sanity check registers data structure */
 256        BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
 257                              mic_df_ecc_address_0) != 0xf8);
 258        BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
 259                              mic_df_ecc_address_1) != 0x1b8);
 260        BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
 261                              mic_df_config) != 0x218);
 262        BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
 263                              mic_fir) != 0x230);
 264        BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
 265                              mic_mnt_cfg) != 0x210);
 266        BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
 267                              mic_exc) != 0x208);
 268
 269        return platform_driver_register(&cell_edac_driver);
 270}
 271
 272static void __exit cell_edac_exit(void)
 273{
 274        platform_driver_unregister(&cell_edac_driver);
 275}
 276
 277module_init(cell_edac_init);
 278module_exit(cell_edac_exit);
 279
 280MODULE_LICENSE("GPL");
 281MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
 282MODULE_DESCRIPTION("ECC counting for Cell MIC");
 283
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