linux/drivers/edac/Kconfig
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   1#
   2#       EDAC Kconfig
   3#       Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
   4#       Licensed and distributed under the GPL
   5#
   6
   7config EDAC_SUPPORT
   8        bool
   9
  10menuconfig EDAC
  11        bool "EDAC (Error Detection And Correction) reporting"
  12        depends on HAS_IOMEM
  13        depends on X86 || PPC || TILE || ARM || EDAC_SUPPORT
  14        help
  15          EDAC is designed to report errors in the core system.
  16          These are low-level errors that are reported in the CPU or
  17          supporting chipset or other subsystems:
  18          memory errors, cache errors, PCI errors, thermal throttling, etc..
  19          If unsure, select 'Y'.
  20
  21          If this code is reporting problems on your system, please
  22          see the EDAC project web pages for more information at:
  23
  24          <http://bluesmoke.sourceforge.net/>
  25
  26          and:
  27
  28          <http://buttersideup.com/edacwiki>
  29
  30          There is also a mailing list for the EDAC project, which can
  31          be found via the sourceforge page.
  32
  33if EDAC
  34
  35config EDAC_LEGACY_SYSFS
  36        bool "EDAC legacy sysfs"
  37        default y
  38        help
  39          Enable the compatibility sysfs nodes.
  40          Use 'Y' if your edac utilities aren't ported to work with the newer
  41          structures.
  42
  43config EDAC_DEBUG
  44        bool "Debugging"
  45        help
  46          This turns on debugging information for the entire EDAC subsystem.
  47          You do so by inserting edac_module with "edac_debug_level=x." Valid
  48          levels are 0-4 (from low to high) and by default it is set to 2.
  49          Usually you should select 'N' here.
  50
  51config EDAC_DECODE_MCE
  52        tristate "Decode MCEs in human-readable form (only on AMD for now)"
  53        depends on CPU_SUP_AMD && X86_MCE_AMD
  54        default y
  55        ---help---
  56          Enable this option if you want to decode Machine Check Exceptions
  57          occurring on your machine in human-readable form.
  58
  59          You should definitely say Y here in case you want to decode MCEs
  60          which occur really early upon boot, before the module infrastructure
  61          has been initialized.
  62
  63config EDAC_MCE_INJ
  64        tristate "Simple MCE injection interface over /sysfs"
  65        depends on EDAC_DECODE_MCE
  66        default n
  67        help
  68          This is a simple interface to inject MCEs over /sysfs and test
  69          the MCE decoding code in EDAC.
  70
  71          This is currently AMD-only.
  72
  73config EDAC_MM_EDAC
  74        tristate "Main Memory EDAC (Error Detection And Correction) reporting"
  75        help
  76          Some systems are able to detect and correct errors in main
  77          memory.  EDAC can report statistics on memory error
  78          detection and correction (EDAC - or commonly referred to ECC
  79          errors).  EDAC will also try to decode where these errors
  80          occurred so that a particular failing memory module can be
  81          replaced.  If unsure, select 'Y'.
  82
  83config EDAC_AMD64
  84        tristate "AMD64 (Opteron, Athlon64) K8, F10h"
  85        depends on EDAC_MM_EDAC && AMD_NB && X86_64 && EDAC_DECODE_MCE
  86        help
  87          Support for error detection and correction of DRAM ECC errors on
  88          the AMD64 families of memory controllers (K8 and F10h)
  89
  90config EDAC_AMD64_ERROR_INJECTION
  91        bool "Sysfs HW Error injection facilities"
  92        depends on EDAC_AMD64
  93        help
  94          Recent Opterons (Family 10h and later) provide for Memory Error
  95          Injection into the ECC detection circuits. The amd64_edac module
  96          allows the operator/user to inject Uncorrectable and Correctable
  97          errors into DRAM.
  98
  99          When enabled, in each of the respective memory controller directories
 100          (/sys/devices/system/edac/mc/mcX), there are 3 input files:
 101
 102          - inject_section (0..3, 16-byte section of 64-byte cacheline),
 103          - inject_word (0..8, 16-bit word of 16-byte section),
 104          - inject_ecc_vector (hex ecc vector: select bits of inject word)
 105
 106          In addition, there are two control files, inject_read and inject_write,
 107          which trigger the DRAM ECC Read and Write respectively.
 108
 109config EDAC_AMD76X
 110        tristate "AMD 76x (760, 762, 768)"
 111        depends on EDAC_MM_EDAC && PCI && X86_32
 112        help
 113          Support for error detection and correction on the AMD 76x
 114          series of chipsets used with the Athlon processor.
 115
 116config EDAC_E7XXX
 117        tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
 118        depends on EDAC_MM_EDAC && PCI && X86_32
 119        help
 120          Support for error detection and correction on the Intel
 121          E7205, E7500, E7501 and E7505 server chipsets.
 122
 123config EDAC_E752X
 124        tristate "Intel e752x (e7520, e7525, e7320) and 3100"
 125        depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG
 126        help
 127          Support for error detection and correction on the Intel
 128          E7520, E7525, E7320 server chipsets.
 129
 130config EDAC_I82443BXGX
 131        tristate "Intel 82443BX/GX (440BX/GX)"
 132        depends on EDAC_MM_EDAC && PCI && X86_32
 133        depends on BROKEN
 134        help
 135          Support for error detection and correction on the Intel
 136          82443BX/GX memory controllers (440BX/GX chipsets).
 137
 138config EDAC_I82875P
 139        tristate "Intel 82875p (D82875P, E7210)"
 140        depends on EDAC_MM_EDAC && PCI && X86_32
 141        help
 142          Support for error detection and correction on the Intel
 143          DP82785P and E7210 server chipsets.
 144
 145config EDAC_I82975X
 146        tristate "Intel 82975x (D82975x)"
 147        depends on EDAC_MM_EDAC && PCI && X86
 148        help
 149          Support for error detection and correction on the Intel
 150          DP82975x server chipsets.
 151
 152config EDAC_I3000
 153        tristate "Intel 3000/3010"
 154        depends on EDAC_MM_EDAC && PCI && X86
 155        help
 156          Support for error detection and correction on the Intel
 157          3000 and 3010 server chipsets.
 158
 159config EDAC_I3200
 160        tristate "Intel 3200"
 161        depends on EDAC_MM_EDAC && PCI && X86 && EXPERIMENTAL
 162        help
 163          Support for error detection and correction on the Intel
 164          3200 and 3210 server chipsets.
 165
 166config EDAC_X38
 167        tristate "Intel X38"
 168        depends on EDAC_MM_EDAC && PCI && X86
 169        help
 170          Support for error detection and correction on the Intel
 171          X38 server chipsets.
 172
 173config EDAC_I5400
 174        tristate "Intel 5400 (Seaburg) chipsets"
 175        depends on EDAC_MM_EDAC && PCI && X86
 176        help
 177          Support for error detection and correction the Intel
 178          i5400 MCH chipset (Seaburg).
 179
 180config EDAC_I7CORE
 181        tristate "Intel i7 Core (Nehalem) processors"
 182        depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL
 183        help
 184          Support for error detection and correction the Intel
 185          i7 Core (Nehalem) Integrated Memory Controller that exists on
 186          newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
 187          and Xeon 55xx processors.
 188
 189config EDAC_I82860
 190        tristate "Intel 82860"
 191        depends on EDAC_MM_EDAC && PCI && X86_32
 192        help
 193          Support for error detection and correction on the Intel
 194          82860 chipset.
 195
 196config EDAC_R82600
 197        tristate "Radisys 82600 embedded chipset"
 198        depends on EDAC_MM_EDAC && PCI && X86_32
 199        help
 200          Support for error detection and correction on the Radisys
 201          82600 embedded chipset.
 202
 203config EDAC_I5000
 204        tristate "Intel Greencreek/Blackford chipset"
 205        depends on EDAC_MM_EDAC && X86 && PCI
 206        help
 207          Support for error detection and correction the Intel
 208          Greekcreek/Blackford chipsets.
 209
 210config EDAC_I5100
 211        tristate "Intel San Clemente MCH"
 212        depends on EDAC_MM_EDAC && X86 && PCI
 213        help
 214          Support for error detection and correction the Intel
 215          San Clemente MCH.
 216
 217config EDAC_I7300
 218        tristate "Intel Clarksboro MCH"
 219        depends on EDAC_MM_EDAC && X86 && PCI
 220        help
 221          Support for error detection and correction the Intel
 222          Clarksboro MCH (Intel 7300 chipset).
 223
 224config EDAC_SBRIDGE
 225        tristate "Intel Sandy-Bridge Integrated MC"
 226        depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
 227        depends on PCI_MMCONFIG && EXPERIMENTAL
 228        help
 229          Support for error detection and correction the Intel
 230          Sandy Bridge Integrated Memory Controller.
 231
 232config EDAC_MPC85XX
 233        tristate "Freescale MPC83xx / MPC85xx"
 234        depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
 235        help
 236          Support for error detection and correction on the Freescale
 237          MPC8349, MPC8560, MPC8540, MPC8548
 238
 239config EDAC_MV64X60
 240        tristate "Marvell MV64x60"
 241        depends on EDAC_MM_EDAC && MV64X60
 242        help
 243          Support for error detection and correction on the Marvell
 244          MV64360 and MV64460 chipsets.
 245
 246config EDAC_PASEMI
 247        tristate "PA Semi PWRficient"
 248        depends on EDAC_MM_EDAC && PCI
 249        depends on PPC_PASEMI
 250        help
 251          Support for error detection and correction on PA Semi
 252          PWRficient.
 253
 254config EDAC_CELL
 255        tristate "Cell Broadband Engine memory controller"
 256        depends on EDAC_MM_EDAC && PPC_CELL_COMMON
 257        help
 258          Support for error detection and correction on the
 259          Cell Broadband Engine internal memory controller
 260          on platform without a hypervisor
 261
 262config EDAC_PPC4XX
 263        tristate "PPC4xx IBM DDR2 Memory Controller"
 264        depends on EDAC_MM_EDAC && 4xx
 265        help
 266          This enables support for EDAC on the ECC memory used
 267          with the IBM DDR2 memory controller found in various
 268          PowerPC 4xx embedded processors such as the 405EX[r],
 269          440SP, 440SPe, 460EX, 460GT and 460SX.
 270
 271config EDAC_AMD8131
 272        tristate "AMD8131 HyperTransport PCI-X Tunnel"
 273        depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
 274        help
 275          Support for error detection and correction on the
 276          AMD8131 HyperTransport PCI-X Tunnel chip.
 277          Note, add more Kconfig dependency if it's adopted
 278          on some machine other than Maple.
 279
 280config EDAC_AMD8111
 281        tristate "AMD8111 HyperTransport I/O Hub"
 282        depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
 283        help
 284          Support for error detection and correction on the
 285          AMD8111 HyperTransport I/O Hub chip.
 286          Note, add more Kconfig dependency if it's adopted
 287          on some machine other than Maple.
 288
 289config EDAC_CPC925
 290        tristate "IBM CPC925 Memory Controller (PPC970FX)"
 291        depends on EDAC_MM_EDAC && PPC64
 292        help
 293          Support for error detection and correction on the
 294          IBM CPC925 Bridge and Memory Controller, which is
 295          a companion chip to the PowerPC 970 family of
 296          processors.
 297
 298config EDAC_TILE
 299        tristate "Tilera Memory Controller"
 300        depends on EDAC_MM_EDAC && TILE
 301        default y
 302        help
 303          Support for error detection and correction on the
 304          Tilera memory controller.
 305
 306config EDAC_HIGHBANK_MC
 307        tristate "Highbank Memory Controller"
 308        depends on EDAC_MM_EDAC && ARCH_HIGHBANK
 309        help
 310          Support for error detection and correction on the
 311          Calxeda Highbank memory controller.
 312
 313config EDAC_HIGHBANK_L2
 314        tristate "Highbank L2 Cache"
 315        depends on EDAC_MM_EDAC && ARCH_HIGHBANK
 316        help
 317          Support for error detection and correction on the
 318          Calxeda Highbank memory controller.
 319
 320config EDAC_OCTEON_PC
 321        tristate "Cavium Octeon Primary Caches"
 322        depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
 323        help
 324          Support for error detection and correction on the primary caches of
 325          the cnMIPS cores of Cavium Octeon family SOCs.
 326
 327config EDAC_OCTEON_L2C
 328        tristate "Cavium Octeon Secondary Caches (L2C)"
 329        depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
 330        help
 331          Support for error detection and correction on the
 332          Cavium Octeon family of SOCs.
 333
 334config EDAC_OCTEON_LMC
 335        tristate "Cavium Octeon DRAM Memory Controller (LMC)"
 336        depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
 337        help
 338          Support for error detection and correction on the
 339          Cavium Octeon family of SOCs.
 340
 341config EDAC_OCTEON_PCI
 342        tristate "Cavium Octeon PCI Controller"
 343        depends on EDAC_MM_EDAC && PCI && CPU_CAVIUM_OCTEON
 344        help
 345          Support for error detection and correction on the
 346          Cavium Octeon family of SOCs.
 347
 348endif # EDAC
 349
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