LXR linux/drivers/cpufreq/exynos4210-cpufreq.c

   1/*
   2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3 *              http://www.samsung.com
   4 *
   5 * EXYNOS4210 - CPU frequency scaling support
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License version 2 as
   9 * published by the Free Software Foundation.
  10*/
  11
  12#include <linux/module.h>
  13#include <linux/kernel.h>
  14#include <linux/err.h>
  15#include <linux/clk.h>
  16#include <linux/io.h>
  17#include <linux/slab.h>
  18#include <linux/cpufreq.h>
  19
  20#include <mach/regs-clock.h>
  21#include <mach/cpufreq.h>
  22
  23#define CPUFREQ_LEVEL_END       L5
  24
  25static int max_support_idx = L0;
  26static int min_support_idx = (CPUFREQ_LEVEL_END - 1);
  27
  28static struct clk *cpu_clk;
  29static struct clk *moutcore;
  30static struct clk *mout_mpll;
  31static struct clk *mout_apll;
  32
  33struct cpufreq_clkdiv {
  34        unsigned int index;
  35        unsigned int clkdiv;
  36};
  37
  38static unsigned int exynos4210_volt_table[CPUFREQ_LEVEL_END] = {
  39        1250000, 1150000, 1050000, 975000, 950000,
  40};
  41
  42
  43static struct cpufreq_clkdiv exynos4210_clkdiv_table[CPUFREQ_LEVEL_END];
  44
  45static struct cpufreq_frequency_table exynos4210_freq_table[] = {
  46        {L0, 1200*1000},
  47        {L1, 1000*1000},
  48        {L2, 800*1000},
  49        {L3, 500*1000},
  50        {L4, 200*1000},
  51        {0, CPUFREQ_TABLE_END},
  52};
  53
  54static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
  55        /*
  56         * Clock divider value for following
  57         * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
  58         *              DIVATB, DIVPCLK_DBG, DIVAPLL }
  59         */
  60
  61        /* ARM L0: 1200MHz */
  62        { 0, 3, 7, 3, 4, 1, 7 },
  63
  64        /* ARM L1: 1000MHz */
  65        { 0, 3, 7, 3, 4, 1, 7 },
  66
  67        /* ARM L2: 800MHz */
  68        { 0, 3, 7, 3, 3, 1, 7 },
  69
  70        /* ARM L3: 500MHz */
  71        { 0, 3, 7, 3, 3, 1, 7 },
  72
  73        /* ARM L4: 200MHz */
  74        { 0, 1, 3, 1, 3, 1, 0 },
  75};
  76
  77static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
  78        /*
  79         * Clock divider value for following
  80         * { DIVCOPY, DIVHPM }
  81         */
  82
  83        /* ARM L0: 1200MHz */
  84        { 5, 0 },
  85
  86        /* ARM L1: 1000MHz */
  87        { 4, 0 },
  88
  89        /* ARM L2: 800MHz */
  90        { 3, 0 },
  91
  92        /* ARM L3: 500MHz */
  93        { 3, 0 },
  94
  95        /* ARM L4: 200MHz */
  96        { 3, 0 },
  97};
  98
  99static unsigned int exynos4210_apll_pms_table[CPUFREQ_LEVEL_END] = {
 100        /* APLL FOUT L0: 1200MHz */
 101        ((150 << 16) | (3 << 8) | 1),
 102
 103        /* APLL FOUT L1: 1000MHz */
 104        ((250 << 16) | (6 << 8) | 1),
 105
 106        /* APLL FOUT L2: 800MHz */
 107        ((200 << 16) | (6 << 8) | 1),
 108
 109        /* APLL FOUT L3: 500MHz */
 110        ((250 << 16) | (6 << 8) | 2),
 111
 112        /* APLL FOUT L4: 200MHz */
 113        ((200 << 16) | (6 << 8) | 3),
 114};
 115
 116static void exynos4210_set_clkdiv(unsigned int div_index)
 117{
 118        unsigned int tmp;
 119
 120        /* Change Divider - CPU0 */
 121
 122        tmp = exynos4210_clkdiv_table[div_index].clkdiv;
 123
 124        __raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
 125
 126        do {
 127                tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU);
 128        } while (tmp & 0x1111111);
 129
 130        /* Change Divider - CPU1 */
 131
 132        tmp = __raw_readl(EXYNOS4_CLKDIV_CPU1);
 133
 134        tmp &= ~((0x7 << 4) | 0x7);
 135
 136        tmp |= ((clkdiv_cpu1[div_index][0] << 4) |
 137                (clkdiv_cpu1[div_index][1] << 0));
 138
 139        __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
 140
 141        do {
 142                tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1);
 143        } while (tmp & 0x11);
 144}
 145
 146static void exynos4210_set_apll(unsigned int index)
 147{
 148        unsigned int tmp;
 149
 150        /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
 151        clk_set_parent(moutcore, mout_mpll);
 152
 153        do {
 154                tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
 155                        >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
 156                tmp &= 0x7;
 157        } while (tmp != 0x2);
 158
 159        /* 2. Set APLL Lock time */
 160        __raw_writel(EXYNOS4_APLL_LOCKTIME, EXYNOS4_APLL_LOCK);
 161
 162        /* 3. Change PLL PMS values */
 163        tmp = __raw_readl(EXYNOS4_APLL_CON0);
 164        tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
 165        tmp |= exynos4210_apll_pms_table[index];
 166        __raw_writel(tmp, EXYNOS4_APLL_CON0);
 167
 168        /* 4. wait_lock_time */
 169        do {
 170                tmp = __raw_readl(EXYNOS4_APLL_CON0);
 171        } while (!(tmp & (0x1 << EXYNOS4_APLLCON0_LOCKED_SHIFT)));
 172
 173        /* 5. MUX_CORE_SEL = APLL */
 174        clk_set_parent(moutcore, mout_apll);
 175
 176        do {
 177                tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
 178                tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
 179        } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
 180}
 181
 182bool exynos4210_pms_change(unsigned int old_index, unsigned int new_index)
 183{
 184        unsigned int old_pm = (exynos4210_apll_pms_table[old_index] >> 8);
 185        unsigned int new_pm = (exynos4210_apll_pms_table[new_index] >> 8);
 186
 187        return (old_pm == new_pm) ? 0 : 1;
 188}
 189
 190static void exynos4210_set_frequency(unsigned int old_index,
 191                                     unsigned int new_index)
 192{
 193        unsigned int tmp;
 194
 195        if (old_index > new_index) {
 196                if (!exynos4210_pms_change(old_index, new_index)) {
 197                        /* 1. Change the system clock divider values */
 198                        exynos4210_set_clkdiv(new_index);
 199
 200                        /* 2. Change just s value in apll m,p,s value */
 201                        tmp = __raw_readl(EXYNOS4_APLL_CON0);
 202                        tmp &= ~(0x7 << 0);
 203                        tmp |= (exynos4210_apll_pms_table[new_index] & 0x7);
 204                        __raw_writel(tmp, EXYNOS4_APLL_CON0);
 205                } else {
 206                        /* Clock Configuration Procedure */
 207                        /* 1. Change the system clock divider values */
 208                        exynos4210_set_clkdiv(new_index);
 209                        /* 2. Change the apll m,p,s value */
 210                        exynos4210_set_apll(new_index);
 211                }
 212        } else if (old_index < new_index) {
 213                if (!exynos4210_pms_change(old_index, new_index)) {
 214                        /* 1. Change just s value in apll m,p,s value */
 215                        tmp = __raw_readl(EXYNOS4_APLL_CON0);
 216                        tmp &= ~(0x7 << 0);
 217                        tmp |= (exynos4210_apll_pms_table[new_index] & 0x7);
 218                        __raw_writel(tmp, EXYNOS4_APLL_CON0);
 219
 220                        /* 2. Change the system clock divider values */
 221                        exynos4210_set_clkdiv(new_index);
 222                } else {
 223                        /* Clock Configuration Procedure */
 224                        /* 1. Change the apll m,p,s value */
 225                        exynos4210_set_apll(new_index);
 226                        /* 2. Change the system clock divider values */
 227                        exynos4210_set_clkdiv(new_index);
 228                }
 229        }
 230}
 231
 232int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
 233{
 234        int i;
 235        unsigned int tmp;
 236        unsigned long rate;
 237
 238        cpu_clk = clk_get(NULL, "armclk");
 239        if (IS_ERR(cpu_clk))
 240                return PTR_ERR(cpu_clk);
 241
 242        moutcore = clk_get(NULL, "moutcore");
 243        if (IS_ERR(moutcore))
 244                goto err_moutcore;
 245
 246        mout_mpll = clk_get(NULL, "mout_mpll");
 247        if (IS_ERR(mout_mpll))
 248                goto err_mout_mpll;
 249
 250        rate = clk_get_rate(mout_mpll) / 1000;
 251
 252        mout_apll = clk_get(NULL, "mout_apll");
 253        if (IS_ERR(mout_apll))
 254                goto err_mout_apll;
 255
 256        tmp = __raw_readl(EXYNOS4_CLKDIV_CPU);
 257
 258        for (i = L0; i <  CPUFREQ_LEVEL_END; i++) {
 259                tmp &= ~(EXYNOS4_CLKDIV_CPU0_CORE_MASK |
 260                        EXYNOS4_CLKDIV_CPU0_COREM0_MASK |
 261                        EXYNOS4_CLKDIV_CPU0_COREM1_MASK |
 262                        EXYNOS4_CLKDIV_CPU0_PERIPH_MASK |
 263                        EXYNOS4_CLKDIV_CPU0_ATB_MASK |
 264                        EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK |
 265                        EXYNOS4_CLKDIV_CPU0_APLL_MASK);
 266
 267                tmp |= ((clkdiv_cpu0[i][0] << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) |
 268                        (clkdiv_cpu0[i][1] << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) |
 269                        (clkdiv_cpu0[i][2] << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) |
 270                        (clkdiv_cpu0[i][3] << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) |
 271                        (clkdiv_cpu0[i][4] << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) |
 272                        (clkdiv_cpu0[i][5] << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) |
 273                        (clkdiv_cpu0[i][6] << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT));
 274
 275                exynos4210_clkdiv_table[i].clkdiv = tmp;
 276        }
 277
 278        info->mpll_freq_khz = rate;
 279        info->pm_lock_idx = L2;
 280        info->pll_safe_idx = L2;
 281        info->max_support_idx = max_support_idx;
 282        info->min_support_idx = min_support_idx;
 283        info->cpu_clk = cpu_clk;
 284        info->volt_table = exynos4210_volt_table;
 285        info->freq_table = exynos4210_freq_table;
 286        info->set_freq = exynos4210_set_frequency;
 287        info->need_apll_change = exynos4210_pms_change;
 288
 289        return 0;
 290
 291err_mout_apll:
 292        if (!IS_ERR(mout_mpll))
 293                clk_put(mout_mpll);
 294err_mout_mpll:
 295        if (!IS_ERR(moutcore))
 296                clk_put(moutcore);
 297err_moutcore:
 298        if (!IS_ERR(cpu_clk))
 299                clk_put(cpu_clk);
 300
 301        pr_debug("%s: failed initialization\n", __func__);
 302        return -EINVAL;
 303}
 304EXPORT_SYMBOL(exynos4210_cpufreq_init);
 305