linux/drivers/clk/clk-u300.c
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   1/*
   2 * U300 clock implementation
   3 * Copyright (C) 2007-2012 ST-Ericsson AB
   4 * License terms: GNU General Public License (GPL) version 2
   5 * Author: Linus Walleij <linus.walleij@stericsson.com>
   6 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
   7 */
   8#include <linux/clk.h>
   9#include <linux/clkdev.h>
  10#include <linux/err.h>
  11#include <linux/io.h>
  12#include <linux/clk-provider.h>
  13#include <linux/spinlock.h>
  14#include <mach/syscon.h>
  15
  16/*
  17 * The clocking hierarchy currently looks like this.
  18 * NOTE: the idea is NOT to show how the clocks are routed on the chip!
  19 * The ideas is to show dependencies, so a clock higher up in the
  20 * hierarchy has to be on in order for another clock to be on. Now,
  21 * both CPU and DMA can actually be on top of the hierarchy, and that
  22 * is not modeled currently. Instead we have the backbone AMBA bus on
  23 * top. This bus cannot be programmed in any way but conceptually it
  24 * needs to be active for the bridges and devices to transport data.
  25 *
  26 * Please be aware that a few clocks are hw controlled, which mean that
  27 * the hw itself can turn on/off or change the rate of the clock when
  28 * needed!
  29 *
  30 *  AMBA bus
  31 *  |
  32 *  +- CPU
  33 *  +- FSMC NANDIF NAND Flash interface
  34 *  +- SEMI Shared Memory interface
  35 *  +- ISP Image Signal Processor (U335 only)
  36 *  +- CDS (U335 only)
  37 *  +- DMA Direct Memory Access Controller
  38 *  +- AAIF APP/ACC Inteface (Mobile Scalable Link, MSL)
  39 *  +- APEX
  40 *  +- VIDEO_ENC AVE2/3 Video Encoder
  41 *  +- XGAM Graphics Accelerator Controller
  42 *  +- AHB
  43 *  |
  44 *  +- ahb:0 AHB Bridge
  45 *  |  |
  46 *  |  +- ahb:1 INTCON Interrupt controller
  47 *  |  +- ahb:3 MSPRO  Memory Stick Pro controller
  48 *  |  +- ahb:4 EMIF   External Memory interface
  49 *  |
  50 *  +- fast:0 FAST bridge
  51 *  |  |
  52 *  |  +- fast:1 MMCSD MMC/SD card reader controller
  53 *  |  +- fast:2 I2S0  PCM I2S channel 0 controller
  54 *  |  +- fast:3 I2S1  PCM I2S channel 1 controller
  55 *  |  +- fast:4 I2C0  I2C channel 0 controller
  56 *  |  +- fast:5 I2C1  I2C channel 1 controller
  57 *  |  +- fast:6 SPI   SPI controller
  58 *  |  +- fast:7 UART1 Secondary UART (U335 only)
  59 *  |
  60 *  +- slow:0 SLOW bridge
  61 *     |
  62 *     +- slow:1 SYSCON (not possible to control)
  63 *     +- slow:2 WDOG Watchdog
  64 *     +- slow:3 UART0 primary UART
  65 *     +- slow:4 TIMER_APP Application timer - used in Linux
  66 *     +- slow:5 KEYPAD controller
  67 *     +- slow:6 GPIO controller
  68 *     +- slow:7 RTC controller
  69 *     +- slow:8 BT Bus Tracer (not used currently)
  70 *     +- slow:9 EH Event Handler (not used currently)
  71 *     +- slow:a TIMER_ACC Access style timer (not used currently)
  72 *     +- slow:b PPM (U335 only, what is that?)
  73 */
  74
  75/* Global syscon virtual base */
  76static void __iomem *syscon_vbase;
  77
  78/**
  79 * struct clk_syscon - U300 syscon clock
  80 * @hw: corresponding clock hardware entry
  81 * @hw_ctrld: whether this clock is hardware controlled (for refcount etc)
  82 *      and does not need any magic pokes to be enabled/disabled
  83 * @reset: state holder, whether this block's reset line is asserted or not
  84 * @res_reg: reset line enable/disable flag register
  85 * @res_bit: bit for resetting or taking this consumer out of reset
  86 * @en_reg: clock line enable/disable flag register
  87 * @en_bit: bit for enabling/disabling this consumer clock line
  88 * @clk_val: magic value to poke in the register to enable/disable
  89 *      this one clock
  90 */
  91struct clk_syscon {
  92        struct clk_hw hw;
  93        bool hw_ctrld;
  94        bool reset;
  95        void __iomem *res_reg;
  96        u8 res_bit;
  97        void __iomem *en_reg;
  98        u8 en_bit;
  99        u16 clk_val;
 100};
 101
 102#define to_syscon(_hw) container_of(_hw, struct clk_syscon, hw)
 103
 104static DEFINE_SPINLOCK(syscon_resetreg_lock);
 105
 106/*
 107 * Reset control functions. We remember if a block has been
 108 * taken out of reset and don't remove the reset assertion again
 109 * and vice versa. Currently we only remove resets so the
 110 * enablement function is defined out.
 111 */
 112static void syscon_block_reset_enable(struct clk_syscon *sclk)
 113{
 114        unsigned long iflags;
 115        u16 val;
 116
 117        /* Not all blocks support resetting */
 118        if (!sclk->res_reg)
 119                return;
 120        spin_lock_irqsave(&syscon_resetreg_lock, iflags);
 121        val = readw(sclk->res_reg);
 122        val |= BIT(sclk->res_bit);
 123        writew(val, sclk->res_reg);
 124        spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
 125        sclk->reset = true;
 126}
 127
 128static void syscon_block_reset_disable(struct clk_syscon *sclk)
 129{
 130        unsigned long iflags;
 131        u16 val;
 132
 133        /* Not all blocks support resetting */
 134        if (!sclk->res_reg)
 135                return;
 136        spin_lock_irqsave(&syscon_resetreg_lock, iflags);
 137        val = readw(sclk->res_reg);
 138        val &= ~BIT(sclk->res_bit);
 139        writew(val, sclk->res_reg);
 140        spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
 141        sclk->reset = false;
 142}
 143
 144static int syscon_clk_prepare(struct clk_hw *hw)
 145{
 146        struct clk_syscon *sclk = to_syscon(hw);
 147
 148        /* If the block is in reset, bring it out */
 149        if (sclk->reset)
 150                syscon_block_reset_disable(sclk);
 151        return 0;
 152}
 153
 154static void syscon_clk_unprepare(struct clk_hw *hw)
 155{
 156        struct clk_syscon *sclk = to_syscon(hw);
 157
 158        /* Please don't force the console into reset */
 159        if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN)
 160                return;
 161        /* When unpreparing, force block into reset */
 162        if (!sclk->reset)
 163                syscon_block_reset_enable(sclk);
 164}
 165
 166static int syscon_clk_enable(struct clk_hw *hw)
 167{
        struct clk_syscon *sclk = to_syscon(hw);
  31L86"> 31  31 *  1   +-170hen unpreparing, force block into resD*/touchge the/span>
 *  1   +-171lass="sref">sclk->clk_val ==  *  1   +-172rivers/clk/clk-u300.c#L16152" id="L152" class="line" name="L152" 73 */<1/span17Not all blocks support resetting */}a href="drivers/clk/clk-1u300.17 class="sref">scl->clk_val == 
pan class="comment">/* G1lobal17drivers/clk/clk-u300.c#L13652" id="L152" class="line" name="L152"  166satic void 
<1a href="drivers/clk/clk-1u300.17="sref">val = val, clk_val == U300_SYSCONCLK_EN)
  31/**<1/span17_syscon" clasc#L13652" id="L152" class="line" name="L152"  class="cpan class="comment"> * s1truct1clk_sy" id="L165" class="line" name="L165" 80 * @1hw: c1rrespo id="L165" class="line" name="L165" 71 * @1hw_ct181clk_unprepare" class="sref">syscon_clk_unpet_disable(clk_hw *hw)
 *  1    a1d does" id="L168" class="line" name="L1s=" 83 * @1reset183syscon" class="sref">clk_syscon *sclk = to_syscon(hw);
  31 * @1res_r18L75" id="L75" class="line" name="L75"> 1 85 * @1res_b185hen unpreparing, force block into resD*/touchge the/span>
 * @1en_re186lass="sref">sclk->clk_val ==  * @1en_bi187rivers/clk/clk-u300.c#L136+code=sclk" class="L31">  31 * NOTspan18 class="sref">scl->clk_val ==  *  1    t18drivers/clk/clk-u300.c#L120" id="L120" class="line" name="L120" 90 */<1/span190hen unpreparing, force block into reso reset */drivers/ef="drivers/ers/c0.c#L162" id="L162" class="line" name="L162" 91st1ruct sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN)
  1      struct   1      bool val, clk_val == U300_SYSCDNCLK_EN)
  31  1      void   1        1      void syscon_clk_enableishw" cla"drivers/clk/clk_clk_enableishw" cla"ss="sref">clk_hw *hw)
  1        1      u16clk_syscon *sclk = to_syscon(hw);
  31 1002;
sde=val" class="sref">val;
sclkk->reset)
/*<2span>20irqsave" class="sref">spin_lcode=readw" class="sref">readw(sclk->res_reg);
 * 2eset 20="sref">val = rf">BIT = sclk->res_bit);
 * 2aken 2ut of  id="L132" class="line" name="L1322>29 * 2nd vi20="sref">u16 = r? 1 :52" id="L152" class="line" name="L1522> 1102span class="comment"> * 2nable2ent fu" id="L165" class="line" name="L1652> 1112span class="comment"> */2/span21L102" id="L102" class="line" name="L1022> 1122tatic void sde=val" class="sref">val;
sclkre" " id="L167" class="line" name="L1672> 1132
bool val;
 2> 1162spin_lcode=readw" class="sref">readw(sclk->;
U300_SCCNCLK_EN)
/21="sref">val = rf">BIT = ;
 * hin_loc22respo id="L165" class="line" name="L1652 21 * bo" cla221clk_unprepalass="sref">i id="L165" class="line" name="L1652 22 * is sysc2modeled="sref">syscon_clk_enablerecalc_"dridrivers/clk/clk_clk_enablerecalc_"driss="sref">clk_hw *hw)
 * totew" 22scon_block_reset_enabbbbbbbblass="sref">iflags;
 * nen_unl2ck_irq" id="L114" class="line" name="L1142 25 *sclks="sref">clk_syscon *sclk = to_syscon(hw);
  31 * Pl-u30022"sref">u8 val;
sclef">to_syscon(_clk_enget_peref="+code=_hw" c_clk_enget_pere>sclk"+code=sclk" class="L31">  312pan class="comment"> * thu300.2#L128" id="L128" class="line" name="L1282 28 * ne=sysc22_syscon" classwitch/a>, clk_val ==  2 29 *u16U300_SYSCON_k/cl_BRIDGER_UART_CLK_EN)
 2> 1302       unsigned long U300_SYSCON_)
 2>21u16U300_SYSCON_)
 2>22u16U300_SYSCON_MMCR_UART_CLK_EN)
 2> 1132       /2 Not all blockcesetCLK_EN" class="sref">U300_SYSCON_SPIR_UART_CLK_EN)
 2>24, scl)" id="L92" class="line" name="L92"> 2> 1362       U300_SCCNu300ING_PERFORMANCE_LOW_POWONCLK_EN)
 2> 1172       U300_SCCNu300ING_PERFORMANCE_LOWCLK_EN)
 2>28val  31 1392        2> 1402       sclkkkkkkkkk" id="L165" class="line" name="L1652> 1422
u16U300_SYSCON_DMACR_UART_CLK_EN)
 2> 1432U300_SYSCON_NANDIFR_UART_CLK_EN)
 2>24U300_SYSCON_XGAMR_UART_CLK_EN)
 2> 1352
, scl)" id="L92" class="line" name="L92"> 2> 1472U300_SCCNu300ING_PERFORMANCE_LOW_POWONCLK_EN)
 2> 1482       /24="sref">valU300_SCCNu300ING_PERFORMANCE_LOWCLK_EN)
 2> 1492       if (  31 1502               U300_SCCNu300ING_PERFORMANCE_INTERMEDIATECLK_EN)
 2> 1512       return 0;
sclkkkkkkkkk////////c#L161 26L99999+code=sclk" class="L31">  31 1522
 2> 1532U300_SYSCON_SEMIR_UART_CLK_EN)
 2> 1462       struct U300_SYSCON_EMIFR_UART_CLK_EN)
 2> 1472/25="sref">val, scl)" id="L92" class="line" name="L92"> 2> 1592       if (U300_SCCNu300ING_PERFORMANCE_LOW_POWONCLK_EN)
 2> 1602               return;
<2 href2"drivers/clk/clk-u300.cesetCLK_EN" class="sref">U300_SCCNu300ING_PERFORMANCE_LOWCLK_EN)
 2> 1612       /26s="sref">sclkkkkkkkkk////////c#L161 1"L99999+code=sclk" class="L31">  31 1622       if (!U300_SCCNu300ING_PERFORMANCE_INTERMEDIATECLK_EN)
 2> 1632                 31 1542
 2> 1652  31 1462tatic int U300_SYSCON_CPUR_UART_CLK_EN)
 2> 1582       struct valL86"> 31, scl)" id="L92" class="line" name="L92"> 2 70 *  2   +-27drivers/clk/clk-u300.cesetCLK_EN" class="sref">U300_SCCNu300ING_PERFORMANCE_LOW_POWONCLK_EN)
 2 71 *  2   +-27s="sref">sclkkkkkkkkkcesetCLK_EN" class="sref">U300_SCCNu300ING_PERFORMANCE_LOWCLK_EN)
 2 72 *  2   +-272rivers/clk/clk-u300.////////c#L161 1"L99999+code=sclk" class="L31">  31 */<2/span27scon_block_reset_enabcesetCLK_EN" class="sref">U300_SCCNu300ING_PERFORMANCE_INTERMEDIATECLK_EN)
 2  1642a href="drivers/clk/clk-2u300.274rivers/clk/clk-u300.////////c#L161 52L99999+code=sclk" class="L31">  312pan class="comment">/* G2lobal27drivers/clk/clk-u300.cesetCLK_EN" class="sref">U300_SCCNu300ING_PERFORMANCE_HIGHCLK_EN)
 2  1462atic void   31
<2a href="drivers/clk/clk-2u300.277rivers/clk/clk-u300.default:id="L92" class="line" name="L92"> 2 78/**<2/span27="sref">val;
 * s2truct27drivers/clk/clk-u300." id="L165" class="line" name="L1652 80 * @2hw: c28drivers/clk/cdefault:id="L92" class="line" name="L92"> 2 71 * @2hw_ct28s="sref">sclkkkkkkkkkf="drivers/clk/clk-u300.c#L107" id="L107" class="line" name="L1072 82 *  2    a2d doesef="drivers/clk/clk-u300000000000000000/sThllSLOWkhat_hL107" id="L107" class="line" name="L1072 73 * @2reset283syscef="drivers/clk/clk-u300000000000000000/sef=ir  clant (typically PLL13 1" MHz).c#L111" id="L111" class="line" name="L1112 84 * @2res_r28L75" ef="drivers/clk/clk-u300000000000000000/.c#L162" id="L162" class="line" name="L1622 85 * @2res_b28drivers/clk/clk-u300.c#L1365lags;
 * @2en_re286lass="sref">" id="L165" class="line" name="L1652 77
<2pan class="comment"> * @2en_bi287rive" id="L165" class="line" name="L1652 78 * N2Tspan28t of  id="L132" class="line" name="L1322 89 *  2    t28driveunprepaf">i id="L165" class="line" name="L1652 90 */<2/span290hen d="sref">syscon_clk_enableround_"dridrivers/clk/clk_clk_enableround_"driss="sref">clk_hw *hw)
iflags;
sclkkkkkkkkk//////lass="sref">if>)
clk_syscon *sclk = to_syscon(hw);
  31  2       2 95  2      void clk_val == U300_SYSCON_CPUR_UART_CLK_EN)
)
  31
<2      void 0ef="CPUkhatscl->  31 1003;
scl->sclkkkkkkkkkc#L161 52L99999+code=sclk" class="L31">  31 1023define scl->  31 1043tatic   3151043t     void /*<3span>30L117" id="L117" class="line" name="L1173>27 * 3eset 30em" cnable" class="sref">syscon_clk_enableass="dridrivers/clk/clk_clk_enableass="driss="sref">clk_hw *hw)
iflags;
 * 3aken 30="sref">valiflags;
 * 3nable31k_irqrestore"s="sref">clk_syscon *sclk = to_syscon(hw);
  31 1113span class="comment"> */3/span31="sref">u16 val;
0ef="CPUkhatscl->clk_val == U300_SYSCON_CPUR_UART_CLK_EN)
-> 3> 1173       /317syscon" clasceset1"L99999:id="L92" class="line" name="L92"> 3>28val;
to_syscon(sref">U300_SCCNu300ING_PERFORMANCE_LOW_POWONCLK_EN)
 * h3n_loc32ode=iflags" cceset52L99999:id="L92" class="line" name="L92"> 3 21 * b3" cla32s="sref">sclkkkkkkkkkf>;
to_syscon(sref">U300_SCCNu300ING_PERFORMANCE_INTERMEDIATECLK_EN)
 * i3 sysc322rivers/clk/clk-u300.b hak" id="L132" class="line" name="L1323  1133pan class="comment"> * t3tew" 32Not all blockceset104L99999:id="L92" class="line" name="L92"> 3  1143pan class="comment"> * n3n_unl324rivers/clk/clk-u300.s>;
to_syscon(sref">U300_SCCNu300ING_PERFORMANCE_HIGHCLK_EN)
 *3pan class="comment"> * P3-u30032_syscon" clasceset208L99999:id="L92" class="line" name="L92"> 3  1173pan class="comment"> * t3u300.327rivers/clk/clk-u300.s>;
to_syscon(sref">U300_SCCNu300ING_PERFORMANCE_BES=sclk" class="srsref">U300_SCCNu300ING_PERFORMANCE_BES="sre" id="L132" class="line" name="L1323 28 * n3=sysc32="sref">val *u16 3> 1303       unsigned long u1622u16;
sclk->;
U300_SCCNCLK_EN)
BI id="L165" class="line" name="L1653> 1133       /33scon_block_reset_enab/a>(U300_SCCNu300ING_PERFORMANCE_MAS href="+code=syshref="driverCCNu300ING_PERFORMANCE_MAS L132 I id="L165" class="line" name="L1653> 1143       if (!bool val, sclk->;
U300_SCCNCLK_EN)
clk_syscon * *;
 3> 1393       (struct to_syscon(_clk_encepare(struct to_syscon(_clk_enceparepare(struct sclk.)
to_syscon(_clk_encepa(struct u16(to_syscon(_clk_encepaet_disable(to_syscon(_clk_encepaishw" cla"drivers/clk/clk_clk_enableishw" cla"ss=", id="L165" class="line" name="L1653> 1143tatic int to_syscon(_clk_enceparecalc_"dridrivers/clk/clk_clk_enablerecalc_"driss=", id="L165" class="line" name="L1653> 1353
to_syscon(_clk_enceparound_"dridrivers/clk/clk_clk_enableround_"driss=", id="L165" class="line" name="L1653> 1363       struct to_syscon(_clk_encepaass="dridrivers/clk/clk_clk_enableass="driss=", id="L165" class="line" name="L1653> 1173/34t of  id="L132" class="line" name="L1323> 1493       if (clk_syscon *rivers/clk/clk-> *">sclkf">clk_sysconsyscon_clk_enableref="dridrivers/clk/clk_clk_enableref="driss="sref">clk_hw *(sclk = (sclkdrivt"charlk = (sclkkkkkkkkk////drivt"charlk = (iflags;
 sys__iomemivers/clk/clk-u__iomem">sclk = sclk->;
sys__iomemivers/clk/clk-u__iomem">sclk = ->;
 val;
 3> 1473clk_syscon *rivers/clk/clk-> *">sclk">clk_syscon *rivers/clk/clk-> *">sc" id="L152" class="line" name="L1523> 1583       /35_syscon" class="sref">clk_syscon *sclk = u16clk_syscon *;
/36="sref">u16 to_syscon(kzallocde=to_syscon" ckzallocss="srizeofsref">clk_hw *sc)lk->)
sclk-> 3> 1633               "could ptuaallocdri ="srefkhat;
)
" id="L165" class="line" name="L1653> 1673
val = (to_syscon( hreble(val = BIa>;
L86"> 31 = to_syscon(flagdrivers/clk/clk-flagdss="" id="L132" class="line" name="L1323 70 *  3   +-37k_irqrestore" class="sref">sindrivers/clk/clk-uindr of .)
, BIa>;
sNULLCLK_EN)
 *  3   +-37="sref">u16 ,  *  3   +-372"sref">u16;
clk_val == BIa>;
 */<3/span37scon_block_res>;
clk_val == to_syscon(a href="drivers/clk/clk-u300.c#L94"" id="L152" class="line" name="L1523  1543a href="drivers/clk/clk-3u300.374rivers/clk/cs support resetting *//* G3lobal37drivers/clk/cs>;
clk_val == to_syscon(ef"eble(u8 clk_val == screadw(sc" id="L152" class="line" name="L1523  1673a href="drivers/clk/clk-3u300.37="sref">val = clk_val == (/**<3/span37="sref">val = res_reg);
( * s3truct37drivers/clk/ca> = res_bit);
( * @3hw: c38k_irqrestore" class="sref">sf="+code=clk_val" class="sref">clk_val ==  * @3hw_ct38L102" id="L102" class="line" name="L1023 82 *  3    a382"sref">u16;
scleadw(sclkf">BIa>;
clk_val ==  * @3reset383lass="sref">sclklk_val == sc)" id="L167" class="line" name="L1673 84 * @3res_r384rivers/clk/clk-u300.s>;
 =  * @3res_b38L16" id="L16" class="line" name="L16"> 3  1463pan class="comment"> * @3en_re386lass="sref">c#L1365lags;
 *rivers/clk/clk-> *">sc" id="L152" class="line" name="L1523 77
<3pan class="comment"> * @3en_bi387rive" id="L165" class="line" name="L1653 78 * N3Tspan38t of  id="L132" class="line" name="L1323 89 *  3    t38drives support resetting */ */<3/span390hen df="drivers/clk/clk-u30*/s="srefablemabl - href MCLKkhatclk_hw * *lass= id="L92" class="line" name="L92"> 3 95  3      void clk_hw *hw == u8 to_syscon( *rivers/clk/clk- *ss="s = hw * = hwclk_hw * *lasslk->sysconm> *nablepare(struct  *nablepareclk_hw *hw)
clk_syscon * *rivers/clk/clk-> *"m> *lass=>)
to_syscon( *rivers/clk/clk- *ss="s = bool val;
 4> 1064span class="comment">/*<4span>40"sref">u8  support resetting */ * 4eset 40="sref">valsclk-> *rivers/clk/clk-m> *lassef">clk_val ==  4>28 * 4aken 40="sref">val98val->;
U300_SMMF0NCLK_EN)
 * 4nable41drivers/clk/clk-u300.a>;
sclk->;
U300_SMMCNCLK_EN)
 */4/span41s="sref">sclkkkkkkkkkf="drivers/clk/clk-u300. Dt_disa/ef="MMCpfeedba;
BI=b/a>(U300_SMMCN/MMCRFBR_UARSEL_ENABLECLK_EN)
;
BI=b/a>(U300_SMMCN/MSPRO_FREQSEL_ENABLECLK_EN)
 == val;
U300_SMMCNCLK_EN)
 4> 1174       /417rivers/clk/clk-u300.s>;
to_syscon("+code=sclk" class="sref">sclk->;
U300_SMMCNCLK_EN)
val98;
BI=b/a>(U300_SMMCN/MMCRFBR_UARSEL_ENABLECLK_EN)
 * h4n_loc42drivers/clk/clk-u300.a support resetting */ * b4" cla42s="sref">sclkkkkkkkkkf>;
U300_SMMCN/MSPRO_FREQSEL_ENABLECLK_EN)
 * i4 sysc422rivers/clk/clk-u300.lk_val == val;
U300_SMMCNCLK_EN)
 * t4tew" 42Not all block" id="L165" class="line" name="L1654  1144pan class="comment"> * n4n_unl42L75" id="L75" class="line" name="L75"> 4  1154pan class="comment"> *4pan class="comment"> * P4-u30042irqsa" id="L165" class="line" name="L1654  1174pan class="comment"> * t4u300.42L128" id="L128" class="line" name="L1284 28 * n4=sysc42="srenable" lass="sref">i id="L128" class="line" name="L1284 98 *sysconm> *nablerecalc_"dridrivers/clk/clkm> *nablerecalc_"driss="sref">clk_hw *hw)
iflags;
 4>22u16;
val;
sclef">to_syscon(_clk_enget_peref="+code=_hw" c_clk_enget_peress="s"" id="L132" class="line" name="L1324> 1134       /43scon_ id="L132" class="line" name="L1324> 1144       if (!boolswitchcl->scl)" id="L92" class="line" name="L92"> 4> 1354               return;
<4 href4"drivers/clk/ccesetCLK_EN" class="sref">U300_SCCNu300ING_PERFORMANCE_LOW_POWONCLK_EN)
 4> 1364       sclkkkkkkkkkc#L161 1"L99999+code=sclk" class="L31">  3122u16U300_SCCNu300ING_PERFORMANCE_LOWCLK_EN)
 4> 1134U300_SCCNu300ING_PERFORMANCE_INTERMEDIATECLK_EN)
 4> 1144tatic int U300_SCCNu300ING_PERFORMANCE_HIGHCLK_EN)
 4> 1354
U300_SCCNu300ING_PERFORMANCE_BES=sclk" class="srsref">U300_SCCNu300ING_PERFORMANCE_BES="sre:id="L92" class="line" name="L92"> 4> 1364       struct  4> 1174/44="sreef="drivers/clk/clk-u300000000000000000/sThis catclsL107" id="L107" class="line" name="L1074> 1484       /45="sreef="drivers/clk/clk-u300000000000000000/sf = 208 / ((5+1) + (4+1)) = 208 / 11 = 18.9 MHzlsL107" id="L107" class="line" name="L1074>98val;
to_syscon("+code=sclk" class="sref">sclk->;
U300_SMMF0NCLK_EN)
BI id="L165" class="line" name="L1654> 1614       /46s="sref">sclkkkkkkkkk//////0.a>;
-> 4> 1634                4> 1544
  31 1354 4> 1364tatic int   31 1174
 4> 1484       struct val  3198L86"> 31 4 70 *  4   +-47drivers/clk/clk-u300......///c#L161 26L99999+code=sclk" class="L31">  31 *  4   +-47s="sref">sclkkkkkkkkkceset0x0032:id="L92" class="line" name="L92"> 4  1624pan class="comment"> *  4   +-472rivers/clk/clk-u300.bool.///c#L161 29799999+code=sclk" class="L31">  314pan class="comment"> */<4/span47scon_block_reset_enabceset0x0022:id="L92" class="line" name="L92"> 4  1544a href="drivers/clk/clk-4u300.474rivers/clk/clk-u300.set_enabc#L161 34799999+code=sclk" class="L31">  314pan class="comment">/* G4lobal47drivers/clk/clk-u300.ceset0x0021:id="L92" class="line" name="L92"> 4  1364atic void   314a href="drivers/clk/clk-4u300.477rivers/clk/clk-u300.ceset0x0011:id="L92" class="line" name="L92"> 4  1484pan class="comment">/**<4/span47="sref">val  314pan class="comment"> * s4truct47drivers/clk/clk-u300.ceset0x0099:id="L92" class="line" name="L92"> 4 80 * @4hw: c48drivers/clk/clk-u300......///c#L161 104L99999+code=sclk" class="L31">  31 * @4hw_ct48s="sref">sclkkkkkkkkkdefault:id="L92" class="line" name="L92"> 4 82 *  4    a482rivers/clk/clk-u300.bool.///b hak" id="L132" class="line" name="L1324 73 * @4reset48scon_block_reset_enab" id="L165" class="line" name="L1654 84 * @4res_r484rivers/clk/c" id="L165" class="line" name="L1654  1354pan class="comment"> * @4res_b48drivers/clk/cdefault:id="L92" class="line" name="L92"> 4  1364pan class="comment"> * @4en_re48irqsave" clasll blockb hak" id="L132" class="line" name="L1324  1174pan class="comment"> * @4en_bi487rivers/clk/c" id="L165" class="line" name="L1654  1484aan class="comment"> * N4Tspan48="sref">val;
 *  4    t48drive" id="L165" class="line" name="L1654 90 */<4/span49respo id="L165" class="line" name="L1654 71i id="L128" class="line" name="L1284 82sysconm> *nableround_"dridrivers/clk/clkm> *nableround_"driss="sref">clk_hw *hw)
iflags;
if>)
 4 95  4      void   31
<4      void valscllk_val == <"dridrivers/clk/clk"driss=" <= 208L9999" id="L167" class="line" name="L1674  1484      val  31valscllk_val == <"dridrivers/clk/clk"driss=" <= 231L9999" id="L167" class="line" name="L1675> 1005;
  31 1015valscllk_val == <"dridrivers/clk/clk"driss=" <= 26L99999" id="L167" class="line" name="L1675>21015<     struct   3131025d     sclklk_val == <"dridrivers/clk/clk"driss=" <= 29799999" id="L167" class="line" name="L1675>41025d       3151045t     void 50irqsave" clasll blockc#L161 34799999+code=sclk" class="L31">  3127 * 5eset 50="sref">valscllk_val == <"dridrivers/clk/clk"driss=" <= 41699999" id="L167" class="line" name="L1675>87val  3198 * 5nable51drivers/clk/cc#L161 52L99999+code=sclk" class="L31">  31 1115span class="comment"> */5/span51s="sr" id="L165" class="line" name="L1655> 1125tatic void sysconm> *nableass="dridrivers/clk/clkm> *nableass="driss="sref">clk_hw *hw)
iflags;
iflags;
 5> 1065u8 val;
/517rivers/clk/c val;
 5 20 * h5n_loc52drivers/clk/cceset18999999:id="L92" class="line" name="L92"> 5 21 * b5" cla52s="sref">sclkkkkkkkkkf>;
 * i5 sysc522rivers/clk/clk-u300.b hak" id="L132" class="line" name="L1325  1135pan class="comment"> * t5tew" 52Not all blockceset208L9999:id="L92" class="line" name="L92"> 5  1045pan class="comment"> * n5n_unl524rivers/clk/clk-u300.s>;
 *5pan class="comment"> * P5-u300526ot all blockceset231L9999:id="L92" class="line" name="L92"> 5  1175pan class="comment"> * t5u300.527rivers/clk/clk-u300.s>;
 * n5=sysc52="sref">val * 5> 1305       unsigned long sclkkkkkkkkkb hak" id="L132" class="line" name="L1325>22u16 5> 1135       /53scon_block_reset_enab)
 5> 1065        5>98;
sclkceset52L99999:id="L92" class="line" name="L92"> 5>22 5>51045
  31 1365       struct  5> 1485       /54="sref">val)
u16 to_syscon("+code=sclk" class="sref">sclk->;
U300_SMMF0NCLK_EN)
BI id="L165" class="line" name="L1655>22U300_SMMF0N_MAS href="+code=syshref="driverMMF0N_MAS L132" id="L132" class="line" name="L1325> 1135val;
;
U300_SMMF0NCLK_EN)
clk_hw *sysconm> *nopdrivers/clk/clk-mcbleopdL132s=" id="L92" class="line" name="L92"> 5> 1485       /55_syscon" clas.)
to_syscon(m> *nablepare(struct  *nablepareu16to_syscon(m> *nablerecalc_"dridrivers/clk/clkm> *nablerecalc_"driss=", id="L165" class="line" name="L1655> 1605               return;
<5 href56drivers/clk/c.)
to_syscon(m> *nableround_"dridrivers/clk/clkm> *nableround_"driss=", id="L165" class="line" name="L1655> 1515       /56s="sref">sclk.)
to_syscon(m> *nableass="dridrivers/clk/clkm> *nableass="driss=", id="L165" class="line" name="L1655>22clk_syscon *rivers/clk/clk-> *">sclkf">clk_sysconto_syscon(m> *nableref="dridrivers/clk/clkm> *nableref="driss="sref">clk_hw *)
sclkdrivt"chara>)
)
 5> 1485       struct valclk_syscon *rivers/clk/clk-> *">sclk">clk_syscon *rivers/clk/clk-> *">sc" id="L152" class="line" name="L1525>98L86"> 31clk_syscon * *rivers/clk/clk-> *"m> *lass=>)
 *  5   +-57drivers/clk/cs="sref">clk_syscon * *"indr_dataval;
 *  5   +-57L102" id="L102" class="line" name="L1025  1625pan class="comment"> *  5   +-572"sref">u16;
to_syscon(kzallocrivers/clk/clk-kzallocss="srizeofsref">clk_hw * *lass)lk->)
 */<5/span573lass="sref">sclkk-> *rivers/clk/clk-m> *lass)" id="L92" class="line" name="L92"> 5  1545a href="drivers/clk/clk-5u300.574rivers/clk/clk-u300.)
"could not allocdri0MMC/SDkhat5pan class="comment">/* G5lobal57drivers/clk/clk-u300.k-u300.)
;
)
/**<5/span57="sref">val = ( support res_tring">"m> *"c#L162"" id="L132" class="line" name="L1325 98 * s5truct57drivers/clk/ca> = BIa>;
 * @5hw: c58k_irqrestore" class="sref">sindrivers/clk/clk-uindr of .)
 * @5hw_ct58="sref">u16 ->(BIa>;
)
 *  5    a582"sref">u16;
->( * @5reset58scon_block_res>;
clk_val == BIa>;
 * @5res_r58s="sref">bool clk_val == to_syscon(is_msproivers/clk/clk-uis_mspro of " id="L152" class="line" name="L1525  1355pan class="comment"> * @5res_b58L16" id="L16" class="line" name="L16"> 5  1365pan class="comment"> * @5en_re58"sref">u8 scleadw(sclkf">BIa>;
clk_val ==  * @5en_bi58="sref">valscllk_val == sc)" id="L167" class="line" name="L1675  1485aan class="comment"> * N5Tspan58="sref">val(kfreeble( *  5    t58drive id="L132" class="line" name="L1325 90 */<5/span59drivers/clk/cc#L161 ">clk_syscon *rivers/clk/clk-> *">sc" id="L152" class="line" name="L1525 71clk_syscon *"indrss="svoidf">clk_syscon)
 5 95  5      void val;
clk_syscon *rivers/clk/clk-> *">sclk">clk_syscon *rivers/clk/clk-> *">sc" id="L152" class="line" name="L1525 77
<5      void val = (u16 to_syscon("+code=sclk" class="sref">sclk->;
U300_SCCNCLK_EN)
u16;
BI=b/a>(U300_SCCNu300ING_PERFORMANCE_MAS href="+code=syshref="driverCCNu300ING_PERFORMANCE_MAS L77"" id="L152" class="line" name="L1526>31026d     val;
U300_SCCNCLK_EN)
bool< support resetting */;
sclk->;
U300_SCSNCLK_EN)
BI id="L165" class="line" name="L1656>61046t     60irqsave" clasll block_CLK_EN" class="sref">U300_SCSN_PLL208_LOCK_INDCLK_EN)
sc)"I id="L165" class="line" name="L1656>71046t     void val97to_syscon("+code=sclk" class="sref">sclk->;
U300_SPMCNCLK_EN)
 * 6nable61k_irqrestore" class="sref">sivers/clk/clk-u300.c#L132e|eadw(U300_SPMCN_PWR_MGNT_ENABLECLK_EN)
 */6/span61="sref">u16 val;
U300_SPMCNCLK_EN)
bool scleadw(;
 support res_tring">"app_32_> *"c#L162"lk->)
->u8  support resetting *//617rivers/clk/c ( =  *rivers/clk/clk-> *">sclk->)
 support res_tring">"coh901327_wdog"c#L162""" id="L132" class="line" name="L1326>87val = scleadw(;
 support res_tring">"pll13"c#L162"lk->)
 * h6n_loc62respo id="L165" class="line" name="L1656 21 * b6" cla62s="sref">sclk< support resetting */ * i6 sysc622"sref">u16;
scleadw(;
 support res_tring">"pll208"c#L162"lk->)
 * t6tew" 62scon_block_reset_enabbbbb..................-> * n6n_unl62s="sref">bool scleadw(;
 support res_tring">"app_208_> *"c#L162"lk< support res_tring">"pll208"c#L162"l id="L132" class="line" name="L1326 51026pan class="comment"> *6pan class="comment"> * P6-u30062"sref">u8 scleadw(;
 support res_tring">"app_104_> *"c#L162"lk< support res_tring">"pll208"c#L162"l id="L132" class="line" name="L1326  1176pan class="comment"> * t6u300.627rivers/clk/clk-u300.........................0,"1,"2"" id="L132" class="line" name="L1326 87 * n6=sysc62="sref">val = scleadw(;
 support res_tring">"app_52_> *"c#L162"lk< support res_tring">"pll208"c#L162"l id="L132" class="line" name="L1326 97 * 1306       unsigned long u16 scleadw(;
 support res_tring">"app_26_> *"c#L162"lk< support res_tring">"app_52_> *"c#L162"l id="L162" class="line" name="L1626> 1126/63scon_ id="L132" class="line" name="L1326> 1046       if (!bool< support resetting */ *rivers/clk/clk-> *">scleadw(;
 support res_tring">"cpu_> *"c#L162"lk< support res_tring">"app_208_> *"c#L162"lk0lk->->;
U300_SRRRdrivers/clk/clksref">U300_SRRRss=","3, id="L162" class="line" name="L1626> 1176       ->;
U300_SCERRdrivers/clk/clksref">U300_SCERRss=","3, id="L162" class="line" name="L1626>87val->U300_SSBCER_CPUu300_ENdrivers/clk/clksref">U300_SSBCER_CPUu300_ENL99""" id="L132" class="line" name="L1326>98 = scleadw(;
 support res_tring">"dmac_> *"c#L162"lk< support res_tring">"app_52_> *"c#L162"lk0lk->->;
U300_SRRRdrivers/clk/clksref">U300_SRRRss=","4, id="L162" class="line" name="L1626>21sclkkkkkkkkk//////0.kkkkkkkkkk->;
U300_SCERRdrivers/clk/clksref">U300_SCERRss=","4, id="L162" class="line" name="L1626> 1126
U300_SSBCER_DMACu300_ENdrivers/clk/clksref">U300_SSBCER_DMACu300_ENL99""" id="L132" class="line" name="L1326> 1136sclk->)
 support res_tring">"dma"c#L162""" id="L132" class="line" name="L1326> 1046tatic int bool scleadw(;
 support res_tring">"fsmc_> *"c#L162"lk< support res_tring">"app_52_> *"c#L162"lk0lk->->;
U300_SRRRdrivers/clk/clksref">U300_SRRRss=","6, id="L162" class="line" name="L1626> 1066       struct ->;
U300_SCERRdrivers/clk/clksref">U300_SCERRss=","6, id="L162" class="line" name="L1626> 1176U300_SSBCER_NANDIFu300_ENdrivers/clk/clksref">U300_SSBCER_NANDIFu300_ENL99""" id="L132" class="line" name="L1326>87/64="sref">val = ( =  *rivers/clk/clk-> *">sclk->)
 support res_tring">"fsmc-nand"c#L162""" id="L132" class="line" name="L1326>98 *rivers/clk/clk-> *">scleadw(;
 support res_tring">"xgam_> *"c#L162"lk< support res_tring">"app_52_> *"c#L162"lk0lk->->;
U300_SRRRdrivers/clk/clksref">U300_SRRRss=","8, id="L162" class="line" name="L1626>21sclkkkkkkkkk//////0.kkkkkkkkkk->;
U300_SCERRdrivers/clk/clksref">U300_SCERRss=","8, id="L162" class="line" name="L1626> 1126
U300_SSBCER_XGAMu300_ENdrivers/clk/clksref">U300_SSBCER_XGAMu300_ENL99""" id="L132" class="line" name="L1326> 1136 *rref="dri_a heevble( =  *rivers/clk/clk-> *">sclk->)
 support res_tring">"xgam"c#L162""" id="L132" class="line" name="L1326> 1146tatic void bool scleadw(;
 support res_tring">"semi_> *"c#L162"lk< support res_tring">"app_104_> *"c#L162"lk0lk->->;
U300_SRRRdrivers/clk/clksref">U300_SRRRss=","9, id="L162" class="line" name="L1626> 1066       struct ->;
U300_SCERRdrivers/clk/clksref">U300_SCERRss=","9, id="L162" class="line" name="L1626> 1176U300_SSBCER_SEMIu300_ENdrivers/clk/clksref">U300_SSBCER_SEMIu300_ENL99""" id="L132" class="line" name="L1326>87/65="sref">val = ( =  *rivers/clk/clk-> *">sclk->)
 support res_tring">"semi"c#L162""" id="L132" class="line" name="L1326>98/66="sref">u16 scleadw(;
 support res_tring">"ahb_sub/cl_> *"c#L162"lk< support res_tring">"app_52_> *"c#L162"lk0lk->->;
U300_SRRRdrivers/clk/clksref">U300_SRRRss=","10, id="L162" class="line" name="L1626> 1136               U300_SCERRdrivers/clk/clksref">U300_SCERRss=","10, id="L162" class="line" name="L1626> 1146
U300_SSBCER_AHB_SUB>U3_BRIDGEu300_ENdrivers/clk/clksref">U300_SSBCER_AHB_SUB>U3_BRIDGEu300_ENL99""" id="L132" class="line" name="L1326> 1356 *rivers/clk/clk-> *">scleadw(;
 support res_tring">"intk-u3c h"c#L162"lk< support res_tring">"ahb_sub/cl_> *"c#L162"lk0lk->->;
U300_SRRRdrivers/clk/clksref">U300_SRRRss=","12, id="L162" class="line" name="L1626> 1176
U300_SCERRdrivers/clk/clksref">U300_SCERRss=","12, id="L162" class="line" name="L1626>87val98L86"> 31 *  6   +-67k_irqrestore" class="sref">s> *rref="dri_a heevble( =  *rivers/clk/clk-> *">sclk->)
 support res_tring">"intk-u"c#L162""" id="L132" class="line" name="L1326 71 *  6   +-67="sref">u16 scleadw(;
 support res_tring">"emif3c h"c#L162"lk< support res_tring">"ahb_sub/cl_> *"c#L162"lk0lk-> *  6   +-672rivers/clk/clk-u300.kkkkkkkkkkkkkkkkkk->;
U300_SRRRdrivers/clk/clksref">U300_SRRRss=","5, id="L162" class="line" name="L1626  1136pan class="comment"> */<6/span67scon_block_reset_enabbbbb..............->;
U300_SCERRdrivers/clk/clksref">U300_SCERRss=","5, id="L162" class="line" name="L1626  1146a href="drivers/clk/clk-6u300.674rivers/clk/clk-u300.bbbb..............->U300_SSBCER_EMIFu300_ENdrivers/clk/clksref">U300_SSBCER_EMIFu300_ENL99""" id="L132" class="line" name="L1326  1356pan class="comment">/* G6lobal67drivers/clk/c ( =  *rivers/clk/clk-> *">sclk->)
 support res_tring">"pl172"c#L162""" id="L132" class="line" name="L1326  1366atic void /**<6/span67="sref">val = scleadw(;
 support res_tring">"fast_> *"c#L162"lk< support res_tring">"app_26_> *"c#L162"lk0lk-> * s6truct67drivers/clk/clk-u300...................->;
U300_SRFRdrivers/clk/clksref">U300_SRFRss=","0, id="L162" class="line" name="L1626 80 * @6hw: c68drivers/clk/clk-u300.kkkkkkkkkkkkkkkkkk->;
U300_SCEFRdrivers/clk/clksref">U300_SCEFRss=","0, id="L162" class="line" name="L1626 71 * @6hw_ct68s="sref">sclkkkkkkkkk//////0.kkkkkkkkkk->U300_SSBCER_FAST_BRIDGEu300_ENdrivers/clk/clksref">U300_SSBCER_FAST_BRIDGEu300_ENL99""" id="L132" class="line" name="L1326 82 *  6    a682"sref">u16;
scleadw(;
 support res_tring">"i2c0_p_> *"c#L162"lk< support res_tring">"fast_> *"c#L162"lk0lk-> * @6reset68scon_block_reset_enabbbbb..............->;
U300_SRFRdrivers/clk/clksref">U300_SRFRss=","1, id="L162" class="line" name="L1626  1146pan class="comment"> * @6res_r684rivers/clk/clk-u300.bbbb..............->;
U300_SCEFRdrivers/clk/clksref">U300_SCEFRss=","1, id="L162" class="line" name="L1626  1356pan class="comment"> * @6res_b68drivers/clk/clk-u300.kkkkkkkkkkkkkkkkkk->U300_SSBCER_I2C0u300_ENdrivers/clk/clksref">U300_SSBCER_I2C0u300_ENL99""" id="L132" class="line" name="L1326  1366pan class="comment"> * @6en_re68"sref">u8 ( =  *rivers/clk/clk-> *">sclk->)
 support res_tring">"stme="L0"c#L162""" id="L132" class="line" name="L1326  1176pan class="comment"> * @6en_bi687rivers/clk/c scleadw(;
 support res_tring">"i2c1_p_> *"c#L162"lk< support res_tring">"fast_> *"c#L162"lk0lk-> * N6Tspan68="sref">val->;
U300_SRFRdrivers/clk/clksref">U300_SRFRss=","2, id="L162" class="line" name="L1626 98 *  6    t68drivers/clk/clk-u300...................->;
U300_SCEFRdrivers/clk/clksref">U300_SCEFRss=","2, id="L162" class="line" name="L1626 90 */<6/span69drivers/clk/clk-u300.kkkkkkkkkkkkkkkkkk->U300_SSBCER_I2C1u300_ENdrivers/clk/clksref">U300_SSBCER_I2C1u300_ENL99""" id="L132" class="line" name="L1326 71u16 ( =  *rivers/clk/clk-> *">sclk->)
 support res_tring">"stme="L1"c#L162""" id="L132" class="line" name="L1326 82u16;
scleadw(;
 support res_tring">"mmc_p_> *"c#L162"lk< support res_tring">"fast_> *"c#L162"lk0lk->->;
U300_SRFRdrivers/clk/clksref">U300_SRFRss=","5, id="L162" class="line" name="L1626 94  6      ->;
U300_SCEFRdrivers/clk/clksref">U300_SCEFRss=","5, id="L162" class="line" name="L1626  1356      void U300_SSBCER_MMCu300_ENdrivers/clk/clksref">U300_SSBCER_MMCu300_ENL99""" id="L132" class="line" name="L1326  1366      u8 ( =  *rivers/clk/clk-> *">sclk< support res_tring">"apb_p> *"c#L162"lk< support res_tring">"mmci"c#L162""" id="L132" class="line" name="L1326 77
<6      void  *">scleadw(;
 support res_tring">"spi_p_> *"c#L162"lk< support res_tring">"fast_> *"c#L162"lk0lk->val->;
U300_SRFRdrivers/clk/clksref">U300_SRFRss=","6, id="L162" class="line" name="L1626 98->;
U300_SCEFRdrivers/clk/clksref">U300_SCEFRss=","6, id="L162" class="line" name="L1627> 1007;
U300_SSBCER_SPIu300_ENdrivers/clk/clksref">U300_SSBCER_SPIu300_ENL99""" id="L132" class="line" name="L1327> 1017sclk< support resetting */ *c0.c#L162" id="L162" class="line" name="L1627>21017<     struct u16;
( =  *rivers/clk/clk-> *">sclk->)
 support res_tring">"pl022"c#L162""" id="L132" class="line" name="L1327>31027d      *rref="dri_a heevble( =  *rivers/clk/clk-> *">sclk< support res_tring">"apb_p> *"c#L162"lk< support res_tring">"pl022"c#L162""" id="L132" class="line" name="L1327>41027d     70"sref">u8 scleadw(;
 support res_tring">"slow_> *"c#L162"lk< support res_tring">"pll13"c#L162"lk0lk->->;
U300_SRSNCLK_EN)
val->;
U300_SCESNCLK_EN)
->U300_SSBCER_SLOW_BRIDGEu300_ENdrivers/clk/clksref">U300_SSBCER_SLOW_BRIDGEu300_ENL99""" id="L132" class="line" name="L1327> 1107span class="comment"> * 7nable71k_irqrestore" class="sref">s> *rivers/clk/clk-> *">scleadw(;
 support res_tring">"uart0_> *"c#L162"lk< support res_tring">"slow_> *"c#L162"lk0lk-> */7/span71s="sref">sclkkkkkkkkk//////0.kkkkkkkkkk->;
U300_SRSNCLK_EN)
->;
U300_SCESNCLK_EN)
->U300_SSBCER_UARTu300_ENdrivers/clk/clksref">U300_SSBCER_UARTu300_ENL99""" id="L132" class="line" name="L1327>41027       unsigned long bool< support resetting */( =  *rivers/clk/clk-> *">sclk->)
 support res_tring">"uart0"c#L162""" id="L132" class="line" name="L1327>61047u8 ( =  *rivers/clk/clk-> *">sclk< support res_tring">"apb_p> *"c#L162"lk< support res_tring">"uart0"c#L162""" id="L132" class="line" name="L1327>71047       /717rivers/clk/c scleadw(;
 support res_tring">"gpio_> *"c#L162"lk< support res_tring">"slow_> *"c#L162"lk0lk->val->;
U300_SRSNCLK_EN)
U300_SCESNCLK_EN)
 * h7n_loc72drivers/clk/clk-u300.kkkkkkkkkkkkkkkkkk->U300_SSBCER_GPIOu300_ENdrivers/clk/clksref">U300_SSBCER_GPIOu300_ENL99""" id="L132" class="line" name="L1327 21 * b7" cla72="sref">u16 ( =  *rivers/clk/clk-> *">sclk->)
 support res_tring">"me="-gpio"c#L162""" id="L132" class="line" name="L1327  1127aan class="comment"> * i7 sysc722"sref">u16;
scleadw(;
 support res_tring">"keypad_> *"c#L162"lk< support res_tring">"slow_> *"c#L162"lk0lk-> * t7tew" 72scon_block_reset_enabbbbb..............->;
U300_SRSNCLK_EN)
 * n7n_unl724rivers/clk/clk-u300.bbbb..............->;
U300_SCESNCLK_EN)
 *->U300_SSBCER_KEYPADu300_ENdrivers/clk/clksref">U300_SSBCER_KEYPADu300_ENL99""" id="L132" class="line" name="L1327 61047pan class="comment"> * P7-u30072"sref">u8 ( =  *rivers/clk/clk-> *">sclk->)
 support res_tring">"coh901461-keypad"c#L162""" id="L132" class="line" name="L1327 71047pan class="comment"> * t7u300.727rivers/clk/c scleadw(;
 support res_tring">"rtc_> *"c#L162"lk< support res_tring">"slow_> *"c#L162"lk0lk-> * n7=sysc72="sref">val->;
U300_SRSNCLK_EN)
 * 1307       unsigned long u16 ( =  *rivers/clk/clk-> *">sclk->)
 support res_tring">"rtc-coh901331"c#L162""" id="L132" class="line" name="L1327> 1127u16;
scleadw(;
 support res_tring">"app_tmr_> *"c#L162"lk< support res_tring">"slow_> *"c#L162"lk0lk->/73scon_block_reset_enabbbbb..............->;
U300_SRSNCLK_EN)
->;
U300_SCESNCLK_EN)
U300_SSBCER_APP_TMRu300_ENdrivers/clk/clksref">U300_SSBCER_APP_TMRu300_ENL99""" id="L132" class="line" name="L1327> 1067       u8 ( =  *rivers/clk/clk-> *">sclk->)
 support res_tring">"apptimer"c#L162""" id="L132" class="line" name="L1327>71047       scleadw(;
 support res_tring">"acc_tmr_> *"c#L162"lk< support res_tring">"slow_> *"c#L162"lk0lk->val->;
U300_SRSNCLK_EN)
->;
U300_SCESNCLK_EN)
->U300_SSBCER_ACC_TMRu300_ENdrivers/clk/clksref">U300_SSBCER_ACC_TMRu300_ENL99""" id="L132" class="line" name="L1327>21u16 ( =  *rivers/clk/clk-> *">sclk->)
 support res_tring">"timer"c#L162""" id="L132" class="line" name="L1327> 1127
bool scleadw(;
 support res_tring">"mmc_> *"c#L162"lk< support res_tring">"mmc_p_> *"c#L162"lk->( =  *rivers/clk/clk-> *">sclk->)
 support res_tring">"mmci"c#L162""" id="L132" class="line" name="L1327> 1067       struct 


Tf= original LXR software by ef="id="L132"http://sourceforge.net/projects/lxid>LXR ettiunityss=","efis experiing al ass=ion by id="L132"mailto:lxi@iveux.no">lxi@iveux.noss=".
lxi.iveux.no kindly ho"drd by id="L132"http://www.redpill-ivepro.no">Redpill Lvepro ASss=","providsr of Lveux etnsulting on aoperations services since 1995.