LXR linux/drivers/bcma/driver_chipcommon

   1/*
   2 * Broadcom specific AMBA
   3 * ChipCommon Power Management Unit driver
   4 *
   5 * Copyright 2009, Michael Buesch <m@bues.ch>
   6 * Copyright 2007, 2011, Broadcom Corporation
   7 * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
   8 *
   9 * Licensed under the GNU/GPL. See COPYING for details.
  10 */
  11
  12#include "bcma_private.h"
  13#include <linux/export.h>
  14#include <linux/bcma/bcma.h>
  15
  16u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
  17{
  18        bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
  19        bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
  20        return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
  21}
  22EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
  23
  24void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
  25{
  26        bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
  27        bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
  28        bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
  29}
  30EXPORT_SYMBOL_GPL(bcma_chipco_pll_write);
  31
  32void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
  33                             u32 set)
  34{
  35        bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
  36        bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
  37        bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set);
  38}
  39EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset);
  40
  41void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
  42                                 u32 offset, u32 mask, u32 set)
  43{
  44        bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);
  45        bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
  46        bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set);
  47}
  48EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset);
  49
  50void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
  51                                u32 set)
  52{
  53        bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset);
  54        bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR);
  55        bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set);
  56}
  57EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
  58
  59static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
  60{
  61        struct bcma_bus *bus = cc->core->bus;
  62        u32 min_msk = 0, max_msk = 0;
  63
  64        switch (bus->chipinfo.id) {
  65        case BCMA_CHIP_ID_BCM4313:
  66                min_msk = 0x200D;
  67                max_msk = 0xFFFF;
  68                break;
  69        default:
  70                bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
  71                           bus->chipinfo.id);
  72        }
  73
  74        /* Set the resource masks. */
  75        if (min_msk)
  76                bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
  77        if (max_msk)
  78                bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
  79
  80        /*
  81         * Add some delay; allow resources to come up and settle.
  82         * Delay is required for SoC (early init).
  83         */
  84        mdelay(2);
  85}
  86
  87/* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
  88void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable)
  89{
  90        struct bcma_bus *bus = cc->core->bus;
  91        u32 val;
  92
  93        val = bcma_cc_read32(cc, BCMA_CC_CHIPCTL);
  94        if (enable) {
  95                val |= BCMA_CHIPCTL_4331_EXTPA_EN;
  96                if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11)
  97                        val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
  98                else if (bus->chipinfo.rev > 0)
  99                        val |= BCMA_CHIPCTL_4331_EXTPA_EN2;
 100        } else {
 101                val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
 102                val &= ~BCMA_CHIPCTL_4331_EXTPA_EN2;
 103                val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
 104        }
 105        bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
 106}
 107
 108static void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
 109{
 110        struct bcma_bus *bus = cc->core->bus;
 111
 112        switch (bus->chipinfo.id) {
 113        case BCMA_CHIP_ID_BCM4313:
 114                /* enable 12 mA drive strenth for 4313 and set chipControl
 115                   register bit 1 */
 116                bcma_chipco_chipctl_maskset(cc, 0,
 117                                            ~BCMA_CCTRL_4313_12MA_LED_DRIVE,
 118                                            BCMA_CCTRL_4313_12MA_LED_DRIVE);
 119                break;
 120        case BCMA_CHIP_ID_BCM4331:
 121        case BCMA_CHIP_ID_BCM43431:
 122                /* Ext PA lines must be enabled for tx on BCM4331 */
 123                bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true);
 124                break;
 125        case BCMA_CHIP_ID_BCM43224:
 126        case BCMA_CHIP_ID_BCM43421:
 127                /* enable 12 mA drive strenth for 43224 and set chipControl
 128                   register bit 15 */
 129                if (bus->chipinfo.rev == 0) {
 130                        bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL,
 131                                          ~BCMA_CCTRL_43224_GPIO_TOGGLE,
 132                                          BCMA_CCTRL_43224_GPIO_TOGGLE);
 133                        bcma_chipco_chipctl_maskset(cc, 0,
 134                                                    ~BCMA_CCTRL_43224A0_12MA_LED_DRIVE,
 135                                                    BCMA_CCTRL_43224A0_12MA_LED_DRIVE);
 136                } else {
 137                        bcma_chipco_chipctl_maskset(cc, 0,
 138                                                    ~BCMA_CCTRL_43224B0_12MA_LED_DRIVE,
 139                                                    BCMA_CCTRL_43224B0_12MA_LED_DRIVE);
 140                }
 141                break;
 142        default:
 143                bcma_debug(bus, "Workarounds unknown or not needed for device 0x%04X\n",
 144                           bus->chipinfo.id);
 145        }
 146}
 147
 148void bcma_pmu_early_init(struct bcma_drv_cc *cc)
 149{
 150        u32 pmucap;
 151
 152        pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
 153        cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
 154
 155        bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
 156                   cc->pmu.rev, pmucap);
 157}
 158
 159void bcma_pmu_init(struct bcma_drv_cc *cc)
 160{
 161        if (cc->pmu.rev == 1)
 162                bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
 163                              ~BCMA_CC_PMU_CTL_NOILPONW);
 164        else
 165                bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
 166                             BCMA_CC_PMU_CTL_NOILPONW);
 167
 168        bcma_pmu_resources_init(cc);
 169        bcma_pmu_workarounds(cc);
 170}
 171
 172u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
 173{
 174        struct bcma_bus *bus = cc->core->bus;
 175
 176        switch (bus->chipinfo.id) {
 177        case BCMA_CHIP_ID_BCM4716:
 178        case BCMA_CHIP_ID_BCM4748:
 179        case BCMA_CHIP_ID_BCM47162:
 180        case BCMA_CHIP_ID_BCM4313:
 181        case BCMA_CHIP_ID_BCM5357:
 182        case BCMA_CHIP_ID_BCM4749:
 183        case BCMA_CHIP_ID_BCM53572:
 184                /* always 20Mhz */
 185                return 20000 * 1000;
 186        case BCMA_CHIP_ID_BCM5356:
 187        case BCMA_CHIP_ID_BCM4706:
 188                /* always 25Mhz */
 189                return 25000 * 1000;
 190        default:
 191                bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
 192                          bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
 193        }
 194        return BCMA_CC_PMU_ALP_CLOCK;
 195}
 196
 197/* Find the output of the "m" pll divider given pll controls that start with
 198 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
 199 */
 200static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
 201{
 202        u32 tmp, div, ndiv, p1, p2, fc;
 203        struct bcma_bus *bus = cc->core->bus;
 204
 205        BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0));
 206
 207        BUG_ON(!m || m > 4);
 208
 209        if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
 210            bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) {
 211                /* Detect failure in clock setting */
 212                tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
 213                if (tmp & 0x40000)
 214                        return 133 * 1000000;
 215        }
 216
 217        tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF);
 218        p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT;
 219        p2 = (tmp & BCMA_CC_PPL_P2_MASK) >> BCMA_CC_PPL_P2_SHIFT;
 220
 221        tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF);
 222        div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) &
 223                BCMA_CC_PPL_MDIV_MASK;
 224
 225        tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF);
 226        ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
 227
 228        /* Do calculation in Mhz */
 229        fc = bcma_pmu_get_alp_clock(cc) / 1000000;
 230        fc = (p1 * ndiv * fc) / p2;
 231
 232        /* Return clock in Hertz */
 233        return (fc / div) * 1000000;
 234}
 235
 236static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
 237{
 238        u32 tmp, ndiv, p1div, p2div;
 239        u32 clock;
 240
 241        BUG_ON(!m || m > 4);
 242
 243        /* Get N, P1 and P2 dividers to determine CPU clock */
 244        tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PMU6_4706_PROCPLL_OFF);
 245        ndiv = (tmp & BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK)
 246                >> BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT;
 247        p1div = (tmp & BCMA_CC_PMU6_4706_PROC_P1DIV_MASK)
 248                >> BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT;
 249        p2div = (tmp & BCMA_CC_PMU6_4706_PROC_P2DIV_MASK)
 250                >> BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT;
 251
 252        tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
 253        if (tmp & BCMA_CC_CHIPST_4706_PKG_OPTION)
 254                /* Low cost bonding: Fixed reference clock 25MHz and m = 4 */
 255                clock = (25000000 / 4) * ndiv * p2div / p1div;
 256        else
 257                /* Fixed reference clock 25MHz and m = 2 */
 258                clock = (25000000 / 2) * ndiv * p2div / p1div;
 259
 260        if (m == BCMA_CC_PMU5_MAINPLL_SSB)
 261                clock = clock / 4;
 262
 263        return clock;
 264}
 265
 266/* query bus clock frequency for PMU-enabled chipcommon */
 267static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
 268{
 269        struct bcma_bus *bus = cc->core->bus;
 270
 271        switch (bus->chipinfo.id) {
 272        case BCMA_CHIP_ID_BCM4716:
 273        case BCMA_CHIP_ID_BCM4748:
 274        case BCMA_CHIP_ID_BCM47162:
 275                return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
 276                                          BCMA_CC_PMU5_MAINPLL_SSB);
 277        case BCMA_CHIP_ID_BCM5356:
 278                return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
 279                                          BCMA_CC_PMU5_MAINPLL_SSB);
 280        case BCMA_CHIP_ID_BCM5357:
 281        case BCMA_CHIP_ID_BCM4749:
 282                return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
 283                                          BCMA_CC_PMU5_MAINPLL_SSB);
 284        case BCMA_CHIP_ID_BCM4706:
 285                return bcma_pmu_pll_clock_bcm4706(cc,
 286                                                  BCMA_CC_PMU4706_MAINPLL_PLL0,
 287                                                  BCMA_CC_PMU5_MAINPLL_SSB);
 288        case BCMA_CHIP_ID_BCM53572:
 289                return 75000000;
 290        default:
 291                bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
 292                          bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
 293        }
 294        return BCMA_CC_PMU_HT_CLOCK;
 295}
 296
 297/* query cpu clock frequency for PMU-enabled chipcommon */
 298u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
 299{
 300        struct bcma_bus *bus = cc->core->bus;
 301
 302        if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
 303                return 300000000;
 304
 305        /* New PMUs can have different clock for bus and CPU */
 306        if (cc->pmu.rev >= 5) {
 307                u32 pll;
 308                switch (bus->chipinfo.id) {
 309                case BCMA_CHIP_ID_BCM4706:
 310                        return bcma_pmu_pll_clock_bcm4706(cc,
 311                                                BCMA_CC_PMU4706_MAINPLL_PLL0,
 312                                                BCMA_CC_PMU5_MAINPLL_CPU);
 313                case BCMA_CHIP_ID_BCM5356:
 314                        pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
 315                        break;
 316                case BCMA_CHIP_ID_BCM5357:
 317                case BCMA_CHIP_ID_BCM4749:
 318                        pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
 319                        break;
 320                default:
 321                        pll = BCMA_CC_PMU4716_MAINPLL_PLL0;
 322                        break;
 323                }
 324
 325                return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
 326        }
 327
 328        /* On old PMUs CPU has the same clock as the bus */
 329        return bcma_pmu_get_bus_clock(cc);
 330}
 331
 332static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
 333                                         u32 value)
 334{
 335        bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
 336        bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
 337}
 338
 339void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
 340{
 341        u32 tmp = 0;
 342        u8 phypll_offset = 0;
 343        u8 bcm5357_bcm43236_p1div[] = {0x1, 0x5, 0x5};
 344        u8 bcm5357_bcm43236_ndiv[] = {0x30, 0xf6, 0xfc};
 345        struct bcma_bus *bus = cc->core->bus;
 346
 347        switch (bus->chipinfo.id) {
 348        case BCMA_CHIP_ID_BCM5357:
 349        case BCMA_CHIP_ID_BCM4749:
 350        case BCMA_CHIP_ID_BCM53572:
 351                /* 5357[ab]0, 43236[ab]0, and 6362b0 */
 352
 353                /* BCM5357 needs to touch PLL1_PLLCTL[02],
 354                   so offset PLL0_PLLCTL[02] by 6 */
 355                phypll_offset = (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
 356                       bus->chipinfo.id == BCMA_CHIP_ID_BCM4749 ||
 357                       bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;
 358
 359                /* RMW only the P1 divider */
 360                bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
 361                                BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
 362                tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
 363                tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
 364                tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
 365                bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
 366
 367                /* RMW only the int feedback divider */
 368                bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
 369                                BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
 370                tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
 371                tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
 372                tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
 373                bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
 374
 375                tmp = 1 << 10;
 376                break;
 377
 378        case BCMA_CHIP_ID_BCM4331:
 379        case BCMA_CHIP_ID_BCM43431:
 380                if (spuravoid == 2) {
 381                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
 382                                                     0x11500014);
 383                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
 384                                                     0x0FC00a08);
 385                } else if (spuravoid == 1) {
 386                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
 387                                                     0x11500014);
 388                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
 389                                                     0x0F600a08);
 390                } else {
 391                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
 392                                                     0x11100014);
 393                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
 394                                                     0x03000a08);
 395                }
 396                tmp = 1 << 10;
 397                break;
 398
 399        case BCMA_CHIP_ID_BCM43224:
 400        case BCMA_CHIP_ID_BCM43225:
 401        case BCMA_CHIP_ID_BCM43421:
 402                if (spuravoid == 1) {
 403                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
 404                                                     0x11500010);
 405                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
 406                                                     0x000C0C06);
 407                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
 408                                                     0x0F600a08);
 409                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
 410                                                     0x00000000);
 411                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
 412                                                     0x2001E920);
 413                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
 414                                                     0x88888815);
 415                } else {
 416                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
 417                                                     0x11100010);
 418                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
 419                                                     0x000c0c06);
 420                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
 421                                                     0x03000a08);
 422                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
 423                                                     0x00000000);
 424                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
 425                                                     0x200005c0);
 426                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
 427                                                     0x88888815);
 428                }
 429                tmp = 1 << 10;
 430                break;
 431
 432        case BCMA_CHIP_ID_BCM4716:
 433        case BCMA_CHIP_ID_BCM4748:
 434        case BCMA_CHIP_ID_BCM47162:
 435                if (spuravoid == 1) {
 436                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
 437                                                     0x11500060);
 438                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
 439                                                     0x080C0C06);
 440                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
 441                                                     0x0F600000);
 442                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
 443                                                     0x00000000);
 444                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
 445                                                     0x2001E924);
 446                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
 447                                                     0x88888815);
 448                } else {
 449                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
 450                                                     0x11100060);
 451                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
 452                                                     0x080c0c06);
 453                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
 454                                                     0x03000000);
 455                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
 456                                                     0x00000000);
 457                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
 458                                                     0x200005c0);
 459                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
 460                                                     0x88888815);
 461                }
 462
 463                tmp = 3 << 9;
 464                break;
 465
 466        case BCMA_CHIP_ID_BCM43227:
 467        case BCMA_CHIP_ID_BCM43228:
 468        case BCMA_CHIP_ID_BCM43428:
 469                /* LCNXN */
 470                /* PLL Settings for spur avoidance on/off mode,
 471                   no on2 support for 43228A0 */
 472                if (spuravoid == 1) {
 473                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
 474                                                     0x01100014);
 475                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
 476                                                     0x040C0C06);
 477                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
 478                                                     0x03140A08);
 479                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
 480                                                     0x00333333);
 481                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
 482                                                     0x202C2820);
 483                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
 484                                                     0x88888815);
 485                } else {
 486                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
 487                                                     0x11100014);
 488                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
 489                                                     0x040c0c06);
 490                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
 491                                                     0x03000a08);
 492                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
 493                                                     0x00000000);
 494                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
 495                                                     0x200005c0);
 496                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
 497                                                     0x88888815);
 498                }
 499                tmp = 1 << 10;
 500                break;
 501        default:
 502                bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
 503                         bus->chipinfo.id);
 504                break;
 505        }
 506
 507        tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL);
 508        bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp);
 509}
 510EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);
 511