linux/drivers/ata/pata_icside.c
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   1#include <linux/kernel.h>
   2#include <linux/module.h>
   3#include <linux/init.h>
   4#include <linux/blkdev.h>
   5#include <linux/gfp.h>
   6#include <scsi/scsi_host.h>
   7#include <linux/ata.h>
   8#include <linux/libata.h>
   9
  10#include <asm/dma.h>
  11#include <asm/ecard.h>
  12
  13#define DRV_NAME        "pata_icside"
  14
  15#define ICS_IDENT_OFFSET                0x2280
  16
  17#define ICS_ARCIN_V5_INTRSTAT           0x0000
  18#define ICS_ARCIN_V5_INTROFFSET         0x0004
  19
  20#define ICS_ARCIN_V6_INTROFFSET_1       0x2200
  21#define ICS_ARCIN_V6_INTRSTAT_1         0x2290
  22#define ICS_ARCIN_V6_INTROFFSET_2       0x3200
  23#define ICS_ARCIN_V6_INTRSTAT_2         0x3290
  24
  25struct portinfo {
  26        unsigned int dataoffset;
  27        unsigned int ctrloffset;
  28        unsigned int stepping;
  29};
  30
  31static const struct portinfo pata_icside_portinfo_v5 = {
  32        .dataoffset     = 0x2800,
  33        .ctrloffset     = 0x2b80,
  34        .stepping       = 6,
  35};
  36
  37static const struct portinfo pata_icside_portinfo_v6_1 = {
  38        .dataoffset     = 0x2000,
  39        .ctrloffset     = 0x2380,
  40        .stepping       = 6,
  41};
  42
  43static const struct portinfo pata_icside_portinfo_v6_2 = {
  44        .dataoffset     = 0x3000,
  45        .ctrloffset     = 0x3380,
  46        .stepping       = 6,
  47};
  48
  49struct pata_icside_state {
  50        void __iomem *irq_port;
  51        void __iomem *ioc_base;
  52        unsigned int type;
  53        unsigned int dma;
  54        struct {
  55                u8 port_sel;
  56                u8 disabled;
  57                unsigned int speed[ATA_MAX_DEVICES];
  58        } port[2];
  59};
  60
  61struct pata_icside_info {
  62        struct pata_icside_state *state;
  63        struct expansion_card   *ec;
  64        void __iomem            *base;
  65        void __iomem            *irqaddr;
  66        unsigned int            irqmask;
  67        const expansioncard_ops_t *irqops;
  68        unsigned int            mwdma_mask;
  69        unsigned int            nr_ports;
  70        const struct portinfo   *port[2];
  71        unsigned long           raw_base;
  72        unsigned long           raw_ioc_base;
  73};
  74
  75#define ICS_TYPE_A3IN   0
  76#define ICS_TYPE_A3USER 1
  77#define ICS_TYPE_V6     3
  78#define ICS_TYPE_V5     15
  79#define ICS_TYPE_NOTYPE ((unsigned int)-1)
  80
  81/* ---------------- Version 5 PCB Support Functions --------------------- */
  82/* Prototype: pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  83 * Purpose  : enable interrupts from card
  84 */
  85static void pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  86{
  87        struct pata_icside_state *state = ec->irq_data;
  88
  89        writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
  90}
  91
  92/* Prototype: pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
  93 * Purpose  : disable interrupts from card
  94 */
  95static void pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
  96{
  97        struct pata_icside_state *state = ec->irq_data;
  98
  99        readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
 100}
 101
 102static const expansioncard_ops_t pata_icside_ops_arcin_v5 = {
 103        .irqenable      = pata_icside_irqenable_arcin_v5,
 104        .irqdisable     = pata_icside_irqdisable_arcin_v5,
 105};
 106
 107
 108/* ---------------- Version 6 PCB Support Functions --------------------- */
 109/* Prototype: pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 110 * Purpose  : enable interrupts from card
 111 */
 112static void pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 113{
 114        struct pata_icside_state *state = ec->irq_data;
 115        void __iomem *base = state->irq_port;
 116
 117        if (!state->port[0].disabled)
 118                writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
 119        if (!state->port[1].disabled)
 120                writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
 121}
 122
 123/* Prototype: pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 124 * Purpose  : disable interrupts from card
 125 */
 126static void pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 127{
 128        struct pata_icside_state *state = ec->irq_data;
 129
 130        readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 131        readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 132}
 133
 134/* Prototype: pata_icside_irqprobe(struct expansion_card *ec)
 135 * Purpose  : detect an active interrupt from card
 136 */
 137static int pata_icside_irqpending_arcin_v6(struct expansion_card *ec)
 138{
 139        struct pata_icside_state *state = ec->irq_data;
 140
 141        return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
 142               readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
 143}
 144
 145static const expansioncard_ops_t pata_icside_ops_arcin_v6 = {
 146        .irqenable      = pata_icside_irqenable_arcin_v6,
 147        .irqdisable     = pata_icside_irqdisable_arcin_v6,
 148        .irqpending     = pata_icside_irqpending_arcin_v6,
 149};
 150
 151
 152/*
 153 * SG-DMA support.
 154 *
 155 * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
 156 * There is only one DMA controller per card, which means that only
 157 * one drive can be accessed at one time.  NOTE! We do not enforce that
 158 * here, but we rely on the main IDE driver spotting that both
 159 * interfaces use the same IRQ, which should guarantee this.
 160 */
 161
 162/*
 163 * Configure the IOMD to give the appropriate timings for the transfer
 164 * mode being requested.  We take the advice of the ATA standards, and
 165 * calculate the cycle time based on the transfer mode, and the EIDE
 166 * MW DMA specs that the drive provides in the IDENTIFY command.
 167 *
 168 * We have the following IOMD DMA modes to choose from:
 169 *
 170 *      Type    Active          Recovery        Cycle
 171 *      A       250 (250)       312 (550)       562 (800)
 172 *      B       187 (200)       250 (550)       437 (750)
 173 *      C       125 (125)       125 (375)       250 (500)
 174 *      D       62  (50)        125 (375)       187 (425)
 175 *
 176 * (figures in brackets are actual measured timings on DIOR/DIOW)
 177 *
 178 * However, we also need to take care of the read/write active and
 179 * recovery timings:
 180 *
 181 *                      Read    Write
 182 *      Mode    Active  -- Recovery --  Cycle   IOMD type
 183 *      MW0     215     50      215     480     A
 184 *      MW1     80      50      50      150     C
 185 *      MW2     70      25      25      120     C
 186 */
 187static void pata_icside_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 188{
 189        struct pata_icside_state *state = ap->host->private_data;
 190        struct ata_timing t;
 191        unsigned int cycle;
 192        char iomd_type;
 193
 194        /*
 195         * DMA is based on a 16MHz clock
 196         */
 197        if (ata_timing_compute(adev, adev->dma_mode, &t, 1000, 1))
 198                return;
 199
 200        /*
 201         * Choose the IOMD cycle timing which ensure that the interface
 202         * satisfies the measured active, recovery and cycle times.
 203         */
 204        if (t.active <= 50 && t.recover <= 375 && t.cycle <= 425)
 205                iomd_type = 'D', cycle = 187;
 206        else if (t.active <= 125 && t.recover <= 375 && t.cycle <= 500)
 207                iomd_type = 'C', cycle = 250;
 208        else if (t.active <= 200 && t.recover <= 550 && t.cycle <= 750)
 209                iomd_type = 'B', cycle = 437;
 210        else
 211                iomd_type = 'A', cycle = 562;
 212
 213        ata_dev_info(adev, "timings: act %dns rec %dns cyc %dns (%c)\n",
 214                     t.active, t.recover, t.cycle, iomd_type);
 215
 216        state->port[ap->port_no].speed[adev->devno] = cycle;
 217}
 218
 219static void pata_icside_bmdma_setup(struct ata_queued_cmd *qc)
 220{
 221        struct ata_port *ap = qc->ap;
 222        struct pata_icside_state *state = ap->host->private_data;
 223        unsigned int write = qc->tf.flags & ATA_TFLAG_WRITE;
 224
 225        /*
 226         * We are simplex; BUG if we try to fiddle with DMA
 227         * while it's active.
 228         */
 229        BUG_ON(dma_channel_active(state->dma));
 230
 231        /*
 232         * Route the DMA signals to the correct interface
 233         */
 234        writeb(state->port[ap->port_no].port_sel, state->ioc_base);
 235
 236        set_dma_speed(state->dma, state->port[ap->port_no].speed[qc->dev->devno]);
 237        set_dma_sg(state->dma, qc->sg, qc->n_elem);
 238        set_dma_mode(state->dma, write ? DMA_MODE_WRITE : DMA_MODE_READ);
 239
 240        /* issue r/w command */
 241        ap->ops->sff_exec_command(ap, &qc->tf);
 242}
 243
 244static void pata_icside_bmdma_start(struct ata_queued_cmd *qc)
 245{
 246        struct ata_port *ap = qc->ap;
 247        struct pata_icside_state *state = ap->host->private_data;
 248
 249        BUG_ON(dma_channel_active(state->dma));
 250        enable_dma(state->dma);
 251}
 252
 253static void pata_icside_bmdma_stop(struct ata_queued_cmd *qc)
 254{
 255        struct ata_port *ap = qc->ap;
 256        struct pata_icside_state *state = ap->host->private_data;
 257
 258        disable_dma(state->dma);
 259
 260        /* see ata_bmdma_stop */
 261        ata_sff_dma_pause(ap);
 262}
 263
 264static u8 pata_icside_bmdma_status(struct ata_port *ap)
 265{
 266        struct pata_icside_state *state = ap->host->private_data;
 267        void __iomem *irq_port;
 268
 269        irq_port = state->irq_port + (ap->port_no ? ICS_ARCIN_V6_INTRSTAT_2 :
 270                                                    ICS_ARCIN_V6_INTRSTAT_1);
 271
 272        return readb(irq_port) & 1 ? ATA_DMA_INTR : 0;
 273}
 274
 275static int icside_dma_init(struct pata_icside_info *info)
 276{
 277        struct pata_icside_state *state = info->state;
 278        struct expansion_card *ec = info->ec;
 279        int i;
 280
 281        for (i = 0; i < ATA_MAX_DEVICES; i++) {
 282                state->port[0].speed[i] = 480;
 283                state->port[1].speed[i] = 480;
 284        }
 285
 286        if (ec->dma != NO_DMA && !request_dma( 193

 276{
 2e" name="L234"> R_icside.c#L193" id="L193" class="line" name="L1side.393drivef="drivers/ata/pataaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa0Rn54h1code=private_data" class="sref(375)       187 _29 /pataaaaaaaaaaaaaaaaaaaae        for (
active <= 50 &&3 :
       L279"> 279        struct  120        struct  121        unsigned in2  122        char  123
 124         125   29cside_dma_incard" class="sref">expsine_ate__templvef="drivers/ata/paine_ate__templvefbmdma_status" class="sref">pata_sha_start(struct  126   29dma_speed" class="sref">set_ode=BASE_SHTSTAT_2 :

 276{
 127        if (irqdisasg_te" csizf="drivers/ata/pag_te" csizf
; irqpendef"hbouers/y="sref(375)       hbouers/y
);
 279
 230         231   3     *icside_bmdma_stop" class="sref">pata_icpte_resea_start(struct ata_port clae=speed" class="/a> claesref">ec = (strpeed"eaicside.c#L276" id="L276" class="line" name3"L202"> 232   3     *       187 (425)
 233   30ode=state" clclass="sref">ata_port *ap = qc->ap;
 234        if (pata_icside_state *state = info->ref="+code=host" class="sref">host->private_data;
 235                 236        else if (ec->(strpeed"eaicsi[0]="sref">NO_DMA riverErefON76"> 276{
cycle;
(strpeed"eaicsi[1]="sref">NO_DMA riverErefON76"> 276{
 236        if (readb((strucode=ap"pte_reseaa>
(strpeed"eaicsidde.c#L267" id="L267" class="line" name3"8206"> 236                ret3href=30icside.c#L269" id="L269" class="line" name3"L209"> 239                irq_portport[ap->port_no].speed[ 230        else
 231                ec->port[ 232
 233         234                   3  235
 236         237}
__iomem *irq_port;
state->irq_port + ( 238
port_no ? ICS_ARCIN_VOFFSENTRSTAT_2 :
ICS_ARCIN_VOFFSENTRSTAT_1);
 239static void iomd_typ href="+code=irq_port" class="sref">irq_port) & 1 ?  230{
 231        struct  232        struct  233        unsigned in3 ata_port *(str/a> *pata_*(struct 
 234
speed[(strinheritade=iomd_type" class=sref">qc->(stra"drivers/* 235        /*
face*ta_icside.c#L261" id="L261" class="line" name3"L226"> 236   326" class="sreef">speed[info->rs="noop_qc_preef="+code=port_nrs="noop_qc_pree cl76e.c#L214" id="L214" class="line" name3"L217"> 237   32disable" class="sref">irqdisasap" ss="xf href="+code=t" csap" ss="xf hde=iomd_type" ef">info->rs="sap" ss="xf h"no"+c_start(strucode=ap" ss="xf h"no"+c cl76e.c#L214" id="L214" class="line" name3"8206"> 238   32pending" class="sref">irqpendcside_bmdma_setup(stru+code=ata_queuetype" class=ef">info->uct  239        irqpendcside_bmdma_start(stru+code=ata_queuetype" class=ef">info->uct  230
irqpendcside_bmma_stop(struccode=ata_queue_type" class=ef">info->ref">pata_icside_bmdma_stop(struct  231        /*
s="sref">irqpendcside_bmddma_status(str"+code=ata_port"ype" class=ef">info->uct  232   33icside.c#L253" id="L253" class="line" name3"L233"> 233   333">/*
s="sref">irqpendce" claeteca_start(struce" claetecaort"ype" class=ef">info->ss="ce" cl40wire( 234        speed[(stru+code=ata_port"type" class=ef">info->ref">pata_iccside_set_dmamode(struct  235
speed[(structe_reseaa>
info->ref">pata_icpte_resea_start(struct  236         237        irqdisate" clmdma_start(struce" clmdmaueue_type" class=ef">info->riveOP_NULL6"> 276{
 238         239
 230        /*icside_set_dmamode" class="sref">pata_icsiup_ioaddhref="+code=t" csref">pata_icsiup_ioaddhort" class="sref">ata_port *ap, struct __iomem *irq_port<;
 231        >>>>>>>>>>>>>>>>>>>>>>>>>>>>>e_info" class="sref">pata_icside_info *info)
 232}
pas="nfo *info)
 233
 234static void info)
qc->port_no 235{
__iomem *irq_port< *info->;
pas=""+code=ap" class="sref"ode=private_data" class=offsea_start(struass=offseaort"de.c#L150" id="L150" class="line" name3"L226"> 236        struct  237        struct set_dmahoaddhref="+code=t" cioaddhort"ode=private_data" cls="_addhref="+code=t" cs="_addhma_sg" classref">cycle;
 * 238
disablhoaddhref="+code=t" cioaddhort"ode=private_data" cl ss="addhref="+code=t" c ss="addhle_dma" claref">cycle;
 *ap-> 276{
ATas=""+code=ap" class="sref"ode=private_data" clstepp  239        BUG_ON(hoaddhref="+code=t" cioaddhort"ode=private_data" clerror"addhref="+code=t" cerror"addhN" class="ref">cycle;
 *ap->ATas=""+code=ap" class="sref"ode=private_data" clstepp  230        enable_hoaddhref="+code=t" cioaddhort"ode=private_data" clfeature"addhref="+code=t" cfeature"addhe_dma" cref">cycle;
 *ap-> 276{
ATas=""+code=ap" class="sref"ode=private_data" clstepp  231}
hoaddhref="+code=t" cioaddhort"ode=private_data" clnsect"addhref="+code=t" cnsect"addhN" class="ref">cycle;
 *ap-> :
ATas=""+code=ap" class="sref"ode=private_data" clstepp  232
hoaddhref="+code=t" cioaddhort"ode=private_data" cllbal"addhref="+code=t" clbal"addhle_dma" claref">cycle;
 *ap-> 276{
ATas=""+code=ap" class="sref"ode=private_data" clstepp  233static void ata_dhoaddhref="+code=t" cioaddhort"ode=private_data" cllbam"addhref="+code=t" clbam"addhle_dma" claref">cycle;
 *ap-> 276{
ATas=""+code=ap" class="sref"ode=private_data" clstepp  234{
writeb(hoaddhref="+code=t" cioaddhort"ode=private_data" cllbah"addhref="+code=t" clbah"addhle_dma" claref">cycle;
 *ap-> 276{
ATas=""+code=ap" class="sref"ode=private_data" clstepp  235        struct disablhoaddhref="+code=t" cioaddhort"ode=private_data" cl evice"addhref="+code=t" c evice"addhe=ata_porref">cycle;
 *ap-> 276{
ATas=""+code=ap" class="sref"ode=private_data" clstepp  236        struct set_hoaddhref="+code=t" cioaddhort"ode=private_data" cl=ata_p"addhref="+code=t" c=ata_p"addhe=ata_porref">cycle;
 *ap->; ATas=""+code=ap" class="sref"ode=private_data" clstepp  237
set_dmahoaddhref="+code=t" cioaddhort"ode=private_data" clsass="s_addhref="+code=t" csass="s_addhe_dma" cref">cycle;
 *ap->);
ATas=""+code=ap" class="sref"ode=private_data" clstepp  238         239
BUG_ON(hoaddhref="+code=t" cioaddhort"ode=private_data" clctl"addhref="+code=t" cctl"addhma_sg" classref">cycle;
<;
pas=""+code=ap" class="sref"ode=private_data" clctrloffsea_start(structrloffseasrefde.c#L150" id="L150" class="line" name3"L260"> 230        enable_hoaddhref="+code=t" cioaddhort"ode=private_data" clalt=ata_p"addhref="+code=t" calt=ata_p"addhe_dma"ef">info-> 231         232}
/a> * *, struct "s=" 0x%lx ctl 0x%lx"a_icsid6e.c#L214" id="L214" class="line" name3"L263"> 233
enable_h;= 50 &&3pas=""+code=ap" class="sref"ode=private_data" class=offsea_start(struass=offseaort"6e.c#L214" id="L214" class="line" name3"L244"> 234static enable_h;= 50 &&3pas=""+code=ap" class="sref"ode=private_data" clctrloffsea_start(structrloffseasrefMde.c#L267" id="L267" class="line" name3"L265"> 235{
 236        struct ec->);
 237        void , struct "/a>;
enable_h;= 50 &&3);
 238
 239         230                   3     37t">/*icside_f">i;
pata_icside_info *info)
 231
 232        return pata_icside_state *state = info->state;
 233}
__iomem *irq_port<;
 234
 235static int disabl;
, struct ec;
enable_ECARDeRES_MEMCdrivers/ata/patECARDeRES_MEMCicsi6s06s0dde.c#L267" id="L267" class="line" name3"L276"> 236{
ss="sref">reques;
 237        struct enable_ENOMEMdrivers/ata/patENOMEM_icsde.c#L278" id="L278" class="line" name3"L238"> 238        struct  239        int irq_portport[;
state-&g;
 230
 231        for (ha href="+code=ec" class="sref">ec;
 232                ha href="+code=ec" class="sref">ec;
p href="driv5rs/ata/pa href="drivers/ href="driv5rs/ata/pa_icsde.c#L278" id="L278" class="line" name3"L273"> 233                ata_dha href="+code=ec" class="sref">ec;
 234        }
writeb(ha href="+code=ec" class="sref">ec;
(strta/opa_ics aaref">qc-> 235
disablha href="+code=ec" class="sref">ec;
 236        if (set_ha href="+code=ec" class="sref">ec;
qc-> 23me="L234"> R_icside.c#L133" id38icside.c#L258" id="L258" class="line" name3  for (disablh;= 50 &&3(struaaardcresourceclmdmaort" ap, struct ec;
enable_ECARDeRES_MEMCdrivers/ata/patECARDeRES_MEMCicsidde.c#L267" id="L267" class="line" name3 L279"> 239        struct  130        struct  131        unsigned in3  132        char  133
i;
pata_icside_info *info)
 134         135   39de=ata_port" class="sref">ata_port *state = info->state;
 136   39de=pata_icside_state" class="sref">ansion_card *ec = info->ec;
 137        if (__iomem *irq_port);
ec =                 ret3rn;
<39pending" clase" class="sref">state;
 239
 240        enable_ho>);
, struct ="drivers/ata/pata_icsi6s="sref">enable_ECARDeRES_IOCFASa href="drivers/ECARDeRES_IOCFASaicsi6s06s0dde.c#L267" id="L267" class="line" name4"L201"> 241   40ode=iomd_typeef">ss="sref">requesho>);
 242   40ode=state" class="sress="sre-="sref">enable_ENOMEMdrivers/ata/patENOMEM_icsde.c#L278" id="L278" class="line" name4"L203"> 243   40icside.c#L194" id="L194" class="line" name4"L204"> 244        if (writeb(fasi);
info->);
 244 246        else if (ec->(straaardcresourcecflagaort" ap, struct ="drivers/ata/pata_icsi6s="sref">enable_ECARDeRES_EASI href="drivers/ECARDeRES_EASIref"dMA       187 (425)
 246        if (writeb(fasi);
info->aaardmort", struct ="drivers/ata/pata_icsi6s="sref">enable_ECARDeRES_EASI href="drivers/ECARDeRES_EASIref"6s06s0dde.c#L267" id="L267" class="line" name4"8206"> 246                ret4href=40>
ss="sref">requesfasi);
 246
enable_ENOMEMdrivers/ata/patENOMEM_icsde.c#L278" id="L278" class="line" name4"L210"> 240        else
 241                >>>>>>>>fa href="drivers/ata/pata_icside.c#L232" id="L232" class="line" name4"L212"> 242
 243         244                   4 state;
 245
 246         247}
set_dmawritef="+code=irq_porwritefort" ap, struct aelf="drivers/ata/pels="s6s="sref">enable_ho>);
 248
 249static void irq_portport[;
state-&gfasi);
 240{
enable_t;port[);
);
 241        struct t;port[0].speed[ 242        struct t;port[1].speed[ 243        unsigned in4  244
writeb(ha href="+code=ec" class="sref">ec;
 245        disablha href="+code=ec" class="sref">ec;
(strta/opa_ics aaref">qc-> 246   42dma_speed" class="sref">set_ha href="+code=ec" class="sref">ec;
 247   42dma_sg" class="sref">set_dmaha href="+code=ec" class="sref">ec;
qc->);
 248   42ble_dma" class="sref">disablh;= 50 &&3qc-> :
 249         240
enable_h;= 50 &&3(struaaardcresourceclmdmaort" ap, struct ="drivers/ata/pata_icsi6s="sref">enable_ECARDeRES_EASI href="drivers/ECARDeRES_EASIref"dde.c#L279" id="L279" class="line" name4"L221"> 241        ha href="+code=ec" class="sref">ec;
);
(struaaardcresourceclmdmaort" ap, struct ="drivers/ata/pata_icsi6s="sref">enable_ECARDeRES_IOCFASa href="drivers/ECARDeRES_IOCFASaicsidde.c#L279" id="L279" class="line" name4"L212"> 242   43icside.c#L253" id="L253" class="line" name4"L233"> 243   433">/*
ss="sref">readb(, struct  244         245
 246        i;
pata_icside_info *info)
 247         248        ansion_card *ec = info->ec;
 249
ss="ec =  240        i;
 241         242}
ec->
 243
ec;
 244static void state;
<="drivers/ata/pata_icsiref">ec;
 245{
 246        struct ec-> 247        struct writeb(faardcset"+c_start(strufaardcset"+cort" ap, struct ="drivers/ata/pata_icsi6s="sref">enable_h;= 50 &&3enable_h;= 50 &&3 248
 249         240         241}
 242
="drivers/ata/pata_icsiref">ec;
(stropa_ics="56port[1].(strta/date" cort" ap, struct ="drivers/ata/pata_icsi6s="sref">enable_="drivers/ata/pata_icsiref">ec;
(strta/ass=dde.c#L279" id="L279" class="line" name4"L253"> 243static void  244{
writeb(info->ss="ate__alloaaaaaaaaaaaaaa0R/a> ate__alloaort" ref">qc->ec;
enable_h;= 50 &&3(strnr_s="sa_icsdde.c#L279" id="L279" class="line" name4"L225"> 245        struct ss="sref">reques 246        struct enable_ENOMEMdrivers/ata/patENOMEM_icsde.c#L278" id="L278" class="line" name4"L247"> 247
 248        disabl[1]. * 249
BUG_ON([1].(strflagaort"=ef">info->riveHOST_SIMPLEX_status(strriveHOST_SIMPLEXicside.c#L278" id="L278" class="line" name4"L260"> 240         241        >ec->;
ATh;= 50 &&3(strnr_s="sa_icsdi;

 242}
ata_port *ap, struct info->[1].;
 243
 244static [1].info->rivePIO4_status(strrivePIO4icside.c#L278" id="L278" class="line" name4"L225"> 245{
[1]. 246        struct , struct [1].(strflagaort"=|ef">info->riveFLAG_SLAVE_POS/a>;  247        void [1].(stropa_ics aaref">qc->(struct  248
 249        iomd_typ+code=state" siup_ioaddhref="+code=t" csref">pata_icsiup_ioaddhort" me="L1side.393d/a href="+code=ata_devi6s="sref">enable_h;= 50 &&3enable_h;= 50 &&3enable_h;= 50 &&3 240                   4     47             de.c#L263" id="L263" class="line" name4"L271"> 241
 242        return readb( ate__act=" claaaaaaaaaaaaa0R/a> ate__act=" clort" me="L1side.393denable_="drivers/ata/pata_icsiref">ec;
(strta/ass=6s="sref">enable_/a> "+codes/ataruptaaaaaaaaaaaaa0R/a> "+codes/ataruptass=6s06e.c#L214" id="L214" class="line" name4"L273"> 243}
qc->(struct  244
 245static int  246{
i;
 *pansion_card *ec =  247        struct e_info" class="sref">pfaardcia> *ec =  * 248        struct  249        int pata_icside_state *state =  240
pata_icside_nfo *enable_h;= 50 &&3 241        for (__iomem *irq_port 242                i;
 243                 244        }
writeb(rea_start(strureasref aaaaaaaaaaaaaaaaaaaardcrequee__resourcea_status(straaardcrequee__resourceaort" ap, struct ="drivers/ata/pata_icsidde.c#L279" id="L279" class="line" name4"L275"> 245
ef">writeb(rea_start(strureasrefde.c#L276" id="L276" class="line" name4"L276"> 246        if ((struouasrefde.c#L150" id="L150" class="line" name4"L247"> 24me="L234"> R_icside.c#L143" id48icside.c#L258" id="L258" class="line" name4  for (disablinfo->devm_kzalloaaaaaaaaaaaaaa0Rdevm_kzalloaort" ref">qc->ec;
state = enable_GFP_KERNEL6"> 276{
 249        struct ss="sref">reques 140        struct writeb(rea_start(strureasref aa-="sref">enable_ENOMEMdrivers/ata/patENOMEM_icsde.c#L278" id="L278" class="line" name4"L191"> 141        unsigned in4 >>>>>>>>gotoaaaaaaaaaaaaaaaarele
 242        char  143
 144        writeb(t;port[1].info-> hreTYPE_NOTYPEhref="+code=por hreTYPE_NOTYPE_icsde.c#L278" id="L278" class="line" name4"L275"> 245   49de=ata_port" s="sref">disablt;port[1]. 276{
 246   49dma_se.c#L214" id="L214" class="line" name4"L197"> 147        if (set_dmahda href="+code=irq_/da hlass aaaaaaaaaaaaaaaaaaaardmort", struct ="drivers/ata/pata_icsi6s="sref">enable_ECARDeRES_IOCFASa href="drivers/ECARDeRES_IOCFASaicsi6s06s0dde.c#L267" id="L267" class="line" name4" for (                ret4rn;
<49pending" clasef">ec-> 249
state;
 250         251   50class="sref">>>>>>>>>f>port[1].info->readf="+code=irq_porreadfort" ap, struct hda href="+code=irq_/da hlass +" class="sref">p hreIDENT_OFFSEa href="drivers/ hreIDENT_OFFSEalass)Aref">aide.c#L143" id="L143" class="line" name5"L202"> 252   50ode=state" class="sref>port[1].writeb(readf="+code=irq_porreadfort" ap, struct hda href="+code=irq_/da hlass +" class="sref">p hreIDENT_OFFSEa href="drivers/ hreIDENT_OFFSEalass +"4)Aref">ai)=CES"CES" ide.c#L143" id="L143" class="line" name5"3202"> 252
   50ode=state" class="sreec;
writeb(readf="+code=irq_porreadfort" ap, struct hda href="+code=irq_/da hlass +" class="sref">p hreIDENT_OFFSEa href="drivers/ hreIDENT_OFFSEalass +"8)Aref">ai)=CES"CES" 2de.c#L279" id="L279" class="line" name5"L204"> 254        if (ef">writeb(readf="+code=irq_porreadfort" ap, struct hda href="+code=irq_/da hlass +" class="sref">p hreIDENT_OFFSEa href="drivers/ hreIDENT_OFFSEalass +"12)Aref">ai)=CES"CES" 3de.c#L279" id="L279" class="line" name5"5204"> 254, struct ="drivers/ata/pata_icsi6s="sref">enable_hda href="+code=irq_/da hlass)de.c#L279" id="L279" class="line" name5"6204"> 254 256        if (writeb(t;port[1].info->typ href="+code=portyp s="sde.c#L267" id="L267" class="line" name5"8206"> 256                ret5href=50>
 256
 250        else
enable_a hsea_start(strua hseaort" ref">qc->-> 251                ha href="+code=ec" class="sef">speed[info-> 252
ha href="+code=ec" class="sef">speed[info->="drivers/ata/pata_icside.c#L279" id="L279" class="line" name5"L213"> 253         254                   5 ef">writeb(t;port[1].
 255
info-> hreTYPE_A3INhref="+code=por hreTYPE_A3INe=at:      187 (425)
 256        , struct dev_warndrivers/ata/patdev_warnort" ref">qc->ec;
 257}
writeb(rea_start(strureasref aa-="sref">enable_ENODEVdrivers/ata/patENODEVicside.c#L279" id="L279" class="line" name5"8206"> 258
 259static void  250{
info-> hreTYPE_A3USERhref="+code=por hreTYPE_A3USERe=at:      187 (425)
 251        struct >>>>>>>>f>port[1].qc->ec;
 252        struct enable_ENODEVdrivers/ata/patENODEVicside.c#L279" id="L279" class="line" name5"L223"> 253        unsigned in5  254
 255        info-> hreTYPE_V5href="+code=por hreTYPE_V5e=at:      187 (425)
 256   52dma_speed" clllllllllap, struct rea_start(strureasref aaaaaaaaaaaaaaaaacode=info" cregister_v5"+code=ap" classode=info" cregister_v5ort" ref">qc-> 257   52ode=iomd_type" class=breakde.c#L279" id="L279" class="line" name5"8206"> 258   52icside.c#L269" id="L269" class="line" name5"L219"> 259        info-> hreTYPE_Vending_arcin_v6< hreTYPE_Vee=at:      187 (425)
 250
writeb(rea_start(strureasref aaaaaaaaaaaaaaaaacode=info" cregister_vending_arcin_v6qc-> 251        >>>>>>>>breakde.c#L279" id="L279" class="line" name5"L212"> 252   53icside.c#L253" id="L253" class="line" name5"L233"> 253   533">/*
default:      187 (425)
 254        qc->ec;
 255
enable_ENODEVdrivers/ata/patENODEVicside.c#L279" id="L279" class="line" name5"L226"> 256         257         258         259
ap, struct rea_start(strureasref a= 0de.c#L276" id="L276" class="line" name5"L240"> 250        writeb(rea_start(strureasref aaaaaaaaaaaaaaaaacode=info" cadd_s="sa_status(strcode=info" cadd_s="saort" ref">qc-> 251         252}
ec->(strureasref a= 0de.c#L276" id="L276" class="line" name5"L233"> 253
 254static void  255{

 256        struct set_aaardcrele
(straaardcrele
, struct ="drivers/ata/pata_icsi)de.c#L279" id="L279" class="line" name5"7206"> 257        struct  258
readb((strureasrefde.c#L150" id="L150" class="line" name5"L249"> 259         250         251}
__iomempansion_card *ec =  252
 253static void ss="ec = , struct ="drivers/ata/pata_icsi)de.c#L279" id="L279" class="line" name5"L244"> 254{
(strflagaort"de.c#L279" id="L279" class="line" name5"L225"> 255        struct  256        struct  257
 258         259

 250        
 251        local_ta/psava href="drivers/local_ta/psavaort" ap, struct flaga_status(strflagaort")de.c#L279" id="L279" class="line" name5"L262"> 252}
="drivers/ata/pata_icsiref">ec;
(stropa_ics="56port[1].(strta/date" cort" ap, struct ="drivers/ata/pata_icsi6s="sref">enable_="drivers/ata/pata_icsiref">ec;
(strta/ort")de.c#L279" id="L279" class="line" name5"L253"> 253
local_ta/prestore href="drivers/local_ta/prestoreort" ap, struct flaga_status(strflagaort")de.c#L279" id="L279" class="line" name5"L244"> 254static  255{
 256        struct  257        void  258
 259        
 250                   5     57             ef">ec-> 251
>>>>>>>>class="sref">ata_port *state = info->[1]. * 252        return ec->port[);
 253}
port[enable_t;port[);
 254
 255static int  256{
 257        struct __iomempansion_card *ec =  258        struct  259        int ss="ec = , struct ="drivers/ata/pata_icsi)de.c#L279" id="L279" class="line" name5"L280"> 250
pata_icside_state *state = info->[1]. * 251        for ( 252                ss=", struct  253                 254        }
writeb(ct , struct ="drivers/ata/pata_icsi)de.c#L279" id="L279" class="line" name5"L275"> 255
 256        if ( 25me="L234"> R_icside.c#L153" id58icsid/
 25href="+code=i" class=(425)
 259        struct 
 150        struct ec->port[1]. 276{
 151        unsigned in5 >>>>>>>>ap, struct free_coddrivers/ata/patfree_codort" ap, struct t;port[1]. 252        char  153
aaardcrele
(straaardcrele
, struct ="drivers/ata/pata_icsi)de.c#L279" id="L279" class="line" name5"L194"> 154         255   59icside.c#L286" id="L286" class="line" name5"L276"> 256   59dma_sicside_conat>e_info" class="sref">pfaardcia> *writeb(ct 
 157        if (writeb(MANU_IC/a>; writeb(PROD_ hreIDEa>;                 ret5rn;
<59pending" clas{"ef">writeb(MANU_IC/RSTAT_2 :
enable_PROD_ hr2eIDEa>;  259
 260         261   60icside.c#L272" id="L272" class="line" name6"L202"> 262   60ode=sicside_e_info" class="sref">pfaardcid="L2> *writeb(ct  *
 262
   60ode=state" clef">speed[ *>>>>>>>>aaaaaaaaaaaaaaaaacode=info" cprobe * 264        if (speed[>>>>>>>>aaaaaaaaaaaaaaaaacode=info" cremova href="drivers/ct  264speed[(strshutdownort">>>>>>>aaaaaaaaaaaaaaaaacode=info" cshutdown_status(strcode=info" cshutdownort"6e.c#L214" id="L214" class="line" name6"6204"> 264speed[(strtd_te" cort">>>>>>>aaaaaaaaaaaaaaaaacode=info" cida_status(strcode=info" cidasref6e.c#L214" id="L214" class="line" name6"7204"> 264        if (speed[ 264                ret6href=60>
speed[;  264
 260        else
 261                 262
state;
<_eini href="drivers/a_eini ort"e" class="sref">pata_icside_nfi href="drivers/apata_icside_nfi ort" ss="de.c#L276" id="L276" class="line" name6"L213"> 263         264                   6 readb( *qc-> * 265
 266         267}
__iomempata_icside_exi href="drivers/apata_icside_exi ort" ss="de.c#L276" id="L276" class="line" name6"8204"> 268
 269static void BUG_ON(daardcremova_id="L2> *qc-> * 260{
 261        struct  262        struct writeb(MODULE_AUTHORhref="+code=porMODULE_AUTHORort" aa href="drivstr "Russell K  263        unsigned in6 writeb(MODULE_LICENSEa>;  264
writeb(MODULE_DESCRIPTIONhref="+code=porMODULE_DESCRIPTIONort" aa href="drivstr " hr PATA id="L2"a_icsid)de.c#L279" id="L279" class="line" name6"5204"> 265         266   62dma_sef">writeb(module_nfi href="drivers/amodule_nfi ort" ap, struct pata_icside_nfi href="drivers/apata_icside_nfi ort")de.c#L279" id="L279" class="line" name6"7206"> 267   62ode=ief">writeb(module_exi href="drivers/amodule_exi ort" ap, struct pata_icside_exi href="drivers/apata_icside_exi ort")de.c#L279" id="L279" class="line" name6"8204"> 268   62icsid


The original LXR software byia/e .c#L279" http://sourceforge.net/projects/lxr">LXR ref=ufi yicsi6sthis experi="dral "L27ion byi.c#L279" mailto:lxr@ sux.no">lxr@ sux.noicsi.
lxr. sux.no kindly Redpill L spro A/icsi6sprove" r of L sux_conault