linux/drivers/ata/ahci.c
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   1/*
   2 *  ahci.c - AHCI SATA support
   3 *
   4 *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
   5 *                  Please ALWAYS copy linux-ide@vger.kernel.org
   6 *                  on emails.
   7 *
   8 *  Copyright 2004-2005 Red Hat, Inc.
   9 *
  10 *
  11 *  This program is free software; you can redistribute it and/or modify
  12 *  it under the terms of the GNU General Public License as published by
  13 *  the Free Software Foundation; either version 2, or (at your option)
  14 *  any later version.
  15 *
  16 *  This program is distributed in the hope that it will be useful,
  17 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 *  GNU General Public License for more details.
  20 *
  21 *  You should have received a copy of the GNU General Public License
  22 *  along with this program; see the file COPYING.  If not, write to
  23 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  24 *
  25 *
  26 * libata documentation is available via 'make {ps|pdf}docs',
  27 * as Documentation/DocBook/libata.*
  28 *
  29 * AHCI hardware documentation:
  30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
  31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
  32 *
  33 */
  34
  35#include <linux/kernel.h>
  36#include <linux/module.h>
  37#include <linux/pci.h>
  38#include <linux/init.h>
  39#include <linux/blkdev.h>
  40#include <linux/delay.h>
  41#include <linux/interrupt.h>
  42#include <linux/dma-mapping.h>
  43#include <linux/device.h>
  44#include <linux/dmi.h>
  45#include <linux/gfp.h>
  46#include <scsi/scsi_host.h>
  47#include <scsi/scsi_cmnd.h>
  48#include <linux/libata.h>
  49#include "ahci.h"
  50
  51#define DRV_NAME        "ahci"
  52#define DRV_VERSION     "3.0"
  53
  54enum {
  55        AHCI_PCI_BAR_STA2X11    = 0,
  56        AHCI_PCI_BAR_ENMOTUS    = 2,
  57        AHCI_PCI_BAR_STANDARD   = 5,
  58};
  59
  60enum board_ids {
  61        /* board IDs by feature in alphabetical order */
  62        board_ahci,
  63        board_ahci_ign_iferr,
  64        board_ahci_nosntf,
  65        board_ahci_yes_fbs,
  66
  67        /* board IDs for specific chipsets in alphabetical order */
  68        board_ahci_mcp65,
  69        board_ahci_mcp77,
  70        board_ahci_mcp89,
  71        board_ahci_mv,
  72        board_ahci_sb600,
  73        board_ahci_sb700,       /* for SB700 and SB800 */
  74        board_ahci_vt8251,
  75
  76        /* aliases */
  77        board_ahci_mcp_linux    = board_ahci_mcp65,
  78        board_ahci_mcp67        = board_ahci_mcp65,
  79        board_ahci_mcp73        = board_ahci_mcp65,
  80        board_ahci_mcp79        = board_ahci_mcp77,
  81};
  82
  83static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
  84static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
  85                                 unsigned long deadline);
  86static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
  87                                unsigned long deadline);
  88#ifdef CONFIG_PM
  89static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
  90static int ahci_pci_device_resume(struct pci_dev *pdev);
  91#endif
  92
  93static struct scsi_host_template ahci_sht = {
  94        AHCI_SHT("ahci"),
  95};
  96
  97static struct ata_port_operations ahci_vt8251_ops = {
  98        .inherits               = &ahci_ops,
  99        .hardreset              = ahci_vt8251_hardreset,
 100};
 101
 102static struct ata_port_operations ahci_p5wdh_ops = {
 103        .inherits               = &ahci_ops,
 104        .hardreset              = ahci_p5wdh_hardreset,
 105};
 106
 107static const struct ata_port_info ahci_port_info[] = {
 108        /* by features */
 109        [board_ahci] = {
 110                .flags          = AHCI_FLAG_COMMON,
 111                .pio_mask       = ATA_PIO4,
 112                .udma_mask      = ATA_UDMA6,
 113                .port_ops       = &ahci_ops,
 114        },
 115        [board_ahci_ign_iferr] = {
 116                AHCI_HFLAGS     (AHCI_HFLAG_IGN_IRQ_IF_ERR),
 117                .flags          = AHCI_FLAG_COMMON,
 118                .pio_mask       = ATA_PIO4,
 119                .udma_mask      = ATA_UDMA6,
 120                .port_ops       = &ahci_ops,
 121        },
 122        [board_ahci_nosntf] = {
 123                AHCI_HFLAGS     (AHCI_HFLAG_NO_SNTF),
 124                .flags          = AHCI_FLAG_COMMON,
 125                .pio_mask       = ATA_PIO4,
 126                .udma_mask      = ATA_UDMA6,
 127                .port_ops       = &ahci_ops,
 128        },
 129        [board_ahci_yes_fbs] = {
 130                AHCI_HFLAGS     (AHCI_HFLAG_YES_FBS),
 131                .flags          = AHCI_FLAG_COMMON,
 132                .pio_mask       = ATA_PIO4,
 133                .udma_mask      = ATA_UDMA6,
 134                .port_ops       = &ahci_ops,
 135        },
 136        /* by chipsets */
 137        [board_ahci_mcp65] = {
 138                AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
 139                                 AHCI_HFLAG_YES_NCQ),
 140                .flags          = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
 141                .pio_mask       = ATA_PIO4,
 142                .udma_mask      = ATA_UDMA6,
 143                .port_ops       = &ahci_ops,
 144        },
 145        [board_ahci_mcp77] = {
 146                AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
 147                .flags          = AHCI_FLAG_COMMON,
 148                .pio_mask       = ATA_PIO4,
 149                .udma_mask      = ATA_UDMA6,
 150                .port_ops       = &ahci_ops,
 151        },
 152        [board_ahci_mcp89] = {
 153                AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA),
 154                .flags          = AHCI_FLAG_COMMON,
 155                .pio_mask       = ATA_PIO4,
 156                .udma_mask      = ATA_UDMA6,
 157                .port_ops       = &ahci_ops,
 158        },
 159        [board_ahci_mv] = {
 160                AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
 161                                 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
 162                .flags          = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
 163                .pio_mask       = ATA_PIO4,
 164                .udma_mask      = ATA_UDMA6,
 165                .port_ops       = &ahci_ops,
 166        },
 167        [board_ahci_sb600] = {
 168                AHCI_HFLAGS     (AHCI_HFLAG_IGN_SERR_INTERNAL |
 169                                 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
 170                                 AHCI_HFLAG_32BIT_ONLY),
 171                .flags          = AHCI_FLAG_COMMON,
 172                .pio_mask       = ATA_PIO4,
 173                .udma_mask      = ATA_UDMA6,
 174                .port_ops       = &ahci_pmp_retry_srst_ops,
 175        },
 176        [board_ahci_sb700] = {  /* for SB700 and SB800 */
 177                AHCI_HFLAGS     (AHCI_HFLAG_IGN_SERR_INTERNAL),
 178                .flags          = AHCI_FLAG_COMMON,
 179                .pio_mask       = ATA_PIO4,
 180                .udma_mask      = ATA_UDMA6,
 181                .port_ops       = &ahci_pmp_retry_srst_ops,
 182        },
 183        [board_ahci_vt8251] = {
 184                AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
 185                .flags          = AHCI_FLAG_COMMON,
 186                .pio_mask       = ATA_PIO4,
 187                .udma_mask      = ATA_UDMA6,
 188                .port_ops       = &ahci_vt8251_ops,
 189        },
 190};
 191
 192static const struct pci_device_id ahci_pci_tbl[] = {
 193        /* Intel */
 194        { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
 195        { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
 196        { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
 197        { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
 198        { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
 199        { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
 200        { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
 201        { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
 202        { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
 203        { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
 204        { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
 205        { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
 206        { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
 207        { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
 208        { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
 209        { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
 210        { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
 211        { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
 212        { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
 213        { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
 214        { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
 215        { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
 216        { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
 217        { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
 218        { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
 219        { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
 220        { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
 221        { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
 222        { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
 223        { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
 224        { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
 225        { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
 226        { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
 227        { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
 228        { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
 229        { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
 230        { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
 231        { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
 232        { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
 233        { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
 234        { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
 235        { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
 236        { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
 237        { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
 238        { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
 239        { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
 240        { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
 241        { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
 242        { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
 243        { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
 244        { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
 245        { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
 246        { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
 247        { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
 248        { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
 249        { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
 250        { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
 251        { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
 252        { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
 253        { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
 254        { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
 255        { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
 256        { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
 257        { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
 258        { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
 259        { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
 260        { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
 261        { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
 262        { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
 263        { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
 264        { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
 265        { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
 266        { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
 267        { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
 268
 269        /* JMicron 360/1/3/5/6, match class to avoid IDE function */
 270        { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 271          PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
 272        /* JMicron 362B and 362C have an AHCI function with IDE class code */
 273        { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
 274        { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
 275
 276        /* ATI */
 277        { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
 278        { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
 279        { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
 280        { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
 281        { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
 282        { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
 283        { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
 284
 285        /* AMD */
 286        { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
 287        /* AMD is using RAID class only for ahci controllers */
 288        { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 289          PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
 290
 291        /* VIA */
 292        { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
 293        { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
 294
 295        /* NVIDIA */
 296        { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 },      /* MCP65 */
 297        { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 },      /* MCP65 */
 298        { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 },      /* MCP65 */
 299        { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 },      /* MCP65 */
 300        { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 },      /* MCP65 */
 301        { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 },      /* MCP65 */
 302        { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 },      /* MCP65 */
 303        { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 },      /* MCP65 */
 304        { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 },      /* MCP67 */
 305        { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 },      /* MCP67 */
 306        { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 },      /* MCP67 */
 307        { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 },      /* MCP67 */
 308        { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 },      /* MCP67 */
 309        { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 },      /* MCP67 */
 310        { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 },      /* MCP67 */
 311        { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 },      /* MCP67 */
 312        { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 },      /* MCP67 */
 313        { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 },      /* MCP67 */
 314        { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 },      /* MCP67 */
 315        { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 },      /* MCP67 */
 316        { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux },  /* Linux ID */
 317        { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux },  /* Linux ID */
 318        { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux },  /* Linux ID */
 319        { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux },  /* Linux ID */
 320        { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux },  /* Linux ID */
 321        { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux },  /* Linux ID */
 322        { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux },  /* Linux ID */
 323        { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux },  /* Linux ID */
 324        { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux },  /* Linux ID */
 325        { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux },  /* Linux ID */
 326        { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux },  /* Linux ID */
 327        { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux },  /* Linux ID */
 328        { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux },  /* Linux ID */
 329        { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux },  /* Linux ID */
 330        { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux },  /* Linux ID */
 331        { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux },  /* Linux ID */
 332        { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 },      /* MCP73 */
 333        { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 },      /* MCP73 */
 334        { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 },      /* MCP73 */
 335        { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 },      /* MCP73 */
 336        { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 },      /* MCP73 */
 337        { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 },      /* MCP73 */
 338        { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 },      /* MCP73 */
 339        { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 },      /* MCP73 */
 340        { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 },      /* MCP73 */
 341        { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 },      /* MCP73 */
 342        { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 },      /* MCP73 */
 343        { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 },      /* MCP73 */
 344        { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 },      /* MCP77 */
 345        { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 },      /* MCP77 */
 346        { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 },      /* MCP77 */
 347        { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 },      /* MCP77 */
 348        { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 },      /* MCP77 */
 349        { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 },      /* MCP77 */
 350        { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 },      /* MCP77 */
 351        { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 },      /* MCP77 */
 352        { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 },      /* MCP77 */
 353        { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 },      /* MCP77 */
 354        { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 },      /* MCP77 */
 355        { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 },      /* MCP77 */
 356        { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 },      /* MCP79 */
 357        { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 },      /* MCP79 */
 358        { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 },      /* MCP79 */
 359        { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 },      /* MCP79 */
 360        { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 },      /* MCP79 */
 361        { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 },      /* MCP79 */
 362        { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 },      /* MCP79 */
 363        { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 },      /* MCP79 */
 364        { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 },      /* MCP79 */
 365        { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 },      /* MCP79 */
 366        { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 },      /* MCP79 */
 367        { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 },      /* MCP79 */
 368        { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 },      /* MCP89 */
 369        { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 },      /* MCP89 */
 370        { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 },      /* MCP89 */
 371        { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 },      /* MCP89 */
 372        { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 },      /* MCP89 */
 373        { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 },      /* MCP89 */
 374        { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 },      /* MCP89 */
 375        { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 },      /* MCP89 */
 376        { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 },      /* MCP89 */
 377        { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 },      /* MCP89 */
 378        { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 },      /* MCP89 */
 379        { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 },      /* MCP89 */
 380
 381        /* SiS */
 382        { PCI_VDEVICE(SI, 0x1184), board_ahci },                /* SiS 966 */
 383        { PCI_VDEVICE(SI, 0x1185), board_ahci },                /* SiS 968 */
 384        { PCI_VDEVICE(SI, 0x0186), board_ahci },                /* SiS 968 */
 385
 386        /* ST Microelectronics */
 387        { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci },           /* ST ConneXt */
 388
 389        /* Marvell */
 390        { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv },        /* 6145 */
 391        { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv },        /* 6121 */
 392        { PCI_DEVICE(0x1b4b, 0x9123),
 393          .class = PCI_CLASS_STORAGE_SATA_AHCI,
 394          .class_mask = 0xffffff,
 395          .driver_data = board_ahci_yes_fbs },                  /* 88se9128 */
 396        { PCI_DEVICE(0x1b4b, 0x9125),
 397          .driver_data = board_ahci_yes_fbs },                  /* 88se9125 */
 398        { PCI_DEVICE(0x1b4b, 0x917a),
 399          .driver_data = board_ahci_yes_fbs },                  /* 88se9172 */
 400        { PCI_DEVICE(0x1b4b, 0x9192),
 401          .driver_data = board_ahci_yes_fbs },                  /* 88se9172 on some Gigabyte */
 402        { PCI_DEVICE(0x1b4b, 0x91a3),
 403          .driver_data = board_ahci_yes_fbs },
 404
 405        /* Promise */
 406        { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci },   /* PDC42819 */
 407
 408        /* Asmedia */
 409        { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci },   /* ASM1060 */
 410        { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci },   /* ASM1060 */
 411        { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci },   /* ASM1061 */
 412        { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci },   /* ASM1062 */
 413
 414        /* Enmotus */
 415        { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
 416
 417        /* Generic, PCI class code for AHCI */
 418        { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 419          PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
 420
 421        { }     /* terminate list */
 422};
 423
 424
 425static struct pci_driver ahci_pci_driver = {
 426        .name                   = DRV_NAME,
 427        .id_table               = ahci_pci_tbl,
 428        .probe                  = ahci_init_one,
 429        .remove                 = ata_pci_remove_one,
 430#ifdef CONFIG_PM
 431        .suspend                = ahci_pci_device_suspend,
 432        .resume                 = ahci_pci_device_resume,
 433#endif
 434};
 435
 436#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
 437static int marvell_enable;
 438#else
 439static int marvell_enable = 1;
 440#endif
 441module_param(marvell_enable, int, 0644);
 442MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
 443
 444
 445static void ahci_pci_save_initial_config(struct pci_dev *pdev,
 446                                         struct ahci_host_priv *hpriv)
 447{
 448        unsigned int force_port_map = 0;
 449        unsigned int mask_port_map = 0;
 450
 451        if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
 452                dev_info(&pdev->dev, "JMB361 has only one port\n");
 453                force_port_map = 1;
 454        }
 455
 456        /*
 457         * Temporary Marvell 6145 hack: PATA port presence
 458         * is asserted through the standard AHCI port
 459         * presence register, as bit 4 (counting from 0)
 460         */
 461        if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
 462                if (pdev->device == 0x6121)
 463                        mask_port_map = 0x3;
 464                else
 465                        mask_port_map = 0xf;
 466                dev_info(&pdev->dev,
 467                          "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
 468        }
 469
 470        ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
 471                                 mask_port_map);
 472}
 473
 474static int ahci_pci_reset_controller(struct ata_host *host)
 475{
 476        struct pci_dev *pdev = to_pci_dev(host->dev);
 477
 478        ahci_reset_controller(host);
 479
 480        if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 481                struct ahci_host_priv *hpriv = host->private_data;
 482                u16 tmp16;
 483
 484                /* configure PCS */
 485                pci_read_config_word(pdev, 0x92, &tmp16);
 486                if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
 487                        tmp16 |= hpriv->port_map;
 488                        pci_write_config_word(pdev, 0x92, tmp16);
 489                }
 490        }
 491
 492        return 0;
 493}
 494
 495static void ahci_pci_init_controller(struct ata_host *host)
 496{
 497        struct ahci_host_priv *hpriv = host->private_data;
 498        struct pci_dev *pdev = to_pci_dev(host->dev);
 499        void __iomem *port_mmio;
 500        u32 tmp;
 501        int mv;
 502
 503        if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
 504                if (pdev->device == 0x6121)
 505                        mv = 2;
 506                else
 507                        mv = 4;
 508                port_mmio = __ahci_port_base(host, mv);
 509
 510                writel(0, port_mmio + PORT_IRQ_MASK);
 511
 512                /* clear port IRQ */
 513                tmp = readl(port_mmio + PORT_IRQ_STAT);
 514                VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
 515                if (tmp)
 516                        writel(tmp, port_mmio + PORT_IRQ_STAT);
 517        }
 518
 519        ahci_init_controller(host);
 520}
 521
 522static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
 523                                 unsigned long deadline)
 524{
 525        struct ata_port *ap = link->ap;
 526        bool online;
 527        int rc;
 528
 529        DPRINTK("ENTER\n");
 530
 531        ahci_stop_engine(ap);
 532
 533        rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
 534                                 deadline, &online, NULL);
 535
 536        ahci_start_engine(ap);
 537
 538        DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
 539
 540        /* vt8251 doesn't clear BSY on signature FIS reception,
 541         * request follow-up softreset.
 542         */
 543        return online ? -EAGAIN : rc;
 544}
 545
 546static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
 547                                unsigned long deadline)
 548{
 549        struct ata_port *ap = link->ap;
 550        struct ahci_port_priv *pp = ap->private_data;
 551        u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
 552        struct ata_taskfile tf;
 553        bool online;
 554        int rc;
 555
 556        ahci_stop_engine(ap);
 557
 558        /* clear D2H reception area to properly wait for D2H FIS */
 559        ata_tf_init(link->device, &tf);
 560        tf.command = 0x80;
 561        ata_tf_to_fis(&tf, 0, 0, d2h_fis);
 562
 563        rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
 564                                 deadline, &online, NULL);
 565
 566        ahci_start_engine(ap);
 567
 568        /* The pseudo configuration device on SIMG4726 attached to
 569         * ASUS P5W-DH Deluxe doesn't send signature FIS after
 570         * hardreset if no device is attached to the first downstream
 571         * port && the pseudo device locks up on SRST w/ PMP==0.  To
 572         * work around this, wait for !BSY only briefly.  If BSY isn't
 573         * cleared, perform CLO and proceed to IDENTIFY (achieved by
 574         * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
 575         *
 576         * Wait for two seconds.  Devices attached to downstream port
 577         * which can't process the following IDENTIFY after this will
 578         * have to be reset again.  For most cases, this should
 579         * suffice while making probing snappish enough.
 580         */
 581        if (online) {
 582                rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
 583                                          ahci_check_ready);
 584                if (rc)
 585                        ahci_kick_engine(ap);
 586        }
 587        return rc;
 588}
 589
 590#ifdef CONFIG_PM
 591static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
 592{
 593        struct ata_host *host = dev_get_drvdata(&pdev->dev);
 594        struct ahci_host_priv *hpriv = host->private_data;
 595        void __iomem *mmio = hpriv->mmio;
 596        u32 ctl;
 597
 598        if (mesg.event & PM_EVENT_SUSPEND &&
 599            hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
 600                dev_err(&pdev->dev,
 601                        "BIOS update required for suspend/resume\n");
 602                return -EIO;
 603        }
 604
 605        if (mesg.event & PM_EVENT_SLEEP) {
 606                /* AHCI spec rev1.1 section 8.3.3:
 607                 * Software must disable interrupts prior to requesting a
 608                 * transition of the HBA to D3 state.
 609                 */
 610                ctl = readl(mmio + HOST_CTL);
 611                ctl &= ~HOST_IRQ_EN;
 612                writel(ctl, mmio + HOST_CTL);
 613                readl(mmio + HOST_CTL); /* flush */
 614        }
 615
 616        return ata_pci_device_suspend(pdev, mesg);
 617}
 618
 619static int ahci_pci_device_resume(struct pci_dev *pdev)
 620{
 621        struct ata_host *host = dev_get_drvdata(&pdev->dev);
 622        int rc;
 623
 624        rc = ata_pci_device_do_resume(pdev);
 625        if (rc)
 626                return rc;
 627
 628        if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
 629                rc = ahci_pci_reset_controller(host);
 630                if (rc)
 631                        return rc;
 632
 633                ahci_pci_init_controller(host);
 634        }
 635
 636        ata_host_resume(host);
 637
 638        return 0;
 639}
 640#endif
 641
 642static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
 643{
 644        int rc;
 645
 646        /*
 647         * If the device fixup already set the dma_mask to some non-standard
 648         * value, don't extend it here. This happens on STA2X11, for example.
 649         */
 650        if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
 651                return 0;
 652
 653        if (using_dac &&
 654            !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
 655                rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
 656                if (rc) {
 657                        rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 658                        if (rc) {
 659                                dev_err(&pdev->dev,
 660                                        "64-bit DMA enable failed\n");
 661                                return rc;
 662                        }
 663                }
 664        } else {
 665                rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 666                if (rc) {
 667                        dev_err(&pdev->dev, "32-bit DMA enable failed\n");
 668                        return rc;
 669                }
 670                rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 671                if (rc) {
 672                        dev_err(&pdev->dev,
 673                                "32-bit consistent DMA enable failed\n");
 674                        return rc;
 675                }
 676        }
 677        return 0;
 678}
 679
 680static void ahci_pci_print_info(struct ata_host *host)
 681{
 682        struct pci_dev *pdev = to_pci_dev(host->dev);
 683        u16 cc;
 684        const char *scc_s;
 685
 686        pci_read_config_word(pdev, 0x0a, &cc);
 687        if (cc == PCI_CLASS_STORAGE_IDE)
 688                scc_s = "IDE";
 689        else if (cc == PCI_CLASS_STORAGE_SATA)
 690                scc_s = "SATA";
 691        else if (cc == PCI_CLASS_STORAGE_RAID)
 692                scc_s = "RAID";
 693        else
 694                scc_s = "unknown";
 695
 696        ahci_print_info(host, scc_s);
 697}
 698
 699/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
 700 * hardwired to on-board SIMG 4726.  The chipset is ICH8 and doesn't
 701 * support PMP and the 4726 either directly exports the device
 702 * attached to the first downstream port or acts as a hardware storage
 703 * controller and emulate a single ATA device (can be RAID 0/1 or some
 704 * other configuration).
 705 *
 706 * When there's no device attached to the first downstream port of the
 707 * 4726, "Config Disk" appears, which is a pseudo ATA device to
 708 * configure the 4726.  However, ATA emulation of the device is very
 709 * lame.  It doesn't send signature D2H Reg FIS after the initial
 710 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
 711 *
 712 * The following function works around the problem by always using
 713 * hardreset on the port and not depending on receiving signature FIS
 714 * afterward.  If signature FIS isn't received soon, ATA class is
 715 * assumed without follow-up softreset.
 716 */
 717static void ahci_p5wdh_workaround(struct ata_host *host)
 718{
 719        static struct dmi_system_id sysids[] = {
 720                {
 721                        .ident = "P5W DH Deluxe",
 722                        .matches = {
 723                                DMI_MATCH(DMI_SYS_VENDOR,
 724                                          "ASUSTEK COMPUTER INC"),
 725                                DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
 726                        },
 727                },
 728                { }
 729        };
 730        struct pci_dev *pdev = to_pci_dev(host->dev);
 731
 732        if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
 733            dmi_check_system(sysids)) {
 734                struct ata_port *ap = host->ports[1];
 735
 736                dev_info(&pdev->dev,
 737                         "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
 738
 739                ap->ops = &ahci_p5wdh_ops;
 740                ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
 741        }
 742}
 743
 744/* only some SB600 ahci controllers can do 64bit DMA */
 745static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
 746{
 747        static const struct dmi_system_id sysids[] = {
 748                /*
 749                 * The oldest version known to be broken is 0901 and
 750                 * working is 1501 which was released on 2007-10-26.
 751                 * Enable 64bit DMA on 1501 and anything newer.
 752                 *
 753                 * Please read bko#9412 for more info.
 754                 */
 755                {
 756                        .ident = "ASUS M2A-VM",
 757                        .matches = {
 758                                DMI_MATCH(DMI_BOARD_VENDOR,
 759                                          "ASUSTeK Computer INC."),
 760                                DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
 761                        },
 762                        .driver_data = "20071026",      /* yyyymmdd */
 763                },
 764                /*
 765                 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
 766                 * support 64bit DMA.
 767                 *
 768                 * BIOS versions earlier than 1.5 had the Manufacturer DMI
 769                 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
 770                 * This spelling mistake was fixed in BIOS version 1.5, so
 771                 * 1.5 and later have the Manufacturer as
 772                 * "MICRO-STAR INTERNATIONAL CO.,LTD".
 773                 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
 774                 *
 775                 * BIOS versions earlier than 1.9 had a Board Product Name
 776                 * DMI field of "MS-7376". This was changed to be
 777                 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
 778                 * match on DMI_BOARD_NAME of "MS-7376".
 779                 */
 780                {
 781                        .ident = "MSI K9A2 Platinum",
 782                        .matches = {
 783                                DMI_MATCH(DMI_BOARD_VENDOR,
 784                                          "MICRO-STAR INTER"),
 785                                DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
 786                        },
 787                },
 788                /*
 789                 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
 790                 * 64bit DMA.
 791                 *
 792                 * This board also had the typo mentioned above in the
 793                 * Manufacturer DMI field (fixed in BIOS version 1.5), so
 794                 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
 795                 */
 796                {
 797                        .ident = "MSI K9AGM2",
 798                        .matches = {
 799                                DMI_MATCH(DMI_BOARD_VENDOR,
 800                                          "MICRO-STAR INTER"),
 801                                DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
 802                        },
 803                },
 804                /*
 805                 * All BIOS versions for the Asus M3A support 64bit DMA.
 806                 * (all release versions from 0301 to 1206 were tested)
 807                 */
 808                {
 809                        .ident = "ASUS M3A",
 810                        .matches = {
 811                                DMI_MATCH(DMI_BOARD_VENDOR,
 812                                          "ASUSTeK Computer INC."),
 813                                DMI_MATCH(DMI_BOARD_NAME, "M3A"),
 814                        },
 815                },
 816                { }
 317        vers/ata/ahci.c#L801" id="L801" an chci.c#L815" id="L815" c Did="L761" class="line" na0n>
dmi_system_id sysids[] = {
 741       8static st8uct evend  741       8        {8 735
 732       8         8      .mivers/ata/ahci.811" i.c#L811" id="L811" ="lief="+code=ports" cysida/ahc_811" i.c#L811" id="Lysida/ahc_811" ARD_NAME,  735
bus->number == 0 && pdev-&|_LFLAG_ASSUME_ATAlass="sref">devfn == PCI_DEVFN!0x1f, 2) &&
 735
&quodma_mask( 746{
"drivers/ata/ahci.c#L6falslass="sref">evenfalsl hrene" name="L741"> 741       8        {       },
 741       8 ers/ata/a
("20071026",   ne" name="L746"> 746{
pci_dev 741       8 tatic st8="drivers/ata/ahci.c#L738" id=82="line" name="L680"> 680static 8struct pci_dev"+code=ports" cysidg/a>, class="sref">evendsidg/a>, clARD_NAME, "M3A";
;
;
evend  735
pci_dev"+code=ports" csna>, , , 
evend  735
pd83="line" name="L653"> 653       8    link., "20071026",   n hrefa>-ne" name="L746"> 746{
ata_portpci_dev 741       8="drivers8ata/ahci.c#L736" id="L738" cla83_MATCH" classs="line" name="L665"> 665       8        <8 href="+code=dev_info" c8ass="8ref">dev_info(&PCI_DEewarcARD_Nhref="+code=dev" class="sref">dev,
 737       8         8       &q8ot;enabling ASUS P5W DH Deluxe on-board SIMG4726 workaroun%s:n>

 737       8 
DMI_MATCHma_mask( 735
8p->evenfalsl hrene" name="L741"> 741       8        <8 href="+code=ap" class="8ref">8p-> 317        }
 732       8f="driver8/ata/ahci.c#L743" id="L783" cl8ss="li="+code=PCI_DEVstruct pci_dev 732       8f   PCI_DEewarcARD_Nhref="+code=dev" class="sref">dev,
 735
/* only some SB600 a8ci co84ass="sref">at"drivers/ata/ahci.c#L6trulass="sref">eventrul hrene" name="L741"> 741       8 "drivers8ode=bool" class="sref">b8ol 317        }       <8/ata/ahci.c#L747" id="L787" cl84ci.c#e" name="L741"> 741       8static co8st struct , ahci_sb600_enable_64bi750" ids[]poweroffe_64bit" class=_64bi750" ids[]poweroffARD_N *pdev)
 746{
/*
84s="line" name="L719"> 719       8ass="comm8nt">                 * T8e old84" class="sref">dmi_s>dmi_system_id sysids[] = {
[s="sref">number[sclass="line" name="L748"> 748       8ass="comm8nt">                 * w8rking85" id="L781" class="line" name="L781"> 781       8ass="comm8nt">                 * E8able 85ss="sref">ident = "MSI K9A2 Platinum",
 737       8ass="comm8nt">                 *
85lass="sref">matches = {
 783       8ass="comm8nt">                 * P8ease 85_MATCH" class="sref">DMI_MATCH(DMI_SYS_VENDOR,
 814        ass="comm8nt">                 */<8span>85ass="string">"MICRO-STAR INTER&q href="+code=DMI_SYS_VENDOR" class="sref">DMI_SYS_VENDOR,
"P5W DH Deluxe"),
 814        a"drivers8 816                 8      .ident = .c#L709" 0/1 or somlass="line" name="L808"> 808                 8      .matches = {
"20071026",      (>ahci*)0x1FULne" name="L816"> 816                <8              ine" name="L816"> 816         ss="comm8                        8span 8lass="string">"ASne" name="L783"> 783       8         8              DMI_MATClass="string">"MSI K9A2 Platinum",
 737       8         8      },
 783       8         8      .driver_dataDMI_SYS_VENDOR,
 814                }8
DMI_SYS_VENDOR,
"P5W DH Deluxe"),
 814         ss="comm8pan class="comment">/*
8a href="drivers/ata/ahhhhhhhhhine" name="L816"> 816        ass="comm8nt">                 * A8l BIO86" id="L756" class="liiiiiiiiiivers/ata/ahci.c#L763" idc#L7slot sref">.c#L709" 0/1 or somlass="line" name="L808"> 808        ass="comm8nt">                 * s8pport86ss="sref">ident = &q="string">"20071026",      (>ahci*)0x1FULne" name="L816"> 816        ass="comm8nt">                 *
868" id="L788" class="line" name="L788"> 788       8ass="comm8nt">                 * B8OS ve86="line" name="L739"> 739       8ass="comm8nt">                 * f8elds 86ass="string">"ASn }iiiiiivers/ata/ahci.c#L763" idtermin  808        ass="comm8nt">                 * T8is sp87-> 741       8ass="comm8nt">                 * 185 and87ci.c#L762" id>dmi_system_id sysids[] = {
sysi="lief="+code=ports" cysida/ahc_811" i.c#L811" id="Lysida/ahc_811" ARD_NAME, [s="sref">number[sclas"ne" name="L735"> 735
                 * &8uot;M87="line" name="L653"> 653       8ass="comm8nt">                 * S8 try 87_MATCH" classref="+code=bus" claysi class="sref">sysi="liline" name="L734"> 734       8ass="comm8nt">                 *
87 href="drivers/ata/ahunan>
ed long>"+code=ports" cslotref">link.
ed long)"+code=bus" claysi class="sref">sysi="li href="+code=PCI_DEVF"string">"20071026",   ne" name="L735"> 735
                 * B8OS ve87" id="L756" class="liivers/ata/ahci.c#L763" idapplyL709"quirkspan>
39;t
/ata/ahci.c#lass="line" name="L808"> 808        ass="comm8nt">                 * D8I fie87ss="sref">ident ="drivers/ata/ahci.c#L6slotref">link., devfn == PCI_DEVFN 735
                 * &8uot;K87L815" id="L815e" name="L735"> 735
                 * m8tch o87="line" name="L739"> 739       8ass="comm8nt">                 */<8span>87ass="string">"drivers/ata/ahci.c#L6falslass="sref">evenfalsl hrene" name="L741"> 741       8        {8 735
 732       8         8      ., ahci_sb600_enable_64bi750" idsusers/e_64bit" class=_64bi750" idsusers/ARD_N *pdev)
 746{
 734       8         8                        8span 8lass="string">="sref">dmi_system_id sysids[] = {
 748       8         8              ci.c#L805" id="L805" class="line" name="L805"> 805
 805
 805/*
88DMI_BOARD_NAME of "MS-7376".
resumspan>ta/aSTR.  Waverers/fail susers/ass="line" name="L806"> 806                 * A8l BIO8 versions for the MSI K9AGM2 (MS-7327) supportss="line" name="L806"> 806                 * 68bit D8A.
 806                 *
8a href="drivers/ata/ahci.c#L792" id="L792" class="line" name="L792"> 792                 * T8is bo8rd also had the typo mentioned above in the 715                 * M8nufac8urer DMI field (fixed in BIOS version 1.5), so
recycquot;boahep="L776"ers/"driverss="line" name="L715"> 715                 * m8tch o8 DMI_BOARD_VENDOR of "MICRO-STAR INTER&quovers/alass="line" name="L711"> 711                 */<8span>8 711 711 808                 8      .matches 748       8         8              DMI_MATClass="string">"MSI K9A2 Platinum",
 737       9         9                        9span 9lass="string">"MICRO-STARa href="drivers/ata/ahci.c#L783" id="L783" class="line" name="L783"> 783       9         9              DMI_MATCH(DMI_BOARD_NAME,  814       9         9      },
DMI_BOARD_NAME, "P5W DH Deluxe")e" name="L814"> 814       9 3       9 t">                 * M9i.c#L904" id="L804" class="lid="L803" class="lH( 725       9        <9pan class="comment">/*
9a href="drivers/ata/ahhhhhhhhhine" name="L788"> 788       9ass="comm9nt">                 * A9l BIO90" id="L756" class="liiiiiiiiia> = "20071026",      /* yyyym9I_05/
 808       9ass="comm9nt">                 * (9ll re90ss="sref">ident =ine" name="L788"> 788       9a7s="comm9n     . 783       9 8s="comm9n     . 737       9 9s="comm9n             ident = &qata/ahci.c#L783" id="L783" class="line" name="L783"> 783       9         9      .matches = {
<<<<<<<<< href="+code=DMI_BOARD_NAME" class="sref">DMI_BOARD_NAME,  814       9         9              DMI_MATCH(DMI_BOARD_VENDOR,
"P5W DH Deluxe")e" name="L814"> 814       9         9                        9span 9lass="string">"ASUSTeK Computer INC."),
 725       9         9              DMI_MATCine" name="L788"> 788       9         9      },
"20071026",      /* yyyym9I50*/
 808       9        }9
 816       9        {9}
 816       9 7s="comm9hci.c#L801" id="L801" an9chci.91ss="sref">ident = "MSI K9AGM2",
 737       9>
 783       9 9s="comm9uct DMI_MATCH(DMI_BOARD_VENDOR,
 814       9        {9matches = {
<<<<<<<<< href="+code=DMI_BOARD_NAME" class="sref">DMI_BOARD_NAME, "P5W DH Deluxe")e" name="L814"> 814       9         9      .DMI_MATCH(),
 725       9         9      . 803       9         9              DMI_MATCa> = "20071026",      /* yyyym9I423/
 808       9         9                        9span 9lass="string">&quos="line" name="L803"> 803       9        }9              ne" name="L783"> 783       9        {9      },
ident = "ASUS M2A-VM",
 737       9 ers/ata/9
matches = {
 758       9 
DMI_BOARD_VENDOR,
 814       9 9s="comm9="drivers/ata/ahci.c#L739" id=92_MATCH" class="sref">DMI_MATCH(DMI_BOARD_VENDOR,
"P5W DH Deluxe")e" name="L814"> 814       9struct "MICRO-STAR INTER"),
 725       9="drivers9ata/ahci.c#L732" id="L739" cla93ci.c#L762" id="L762" class="line" name="L762"> 762       9=        9f="+code=pdev" class="sr9f">pd93a" class="sref">driver_data = "20071026",      /* yyyym9I430/
 808       9     804       9        s9ruct ata_port 805
 805 805&q932 Platinum (MS-7376)" in version 1.9, but>
etween,ns/are are V1.06, V2.06"ers/V3.03ss="line" name="L805"> 805
tha id="dopan>
 80593versions for the MSI K9AGM2 (MS-7327) support 71194.
 711 711 808       9f    758       9ass="comm9nt">/* only some SB600 a9ci co94ci.c#L815" id="L815" class="la> = ,
 737       9 "drivers9ode=bool" class="sref">b9ol 758       9}       <9/ata/ahci.c#L747" id="L797" cl94ss="sref">ident = DMI_BOARD_VENDOR,
 725       9static co9st struct DMI_BOARD_VENDOR,
"P5W DH Deluxe"),
 725       9s
/*
9429" id="L729" class="""""""""ine" name="L804"> 804       9ass="comm9nt">                 * T9e old94ss="sref">ident = &q="string">"20071026",      /* yyyym9121*/
 808       9ass="comm9nt">                 * w9rking95" id="L781" class="liine" name="L804"> 804       9ass="comm9nt">                 * E9able 95ss="sref">ident =n }iiiiiivers/ata/ahci.c#L763" idtermin  808       9ass="comm9nt">                 *
95lass="sref">mnne" name="L741"> 741       9ass="comm9nt">                 * P9ease 95_MATCH" class>dmi_system_id sysids[] = {
sysi="lief="+code=ports" cysida/ahc_811" i.c#L811" id="Lysida/ahc_811" ARD_NAME,  735
                 */<9span>95ass="string">ivers/ata/ahci.c#L6yeade=pdev" class="yeadhref="dvers/ata/ahci.8ont i.c#L811" id="L8ont href="dvers/ata/ahci.d class="sref">evend  741       9a"drivers9 735
 741       9         9      .sysi="lie|_LFLAG_ASSUME_ATAlass="sref">devfn == number == 0 && pdev<|_LFLAG_ASSUME_ATAlass="sref">devfn == PCI_DEVFN!0x1f, 2) &&
 746{
"drivers/ata/ahci.c#L6falslass="sref">evenfalsl hrene" name="L741"> 741       9 ss="comm9                        9span 95="line" name="L680"> 680static 9         9              pci_dev"+code=ports" cysidg/a>, class="sref">evendsidg/a>, clARD_NAME, "M3A";
;
;
evend  735
, , , 
evend  735
 653       9        }9
link., sysi="li href="+code=PCI_DEVF"string">"20071026",   ) < 0ne" name="L735"> 735
/*
9a href5e" name="L735"> 735
                 * A9l BIO96" id=e" name="L735"> 735
                 * s9pport96ss="s="sref"AME, ahci_sb600_enable_64bi750" idpanivee_64bit" class=_64bi750" idpaniveARD_N *pdev)
 746{
                 *
968" idne" name="L758"> 758       9ass="comm9nt">                 * B9OS ve96="lin#defiveAivers/ata/ahci.ENCODE_BUSa href="drivers/ata/ENCODE_BUSa hreARD_NAME, number == , ma_mask(link.(evenfunc,   )                        \e" name="L758"> 758       9ass="comm9nt">                 * f9elds 96ass="string">(>ahci*)(unan>
ed long)((NAME, number == ) << 8) _LFLAG_ASSUME_ATAp;
, link.evenfunc,   ))ne" name="L746"> 746{
                 * T9is sp97->dmi_system_id sysids[] = {
 748       9ass="comm9nt">                 * 195 and97ss="sref">ident =ci.c#L805" id="L805" class="line" name="L805"> 805                 * &9uot;M97d also had the typo mentioned above in the al gigabyte 793                 * S9 try 97rer DMI field (fixed in BIOS version 1.5), sodmfigur" idstgnatware RAID.  Certairss="line" name="L715"> 715                 *
97DMI_BOARD_VENDOR of "MICRO-STAR INTER&quo5723 firmware reviivers/shippedns/are keeprs/atli 805                 * B9OS ve97versions for the Asus M3A support 64bit DMA. 805                 * D9I fie97ase versions from 0301 to 1206 were tested) 805                 * &9uot;K972 Platinum (MS-7376)" in version 1.9, butcaus"L75lib5 805                 * m9tch o97DMI_BOARD_NAME of "MS-7376".
to excess5"> astectd="Ldelayass="line" name="L711"> 711                 */<9span>97versions for the MSI K9AGM2 (MS-7327) supportss="line" name="L806"> 806 806
dmiidei.c# unata/ass="line" name="L806"> 806idstoffniveA>
 711 808       9         9                        9span 98ci.c#L815" id="L815" ne" name="L748"> 748       9         9              >>>>>>>>a> = ,
 737       9         9      },
ident = &qata/ahci.c#L758" id="L758" class="line" name="L758"> 758       9 ss="comm9
DMI_BOARD_VENDOR,
 812       9 ss="comm9pan class="comment">/*
9829" id="L729" class="""""""""""""""""xe ccccccc href="drivers/ata/ahci.c#LGigabyte 813       9ass="comm9nt">                 * A9l BIO98_MATCH" class="sref">DMI_MATCH(DMI_BOARD_VENDOR,
"M3A"),
 813       9ass="comm9nt">                 * 69bit D99ass="string">"MICRO-STARine" name="L804"> 804       9a        9nt">                 *
99ci.c#L762" id="L762" class="la href="drivers/="string">"20071026",       804       9ass="comm9nt">                 * T9is bo99a" class="sref">driveine" name="L804"> 804       9a        9nt">                 * M9nufac994" id="L804" class="lne" name="L758"> 758       9a        9nt">                 * m9tch o99ci.c#L815" id="L815" class="la> = ,
 737       9ass="comm9nt">                 */<9span>99" id="L756" class="liiiiiiiiia> =  758       9a        9ident = DMI_BOARD_VENDORf="drivers/ata/ahci.c#L812" id="L812" class="line" name="L812"> 812    n c8ass="9omm8      . 813             9   8      .match>ident = DMI_BOARD_VENDORf="string">"M3A"),
 725       8     9   8              DMI_riveine" name="L804"> 804   10   9     10   9              10  
99ci.c#L762" id="L762" class="la href="drivers/="string">"20071026",      eine" name="L804"> 804   10 1 9     10   9nt">                10   >10 >
99ci.c#L762" id="L7riveine" name="L804"> 804   10 2 9     10 mm9nt">                10 mm>10 bo99a" class="sref">da> =n }iiiiiivers/ata/ahci.c#L763" idtermin  808   10 3 9     10   9nt">                10   >10 ac994" id="L8f">mnne" name="L741"> 741   10 4 9     10 ac994" id="L804" class=10 ac>10 line"W"aref      741   10 5 9     10 mm9nt">                10 mm>10 L796" id="L756ass>dmi_system_id sysids[] = {
sysi="lief="+code=ports" cysida/ahc_811" i.c#L811" id="Lysida/ahc_811" ARD_NAME,  735
  10 6 9     10   9ng">ivers/ata/ahci.va nable_64bit" clva alsl hrene" name="L741"> 741   10 7 9     10 mm8      . 741   10 8 9     10   8      .(sysi  ))ne" name="L746"> 746{
<10 9 9     10   8              10 ">8p->evenfalsl hrene" name="L741"> 741   101  9     10   9      . 741   1011 9     10   9              10 a/961>pci_dev"+code=portva nable_64bit" clva alsl,      (unan>
ed long)"+code=bus" claysi class="sref">sysi="li href="+code=PCI_DEVF"string">"20071026",   ne" name="L735"> 735
10 _d96="line" name="L653"> 653   10 3 9     10   9              10 #L964" id="L764" "drivers/ata/ahci._ATAlass="sref">devfn == number == 0 && p==  )="NAME, devfn == PCI_DEVFN==  )="NAME,  735
  1014 9     10   9      },
 735
 735
 735
(>">ahci_sb600_enable_gtfLysl" i_iveA 7_hosuot;ASUS M2A-VM&> 7_hosu[] = {
 746{
<1018 9     10ref9"drivers/ata/ahci.c#10ref>10 >
84s="line" name="L719"> 719   10 9 9     10omm9uct dmi_s>dmi_system_id sysids[] = {
 748   102  9     10  {9ident =ci.c#L805" id="L805" class="line" name="L805"> 805 715ngclu lea so /aheinvaopaninvaopanres wh HP.lass="line" name="L715"> 71510 y 97rer DMI field (fixed in BIOS version 1.5),rejectan>bapplyLlhcias.  Amed ltversuco exfulaopaHP.lass="line" name="L715"> 71510 >
97DMI_BOARD_VENDOR of "MICRO-STAR INTERis FPDMA non-zero>idsdtre;s:nd#Lres whIFY w;s:nd#dP.lass="line" name="L715"> 71510 ve97versions for the Asus M3A support 64bit DMA.dmimes iversNCQL70mmandP.lass="line" name="L715"> 715 715 808   10 8 9     10ref9}
matches 748   10 9 9     10omm9="drivers/ata/ahci.c10omm>10 =D8I_MATCH" class="sref">DMI_MATClass="string">"MSI K9A2 Platinum",
 737   103  9     10 10 <>99" id="L756" class="liiiiiiiiia> =  758   10 1 9     10ers9ata/ahci.c#L732" id=10ers>10 =D9I_MATCH" class="sref">DMI_MATCH(DMI_BOARD_NAME,  725   10 2 9     10   9f="+code=pdev" class10   >10 a/9hci.c#L803" id="L803" class="lH(DMI_BOARD_NAME, "P5W DH Deluxe",
 725   10 3 9     10 hr9f="+code=dmi_check_s10 hr>10 =D9I_MATCH" class="sref">DMI_MATCine" name="L788"> 788   10 4 9     10  s9ruct "20071026",  ng">(>ah="la> =  812   10 5 9     10ers9ata/ahci.c#L736" id=10ers>10 #L916" id="L816" class="line" name="L816"> 816   10 6 9     10  {9 href="+code=dev_inf10  {>10 c#9817" id="L817" clas="L815e" name="L735"> 735
 735
  1038 9     10ref9ata/ahci.c#L739" id=10ref>10 s"8class="sre6ass>dmi_system_id sysids[] = {
sysi="lief="+code=ports" cysida/ahc_811" i.c#L811" id="Lysida/ahc_811" ARD_NAME,  735
  1039 9     10omm9 href="+code=ap" cla10omm>10 =D8I_MATCH" ci*)(unan>ng">ivers/ata/ahci.ysl" ialslass="sref">esl" ipan>,   ne" name="L735"> 735
10  "8class="sreeg">ivers/ata/ahci.i.ysi class="sreipan>,   ne" name="L735"> 735
10  c88="line" name="L732"> 732   10 2 9     10   9/ata/ahci.c#L743" id10   >10 a/9hci.c#L803ef="+coddma_mask(sysi  ))ne" name="L746"> 746{
<1043 9     10 hr9ata/ahci.c#L744" id=10 hr>10 =D9I_MATCH" class="sr64" "d,   ne" name="L735"> 735
/* only some SB610omm>10 4c88="line" name="L732"> 732   10 5 9     10ers9ode=bool" class="sre10ers>10 #L916" id="L8ivers/ata/ahci.ysl" ialslass="sref">esl" ipan>,      (unan>
ed long)"+code=bus" claysi class="sref">sysi="li href="+code=PCI_DEVF"string">"20071026",   ne" name="L735"> 735
10 6L916" id="L8ivers/ata/ahci.lhc_infoN" class="sref">PC_info11" ARD_NAME, PC;,
esl" i 0x;02d&x for ;02d&s\n-DSa738" class="lne" name="L737"> 737   1047 9     10 co9st struct esl" ipan>clas, ma_mask(sysi="li href="+code=PCI">"MSI K9A2 Platinum&quoass="ne" name="L735"> 735
  1048 9     10ref9pan class="comment">10ref>10  o87="line" name="L739"> 739   10 9 9     10omm9nt">                10omm>10 =D8I_MATCH" cfor ARD_NAME, ,<&RD_NAME, ,v<|_LFLAG_ASSUMEi.ysi class="sreipan>++="liline" name="L734"> 734   105  9     10omm9nt">                10omm>10omL98t;enabling ASUS PRD_N *link[<|_LFLAG_ASSUMEi.ysi class="sreipan>ass9ine" name="L735"> 735
                10omm>10o=D9I_MATCH" class="srRD_N * 735
                10omm>10oa/9hci.c#L803" id="L8RD_N *PC; 735
                10omm>10o3o87="line" name="L739"> 739   1054 9     10omm9nt">                10omm>10o" 9lass="sref">ata_por href="+code=p> 7_for_each_s/atot;ASUS M2A-VM&> 7_for_each_s/at11" ARD_NAME, acicmsref">linkEDGstring">"P5EDGssysi  ))ne" name="L746"> 746{
<1055 9     10ers9 7_for_each_hDEN" class="sref"> 7_for_each_hDE11" ARD_NAME, PC;, ALLSLOATA_LFLAG_ASALLsysi  ))ne" name="L746"> 746{
<1056 9     10   9      .ident = PC;esl" ipan>,   ne" name="L735"> 735
 735
10o8
9a href5e" name="L735"> 735
10o=D8I_#elseref5e" name="L735"> 735
10  s84class="s<|_LFLAG_ASSUMEi idpanivee_64bit" cli idpanivesg">(>">ahci_sb600_enable_gtfLysl" i_iveA 7_hosuot;ASUS M2A-VM&> 7_hosu[] = {
 746{
<1061 9     10   9      },
 735
 735
 739   1064 9     10omm9pan class="comment">10omm>10 4s84class="seg">ivers/ata/ahci.ass=_init_opanivee_64bit" class=_init_opaniveARD_N *pdev)
dmi_system_id )
 739   1065 9     10omm9nt">                10omm>10 5
84s="line" name="L719"> 719   1066 9     10   9nt">                10   >10 a.9997" cl94si*)(unan>ng">ivers/ata/ahci.yte"20071026",   ne" name="L735"> 735
                10omm>10 ;K87L815" id=RD_N * 7_port_info[] = {
sysi="lief="+code=portass=_port_infoN" class="sref">ss=_port_infopan>[<|_LFLAG_ASSUMEyte 735
                10omm>10 s"8class="sre6ass>dmi_system_id  7_port_infoN" class="sref"> 7_port_info[] = f="drivers/ata/ahpi.ysi class="srepp>sysiclass=ref="5wdh_ops;
 735
  1069 9     10omm9nt">                10omm>10 9K87L815" id=RD_N *PC;;
devfn == PC; 735
                10omm>10omK87L815" id=RD_N *ss=_hosu_p="L[] = {
 735
                10omm>10o1K87L815" id=RD_N * 735
                10omm>10oa/9hci.c#L803eg">ivers/ata/ahci.n_port/ahci.c#L734" idn_port/pan>clas, ma_maski.ysi class="sreipan>clas, ma_maskr funcass="sref">rc[] =ss9ine" name="L735"> 735
                10omm>10o3/9hci.c#L803eg">ivers/ata/ahci.>ss=_ps=_6L6yeade=pdev" cla>ss=_ps=_6L6sysi="lief="+code=portAHCI_ata/BAR_STANDARDSLOATA_LFLAG_ASAHCI_ata/BAR_STANDARD[] =ss9ine" name="L735"> 735
                10omm>10o4c88="line" name="L732"> 732   1075 9     10omm9nt">                10omm>10o#L916" id="L8ivers/ata/ahci.VPRINTKSLOATA_LFLAG_ASVPRINTK11" ARf="drivers/ata/ahci.c#L814"NTER\n-DSa738" clasass="ne" name="L735"> 735
  1076 9     10omm9nt">                10omm>10o c95ci.c#e" name="L741"> 741   10o7 9     10omm9nt">                10omm>10o7L916" id="L8ivers/ata/ahci.WARN_Oa href="drivers/WARN_Oa11" A(eg"h="la> = "P5ATA_MAX_QUEUspan>,>&RD_NAME,  735
  1078 9     10omm9nt">                10omm>10o o87="line" name="L739"> 739   1079 9     10omm9nt">                10omm>10o9L916" id="L8ivers/ata/ahci.> 7_p=sna_L739io50" asot;ASUS M2A-VM&> 7_p=sna_L739io50" as11" Aef="5wdh_ops;
devfn == PC;DRV_VERSIOa href="drivers/DRV_VERSIOa&quoass="ne" name="L735"> 735
  108  9     10  {9 739   1081 9     10omm9      . 808   1082 9     10omm9      .makersurh usass="line" name="L793"> 79310 y 97rer DMI field (fixed in BIOS versiAHCILlasys aid_/ahen, way08" class="line" name="L808"> 808   1084 9     10   9                    10   >10 n>95ass="strinf ARD_NAME, devfn == ,&f="5ef="5v+coddma_maskmarvell_;s:nd#SLOATA_LFLAG_ASmarvell_;s:nd#&quoa"line" name="L739"> 739   1085 9     10   9              10 n>99" id="L756" class64" "dr-as, ma_maskENODEVtring">"P5ENODEV[] =ss9ine" name="L735"> 735
 741   1087 9     10omm9
 808   1088 9     10omm9pan class="comment">10omm>10  o97DMI_BOARD_NAME of "MS-7376&*ut. esommwarason, MCP89MA.pMacBote"7,1 does="dopan>iveAref=" class="line" name="L808"> 808   1089 9     10omm9nt">                10omm>10 n>97versions for the MSI K9AGM2 (MS-* 8 7_gener="segstead=P.lass="line" name="L715"> 715                10omm>10om>97versions for the MSI K9AGM2 (MS-*" class="line" name="L808"> 808   1091 9     10   9nt">                10   >10o1>95ass="strinf ARD_NAME, devfn == ,&f="5ef="5"line" name="L808"> 808   1092 9     10omm9nt">                10omm>10oa/9hci.c#L803" idwdh_ops;
devfn == !0x1f, 2) &&amDEVICE_ID_NVIDIA_NFORCE_MCP89_SATASLOATA_LFLAG_AS;&amDEVICE_ID_NVIDIA_NFORCE_MCP89_SATApan>,&f="5ef="5"line" name="L808"> 808   1093 9     10   9nt">                10   >10o=D9I_MATCH" classwdh_ops;
devfn == "P5;&am724" c_ID_APPLspan>,&f="5ef="5"line" name="L808"> 808   1094 9     10   9nt">                10   >10o" 9lass="sref">atwdh_ops;
devfn ==  739   1095 9     10omm9nt">                10omm>10on>99" id="L756" class64" "dr-as, ma_maskENODEVtring">"P5ENODEV[] =ss9ine" name="L735"> 735
 741   1097 9     10omm8      . 715 71510on>97versions for the MSI K9AGM2 (MS-* revtGfor SAS7l="L7id=Asy"dopare aid_/ahluck=P.lass="line" name="L715"> 715110m>97versions for the MSI K9AGM2 (MS-*" class="line" name="L808"> 808   11 1 9     11   9nt">                11   >1101>95ass="strinf ARD_NAME, devfn == "P5;&am724" c_ID_PROMISs&quoa"line" name="L739"> 739   11 2 9     11 mm9nt">                11 mm>11 bo99a" class="sref">dhref="+code=PCI_DE_infoN" class="sref">PC_info11" Aef="5wdh_ops;
devfn == PC; 739   11 3 9     11   9nt">                11   >110=D9I_MATCH" class="sref">DMI_,
 735
  11 4 9     11 ac994" id="L804" class=11 ac>1104c88="line" name="L732"> 732   11 5 9     11 mm9nt">                11 mm>11 L796" id="L75 808   11 6 9     11   9, devfn == "P5;&am724" c_ID_STMICROpan>,&f="5ef="5vwdh_ops;
devfn ==  739   11 7 9     11 mm8      .ss=_ps=_6L6sysi="lief="+code=portAHCI_ata/BAR_STA2X   9       LAG_ASAHCI_ata/BAR_STA2X  [] =ss9ine" name="L735"> 735
devfn == devfn ==  739   11 9 9     11   8              11 ">8p->ss=_ps=_6L6yeade=pdev" cla>ss=_ps=_6L6sysi="lief="+code=portAHCI_ata/BAR_ENMOTUSSLOATA_LFLAG_ASAHCI_ata/BAR_ENMOTUS[] =ss9ine" name="L735"> 735
 741   1111 9     11   9              111a/961>pci_dev 808   11 2 9     11   9                    11   >111bo99a" class=as, ma_maskr funcass="sref">rc[] =="lief="+code=portps=m_;s:nd#/_DEiasot;ASUS M2A-VM&ps=m_;s:nd#/_DEias11" ARdh_ops;
devfn =ass="ne" name="L735"> 735
  11 3 9     11   9              11 #L964" id="L7nf ARD_NAME, rc[] =a"line" name="L739"> 739   1114 9     11   9      },
ata_po64" "drivers/ata/ahci.r funcass="sref">rc[] =ss9ine" name="L735"> 735
 735
 715 715111 o97DMI_BOARD_NAME of "MS-7376&*" class="line" name="L808"> 808   11 9 9     11omm9uct rc[] =="lief="+code=portps=m_iomap_regevii_request_allot;ASUS M2A-VM&ps=m_iomap_regevii_request_all11" ARdh_ops;
devfn =, 1== ) <&ivers/ata/ahci.>ss=_ps=_6L6yeade=pdev" cla>ss=_ps=_6L6sysiclas, ma_maskDRV_s="string">"P5WRV_s="sa> =ass="ne" name="L735"> 735
  112  9     11  {9, rc[] = "/a-as, ma_maskEBUSYtring">"P5EBUSY[] =a"line" name="L739"> 739   11 1 9     11   9      .ident;
devfn =ass="ne" name="L735"> 735
  11 2 9     11   9      ., rc[] =a"line" name="L739"> 739   11 3 9     11   9              112=D9I_MATCH" class="sr64" "drivers/ata/ahci.r funcass="sref">rc[] =ss9ine" name="L735"> 735
1124c88="line" name="L732"> 732   11 5 9     11  }9              1125/9hci.c#L803ef="RD_NAME, devfn == ,&f="5ef="5"line" name="L808"> 808   11 6 9     11  {9      },
, devfn == devfn ==  734   11 7 9     11ta/9
macicmsref">link 808   11 8 9     11ref9}
 739   11 9 9     11omm9="drivers/ata/ahci.c11omm>11 =D8I_MATCH" class="sr 808   113  9     11 113L798.
 715113 c98ater have the Manufacturer as
m 715113s"98d also had the typo mentioned above in th" class="line" name="L808"> 808   11 3 9     11 hr9f="+code=dmi_check_s11 hr>11 =D9I_MATCH" class="sraef="+code=portps=_read_23s">d_Gigaot;ASUS M2A-VM&ps=_read_23s">d_Giga11" ARdh_ops;
devfn =, Rdh_ops;
devICH_MAPa> =, ef="5wdh_ops;
link 735
  11 4 9     11  s9ruct , link 734   11 5 9     11ers9ata/ahci.c#L736" id=11ers>11 #L916" id="L816" claslass="sraef="+code=port_DE_infoN" class="sref">PC_info11" Aef="5wdh_ops;
devfn == PC; 739   11 6 9     11  {9 href="+code=dev_inf11  {>11 c#9817" id="L817" cla816" claslass="sraspan>,
;s:nd#LAHCILm 735
  11 7 9     11ta/9       ENODEVtring">"P5ENODEV[] =ss9ine" name="L735"> 735
113s"8class="sref">matchhref5e" name="L735"> 735
11 =D8I_MATCH" chref5e" name="L735"> 735
114  hre>mnne" name="L741"> 741   1141 9     11ers9"drivers/ata/ahci.c#11ers>114a/961>pci_dev"+code=porthp="LN" class="sref"hp="L[] =="lief="+code=portsevm_kzallo funcass="sref">sevm_kzallo 11" ARdh_ops;
PC; 735
  11 2 9     11   9/ata/ahci.c#L743" id11   >11 a/9hci.c#L803ef="+coddma_maskhp="LN" class="sref"hp="L[] =)s="ne" name="L735"> 735
  11 3 9     11 hr9ata/ahci.c#L744" id=11 hr>11 =D9I_MATCH" class="sr64" "dr-as, ma_maskENOMEMtring">"P5ENOMEM[] =ss9ine" name="L735"> 735
/* only some SB611omm>1144/961>pci_dev"+code=porthp="LN" class="sref"hp="L[] == |      (unan>
ed long)"+code=bus"pi.ysi class="srep>sysis="la> = "200710p="Latastrin[] =ss9ine" name="L735"> 735
 735
1146/961>pci_devdo MSIth" class="line" name="L808"> 808   1147 9     11 co9st struct ,    s="sreytess=_mcpompan>,&f="5ef="5"line" name="L808"> 808   1148 9     11ref9pan class="comment">11ref>114s"8class="sref">m"RD_NAME, devfn == rre revi[] = "/a0xa1pdev<|_LFLAG_ASSUME_ATAlass="sref">devfn == rre revi[] = "/a0xa2))s="ne" name="L735"> 735
  11 9 9     11omm9nt">                11omm>114">8p->|  ief="+code=portAHCI_HFLAG_NO_MSISLOATA_LFLAG_ASAHCI_HFLAG_NO_MSI[] =ss9ine" name="L735"> 735
                11omm>115  hre>mnne" name="L741"> 741   11o1 9     11omm9nt">                11omm>115a/961>pci_dev 808   11o2 9     11omm9nt">                11omm>115a/9hci.c#L803ef="RD_NAME, ss=_sb7  pan>,&f="5ef="5vwdh_ops;
devfn == rre revi[] =   739   11o3 9     11omm9nt">                11omm>115=D9I_MATCH" class="sraef="+code=porthp="LN" class="sref"hp="L[] == ef="5= ~ief="+code=portAHCI_HFLAG_IGN_SERR_INTERNALSLOATA_LFLAG_ASAHCI_HFLAG_IGN_SERR_INTERNAL[] =ss9ine" name="L735"> 735
                11omm>1154c88="line" name="L732"> 732   1155 9     11ers9 808   11o6 9     11   9      ., ss=_sb600_;s:nd#/64bityeade=pdev" cla>ss=_sb600_;s:nd#/64bit11" ARdh_ops;
devfn =aa"line" name="L739"> 739   11o7 9     11   9      .ef="5= ~ief="+code=portAHCI_HFLAG_32BIT_ONLYtring">"P5AHCI_HFLAG_32BIT_ONLY[] =ss9ine" name="L735"> 735
115 o87="line" name="L739"> 739   1159 9     11omm9                    11omm>1159.9997" cl94snf AARD_NAME, ef="5 ief="+code=portAHCI_HFLAG_NO_MSISLOATA_LFLAG_ASAHCI_HFLAG_NO_MSI[] =)pdev<|_LFLAG_ASSUME_s=_;s:nd#/msi.ysi class="sreps=_;s:nd#/msi11" ARdh_ops;
devfn =aa"line" name="L739"> 739   116  9     11   9              116 d97ss="sref">ident;
devfn =, 1ass="ne" name="L735"> 735
  1161 9     11   9      },
 732   1162 9     11   9      .hp="LN" class="sref"hp="L[] == ;
devfn =a[<|_LFLAG_ASSUME>ss=_ps=_6L6yeade=pdev" cla>ss=_ps=_6L6sysiass9ine" name="L735"> 735
 739   1164 9     11omm9pan class="comment">11omm>1164796" id="L75d h" class="line" name="L808"> 808   1165 9     11omm9nt">                11omm>116#L916" id="L8ivers/ata/ahci.>ss=_ps=_sav#_initial_23s">dyeade=pdev" cla>ss=_ps=_sav#_initial_23s">d11" ARdh_ops;
devfn =, Rdh_ops;
 735
                11   >116 c95ci.c#e" name="L741"> 741   1167 9     11omm9nt">                11omm>1167/961>pci_dev 808   1168 9     11omm9nt">                11omm>116s"8class="sreef="as, ma_maskhp="LN" class="sref"hp="L[] == linklink 734   1169 9     11omm9nt">                11omm>116">8p-> = |  ief="+code=portATA_FLAG_NCQicmsref">link 735
                11omm>117 d97ss="sref">ident =ci.c#L805" id="L805" class="line" name="L805"> 805                11omm>117 c98ater have the Manufacturer as
 793                11omm>117s"98d also had the typo mentioned above in thesupportan>vi all AHCILcontroll5 n>indicatlea NCQ[]sass="line" name="L793"> 793                11omm>117y 97rer DMI field (fixed in BIOS version 1.5),capability, but it seemspondbh brokeivA.Msomm[]sass="line" name="L793"> 793                11omm>117>
97DMI_BOARD_VENDOR of "MICRO-STAR INTERchipsets>ngclu lea NVIDIAs=P.lass="line" name="L715"> 715                11omm>117ve97versions for the Asus M3A support 64bit D" class="line" name="L808"> 808   1176 9     11omm9nt">                11omm>117c#9817" id="L817" claef="+ARD_NAME, ef="5 ief="+code=portAHCI_HFLAG_NO_FPDMA_AASLOATA_LFLAG_ASAHCI_HFLAG_NO_FPDMA_AAa> =aa"line" name="L739"> 739   11o7 9     11omm9nt">                11omm>117#L98t;enabling ASUS P5W DH Deivers/ata/ahci.pi.ysi class="srep>sysis="la> = |  ief="+code=portATA_FLAG_FPDMA_AASLOATA_LFLAG_ASATA_FLAG_FPDMA_AA[] =ss9ine" name="L735"> 735
                11omm>117s"8class="srehref5e" name="L735"> 735
                11omm>11o9L916ref5e" name="L735"> 735
, linkdevHOST_CAP_PMP[] =)s="ne" name="L735"> 735
  1181 9     11omm9      .ident = |  ief="+code=portATA_FLAG_PMPlass="sref">devATA_FLAG_PMP[] =ss9ine" name="L735"> 735
 653   11 3 9     11   9              118=D9I_MATCH" cRD_NAME, ss=_set_em_messagta/ahci.c#L758" i>ss=_set_em_messagta11" ARdh_ops;
;
 735
1184c88="line" name="L732"> 732   1185 9     11   9              1185/9hci.c#L803ef="RD_NAME, ss=_brokeisysidsss=_brokeisysids;
devfn =aapliline" name="L734"> 734   1186 9     11   9      },
 = |  ief="+code=portATA_FLAG_NO_POWEROFF_SPINDOWa href="drivers/ATA_FLAG_NO_POWEROFF_SPINDOWa[] =ss9ine" name="L735"> 735
PC_info11" Aef="5wdh_ops;
devfn == PC; 739   1188 9     11omm9pan class="comment">11omm>118s"8class="sref">matchg ASUS Pispan>,
 735
  1189 9     11omm9nt">                11omm>118=D8I_MATCH" chref5e" name="L735"> 735
                11omm>119  hre>mnne" name="L741"> 741   1191 9     11   9nt">                11   >11o1>95ass="strinf ARD_NAME, ss=_brokeisyuspearnivee_64bit" class=_brokeisyuspear11" ARdh_ops;
devfn =aapliline" name="L734"> 734   1192 9     11omm9nt">                11omm>11oa/9hci.c#L803" idUS Pivers/ata/ahci.hp="LN" class="sref"hp="L[] == |  ief="+code=portAHCI_HFLAG_NO_SUSPENDSLOATA_LFLAG_ASAHCI_HFLAG_NO_SUSPEND[] =ss9ine" name="L735"> 735
                11   >11o=D9I_MATCH" classUS Pivers/ata/ahci._DE_warifuncass="sref">_DE_wari11" Aef="5wdh_ops;
devfn == PC; 739   1194 9     11   9nt">                11   >11o" 9lass="sref">atmatchg ASUS Pispan>,
 735
  1195 9     11omm9nt">                11omm>11on>99" id="L75href5e" name="L735"> 735
 741   1197 9     11omm8      ., ;
devfn =aapliline" name="L734"> 734   1198 9     11   8      .matchivers/ata/ahci.hp="LN" class="sref"hp="L[] == |  ief="+code=portAHCI_HFLAG_SRST_TOUT_IS_OFFLINstring">"P5AHCI_HFLAG_SRST_TOUT_IS_OFFLINs[] =ss9ine" name="L735"> 735
119">8p->PC_info11" Aef="5wdh_ops;
devfn == PC; 739   12   9     12   9              120<>99" id="L756" class="liiiiiPispan>,
 735
  12 1 9     12   9nt">                12   >1201>95ass="strihref5e" name="L735"> 735
                12 mm>120_d96="line" name="L653"> 653   12 3 9     12   9nt">                12   >120=D9I_MATCH" c;s:nd#d class="line" name="L808"> 808   12 4 9     12 ac994" id="L804" class=12 ac>120>
97DMI_BOARD_VENDOR of "MICRO-*7port, "t oen,r times, revtG/ahen, rs/n>possind#Lport, so class="line" name="L808"> 808   12 5 9     12 mm9nt">                12 mm>120ve97versions for the Asus M3A suppor* determinlea en, maximumLport numb,r requires looklea st class="line" name="L808"> 808   12 6 9     12   9 715 808   12 8 9     12   8      .="lief="+code=portmaxN" class="sref"max11" ARdh_ops;
;
link;
;
devfort_mapa> =aass="ne" name="L735"> 735
  12 9 9     12   8              1209L916ref5e" name="L735"> 735
 7_hosu_allo _pinfo11" Aef="5wdh_ops;
devfn == PC;ass="ne" name="L735"> 735
  1211 9     12   9              1211>95ass="strinf A+coddma_maskhosuot;ASUS M2A-VM&hosu[] =  ))ne" name="L746"> 746{
<12 2 9     12   9                    12   >121a/9hci.c#L803" idUS P64" "dr-as, ma_maskENOMEMtring">"P5ENOMEM[] =ss9ine" name="L735"> 735
121=D9I_MATCH" cRD_NAME, "200710p="Latastrin[] =="lief="+code=porthp="LN" class="sref"hp="L[] =ss9ine" name="L735"> 735
 732   12 5 9     12  }9
, link 746{
<12 6 9     12  {9}
|  ief="+code=portATA_HOST_PARALLEL_SCAa href="drivers/ATA_HOST_PARALLEL_SCAa[] =ss9ine" name="L735"> 735
 735
121s"8class="sref">matchivers/ata/ahci.p=snatot;ASUS M2A-VM&p=snat11" ARdh_ops;
"P5KERN_INFO"8claispan>,
 735
  12 9 9     12omm9uct  735
,  = ef="5 ief="+code=portATA_FLAG_EMtring">"P5ATA_FLAG_EM[] =  ))ne" name="L746"> 746{
<12 1 9     12   9      .ident;
 735
  12 2 9     12   9      . 653   12 3 9     12   9              122=D9I_MATCH" cfor ARdh_ops;
=<&ivers/ata/ahci.hosuot;ASUS M2A-VM&hosu[] == 5 ief="+code=porti.ysi class="sreipan>++apliline" name="L734"> 734   12 4 9     12   9                    12   >122" 9lass="sref">atmatcmi_system_id  7_portN" class="sref"> 7_port 9las{
link[<|_LFLAG_ASSUMEi.ysi class="sreipan>ass9ine" name="L735"> 735
122IO96" id=e" name="L735"> 735
a 7_port_pbar_des 11" ARdh_ops;
linkss=_ps=_6L6yeade=pdev" cla>ss=_ps=_6L6sysi, -1,aispan>,
 735
  12 7 9     12ta/9
a 7_port_pbar_des 11" ARdh_ops;
linkss=_ps=_6L6yeade=pdev" cla>ss=_ps=_6L6sysi,s="ne" name="L735"> 735
  12 8 9     12ref9}
matchg ASUS PPPPPPPPPPPP0x100 +aivers/ata/ahci.>cicmsref">link,
 735
  12 9 9     12omm9="drivers/ata/ahci.c12omm>1229L916ref5e" name="L735"> 735
123 d97ss="sref">ident =ci.c#L805" id="L805" set enclosurh manageci.c messagt type"*" class="line" name="L808"> 808   12 1 9     12ers9ata/ahci.c#L732" id=12ers>123nd97ss="sref">ident, linkef="5 ief="+code=portATA_FLAG_EMtring">"P5ATA_FLAG_EM[] =  ))ne" name="L746"> 746{
<12 2 9     12   9f="+code=pdev" class12   >123a/9hci.c#L803" idUS Pg ASUS Pivers/ata/ahci.acicmsref">linklinklink 735
 739   12 4 9     12  s9ruct  732   12 5 9     12ers9ata/ahci.c#L736" id=12ers>12 #L916" id="L816" clasa> =ci.c#L805" id="L805" lis:nd#d/not-impleci.cevaport"*" class="line" name="L808"> 808   12 6 9     12  {9 href="+code=dev_inf12  {>12 c#9817" id="L817" claef="+ARD_NAME, devfort_mapa> =>ef="5 (1== ) <&ivers/ata/ahci.i.ysi class="sreipan>)aa"line" name="L739"> 739   12 7 9     12ta/9       link;
 735
123s"8class="srehref5e" name="L735"> 735
1239L916ref5e" name="L735"> 735
1240"8class="srehiiiivers/ata/ahci.c#L763a ida iveA 808   1241 9     12ers9"drivers/ata/ahci.c#12ers>124a/961>pci_dev"+code=port>ss=_p5wdh_iveAss=_p5wdh_iveA;
 735
  12 2 9     12   9/ata/ahci.c#L743" id12   >124_d96="line" name="L653"> 653   12 3 9     12 hr9ata/ahci.c#L744" id=12 hr>124=D9I_MATCH" c 808   1244 9     12omm9nt">/* only some SB612omm>1244/961>pci_dev"+code=port>ss=_gtf_filter_iveAss=_gtf_filter_iveA;
 735
  12 5 9     12ers9ode=bool" class="sre12ers>124IO96" id=e" name="L735"> 735
1246/961>pci_dev 808   1247 9     12 co9st struct rc[] =="lief="+code=port>ss=_23s">durh_dma_mask/ahci.c#L734" idass=_23s">durh_dma_mask/11" ARdh_ops;
devfn =, Rdh_ops;
link 735
  12 8 9     12ref9pan class="comment">12ref>124s"8class="sreef="as, ma_maskr funcass="sref">rc[] =a"line" name="L739"> 739   12 9 9     12omm9nt">                12omm>124">8p->rc[] =ss9ine" name="L735"> 735
                12omm>125  hre>mnne" name="L741"> 741   12o1 9     12omm9nt">                12omm>125a/961>pci_dev"+code=portr funcass="sref">rc[] =="lief="+code=port>ss=_ps=_reset_controll5 yeade=pdev" cla>ss=_ps=_reset_controll5 11" ARdh_ops;
 735
  12o2 9     12omm9nt">                12omm>125a/9hci.c#L803ef="RD_NAME, rc[] =a"line" name="L739"> 739   12o3 9     12omm9nt">                12omm>125=D9I_MATCH" class="sr64" "drivers/ata/ahci.r funcass="sref">rc[] =ss9ine" name="L735"> 735
                12omm>1254c88="line" name="L732"> 732   1255 9     12ers9ss=_ps=_init_controll5 11" ARdh_ops;
 735
  12o6 9     12   9      .ss=_ps=_p=sna_infoN" class="sref">ss=_ps=_p=sna_info11" ARdh_ops;
 735
  12o7 9     12   9      . 735
  12o8 9     12  <9              125s"8class="srehref="+code=PCIps=_set_mast5 yeade=pdev" claps=_set_mast5 11" ARdh_ops;
devfn = ss="ne" name="L735"> 735
  12o9 9     12omm9                    12omm>1259.9997" cl94s64" "drivers/ata/ahci.> 7_hosu_act"LataN" class="sref"> 7_hosu_act"Lata11" ARdh_ops;
devfn == ss=_interruptyeade=pdev" cla>ss=_interruptsysicaivers/ata/ahci.IRQF_SHAREDSLOATA_LFLAG_ASIRQF_SHAREDsysi,s="ne" name="L735"> 735
  126  9     12   9              126 d97ss="sref">ident;
ss=_shu[] = ss="ne" name="L735"> 735
  1261 9     12   9      },
 735
 653   1263 9     12  }9
;
 735
  1264 9     12omm9pan class="comment">12omm>1264c88="line" name="L732"> 732   1265 9     12omm9nt">                12omm>126#L916Rdh_ops;
,
 735
  1266 9     12   9nt">                12   >126 c95cRdh_ops;
,
 735
  1267 9     12omm9nt">                12omm>1267/961Rdh_ops;
"P5MODULE_LICENSs11" ARspan>,
 735
  1268 9     12omm9nt">                12omm>126s"8clRdh_ops;
"P5MODULE_DEVICE_TABLs11" ARdh_ops;
 735
  1269 9     12omm9nt">                12omm>126">8p;
;
 735
  127  9     12omm9nt">                12omm>127 d97s


foot5 y> The original LXR software by en, ="ne" namhttp://sourasforge.net/projects/lx y>LXR /ahcunitysysicathiceexperici.cal L735evi by ="ne" nammailto:lx @ ux.no">lx @ ux.nosysis
subfoot5 y> lx . ux.no kindly hosued by ="ne" namhttp://www.redpill- pro.no">Redpill L pro ASsysicaproviderG/ahL uxLconsultlea invaoperatevis serEiassrsince 1995.