linux/drivers/ata/acard-ahci.c
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   1
   2/*
   3 *  acard-ahci.c - ACard AHCI SATA support
   4 *
   5 *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
   6 *                  Please ALWAYS copy linux-ide@vger.kernel.org
   7 *                  on emails.
   8 *
   9 *  Copyright 2010 Red Hat, Inc.
  10 *
  11 *
  12 *  This program is free software; you can redistribute it and/or modify
  13 *  it under the terms of the GNU General Public License as published by
  14 *  the Free Software Foundation; either version 2, or (at your option)
  15 *  any later version.
  16 *
  17 *  This program is distributed in the hope that it will be useful,
  18 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 *  GNU General Public License for more details.
  21 *
  22 *  You should have received a copy of the GNU General Public License
  23 *  along with this program; see the file COPYING.  If not, write to
  24 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  25 *
  26 *
  27 * libata documentation is available via 'make {ps|pdf}docs',
  28 * as Documentation/DocBook/libata.*
  29 *
  30 * AHCI hardware documentation:
  31 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
  32 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
  33 *
  34 */
  35
  36#include <linux/kernel.h>
  37#include <linux/module.h>
  38#include <linux/pci.h>
  39#include <linux/init.h>
  40#include <linux/blkdev.h>
  41#include <linux/delay.h>
  42#include <linux/interrupt.h>
  43#include <linux/dma-mapping.h>
  44#include <linux/device.h>
  45#include <linux/dmi.h>
  46#include <linux/gfp.h>
  47#include <scsi/scsi_host.h>
  48#include <scsi/scsi_cmnd.h>
  49#include <linux/libata.h>
  50#include "ahci.h"
  51
  52#define DRV_NAME        "acard-ahci"
  53#define DRV_VERSION     "1.0"
  54
  55/*
  56  Received FIS structure limited to 80h.
  57*/
  58
  59#define ACARD_AHCI_RX_FIS_SZ 128
  60
  61enum {
  62        AHCI_PCI_BAR            = 5,
  63};
  64
  65enum board_ids {
  66        board_acard_ahci,
  67};
  68
  69struct acard_sg {
  70        __le32                  addr;
  71        __le32                  addr_hi;
  72        __le32                  reserved;
  73        __le32                  size;    /* bit 31 (EOT) max==0x10000 (64k) */
  74};
  75
  76static void acard_ahci_qc_prep(struct ata_queued_cmd *qc);
  77static bool acard_ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
  78static int acard_ahci_port_start(struct ata_port *ap);
  79static int acard_ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
  80
  81#ifdef CONFIG_PM
  82static int acard_ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
  83static int acard_ahci_pci_device_resume(struct pci_dev *pdev);
  84#endif
  85
  86static struct scsi_host_template acard_ahci_sht = {
  87        AHCI_SHT("acard-ahci"),
  88};
  89
  90static struct ata_port_operations acard_ops = {
  91        .inherits               = &ahci_ops,
  92        .qc_prep                = acard_ahci_qc_prep,
  93        .qc_fill_rtf            = acard_ahci_qc_fill_rtf,
  94        .port_start             = acard_ahci_port_start,
  95};
  96
  97#define AHCI_HFLAGS(flags)      .private_data   = (void *)(flags)
  98
  99static const struct ata_port_info acard_ahci_port_info[] = {
 100        [board_acard_ahci] =
 101        {
 102                AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ),
 103                .flags          = AHCI_FLAG_COMMON,
 104                .pio_mask       = ATA_PIO4,
 105                .udma_mask      = ATA_UDMA6,
 106                .port_ops       = &acard_ops,
 107        },
 108};
 109
 110static const struct pci_device_id acard_ahci_pci_tbl[] = {
 111        /* ACard */
 112        { PCI_VDEVICE(ARTOP, 0x000d), board_acard_ahci }, /* ATP8620 */
 113
 114        { }    /* terminate list */
 115};
 116
 117static struct pci_driver acard_ahci_pci_driver = {
 118        .name                   = DRV_NAME,
 119        .id_table               = acard_ahci_pci_tbl,
 120        .probe                  = acard_ahci_init_one,
 121        .remove                 = ata_pci_remove_one,
 122#ifdef CONFIG_PM
 123        .suspend                = acard_ahci_pci_device_suspend,
 124        .resume                 = acard_ahci_pci_device_resume,
 125#endif
 126};
 127
 128#ifdef CONFIG_PM
 129static int acard_ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
 130{
 131        struct ata_host *host = dev_get_drvdata(&pdev->dev);
 132        struct ahci_host_priv *hpriv = host->private_data;
 133        void __iomem *mmio = hpriv->mmio;
 134        u32 ctl;
 135
 136        if (mesg.event & PM_EVENT_SUSPEND &&
 137            hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
 138                dev_err(&pdev->dev,
 139                        "BIOS update required for suspend/resume\n");
 140                return -EIO;
 141        }
 142
 143        if (mesg.event & PM_EVENT_SLEEP) {
 144                /* AHCI spec rev1.1 section 8.3.3:
 145                 * Software must disable interrupts prior to requesting a
 146                 * transition of the HBA to D3 state.
 147                 */
 148                ctl = readl(mmio + HOST_CTL);
 149                ctl &= ~HOST_IRQ_EN;
 150                writel(ctl, mmio + HOST_CTL);
 151                readl(mmio + HOST_CTL); /* flush */
 152        }
 153
 154        return ata_pci_device_suspend(pdev, mesg);
 155}
 156
 157static int acard_ahci_pci_device_resume(struct pci_dev *pdev)
 158{
 159        struct ata_host *host = dev_get_drvdata(&pdev->dev);
 160        int rc;
 161
 162        rc = ata_pci_device_do_resume(pdev);
 163        if (rc)
 164                return rc;
 165
 166        if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
 167                rc = ahci_reset_controller(host);
 168                if (rc)
 169                        return rc;
 170
 171                ahci_init_controller(host);
 172        }
 173
 174        ata_host_resume(host);
 175
 176        return 0;
 177}
 178#endif
 179
 180static int acard_ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
 181{
 182        int rc;
 183
 184        if (using_dac &&
 185            !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
 186                rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
 187                if (rc) {
 188                        rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 189                        if (rc) {
 190                                dev_err(&pdev->dev,
 191                                           "64-bit DMA enable failed\n");
 192                                return rc;
 193                        }
 194                }
 195        } else {
 196                rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 197                if (rc) {
 198                        dev_err(&pdev->dev, "32-bit DMA enable failed\n");
 199                        return rc;
 200                }
 201                rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 202                if (rc) {
 203                        dev_err(&pdev->dev,
 204                                "32-bit consistent DMA enable failed\n");
 205                        return rc;
 206                }
 207        }
 208        return 0;
 209}
 210
 211static void acard_ahci_pci_print_info(struct ata_host *host)
 212{
 213        struct pci_dev *pdev = to_pci_dev(host->dev);
 214        u16 cc;
 215        const char *scc_s;
 216
 217        pci_read_config_word(pdev, 0x0a, &cc);
 218        if (cc == PCI_CLASS_STORAGE_IDE)
 219                scc_s = "IDE";
 220        else if (cc == PCI_CLASS_STORAGE_SATA)
 221                scc_s = "SATA";
 222        else if (cc == PCI_CLASS_STORAGE_RAID)
 223                scc_s = "RAID";
 224        else
 225                scc_s = "unknown";
 226
 227        ahci_print_info(host, scc_s);
 228}
 229
 230static unsigned int acard_ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
 231{
 232        struct scatterlist *sg;
 233        struct acard_sg *acard_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
 234        unsigned int si, last_si = 0;
 235
 236        VPRINTK("ENTER\n");
 237
 238        /*
 239         * Next, the S/G list.
 240         */
 241        for_each_sg(qc->sg, sg, qc->n_elem, si) {
 242                dma_addr_t addr = sg_dma_address(sg);
 243                u32 sg_len = sg_dma_len(sg);
 244
 245                /*
 246                 * ACard note:
 247                 * We must set an end-of-table (EOT) bit,
 248                 * and the segment cannot exceed 64k (0x10000)
 249                 */
 250                acard_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
 251                acard_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
 252                acard_sg[si].size = cpu_to_le32(sg_len);
 253                last_si = si;
 254        }
 255
 256        acard_sg[last_si].size |= cpu_to_le32(1 << 31); /* set EOT */
 257
 258        return si;
 259}
 260
 261static void acard_ahci_qc_prep(struct ata_queued_cmd *qc)
 262{
 263        struct ata_port *ap = qc->ap;
 264        struct ahci_port_priv *pp = ap->private_data;
 265        int is_atapi = ata_is_atapi(qc->tf.protocol);
 266        void *cmd_tbl;
 267        u32 opts;
 268        const u32 cmd_fis_len = 5; /* five dwords */
 269        unsigned int n_elem;
 270
 271        /*
 272         * Fill in command table information.  First, the header,
 273         * a SATA Register - Host to Device command FIS.
 274         */
 275        cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
 276
 277        ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
 278        if (is_atapi) {
 279                memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
 280                memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
 281        }
 282
 283        n_elem = 0;
 284        if (qc->flags & ATA_QCFLAG_DMAMAP)
 285                n_elem = acard_ahci_fill_sg(qc, cmd_tbl);
 286
 287        /*
 288         * Fill in command slot information.
 289         *
 290         * ACard note: prd table length not filled in
 291         */
 292        opts = cmd_fis_len | (qc->dev->link->pmp << 12);
 293        if (qc->tf.flags & ATA_TFLAG_WRITE)
 294                opts |= AHCI_CMD_WRITE;
 295        if (is_atapi)
 296                opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
 297
 298        ahci_fill_cmd_slot(pp, qc->tag, opts);
 299}
 300
 301static bool acard_ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
 302{
 303        struct ahci_port_priv *pp = qc->ap->private_data;
 304        u8 *rx_fis = pp->rx_fis;
 305
 306        if (pp->fbs_enabled)
 307                rx_fis += qc->dev->link->pmp * ACARD_AHCI_RX_FIS_SZ;
 308
 309        /*
 310         * After a successful execution of an ATA PIO data-in command,
 311         * the device doesn't send D2H Reg FIS to update the TF and
 312         * the host should take TF and E_Status from the preceding PIO
 313         * Setup FIS.
 314         */
 315        if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
 316            !(qc->flags & ATA_QCFLAG_FAILED)) {
 317                ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
 318                qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
 319        } else
 320                ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
 321
 322        return true;
 323}
 324
 325static int acard_ahci_port_start(struct ata_port *ap)
 326{
 327        struct ahci_host_priv *hpriv = ap->host->private_data;
 328        struct device *dev = ap->host->dev;
 329        struct ahci_port_priv *pp;
 330        void *mem;
 331        dma_addr_t mem_dma;
 332        size_t dma_sz, rx_fis_sz;
 333
 334        pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
 335        if (!pp)
 336                return -ENOMEM;
 337
 338        /* check FBS capability */
 339        if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
 340                void __iomem *port_mmio = ahci_port_base(ap);
 341                u32 cmd = readl(port_mmio + PORT_CMD);
 342                if (cmd & PORT_CMD_FBSCP)
 343                        pp->fbs_supported = true;
 344                else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
 345                        dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
 346                                 ap->port_no);
 347                        pp->fbs_supported = true;
 348                } else
 349                        dev_warn(dev, "port %d is not capable of FBS\n",
 350                                 ap->port_no);
 351        }
 352
 353        if (pp->fbs_supported) {
 354                dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
 355                rx_fis_sz = ACARD_AHCI_RX_FIS_SZ * 16;
 356        } else {
 357                dma_sz = AHCI_PORT_PRIV_DMA_SZ;
 358                rx_fis_sz = ACARD_AHCI_RX_FIS_SZ;
 359        }
 360
 361        mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
 362        if (!mem)
 363                return -ENOMEM;
 364        memset(mem, 0, dma_sz);
 365
 366        /*
 367         * First item in chunk of DMA memory: 32-slot command table,
 368         * 32 bytes each in size
 369         */
 370        pp->cmd_slot = mem;
 371        pp->cmd_slot_dma = mem_dma;
 372
 373        mem += AHCI_CMD_SLOT_SZ;
 374        mem_dma += AHCI_CMD_SLOT_SZ;
 375
 376        /*
 377         * Second item: Received-FIS area
 378         */
 379        pp->rx_fis = mem;
 380        pp->rx_fis_dma = mem_dma;
 381
 382        mem += rx_fis_sz;
 383        mem_dma += rx_fis_sz;
 384
 385        /*
 386         * Third item: data area for storing a single command
 387         * and its scatter-gather table
 388         */
 389        pp->cmd_tbl = mem;
 390        pp->cmd_tbl_dma = mem_dma;
 391
 392        /*
 393         * Save off initial list of interrupts to be enabled.
 394         * This could be changed later
 395         */
 396        pp->intr_mask = DEF_PORT_IRQ;
 397
 398        ap->private_data = pp;
 399
 400        /* engage engines, captain */
 401        return ahci_port_resume(ap);
 402}
 403
 404static int acard_ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 405{
 406        unsigned int board_id = ent->driver_data;
 407        struct ata_port_info pi = acard_ahci_port_info[board_id];
 408        const struct ata_port_info *ppi[] = { &pi, NULL };
 409        struct device *dev = &pdev->dev;
 410        struct ahci_host_priv *hpriv;
 411        struct ata_host *host;
 412        int n_ports, i, rc;
 413
 414        VPRINTK("ENTER\n");
 415
 416        WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
 417
 418        ata_print_version_once(&pdev->dev, DRV_VERSION);
 419
 420        /* acquire resources */
 421        rc = pcim_enable_device(pdev);
 422        if (rc)
 423                return rc;
 424
 425        /* AHCI controllers often implement SFF compatible interface.
 426         * Grab all PCI BARs just in case.
 427         */
 428        rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
 429        if (rc == -EBUSY)
 430                pcim_pin_device(pdev);
 431        if (rc)
 432                return rc;
 433
 434        hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
 435        if (!hpriv)
 436                return -ENOMEM;
 437        hpriv->flags |= (unsigned long)pi.private_data;
 438
 439        if (!(hpriv->flags & AHCI_HFLAG_NO_MSI))
 440                pci_enable_msi(pdev);
 441
 442        hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
 443
 444        /* save initial config */
 445        ahci_save_initial_config(&pdev->dev, hpriv, 0, 0);
 446
 447        /* prepare host */
 448        if (hpriv->cap & HOST_CAP_NCQ)
 449                pi.flags |= ATA_FLAG_NCQ;
 450
 451        if (hpriv->cap & HOST_CAP_PMP)
 452                pi.flags |= ATA_FLAG_PMP;
 453
 454        ahci_set_em_messages(hpriv, &pi);
 455
 456        /* CAP.NP sometimes indicate the index of the last enabled
 457         * port, at other times, that of the last possible port, so
 458         * determining the maximum port number requires looking at
 459         * both CAP.NP and port_map.
 460         */
 461        n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
 462
 463        host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
 464        if (!host)
 465                return -ENOMEM;
 466        host->private_data = hpriv;
 467
 468        if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
 469                host->flags |= ATA_HOST_PARALLEL_SCAN;
 470        else
 471                printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
 472
 473        for (i = 0; i < host->n_ports; i++) {
 474                struct ata_port *ap = host->ports[i];
 475
 476                ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
 477                ata_port_pbar_desc(ap, AHCI_PCI_BAR,
 478                                   0x100 + ap->port_no * 0x80, "port");
 479
 480                /* set initial link pm policy */
 481                /*
 482                ap->pm_policy = NOT_AVAILABLE;
 483                */
 484                /* disabled/not-implemented port */
 485                if (!(hpriv->port_map & (1 << i)))
 486                        ap->ops = &ata_dummy_port_ops;
 487        }
 488
 489        /* initialize adapter */
 490        rc = acard_ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
 491        if (rc)
 492                return rc;
 493
 494        rc = ahci_reset_controller(host);
 495        if (rc)
 496                return rc;
 497
 498        ahci_init_controller(host);
 499        acard_ahci_pci_print_info(host);
 500
 501        pci_set_master(pdev);
 502        return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
 503                                 &acard_ahci_sht);
 504}
 505
 506module_pci_driver(acard_ahci_pci_driver);
 507
 508MODULE_AUTHOR("Jeff Garzik");
 509MODULE_DESCRIPTION("ACard AHCI SATA low-level driver");
 510MODULE_LICENSE("GPL");
 511MODULE_DEVICE_TABLE(pci, acard_ahci_pci_tbl);
 512MODULE_VERSION(DRV_VERSION);
 513
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