linux/drivers/amba/tegra-ahb.c
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   1/*
   2 * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
   3 * Copyright (C) 2011 Google, Inc.
   4 *
   5 * Author:
   6 *      Jay Cheng <jacheng@nvidia.com>
   7 *      James Wylder <james.wylder@motorola.com>
   8 *      Benoit Goby <benoit@android.com>
   9 *      Colin Cross <ccross@android.com>
  10 *      Hiroshi DOYU <hdoyu@nvidia.com>
  11 *
  12 * This software is licensed under the terms of the GNU General Public
  13 * License version 2, as published by the Free Software Foundation, and
  14 * may be copied, distributed, and modified under those terms.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 *
  21 */
  22
  23#include <linux/kernel.h>
  24#include <linux/module.h>
  25#include <linux/platform_device.h>
  26#include <linux/io.h>
  27#include <linux/tegra-ahb.h>
  28
  29#define DRV_NAME "tegra-ahb"
  30
  31#define AHB_ARBITRATION_DISABLE         0x00
  32#define AHB_ARBITRATION_PRIORITY_CTRL   0x04
  33#define   AHB_PRIORITY_WEIGHT(x)        (((x) & 0x7) << 29)
  34#define   PRIORITY_SELECT_USB BIT(6)
  35#define   PRIORITY_SELECT_USB2 BIT(18)
  36#define   PRIORITY_SELECT_USB3 BIT(17)
  37
  38#define AHB_GIZMO_AHB_MEM               0x0c
  39#define   ENB_FAST_REARBITRATE BIT(2)
  40#define   DONT_SPLIT_AHB_WR     BIT(7)
  41
  42#define AHB_GIZMO_APB_DMA               0x10
  43#define AHB_GIZMO_IDE                   0x18
  44#define AHB_GIZMO_USB                   0x1c
  45#define AHB_GIZMO_AHB_XBAR_BRIDGE       0x20
  46#define AHB_GIZMO_CPU_AHB_BRIDGE        0x24
  47#define AHB_GIZMO_COP_AHB_BRIDGE        0x28
  48#define AHB_GIZMO_XBAR_APB_CTLR         0x2c
  49#define AHB_GIZMO_VCP_AHB_BRIDGE        0x30
  50#define AHB_GIZMO_NAND                  0x3c
  51#define AHB_GIZMO_SDMMC4                0x44
  52#define AHB_GIZMO_XIO                   0x48
  53#define AHB_GIZMO_BSEV                  0x60
  54#define AHB_GIZMO_BSEA                  0x70
  55#define AHB_GIZMO_NOR                   0x74
  56#define AHB_GIZMO_USB2                  0x78
  57#define AHB_GIZMO_USB3                  0x7c
  58#define   IMMEDIATE     BIT(18)
  59
  60#define AHB_GIZMO_SDMMC1                0x80
  61#define AHB_GIZMO_SDMMC2                0x84
  62#define AHB_GIZMO_SDMMC3                0x88
  63#define AHB_MEM_PREFETCH_CFG_X          0xd8
  64#define AHB_ARBITRATION_XBAR_CTRL       0xdc
  65#define AHB_MEM_PREFETCH_CFG3           0xe0
  66#define AHB_MEM_PREFETCH_CFG4           0xe4
  67#define AHB_MEM_PREFETCH_CFG1           0xec
  68#define AHB_MEM_PREFETCH_CFG2           0xf0
  69#define   PREFETCH_ENB  BIT(31)
  70#define   MST_ID(x)     (((x) & 0x1f) << 26)
  71#define   AHBDMA_MST_ID MST_ID(5)
  72#define   USB_MST_ID    MST_ID(6)
  73#define   USB2_MST_ID   MST_ID(18)
  74#define   USB3_MST_ID   MST_ID(17)
  75#define   ADDR_BNDRY(x) (((x) & 0xf) << 21)
  76#define   INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
  77
  78#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID    0xf8
  79
  80#define AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE BIT(17)
  81
  82static struct platform_driver tegra_ahb_driver;
  83
  84static const u32 tegra_ahb_gizmo[] = {
  85        AHB_ARBITRATION_DISABLE,
  86        AHB_ARBITRATION_PRIORITY_CTRL,
  87        AHB_GIZMO_AHB_MEM,
  88        AHB_GIZMO_APB_DMA,
  89        AHB_GIZMO_IDE,
  90        AHB_GIZMO_USB,
  91        AHB_GIZMO_AHB_XBAR_BRIDGE,
  92        AHB_GIZMO_CPU_AHB_BRIDGE,
  93        AHB_GIZMO_COP_AHB_BRIDGE,
  94        AHB_GIZMO_XBAR_APB_CTLR,
  95        AHB_GIZMO_VCP_AHB_BRIDGE,
  96        AHB_GIZMO_NAND,
  97        AHB_GIZMO_SDMMC4,
  98        AHB_GIZMO_XIO,
  99        AHB_GIZMO_BSEV,
 100        AHB_GIZMO_BSEA,
 101        AHB_GIZMO_NOR,
 102        AHB_GIZMO_USB2,
 103        AHB_GIZMO_USB3,
 104        AHB_GIZMO_SDMMC1,
 105        AHB_GIZMO_SDMMC2,
 106        AHB_GIZMO_SDMMC3,
 107        AHB_MEM_PREFETCH_CFG_X,
 108        AHB_ARBITRATION_XBAR_CTRL,
 109        AHB_MEM_PREFETCH_CFG3,
 110        AHB_MEM_PREFETCH_CFG4,
 111        AHB_MEM_PREFETCH_CFG1,
 112        AHB_MEM_PREFETCH_CFG2,
 113        AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID,
 114};
 115
 116struct tegra_ahb {
 117        void __iomem    *regs;
 118        struct device   *dev;
 119        u32             ctx[0];
 120};
 121
 122static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset)
 123{
 124        return readl(ahb->regs + offset);
 125}
 126
 127static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset)
 128{
 129        writel(value, ahb->regs + offset);
 130}
 131
 132#ifdef CONFIG_ARCH_TEGRA_3x_SOC
 133static int tegra_ahb_match_by_smmu(struct device *dev, void *data)
 134{
 135        struct tegra_ahb *ahb = dev_get_drvdata(dev);
 136        struct device_node *dn = data;
 137
 138        return (ahb->dev->of_node == dn) ? 1 : 0;
 139}
 140
 141int tegra_ahb_enable_smmu(struct device_node *dn)
 142{
 143        struct device *dev;
 144        u32 val;
 145        struct tegra_ahb *ahb;
 146
 147        dev = driver_find_device(&tegra_ahb_driver.driver, NULL, dn,
 148                                 tegra_ahb_match_by_smmu);
 149        if (!dev)
 150                return -EPROBE_DEFER;
 151        ahb = dev_get_drvdata(dev);
 152        val = gizmo_readl(ahb, AHB_ARBITRATION_XBAR_CTRL);
 153        val |= AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE;
 154        gizmo_writel(ahb, val, AHB_ARBITRATION_XBAR_CTRL);
 155        return 0;
 156}
 157EXPORT_SYMBOL(tegra_ahb_enable_smmu);
 158#endif
 159
 160#ifdef CONFIG_PM_SLEEP
 161static int tegra_ahb_suspend(struct device *dev)
 162{
 163        int i;
 164        struct tegra_ahb *ahb = dev_get_drvdata(dev);
 165
 166        for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
 167                ahb->ctx[i] = gizmo_readl(ahb, tegra_ahb_gizmo[i]);
 168        return 0;
 169}
 170
 171static int tegra_ahb_resume(struct device *dev)
 172{
 173        int i;
 174        struct tegra_ahb *ahb = dev_get_drvdata(dev);
 175
 176        for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
 177                gizmo_writel(ahb, ahb->ctx[i], tegra_ahb_gizmo[i]);
 178        return 0;
 179}
 180#endif
 181
 182static UNIVERSAL_DEV_PM_OPS(tegra_ahb_pm,
 183                            tegra_ahb_suspend,
 184                            tegra_ahb_resume, NULL);
 185
 186static void tegra_ahb_gizmo_init(struct tegra_ahb *ahb)
 187{
 188        u32 val;
 189
 190        val = gizmo_readl(ahb, AHB_GIZMO_AHB_MEM);
 191        val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
 192        gizmo_writel(ahb, val, AHB_GIZMO_AHB_MEM);
 193
 194        val = gizmo_readl(ahb, AHB_GIZMO_USB);
 195        val |= IMMEDIATE;
 196        gizmo_writel(ahb, val, AHB_GIZMO_USB);
 197
 198        val = gizmo_readl(ahb, AHB_GIZMO_USB2);
 199        val |= IMMEDIATE;
 200        gizmo_writel(ahb, val, AHB_GIZMO_USB2);
 201
 202        val = gizmo_readl(ahb, AHB_GIZMO_USB3);
 203        val |= IMMEDIATE;
 204        gizmo_writel(ahb, val, AHB_GIZMO_USB3);
 205
 206        val = gizmo_readl(ahb, AHB_ARBITRATION_PRIORITY_CTRL);
 207        val |= PRIORITY_SELECT_USB |
 208                PRIORITY_SELECT_USB2 |
 209                PRIORITY_SELECT_USB3 |
 210                AHB_PRIORITY_WEIGHT(7);
 211        gizmo_writel(ahb, val, AHB_ARBITRATION_PRIORITY_CTRL);
 212
 213        val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG1);
 214        val &= ~MST_ID(~0);
 215        val |= PREFETCH_ENB |
 216                AHBDMA_MST_ID |
 217                ADDR_BNDRY(0xc) |
 218                INACTIVITY_TIMEOUT(0x1000);
 219        gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG1);
 220
 221        val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG2);
 222        val &= ~MST_ID(~0);
 223        val |= PREFETCH_ENB |
 224                USB_MST_ID |
 225                ADDR_BNDRY(0xc) |
 226                INACTIVITY_TIMEOUT(0x1000);
 227        gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG2);
 228
 229        val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG3);
 230        val &= ~MST_ID(~0);
 231        val |= PREFETCH_ENB |
 232                USB3_MST_ID |
 233                ADDR_BNDRY(0xc) |
 234                INACTIVITY_TIMEOUT(0x1000);
 235        gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG3);
 236
 237        val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG4);
 238        val &= ~MST_ID(~0);
 239        val |= PREFETCH_ENB |
 240                USB2_MST_ID |
 241                ADDR_BNDRY(0xc) |
 242                INACTIVITY_TIMEOUT(0x1000);
 243        gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG4);
 244}
 245
 246static int tegra_ahb_probe(struct platform_device *pdev)
 247{
 248        struct resource *res;
 249        struct tegra_ahb *ahb;
 250        size_t bytes;
 251
 252        bytes = sizeof(*ahb) + sizeof(u32) * ARRAY_SIZE(tegra_ahb_gizmo);
 253        ahb = devm_kzalloc(&pdev->dev, bytes, GFP_KERNEL);
 254        if (!ahb)
 255                return -ENOMEM;
 256
 257        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 258        if (!res)
 259                return -ENODEV;
 260        ahb->regs = devm_request_and_ioremap(&pdev->dev, res);
 261        if (!ahb->regs)
 262                return -EBUSY;
 263
 264        ahb->dev = &pdev->dev;
 265        platform_set_drvdata(pdev, ahb);
 266        tegra_ahb_gizmo_init(ahb);
 267        return 0;
 268}
 269
 270static const struct of_device_id tegra_ahb_of_match[] = {
 271        { .compatible = "nvidia,tegra30-ahb", },
 272        { .compatible = "nvidia,tegra20-ahb", },
 273        {},
 274};
 275
 276static struct platform_driver tegra_ahb_driver = {
 277        .probe = tegra_ahb_probe,
 278        .driver = {
 279                .name = DRV_NAME,
 280                .owner = THIS_MODULE,
 281                .of_match_table = tegra_ahb_of_match,
 282                .pm = &tegra_ahb_pm,
 283        },
 284};
 285module_platform_driver(tegra_ahb_driver);
 286
 287MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
 288MODULE_DESCRIPTION("Tegra AHB driver");
 289MODULE_LICENSE("GPL v2");
 290MODULE_ALIAS("platform:" DRV_NAME);
 291
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