linux/Documentation/memory-barriers.txt
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   1                         ============================
   2                         LINUX KERNEL MEMORY BARRIERS
   3                         ============================
   4
   5By: David Howells <dhowells@redhat.com>
   6    Paul E. McKenney <paulmck@linux.vnet.ibm.com>
   7
   8Contents:
   9
  10 (*) Abstract memory access model.
  11
  12     - Device operations.
  13     - Guarantees.
  14
  15 (*) What are memory barriers?
  16
  17     - Varieties of memory barrier.
  18     - What may not be assumed about memory barriers?
  19     - Data dependency barriers.
  20     - Control dependencies.
  21     - SMP barrier pairing.
  22     - Examples of memory barrier sequences.
  23     - Read memory barriers vs load speculation.
  24     - Transitivity
  25
  26 (*) Explicit kernel barriers.
  27
  28     - Compiler barrier.
  29     - CPU memory barriers.
  30     - MMIO write barrier.
  31
  32 (*) Implicit kernel memory barriers.
  33
  34     - Locking functions.
  35     - Interrupt disabling functions.
  36     - Sleep and wake-up functions.
  37     - Miscellaneous functions.
  38
  39 (*) Inter-CPU locking barrier effects.
  40
  41     - Locks vs memory accesses.
  42     - Locks vs I/O accesses.
  43
  44 (*) Where are memory barriers needed?
  45
  46     - Interprocessor interaction.
  47     - Atomic operations.
  48     - Accessing devices.
  49     - Interrupts.
  50
  51 (*) Kernel I/O barrier effects.
  52
  53 (*) Assumed minimum execution ordering model.
  54
  55 (*) The effects of the cpu cache.
  56
  57     - Cache coherency.
  58     - Cache coherency vs DMA.
  59     - Cache coherency vs MMIO.
  60
  61 (*) The things CPUs get up to.
  62
  63     - And then there's the Alpha.
  64
  65 (*) Example uses.
  66
  67     - Circular buffers.
  68
  69 (*) References.
  70
  71
  72============================
  73ABSTRACT MEMORY ACCESS MODEL
  74============================
  75
  76Consider the following abstract model of the system:
  77
  78                            :                :
  79                            :                :
  80                            :                :
  81                +-------+   :   +--------+   :   +-------+
  82                |       |   :   |        |   :   |       |
  83                |       |   :   |        |   :   |       |
  84                | CPU 1 |<----->| Memory |<----->| CPU 2 |
  85                |       |   :   |        |   :   |       |
  86                |       |   :   |        |   :   |       |
  87                +-------+   :   +--------+   :   +-------+
  88                    ^       :       ^        :       ^
  89                    |       :       |        :       |
  90                    |       :       |        :       |
  91                    |       :       v        :       |
  92                    |       :   +--------+   :       |
  93                    |       :   |        |   :       |
  94                    |       :   |        |   :       |
  95                    +---------->| Device |<----------+
  96                            :   |        |   :
  97                            :   |        |   :
  98                            :   +--------+   :
  99                            :                :
 100
 101Each CPU executes a program that generates memory access operations.  In the
 102abstract CPU, memory operation ordering is very relaxed, and a CPU may actually
 103perform the memory operations in any order it likes, provided program causality
 104appears to be maintained.  Similarly, the compiler may also arrange the
 105instructions it emits in any order it likes, provided it doesn't affect the
 106apparent operation of the program.
 107
 108So in the above diagram, the effects of the memory operations performed by a
 109CPU are perceived by the rest of the system as the operations cross the
 110interface between the CPU and rest of the system (the dotted lines).
 111
 112
 113For example, consider the following sequence of events:
 114
 115        CPU 1           CPU 2
 116        =============== ===============
 117        { A == 1; B == 2 }
 118        A = 3;          x = A;
 119        B = 4;          y = B;
 120
 121The set of accesses as seen by the memory system in the middle can be arranged
 122in 24 different combinations:
 123
 124        STORE A=3,      STORE B=4,      x=LOAD A->3,    y=LOAD B->4
 125        STORE A=3,      STORE B=4,      y=LOAD B->4,    x=LOAD A->3
 126        STORE A=3,      x=LOAD A->3,    STORE B=4,      y=LOAD B->4
 127        STORE A=3,      x=LOAD A->3,    y=LOAD B->2,    STORE B=4
 128        STORE A=3,      y=LOAD B->2,    STORE B=4,      x=LOAD A->3
 129        STORE A=3,      y=LOAD B->2,    x=LOAD A->3,    STORE B=4
 130        STORE B=4,      STORE A=3,      x=LOAD A->3,    y=LOAD B->4
 131        STORE B=4, ...
 132        ...
 133
 134and can thus result in four different combinations of values:
 135
 136        x == 1, y == 2
 137        x == 1, y == 4
 138        x == 3, y == 2
 139        x == 3, y == 4
 140
 141
 142Furthermore, the stores committed by a CPU to the memory system may not be
 143perceived by the loads made by another CPU in the same order as the stores were
 144committed.
 145
 146
 147As a further example, consider this sequence of events:
 148
 149        CPU 1           CPU 2
 150        =============== ===============
 151        { A == 1, B == 2, C = 3, P == &A, Q == &C }
 152        B = 4;          Q = P;
 153        P = &B          D = *Q;
 154
 155There is an obvious data dependency here, as the value loaded into D depends on
 156the address retrieved from P by CPU 2.  At the end of the sequence, any of the
 157following results are possible:
 158
 159        (Q == &A) and (D == 1)
 160        (Q == &B) and (D == 2)
 161        (Q == &B) and (D == 4)
 162
 163Note that CPU 2 will never try and load C into D because the CPU will load P
 164into Q before issuing the load of *Q.
 165
 166
 167DEVICE OPERATIONS
 168-----------------
 169
 170Some devices present their control interfaces as collections of memory
 171locations, but the order in which the control registers are accessed is very
 172important.  For instance, imagine an ethernet card with a set of internal
 173registers that are accessed through an address port register (A) and a data
 174port register (D).  To read internal register 5, the following code might then
 175be used:
 176
 177        *A = 5;
 178        x = *D;
 179
 180but this might show up as either of the following two sequences:
 181
 182        STORE *A = 5, x = LOAD *D
 183        x = LOAD *D, STORE *A = 5
 184
 185the second of which will almost certainly result in a malfunction, since it set
 186the address _after_ attempting to read the register.
 187
 188
 189GUARANTEES
 190----------
 191
 192There are some minimal guarantees that may be expected of a CPU:
 193
 194 (*) On any given CPU, dependent memory accesses will be issued in order, with
 195     respect to itself.  This means that for:
 196
 197        Q = P; D = *Q;
 198
 199     the CPU will issue the following memory operations:
 200
 201        Q = LOAD P, D = LOAD *Q
 202
 203     and always in that order.
 204
 205 (*) Overlapping loads and stores within a particular CPU will appear to be
 206     ordered within that CPU.  This means that for:
 207
 208        a = *X; *X = b;
 209
 210     the CPU will only issue the following sequence of memory operations:
 211
 212        a = LOAD *X, STORE *X = b
 213
 214     And for:
 215
 216        *X = c; d = *X;
 217
 218     the CPU will only issue:
 219
 220        STORE *X = c, d = LOAD *X
 221
 222     (Loads and stores overlap if they are targeted at overlapping pieces of
 223     memory).
 224
 225And there are a number of things that _must_ or _must_not_ be assumed:
 226
 227 (*) It _must_not_ be assumed that independent loads and stores will be issued
 228     in the order given.  This means that for:
 229
 230        X = *A; Y = *B; *D = Z;
 231
 232     we may get any of the following sequences:
 233
 234        X = LOAD *A,  Y = LOAD *B,  STORE *D = Z
 235        X = LOAD *A,  STORE *D = Z, Y = LOAD *B
 236        Y = LOAD *B,  X = LOAD *A,  STORE *D = Z
 237        Y = LOAD *B,  STORE *D = Z, X = LOAD *A
 238        STORE *D = Z, X = LOAD *A,  Y = LOAD *B
 239        STORE *D = Z, Y = LOAD *B,  X = LOAD *A
 240
 241 (*) It _must_ be assumed that overlapping memory accesses may be merged or
 242     discarded.  This means that for:
 243
 244        X = *A; Y = *(A + 4);
 245
 246     we may get any one of the following sequences:
 247
 248        X = LOAD *A; Y = LOAD *(A + 4);
 249        Y = LOAD *(A + 4); X = LOAD *A;
 250        {X, Y} = LOAD {*A, *(A + 4) };
 251
 252     And for:
 253
 254        *A = X; *(A + 4) = Y;
 255
 256     we may get any of:
 257
 258        STORE *A = X; STORE *(A + 4) = Y;
 259        STORE *(A + 4) = Y; STORE *A = X;
 260        STORE {*A, *(A + 4) } = {X, Y};
 261
 262
 263=========================
 264WHAT ARE MEMORY BARRIERS?
 265=========================
 266
 267As can be seen above, independent memory operations are effectively performed
 268in random order, but this can be a problem for CPU-CPU interaction and for I/O.
 269What is required is some way of intervening to instruct the compiler and the
 270CPU to restrict the order.
 271
 272Memory barriers are such interventions.  They impose a perceived partial
 273ordering over the memory operations on either side of the barrier.
 274
 275Such enforcement is important because the CPUs and other devices in a system
 276can use a variety of tricks to improve performance, including reordering,
 277deferral and combination of memory operations; speculative loads; speculative
 278branch prediction and various types of caching.  Memory barriers are used to
 279override or suppress these tricks, allowing the code to sanely control the
 280interaction of multiple CPUs and/or devices.
 281
 282
 283VARIETIES OF MEMORY BARRIER
 284---------------------------
 285
 286Memory barriers come in four basic varieties:
 287
 288 (1) Write (or store) memory barriers.
 289
 290     A write memory barrier gives a guarantee that all the STORE operations
 291     specified before the barrier will appear to happen before all the STORE
 292     operations specified after the barrier with respect to the other
 293     components of the system.
 294
 295     A write barrier is a partial ordering on stores only; it is not required
 296     to have any effect on loads.
 297
 298     A CPU can be viewed as committing a sequence of store operations to the
 299     memory system as time progresses.  All stores before a write barrier will
 300     occur in the sequence _before_ all the stores after the write barrier.
 301
 302     [!] Note that write barriers should normally be paired with read or data
 303     dependency barriers; see the "SMP barrier pairing" subsection.
 304
 305
 306 (2) Data dependency barriers.
 307
 308     A data dependency barrier is a weaker form of read barrier.  In the case
 309     where two loads are performed such that the second depends on the result
 310     of the first (eg: the first load retrieves the address to which the second
 311     load will be directed), a data dependency barrier would be required to
 312     make sure that the target of the second load is updated before the address
 313     obtained by the first load is accessed.
 314
 315     A data dependency barrier is a partial ordering on interdependent loads
 316     only; it is not required to have any effect on stores, independent loads
 317     or overlapping loads.
 318
 319     As mentioned in (1), the other CPUs in the system can be viewed as
 320     committing sequences of stores to the memory system that the CPU being
 321     considered can then perceive.  A data dependency barrier issued by the CPU
 322     under consideration guarantees that for any load preceding it, if that
 323     load touches one of a sequence of stores from another CPU, then by the
 324     time the barrier completes, the effects of all the stores prior to that
 325     touched by the load will be perceptible to any loads issued after the data
 326     dependency barrier.
 327
 328     See the "Examples of memory barrier sequences" subsection for diagrams
 329     showing the ordering constraints.
 330
 331     [!] Note that the first load really has to have a _data_ dependency and
 332     not a control dependency.  If the address for the second load is dependent
 333     on the first load, but the dependency is through a conditional rather than
 334     actually loading the address itself, then it's a _control_ dependency and
 335     a full read barrier or better is required.  See the "Control dependencies"
 336     subsection for more information.
 337
 338     [!] Note that data dependency barriers should normally be paired with
 339     write barriers; see the "SMP barrier pairing" subsection.
 340
 341
 342 (3) Read (or load) memory barriers.
 343
 344     A read barrier is a data dependency barrier plus a guarantee that all the
 345     LOAD operations specified before the barrier will appear to happen before
 346     all the LOAD operations specified after the barrier with respect to the
 347     other components of the system.
 348
 349     A read barrier is a partial ordering on loads only; it is not required to
 350     have any effect on stores.
 351
 352     Read memory barriers imply data dependency barriers, and so can substitute
 353     for them.
 354
 355     [!] Note that read barriers should normally be paired with write barriers;
 356     see the "SMP barrier pairing" subsection.
 357
 358
 359 (4) General memory barriers.
 360
 361     A general memory barrier gives a guarantee that all the LOAD and STORE
 362     operations specified before the barrier will appear to happen before all
 363     the LOAD and STORE operations specified after the barrier with respect to
 364     the other components of the system.
 365
 366     A general memory barrier is a partial ordering over both loads and stores.
 367
 368     General memory barriers imply both read and write memory barriers, and so
 369     can substitute for either.
 370
 371
 372And a couple of implicit varieties:
 373
 374 (5) LOCK operations.
 375
 376     This acts as a one-way permeable barrier.  It guarantees that all memory
 377     operations after the LOCK operation will appear to happen after the LOCK
 378     operation with respect to the other components of the system.
 379
 380     Memory operations that occur before a LOCK operation may appear to happen
 381     after it completes.
 382
 383     A LOCK operation should almost always be paired with an UNLOCK operation.
 384
 385
 386 (6) UNLOCK operations.
 387
 388     This also acts as a one-way permeable barrier.  It guarantees that all
 389     memory operations before the UNLOCK operation will appear to happen before
 390     the UNLOCK operation with respect to the other components of the system.
 391
 392     Memory operations that occur after an UNLOCK operation may appear to
 393     happen before it completes.
 394
 395     LOCK and UNLOCK operations are guaranteed to appear with respect to each
 396     other strictly in the order specified.
 397
 398     The use of LOCK and UNLOCK operations generally precludes the need for
 399     other sorts of memory barrier (but note the exceptions mentioned in the
 400     subsection "MMIO write barrier").
 401
 402
 403Memory barriers are only required where there's a possibility of interaction
 404between two CPUs or between a CPU and a device.  If it can be guaranteed that
 405there won't be any such interaction in any particular piece of code, then
 406memory barriers are unnecessary in that piece of code.
 407
 408
 409Note that these are the _minimum_ guarantees.  Different architectures may give
 410more substantial guarantees, but they may _not_ be relied upon outside of arch
 411specific code.
 412
 413
 414WHAT MAY NOT BE ASSUMED ABOUT MEMORY BARRIERS?
 415----------------------------------------------
 416
 417There are certain things that the Linux kernel memory barriers do not guarantee:
 418
 419 (*) There is no guarantee that any of the memory accesses specified before a
 420     memory barrier will be _complete_ by the completion of a memory barrier
 421     instruction; the barrier can be considered to draw a line in that CPU's
 422     access queue that accesses of the appropriate type may not cross.
 423
 424 (*) There is no guarantee that issuing a memory barrier on one CPU will have
 425     any direct effect on another CPU or any other hardware in the system.  The
 426     indirect effect will be the order in which the second CPU sees the effects
 427     of the first CPU's accesses occur, but see the next point:
 428
 429 (*) There is no guarantee that a CPU will see the correct order of effects
 430     from a second CPU's accesses, even _if_ the second CPU uses a memory
 431     barrier, unless the first CPU _also_ uses a matching memory barrier (see
 432     the subsection on "SMP Barrier Pairing").
 433
 434 (*) There is no guarantee that some intervening piece of off-the-CPU
 435     hardware[*] will not reorder the memory accesses.  CPU cache coherency
 436     mechanisms should propagate the indirect effects of a memory barrier
 437     between CPUs, but might not do so in order.
 438
 439        [*] For information on bus mastering DMA and coherency please read:
 440
 441            Documentation/PCI/pci.txt
 442            Documentation/DMA-API-HOWTO.txt
 443            Documentation/DMA-API.txt
 444
 445
 446DATA DEPENDENCY BARRIERS
 447------------------------
 448
 449The usage requirements of data dependency barriers are a little subtle, and
 450it's not always obvious that they're needed.  To illustrate, consider the
 451following sequence of events:
 452
 453        CPU 1           CPU 2
 454        =============== ===============
 455        { A == 1, B == 2, C = 3, P == &A, Q == &C }
 456        B = 4;
 457        <write barrier>
 458        P = &B
 459                        Q = P;
 460                        D = *Q;
 461
 462There's a clear data dependency here, and it would seem that by the end of the
 463sequence, Q must be either &A or &B, and that:
 464
 465        (Q == &A) implies (D == 1)
 466        (Q == &B) implies (D == 4)
 467
 468But!  CPU 2's perception of P may be updated _before_ its perception of B, thus
 469leading to the following situation:
 470
 471        (Q == &B) and (D == 2) ????
 472
 473Whilst this may seem like a failure of coherency or causality maintenance, it
 474isn't, and this behaviour can be observed on certain real CPUs (such as the DEC
 475Alpha).
 476
 477To deal with this, a data dependency barrier or better must be inserted
 478between the address load and the data load:
 479
 480        CPU 1           CPU 2
 481        =============== ===============
 482        { A == 1, B == 2, C = 3, P == &A, Q == &C }
 483        B = 4;
 484        <write barrier>
 485        P = &B
 486                        Q = P;
 487                        <data dependency barrier>
 488                        D = *Q;
 489
 490This enforces the occurrence of one of the two implications, and prevents the
 491third possibility from arising.
 492
 493[!] Note that this extremely counterintuitive situation arises most easily on
 494machines with split caches, so that, for example, one cache bank processes
 495even-numbered cache lines and the other bank processes odd-numbered cache
 496lines.  The pointer P might be stored in an odd-numbered cache line, and the
 497variable B might be stored in an even-numbered cache line.  Then, if the
 498even-numbered bank of the reading CPU's cache is extremely busy while the
 499odd-numbered bank is idle, one can see the new value of the pointer P (&B),
 500but the old value of the variable B (2).
 501
 502
 503Another example of where data dependency barriers might by required is where a
 504number is read from memory and then used to calculate the index for an array
 505access:
 506
 507        CPU 1           CPU 2
 508        =============== ===============
 509        { M[0] == 1, M[1] == 2, M[3] = 3, P == 0, Q == 3 }
 510        M[1] = 4;
 511        <write barrier>
 512        P = 1
 513                        Q = P;
 514                        <data dependency barrier>
 515                        D = M[Q];
 516
 517
 518The data dependency barrier is very important to the RCU system, for example.
 519See rcu_dereference() in include/linux/rcupdate.h.  This permits the current
 520target of an RCU'd pointer to be replaced with a new modified target, without
 521the replacement target appearing to be incompletely initialised.
 522
 523See also the subsection on "Cache Coherency" for a more thorough example.
 524
 525
 526CONTROL DEPENDENCIES
 527--------------------
 528
 529A control dependency requires a full read memory barrier, not simply a data
 530dependency barrier to make it work correctly.  Consider the following bit of
 531code:
 532
 533        q = &a;
 534        if (p)
 535                q = &b;
 536        <data dependency barrier>
 537        x = *q;
 538
 539This will not have the desired effect because there is no actual data
 540dependency, but rather a control dependency that the CPU may short-circuit by
 541attempting to predict the outcome in advance.  In such a case what's actually
 542required is:
 543
 544        q = &a;
 545        if (p)
 546                q = &b;
 547        <read barrier>
 548        x = *q;
 549
 550
 551SMP BARRIER PAIRING
 552-------------------
 553
 554When dealing with CPU-CPU interactions, certain types of memory barrier should
 555always be paired.  A lack of appropriate pairing is almost certainly an error.
 556
 557A write barrier should always be paired with a data dependency barrier or read
 558barrier, though a general barrier would also be viable.  Similarly a read
 559barrier or a data dependency barrier should always be paired with at least an
 560write barrier, though, again, a general barrier is viable:
 561
 562        CPU 1           CPU 2
 563        =============== ===============
 564        a = 1;
 565        <write barrier>
 566        b = 2;          x = b;
 567                        <read barrier>
 568                        y = a;
 569
 570Or:
 571
 572        CPU 1           CPU 2
 573        =============== ===============================
 574        a = 1;
 575        <write barrier>
 576        b = &a;         x = b;
 577                        <data dependency barrier>
 578                        y = *x;
 579
 580Basically, the read barrier always has to be there, even though it can be of
 581the "weaker" type.
 582
 583[!] Note that the stores before the write barrier would normally be expected to
 584match the loads after the read barrier or the data dependency barrier, and vice
 585versa:
 586
 587        CPU 1                           CPU 2
 588        ===============                 ===============
 589        a = 1;           }----   --->{  v = c
 590        b = 2;           }    \ /    {  w = d
 591        <write barrier>        \        <read barrier>
 592        c = 3;           }    / \    {  x = a;
 593        d = 4;           }----   --->{  y = b;
 594
 595
 596EXAMPLES OF MEMORY BARRIER SEQUENCES
 597------------------------------------
 598
 599Firstly, write barriers act as partial orderings on store operations.
 600Consider the following sequence of events:
 601
 602        CPU 1
 603        =======================
 604        STORE A = 1
 605        STORE B = 2
 606        STORE C = 3
 607        <write barrier>
 608        STORE D = 4
 609        STORE E = 5
 610
 611This sequence of events is committed to the memory coherence system in an order
 612that the rest of the system might perceive as the unordered set of { STORE A,
 613STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E
 614}:
 615
 616        +-------+       :      :
 617        |       |       +------+
 618        |       |------>| C=3  |     }     /\
 619        |       |  :    +------+     }-----  \  -----> Events perceptible to
 620        |       |  :    | A=1  |     }        \/       the rest of the system
 621        |       |  :    +------+     }
 622        | CPU 1 |  :    | B=2  |     }
 623        |       |       +------+     }
 624        |       |   wwwwwwwwwwwwwwww }   <--- At this point the write barrier
 625        |       |       +------+     }        requires all stores prior to the
 626        |       |  :    | E=5  |     }        barrier to be committed before
 627        |       |  :    +------+     }        further stores may take place
 628        |       |------>| D=4  |     }
 629        |       |       +------+
 630        +-------+       :      :
 631                           |
 632                           | Sequence in which stores are committed to the
 633                           | memory system by CPU 1
 634                           V
 635
 636
 637Secondly, data dependency barriers act as partial orderings on data-dependent
 638loads.  Consider the following sequence of events:
 639
 640        CPU 1                   CPU 2
 641        ======================= =======================
 642                { B = 7; X = 9; Y = 8; C = &Y }
 643        STORE A = 1
 644        STORE B = 2
 645        <write barrier>
 646        STORE C = &B            LOAD X
 647        STORE D = 4             LOAD C (gets &B)
 648                                LOAD *C (reads B)
 649
 650Without intervention, CPU 2 may perceive the events on CPU 1 in some
 651effectively random order, despite the write barrier issued by CPU 1:
 652
 653        +-------+       :      :                :       :
 654        |       |       +------+                +-------+  | Sequence of update
 655        |       |------>| B=2  |-----       --->| Y->8  |  | of perception on
 656        |       |  :    +------+     \          +-------+  | CPU 2
 657        | CPU 1 |  :    | A=1  |      \     --->| C->&Y |  V
 658        |       |       +------+       |        +-------+
 659        |       |   wwwwwwwwwwwwwwww   |        :       :
 660        |       |       +------+       |        :       :
 661        |       |  :    | C=&B |---    |        :       :       +-------+
 662        |       |  :    +------+   \   |        +-------+       |       |
 663        |       |------>| D=4  |    ----------->| C->&B |------>|       |
 664        |       |       +------+       |        +-------+       |       |
 665        +-------+       :      :       |        :       :       |       |
 666                                       |        :       :       |       |
 667                                       |        :       :       | CPU 2 |
 668                                       |        +-------+       |       |
 669            Apparently incorrect --->  |        | B->7  |------>|       |
 670            perception of B (!)        |        +-------+       |       |
 671                                       |        :       :       |       |
 672                                       |        +-------+       |       |
 673            The load of X holds --->    \       | X->9  |------>|       |
 674            up the maintenance           \      +-------+       |       |
 675            of coherence of B             ----->| B->2  |       +-------+
 676                                                +-------+
 677                                                :       :
 678
 679
 680In the above example, CPU 2 perceives that B is 7, despite the load of *C
 681(which would be B) coming after the LOAD of C.
 682
 683If, however, a data dependency barrier were to be placed between the load of C
 684and the load of *C (ie: B) on CPU 2:
 685
 686        CPU 1                   CPU 2
 687        ======================= =======================
 688                { B = 7; X = 9; Y = 8; C = &Y }
 689        STORE A = 1
 690        STORE B = 2
 691        <write barrier>
 692        STORE C = &B            LOAD X
 693        STORE D = 4             LOAD C (gets &B)
 694                                <data dependency barrier>
 695                                LOAD *C (reads B)
 696
 697then the following will occur:
 698
 699        +-------+       :      :                :       :
 700        |       |       +------+                +-------+
 701        |       |------>| B=2  |-----       --->| Y->8  |
 702        |       |  :    +------+     \          +-------+
 703        | CPU 1 |  :    | A=1  |      \     --->| C->&Y |
 704        |       |       +------+       |        +-------+
 705        |       |   wwwwwwwwwwwwwwww   |        :       :
 706        |       |       +------+       |        :       :
 707        |       |  :    | C=&B |---    |        :       :       +-------+
 708        |       |  :    +------+   \   |        +-------+       |       |
 709        |       |------>| D=4  |    ----------->| C->&B |------>|       |
 710        |       |       +------+       |        +-------+       |       |
 711        +-------+       :      :       |        :       :       |       |
 712                                       |        :       :       |       |
 713                                       |        :       :       | CPU 2 |
 714                                       |        +-------+       |       |
 715                                       |        | X->9  |------>|       |
 716                                       |        +-------+       |       |
 717          Makes sure all effects --->   \   ddddddddddddddddd   |       |
 718          prior to the store of C        \      +-------+       |       |
 719          are perceptible to              ----->| B->2  |------>|       |
 720          subsequent loads                      +-------+       |       |
 721                                                :       :       +-------+
 722
 723
 724And thirdly, a read barrier acts as a partial order on loads.  Consider the
 725following sequence of events:
 726
 727        CPU 1                   CPU 2
 728        ======================= =======================
 729                { A = 0, B = 9 }
 730        STORE A=1
 731        <write barrier>
 732        STORE B=2
 733                                LOAD B
 734                                LOAD A
 735
 736Without intervention, CPU 2 may then choose to perceive the events on CPU 1 in
 737some effectively random order, despite the write barrier issued by CPU 1:
 738
 739        +-------+       :      :                :       :
 740        |       |       +------+                +-------+
 741        |       |------>| A=1  |------      --->| A->0  |
 742        |       |       +------+      \         +-------+
 743        | CPU 1 |   wwwwwwwwwwwwwwww   \    --->| B->9  |
 744        |       |       +------+        |       +-------+
 745        |       |------>| B=2  |---     |       :       :
 746        |       |       +------+   \    |       :       :       +-------+
 747        +-------+       :      :    \   |       +-------+       |       |
 748                                     ---------->| B->2  |------>|       |
 749                                        |       +-------+       | CPU 2 |
 750                                        |       | A->0  |------>|       |
 751                                        |       +-------+       |       |
 752                                        |       :       :       +-------+
 753                                         \      :       :
 754                                          \     +-------+
 755                                           ---->| A->1  |
 756                                                +-------+
 757                                                :       :
 758
 759
 760If, however, a read barrier were to be placed between the load of B and the
 761load of A on CPU 2:
 762
 763        CPU 1                   CPU 2
 764        ======================= =======================
 765                { A = 0, B = 9 }
 766        STORE A=1
 767        <write barrier>
 768        STORE B=2
 769                                LOAD B
 770                                <read barrier>
 771                                LOAD A
 772
 773then the partial ordering imposed by CPU 1 will be perceived correctly by CPU
 7742:
 775
 776        +-------+       :      :                :       :
 777        |       |       +------+                +-------+
 778        |       |------>| A=1  |------      --->| A->0  |
 779        |       |       +------+      \         +-------+
 780        | CPU 1 |   wwwwwwwwwwwwwwww   \    --->| B->9  |
 781        |       |       +------+        |       +-------+
 782        |       |------>| B=2  |---     |       :       :
 783        |       |       +------+   \    |       :       :       +-------+
 784        +-------+       :      :    \   |       +-------+       |       |
 785                                     ---------->| B->2  |------>|       |
 786                                        |       +-------+       | CPU 2 |
 787                                        |       :       :       |       |
 788                                        |       :       :       |       |
 789          At this point the read ---->   \  rrrrrrrrrrrrrrrrr   |       |
 790          barrier causes all effects      \     +-------+       |       |
 791          prior to the storage of B        ---->| A->1  |------>|       |
 792          to be perceptible to CPU 2            +-------+       |       |
 793                                                :       :       +-------+
 794
 795
 796To illustrate this more completely, consider what could happen if the code
 797contained a load of A either side of the read barrier:
 798
 799        CPU 1                   CPU 2
 800        ======================= =======================
 801                { A = 0, B = 9 }
 802        STORE A=1
 803        <write barrier>
 804        STORE B=2
 805                                LOAD B
 806                                LOAD A [first load of A]
 807                                <read barrier>
 808                                LOAD A [second load of A]
 809
 810Even though the two loads of A both occur after the load of B, they may both
 811come up with different values:
 812
 813        +-------+       :      :                :       :
 814        |       |       +------+                +-------+
 815        |       |------>| A=1  |------      --->| A->0  |
 816        |       |       +------+      \         +-------+
 817        | CPU 1 |   wwwwwwwwwwwwwwww   \    --->| B->9  |
 818        |       |       +------+        |       +-------+
 819        |       |------>| B=2  |---     |       :       :
 820        |       |       +------+   \    |       :       :       +-------+
 821        +-------+       :      :    \   |       +-------+       |       |
 822                                     ---------->| B->2  |------>|       |
 823                                        |       +-------+       | CPU 2 |
 824                                        |       :       :       |       |
 825                                        |       :       :       |       |
 826                                        |       +-------+       |       |
 827                                        |       | A->0  |------>| 1st   |
 828                                        |       +-------+       |       |
 829          At this point the read ---->   \  rrrrrrrrrrrrrrrrr   |       |
 830          barrier causes all effects      \     +-------+       |       |
 831          prior to the storage of B        ---->| A->1  |------>| 2nd   |
 832          to be perceptible to CPU 2            +-------+       |       |
 833                                                :       :       +-------+
 834
 835
 836But it may be that the update to A from CPU 1 becomes perceptible to CPU 2
 837before the read barrier completes anyway:
 838
 839        +-------+       :      :                :       :
 840        |       |       +------+                +-------+
 841        |       |------>| A=1  |------      --->| A->0  |
 842        |       |       +------+      \         +-------+
 843        | CPU 1 |   wwwwwwwwwwwwwwww   \    --->| B->9  |
 844        |       |       +------+        |       +-------+
 845        |       |------>| B=2  |---     |       :       :
 846        |       |       +------+   \    |       :       :       +-------+
 847        +-------+       :      :    \   |       +-------+       |       |
 848                                     ---------->| B->2  |------>|       |
 849                                        |       +-------+       | CPU 2 |
 850                                        |       :       :       |       |
 851                                         \      :       :       |       |
 852                                          \     +-------+       |       |
 853                                           ---->| A->1  |------>| 1st   |
 854                                                +-------+       |       |
 855                                            rrrrrrrrrrrrrrrrr   |       |
 856                                                +-------+       |       |
 857                                                | A->1  |------>| 2nd   |
 858                                                +-------+       |       |
 859                                                :       :       +-------+
 860
 861
 862The guarantee is that the second load will always come up with A == 1 if the
 863load of B came up with B == 2.  No such guarantee exists for the first load of
 864A; that may come up with either A == 0 or A == 1.
 865
 866
 867READ MEMORY BARRIERS VS LOAD SPECULATION
 868----------------------------------------
 869
 870Many CPUs speculate with loads: that is they see that they will need to load an
 871item from memory, and they find a time where they're not using the bus for any
 872other loads, and so do the load in advance - even though they haven't actually
 873got to that point in the instruction execution flow yet.  This permits the
 874actual load instruction to potentially complete immediately because the CPU
 875already has the value to hand.
 876
 877It may turn out that the CPU didn't actually need the value - perhaps because a
 878branch circumvented the load - in which case it can discard the value or just
 879cache it for later use.
 880
 881Consider:
 882
 883        CPU 1                   CPU 2
 884        ======================= =======================
 885                                LOAD B
 886                                DIVIDE          } Divide instructions generally
 887                                DIVIDE          } take a long time to perform
 888                                LOAD A
 889
 890Which might appear as this:
 891
 892                                                :       :       +-------+
 893                                                +-------+       |       |
 894                                            --->| B->2  |------>|       |
 895                                                +-------+       | CPU 2 |
 896                                                :       :DIVIDE |       |
 897                                                +-------+       |       |
 898        The CPU being busy doing a --->     --->| A->0  |~~~~   |       |
 899        division speculates on the              +-------+   ~   |       |
 900        LOAD of A                               :       :   ~   |       |
 901                                                :       :DIVIDE |       |
 902                                                :       :   ~   |       |
 903        Once the divisions are complete -->     :       :   ~-->|       |
 904        the CPU can then perform the            :       :       |       |
 905        LOAD with immediate effect              :       :       +-------+
 906
 907
 908Placing a read barrier or a data dependency barrier just before the second
 909load:
 910
 911        CPU 1                   CPU 2
 912        ======================= =======================
 913                                LOAD B
 914                                DIVIDE
 915                                DIVIDE
 916                                <read barrier>
 917                                LOAD A
 918
 919will force any value speculatively obtained to be reconsidered to an extent
 920dependent on the type of barrier used.  If there was no change made to the
 921speculated memory location, then the speculated value will just be used:
 922
 923                                                :       :       +-------+
 924                                                +-------+       |       |
 925                                            --->| B->2  |------>|       |
 926                                                +-------+       | CPU 2 |
 927                                                :       :DIVIDE |       |
 928                                                +-------+       |       |
 929        The CPU being busy doing a --->     --->| A->0  |~~~~   |       |
 930        division speculates on the              +-------+   ~   |       |
 931        LOAD of A                               :       :   ~   |       |
 932                                                :       :DIVIDE |       |
 933                                                :       :   ~   |       |
 934                                                :       :   ~   |       |
 935                                            rrrrrrrrrrrrrrrr~   |       |
 936                                                :       :   ~   |       |
 937                                                :       :   ~-->|       |
 938                                                :       :       |       |
 939                                                :       :       +-------+
 940
 941
 942but if there was an update or an invalidation from another CPU pending, then
 943the speculation will be cancelled and the value reloaded:
 944
 945                                                :       :       +-------+
 946                                                +-------+       |       |
 947                                            --->| B->2  |------>|       |
 948                                                +-------+       | CPU 2 |
 949                                                :       :DIVIDE |       |
 950                                                +-------+       |       |
 951        The CPU being busy doing a --->     --->| A->0  |~~~~   |       |
 952        division speculates on the              +-------+   ~   |       |
 953        LOAD of A                               :       :   ~   |       |
 954                                                :       :DIVIDE |       |
 955                                                :       :   ~   |       |
 956                                                :       :   ~   |       |
 957                                            rrrrrrrrrrrrrrrrr   |       |
 958                                                +-------+       |       |
 959        The speculation is discarded --->   --->| A->1  |------>|       |
 960        and an updated value is                 +-------+       |       |
 961        retrieved                               :       :       +-------+
 962
 963
 964TRANSITIVITY
 965------------
 966
 967Transitivity is a deeply intuitive notion about ordering that is not
 968always provided by real computer systems.  The following example
 969demonstrates transitivity (also called "cumulativity"):
 970
 971        CPU 1                   CPU 2                   CPU 3
 972        ======================= ======================= =======================
 973                { X = 0, Y = 0 }
 974        STORE X=1               LOAD X                  STORE Y=1
 975                                <general barrier>       <general barrier>
 976                                LOAD Y                  LOAD X
 977
 978Suppose that CPU 2's load from X returns 1 and its load from Y returns 0.
 979This indicates that CPU 2's load from X in some sense follows CPU 1's
 980store to X and that CPU 2's load from Y in some sense preceded CPU 3's
 981store to Y.  The question is then "Can CPU 3's load from X return 0?"
 982
 983Because CPU 2's load from X in some sense came after CPU 1's store, it
 984is natural to expect that CPU 3's load from X must therefore return 1.
 985This expectation is an example of transitivity: if a load executing on
 986CPU A follows a load from the same variable executing on CPU B, then
 987CPU A's load must either return the same value that CPU B's load did,
 988or must return some later value.
 989
 990In the Linux kernel, use of general memory barriers guarantees
 991transitivity.  Therefore, in the above example, if CPU 2's load from X
 992returns 1 and its load from Y returns 0, then CPU 3's load from X must
 993also return 1.
 994
 995However, transitivity is -not- guaranteed for read or write barriers.
 996For example, suppose that CPU 2's general barrier in the above example
 997is changed to a read barrier as shown below:
 998
 999        CPU 1                   CPU 2                   CPU 3
1000        ======================= ======================= =======================
1001                { X = 0, Y = 0 }
1002        STORE X=1               LOAD X                  STORE Y=1
1003                                <read barrier>          <general barrier>
1004                                LOAD Y                  LOAD X
1005
1006This substitution destroys transitivity: in this example, it is perfectly
1007legal for CPU 2's load from X to return 1, its load from Y to return 0,
1008and CPU 3's load from X to return 0.
1009
1010The key point is that although CPU 2's read barrier orders its pair
1011of loads, it does not guarantee to order CPU 1's store.  Therefore, if
1012this example runs on a system where CPUs 1 and 2 share a store buffer
1013or a level of cache, CPU 2 might have early access to CPU 1's writes.
1014General barriers are therefore required to ensure that all CPUs agree
1015on the combined order of CPU 1's and CPU 2's accesses.
1016
1017To reiterate, if your code requires transitivity, use general barriers
1018throughout.
1019
1020
1021========================
1022EXPLICIT KERNEL BARRIERS
1023========================
1024
1025The Linux kernel has a variety of different barriers that act at different
1026levels:
1027
1028  (*) Compiler barrier.
1029
1030  (*) CPU memory barriers.
1031
1032  (*) MMIO write barrier.
1033
1034
1035COMPILER BARRIER
1036----------------
1037
1038The Linux kernel has an explicit compiler barrier function that prevents the
1039compiler from moving the memory accesses either side of it to the other side:
1040
1041        barrier();
1042
1043This is a general barrier - lesser varieties of compiler barrier do not exist.
1044
1045The compiler barrier has no direct effect on the CPU, which may then reorder
1046things however it wishes.
1047
1048
1049CPU MEMORY BARRIERS
1050-------------------
1051
1052The Linux kernel has eight basic CPU memory barriers:
1053
1054        TYPE            MANDATORY               SMP CONDITIONAL
1055        =============== ======================= ===========================
1056        GENERAL         mb()                    smp_mb()
1057        WRITE           wmb()                   smp_wmb()
1058        READ            rmb()                   smp_rmb()
1059        DATA DEPENDENCY read_barrier_depends()  smp_read_barrier_depends()
1060
1061
1062All memory barriers except the data dependency barriers imply a compiler
1063barrier. Data dependencies do not impose any additional compiler ordering.
1064
1065Aside: In the case of data dependencies, the compiler would be expected to
1066issue the loads in the correct order (eg. `a[b]` would have to load the value
1067of b before loading a[b]), however there is no guarantee in the C specification
1068that the compiler may not speculate the value of b (eg. is equal to 1) and load
1069a before b (eg. tmp = a[1]; if (b != 1) tmp = a[b]; ). There is also the
1070problem of a compiler reloading b after having loaded a[b], thus having a newer
1071copy of b than a[b]. A consensus has not yet been reached about these problems,
1072however the ACCESS_ONCE macro is a good place to start looking.
1073
1074SMP memory barriers are reduced to compiler barriers on uniprocessor compiled
1075systems because it is assumed that a CPU will appear to be self-consistent,
1076and will order overlapping accesses correctly with respect to itself.
1077
1078[!] Note that SMP memory barriers _must_ be used to control the ordering of
1079references to shared memory on SMP systems, though the use of locking instead
1080is sufficient.
1081
1082Mandatory barriers should not be used to control SMP effects, since mandatory
1083barriers unnecessarily impose overhead on UP systems. They may, however, be
1084used to control MMIO effects on accesses through relaxed memory I/O windows.
1085These are required even on non-SMP systems as they affect the order in which
1086memory operations appear to a device by prohibiting both the compiler and the
1087CPU from reordering them.
1088
1089
1090There are some more advanced barrier functions:
1091
1092 (*) set_mb(var, value)
1093
1094     This assigns the value to the variable and then inserts a full memory
1095     barrier after it, depending on the function.  It isn't guaranteed to
1096     insert anything more than a compiler barrier in a UP compilation.
1097
1098
1099 (*) smp_mb__before_atomic_dec();
1100 (*) smp_mb__after_atomic_dec();
1101 (*) smp_mb__before_atomic_inc();
1102 (*) smp_mb__after_atomic_inc();
1103
1104     These are for use with atomic add, subtract, increment and decrement
1105     functions that don't return a value, especially when used for reference
1106     counting.  These functions do not imply memory barriers.
1107
1108     As an example, consider a piece of code that marks an object as being dead
1109     and then decrements the object's reference count:
1110
1111        obj->dead = 1;
1112        smp_mb__before_atomic_dec();
1113        atomic_dec(&obj->ref_count);
1114
1115     This makes sure that the death mark on the object is perceived to be set
1116     *before* the reference counter is decremented.
1117
1118     See Documentation/atomic_ops.txt for more information.  See the "Atomic
1119     operations" subsection for information on where to use these.
1120
1121
1122 (*) smp_mb__before_clear_bit(void);
1123 (*) smp_mb__after_clear_bit(void);
1124
1125     These are for use similar to the atomic inc/dec barriers.  These are
1126     typically used for bitwise unlocking operations, so care must be taken as
1127     there are no implicit memory barriers here either.
1128
1129     Consider implementing an unlock operation of some nature by clearing a
1130     locking bit.  The clear_bit() would then need to be barriered like this:
1131
1132        smp_mb__before_clear_bit();
1133        clear_bit( ... );
1134
1135     This prevents memory operations before the clear leaking to after it.  See
1136     the subsection on "Locking Functions" with reference to UNLOCK operation
1137     implications.
1138
1139     See Documentation/atomic_ops.txt for more information.  See the "Atomic
1140     operations" subsection for information on where to use these.
1141
1142
1143MMIO WRITE BARRIER
1144------------------
1145
1146The Linux kernel also has a special barrier for use with memory-mapped I/O
1147writes:
1148
1149        mmiowb();
1150
1151This is a variation on the mandatory write barrier that causes writes to weakly
1152ordered I/O regions to be partially ordered.  Its effects may go beyond the
1153CPU->Hardware interface and actually affect the hardware at some level.
1154
1155See the subsection "Locks vs I/O accesses" for more information.
1156
1157
1158===============================
1159IMPLICIT KERNEL MEMORY BARRIERS
1160===============================
1161
1162Some of the other functions in the linux kernel imply memory barriers, amongst
1163which are locking and scheduling functions.
1164
1165This specification is a _minimum_ guarantee; any particular architecture may
1166provide more substantial guarantees, but these may not be relied upon outside
1167of arch specific code.
1168
1169
1170LOCKING FUNCTIONS
1171-----------------
1172
1173The Linux kernel has a number of locking constructs:
1174
1175 (*) spin locks
1176 (*) R/W spin locks
1177 (*) mutexes
1178 (*) semaphores
1179 (*) R/W semaphores
1180 (*) RCU
1181
1182In all cases there are variants on "LOCK" operations and "UNLOCK" operations
1183for each construct.  These operations all imply certain barriers:
1184
1185 (1) LOCK operation implication:
1186
1187     Memory operations issued after the LOCK will be completed after the LOCK
1188     operation has completed.
1189
1190     Memory operations issued before the LOCK may be completed after the LOCK
1191     operation has completed.
1192
1193 (2) UNLOCK operation implication:
1194
1195     Memory operations issued before the UNLOCK will be completed before the
1196     UNLOCK operation has completed.
1197
1198     Memory operations issued after the UNLOCK may be completed before the
1199     UNLOCK operation has completed.
1200
1201 (3) LOCK vs LOCK implication:
1202
1203     All LOCK operations issued before another LOCK operation will be completed
1204     before that LOCK operation.
1205
1206 (4) LOCK vs UNLOCK implication:
1207
1208     All LOCK operations issued before an UNLOCK operation will be completed
1209     before the UNLOCK operation.
1210
1211     All UNLOCK operations issued before a LOCK operation will be completed
1212     before the LOCK operation.
1213
1214 (5) Failed conditional LOCK implication:
1215
1216     Certain variants of the LOCK operation may fail, either due to being
1217     unable to get the lock immediately, or due to receiving an unblocked
1218     signal whilst asleep waiting for the lock to become available.  Failed
1219     locks do not imply any sort of barrier.
1220
1221Therefore, from (1), (2) and (4) an UNLOCK followed by an unconditional LOCK is
1222equivalent to a full barrier, but a LOCK followed by an UNLOCK is not.
1223
1224[!] Note: one of the consequences of LOCKs and UNLOCKs being only one-way
1225    barriers is that the effects of instructions outside of a critical section
1226    may seep into the inside of the critical section.
1227
1228A LOCK followed by an UNLOCK may not be assumed to be full memory barrier
1229because it is possible for an access preceding the LOCK to happen after the
1230LOCK, and an access following the UNLOCK to happen before the UNLOCK, and the
1231two accesses can themselves then cross:
1232
1233        *A = a;
1234        LOCK
1235        UNLOCK
1236        *B = b;
1237
1238may occur as:
1239
1240        LOCK, STORE *B, STORE *A, UNLOCK
1241
1242Locks and semaphores may not provide any guarantee of ordering on UP compiled
1243systems, and so cannot be counted on in such a situation to actually achieve
1244anything at all - especially with respect to I/O accesses - unless combined
1245with interrupt disabling operations.
1246
1247See also the section on "Inter-CPU locking barrier effects".
1248
1249
1250As an example, consider the following:
1251
1252        *A = a;
1253        *B = b;
1254        LOCK
1255        *C = c;
1256        *D = d;
1257        UNLOCK
1258        *E = e;
1259        *F = f;
1260
1261The following sequence of events is acceptable:
1262
1263        LOCK, {*F,*A}, *E, {*C,*D}, *B, UNLOCK
1264
1265        [+] Note that {*F,*A} indicates a combined access.
1266
1267But none of the following are:
1268
1269        {*F,*A}, *B,    LOCK, *C, *D,   UNLOCK, *E
1270        *A, *B, *C,     LOCK, *D,       UNLOCK, *E, *F
1271        *A, *B,         LOCK, *C,       UNLOCK, *D, *E, *F
1272        *B,             LOCK, *C, *D,   UNLOCK, {*F,*A}, *E
1273
1274
1275
1276INTERRUPT DISABLING FUNCTIONS
1277-----------------------------
1278
1279Functions that disable interrupts (LOCK equivalent) and enable interrupts
1280(UNLOCK equivalent) will act as compiler barriers only.  So if memory or I/O
1281barriers are required in such a situation, they must be provided from some
1282other means.
1283
1284
1285SLEEP AND WAKE-UP FUNCTIONS
1286---------------------------
1287
1288Sleeping and waking on an event flagged in global data can be viewed as an
1289interaction between two pieces of data: the task state of the task waiting for
1290the event and the global data used to indicate the event.  To make sure that
1291these appear to happen in the right order, the primitives to begin the process
1292of going to sleep, and the primitives to initiate a wake up imply certain
1293barriers.
1294
1295Firstly, the sleeper normally follows something like this sequence of events:
1296
1297        for (;;) {
1298                set_current_state(TASK_UNINTERRUPTIBLE);
1299                if (event_indicated)
1300                        break;
1301                schedule();
1302        }
1303
1304A general memory barrier is interpolated automatically by set_current_state()
1305after it has altered the task state:
1306
1307        CPU 1
1308        ===============================
1309        set_current_state();
1310          set_mb();
1311            STORE current->state
1312            <general barrier>
1313        LOAD event_indicated
1314
1315set_current_state() may be wrapped by:
1316
1317        prepare_to_wait();
1318        prepare_to_wait_exclusive();
1319
1320which therefore also imply a general memory barrier after setting the state.
1321The whole sequence above is available in various canned forms, all of which
1322interpolate the memory barrier in the right place:
1323
1324        wait_event();
1325        wait_event_interruptible();
1326        wait_event_interruptible_exclusive();
1327        wait_event_interruptible_timeout();
1328        wait_event_killable();
1329        wait_event_timeout();
1330        wait_on_bit();
1331        wait_on_bit_lock();
1332
1333
1334Secondly, code that performs a wake up normally follows something like this:
1335
1336        event_indicated = 1;
1337        wake_up(&event_wait_queue);
1338
1339or:
1340
1341        event_indicated = 1;
1342        wake_up_process(event_daemon);
1343
1344A write memory barrier is implied by wake_up() and co. if and only if they wake
1345something up.  The barrier occurs before the task state is cleared, and so sits
1346between the STORE to indicate the event and the STORE to set TASK_RUNNING:
1347
1348        CPU 1                           CPU 2
1349        =============================== ===============================
1350        set_current_state();            STORE event_indicated
1351          set_mb();                     wake_up();
1352            STORE current->state          <write barrier>
1353            <general barrier>             STORE current->state
1354        LOAD event_indicated
1355
1356The available waker functions include:
1357
1358        complete();
1359        wake_up();
1360        wake_up_all();
1361        wake_up_bit();
1362        wake_up_interruptible();
1363        wake_up_interruptible_all();
1364        wake_up_interruptible_nr();
1365        wake_up_interruptible_poll();
1366        wake_up_interruptible_sync();
1367        wake_up_interruptible_sync_poll();
1368        wake_up_locked();
1369        wake_up_locked_poll();
1370        wake_up_nr();
1371        wake_up_poll();
1372        wake_up_process();
1373
1374
1375[!] Note that the memory barriers implied by the sleeper and the waker do _not_
1376order multiple stores before the wake-up with respect to loads of those stored
1377values after the sleeper has called set_current_state().  For instance, if the
1378sleeper does:
1379
1380        set_current_state(TASK_INTERRUPTIBLE);
1381        if (event_indicated)
1382                break;
1383        __set_current_state(TASK_RUNNING);
1384        do_something(my_data);
1385
1386and the waker does:
1387
1388        my_data = value;
1389        event_indicated = 1;
1390        wake_up(&event_wait_queue);
1391
1392there's no guarantee that the change to event_indicated will be perceived by
1393the sleeper as coming after the change to my_data.  In such a circumstance, the
1394code on both sides must interpolate its own memory barriers between the
1395separate data accesses.  Thus the above sleeper ought to do:
1396
1397        set_current_state(TASK_INTERRUPTIBLE);
1398        if (event_indicated) {
1399                smp_rmb();
1400                do_something(my_data);
1401        }
1402
1403and the waker should do:
1404
1405        my_data = value;
1406        smp_wmb();
1407        event_indicated = 1;
1408        wake_up(&event_wait_queue);
1409
1410
1411MISCELLANEOUS FUNCTIONS
1412-----------------------
1413
1414Other functions that imply barriers:
1415
1416 (*) schedule() and similar imply full memory barriers.
1417
1418
1419=================================
1420INTER-CPU LOCKING BARRIER EFFECTS
1421=================================
1422
1423On SMP systems locking primitives give a more substantial form of barrier: one
1424that does affect memory access ordering on other CPUs, within the context of
1425conflict on any particular lock.
1426
1427
1428LOCKS VS MEMORY ACCESSES
1429------------------------
1430
1431Consider the following: the system has a pair of spinlocks (M) and (Q), and
1432three CPUs; then should the following sequence of events occur:
1433
1434        CPU 1                           CPU 2
1435        =============================== ===============================
1436        *A = a;                         *E = e;
1437        LOCK M                          LOCK Q
1438        *B = b;                         *F = f;
1439        *C = c;                         *G = g;
1440        UNLOCK M                        UNLOCK Q
1441        *D = d;                         *H = h;
1442
1443Then there is no guarantee as to what order CPU 3 will see the accesses to *A
1444through *H occur in, other than the constraints imposed by the separate locks
1445on the separate CPUs. It might, for example, see:
1446
1447        *E, LOCK M, LOCK Q, *G, *C, *F, *A, *B, UNLOCK Q, *D, *H, UNLOCK M
1448
1449But it won't see any of:
1450
1451        *B, *C or *D preceding LOCK M
1452        *A, *B or *C following UNLOCK M
1453        *F, *G or *H preceding LOCK Q
1454        *E, *F or *G following UNLOCK Q
1455
1456
1457However, if the following occurs:
1458
1459        CPU 1                           CPU 2
1460        =============================== ===============================
1461        *A = a;
1462        LOCK M          [1]
1463        *B = b;
1464        *C = c;
1465        UNLOCK M        [1]
1466        *D = d;                         *E = e;
1467                                        LOCK M          [2]
1468                                        *F = f;
1469                                        *G = g;
1470                                        UNLOCK M        [2]
1471                                        *H = h;
1472
1473CPU 3 might see:
1474
1475        *E, LOCK M [1], *C, *B, *A, UNLOCK M [1],
1476                LOCK M [2], *H, *F, *G, UNLOCK M [2], *D
1477
1478But assuming CPU 1 gets the lock first, CPU 3 won't see any of:
1479
1480        *B, *C, *D, *F, *G or *H preceding LOCK M [1]
1481        *A, *B or *C following UNLOCK M [1]
1482        *F, *G or *H preceding LOCK M [2]
1483        *A, *B, *C, *E, *F or *G following UNLOCK M [2]
1484
1485
1486LOCKS VS I/O ACCESSES
1487---------------------
1488
1489Under certain circumstances (especially involving NUMA), I/O accesses within
1490two spinlocked sections on two different CPUs may be seen as interleaved by the
1491PCI bridge, because the PCI bridge does not necessarily participate in the
1492cache-coherence protocol, and is therefore incapable of issuing the required
1493read memory barriers.
1494
1495For example:
1496
1497        CPU 1                           CPU 2
1498        =============================== ===============================
1499        spin_lock(Q)
1500        writel(0, ADDR)
1501        writel(1, DATA);
1502        spin_unlock(Q);
1503                                        spin_lock(Q);
1504                                        writel(4, ADDR);
1505                                        writel(5, DATA);
1506                                        spin_unlock(Q);
1507
1508may be seen by the PCI bridge as follows:
1509
1510        STORE *ADDR = 0, STORE *ADDR = 4, STORE *DATA = 1, STORE *DATA = 5
1511
1512which would probably cause the hardware to malfunction.
1513
1514
1515What is necessary here is to intervene with an mmiowb() before dropping the
1516spinlock, for example:
1517
1518        CPU 1                           CPU 2
1519        =============================== ===============================
1520        spin_lock(Q)
1521        writel(0, ADDR)
1522        writel(1, DATA);
1523        mmiowb();
1524        spin_unlock(Q);
1525                                        spin_lock(Q);
1526                                        writel(4, ADDR);
1527                                        writel(5, DATA);
1528                                        mmiowb();
1529                                        spin_unlock(Q);
1530
1531this will ensure that the two stores issued on CPU 1 appear at the PCI bridge
1532before either of the stores issued on CPU 2.
1533
1534
1535Furthermore, following a store by a load from the same device obviates the need
1536for the mmiowb(), because the load forces the store to complete before the load
1537is performed:
1538
1539        CPU 1                           CPU 2
1540        =============================== ===============================
1541        spin_lock(Q)
1542        writel(0, ADDR)
1543        a = readl(DATA);
1544        spin_unlock(Q);
1545                                        spin_lock(Q);
1546                                        writel(4, ADDR);
1547                                        b = readl(DATA);
1548                                        spin_unlock(Q);
1549
1550
1551See Documentation/DocBook/deviceiobook.tmpl for more information.
1552
1553
1554=================================
1555WHERE ARE MEMORY BARRIERS NEEDED?
1556=================================
1557
1558Under normal operation, memory operation reordering is generally not going to
1559be a problem as a single-threaded linear piece of code will still appear to
1560work correctly, even if it's in an SMP kernel.  There are, however, four
1561circumstances in which reordering definitely _could_ be a problem:
1562
1563 (*) Interprocessor interaction.
1564
1565 (*) Atomic operations.
1566
1567 (*) Accessing devices.
1568
1569 (*) Interrupts.
1570
1571
1572INTERPROCESSOR INTERACTION
1573--------------------------
1574
1575When there's a system with more than one processor, more than one CPU in the
1576system may be working on the same data set at the same time.  This can cause
1577synchronisation problems, and the usual way of dealing with them is to use
1578locks.  Locks, however, are quite expensive, and so it may be preferable to
1579operate without the use of a lock if at all possible.  In such a case
1580operations that affect both CPUs may have to be carefully ordered to prevent
1581a malfunction.
1582
1583Consider, for example, the R/W semaphore slow path.  Here a waiting process is
1584queued on the semaphore, by virtue of it having a piece of its stack linked to
1585the semaphore's list of waiting processes:
1586
1587        struct rw_semaphore {
1588                ...
1589                spinlock_t lock;
1590                struct list_head waiters;
1591        };
1592
1593        struct rwsem_waiter {
1594                struct list_head list;
1595                struct task_struct *task;
1596        };
1597
1598To wake up a particular waiter, the up_read() or up_write() functions have to:
1599
1600 (1) read the next pointer from this waiter's record to know as to where the
1601     next waiter record is;
1602
1603 (2) read the pointer to the waiter's task structure;
1604
1605 (3) clear the task pointer to tell the waiter it has been given the semaphore;
1606
1607 (4) call wake_up_process() on the task; and
1608
1609 (5) release the reference held on the waiter's task struct.
1610
1611In other words, it has to perform this sequence of events:
1612
1613        LOAD waiter->list.next;
1614        LOAD waiter->task;
1615        STORE waiter->task;
1616        CALL wakeup
1617        RELEASE task
1618
1619and if any of these steps occur out of order, then the whole thing may
1620malfunction.
1621
1622Once it has queued itself and dropped the semaphore lock, the waiter does not
1623get the lock again; it instead just waits for its task pointer to be cleared
1624before proceeding.  Since the record is on the waiter's stack, this means that
1625if the task pointer is cleared _before_ the next pointer in the list is read,
1626another CPU might start processing the waiter and might clobber the waiter's
1627stack before the up*() function has a chance to read the next pointer.
1628
1629Consider then what might happen to the above sequence of events:
1630
1631        CPU 1                           CPU 2
1632        =============================== ===============================
1633                                        down_xxx()
1634                                        Queue waiter
1635                                        Sleep
1636        up_yyy()
1637        LOAD waiter->task;
1638        STORE waiter->task;
1639                                        Woken up by other event
1640        <preempt>
1641                                        Resume processing
1642                                        down_xxx() returns
1643                                        call foo()
1644                                        foo() clobbers *waiter
1645        </preempt>
1646        LOAD waiter->list.next;
1647        --- OOPS ---
1648
1649This could be dealt with using the semaphore lock, but then the down_xxx()
1650function has to needlessly get the spinlock again after being woken up.
1651
1652The way to deal with this is to insert a general SMP memory barrier:
1653
1654        LOAD waiter->list.next;
1655        LOAD waiter->task;
1656        smp_mb();
1657        STORE waiter->task;
1658        CALL wakeup
1659        RELEASE task
1660
1661In this case, the barrier makes a guarantee that all memory accesses before the
1662barrier will appear to happen before all the memory accesses after the barrier
1663with respect to the other CPUs on the system.  It does _not_ guarantee that all
1664the memory accesses before the barrier will be complete by the time the barrier
1665instruction itself is complete.
1666
1667On a UP system - where this wouldn't be a problem - the smp_mb() is just a
1668compiler barrier, thus making sure the compiler emits the instructions in the
1669right order without actually intervening in the CPU.  Since there's only one
1670CPU, that CPU's dependency ordering logic will take care of everything else.
1671
1672
1673ATOMIC OPERATIONS
1674-----------------
1675
1676Whilst they are technically interprocessor interaction considerations, atomic
1677operations are noted specially as some of them imply full memory barriers and
1678some don't, but they're very heavily relied on as a group throughout the
1679kernel.
1680
16a Any atomic
operation reat CPmodifiesome ofste in thmory accndeturns
1586
1586Co(p_mb() ion theach deraf the sttuallyperation re(th them  excepon reofa href="Documentation/memory-barriers.txt#L1681" id="L1674" class="line" name="L1586">1586quexy icilock;
perations.
16scon/memory-barriers.txt#L1680" id="L1680" class="li37504                   3M)561" iss.txtludne" name="L1517">1517
1486LOCKS VS I/O ACCESSES
<6memory-bar6iers.txt#L1587" id="L15876 clas68id="L1657" clxchgine" name="L1657">1657        STORE waiter->ore {
1657        STORE waiter->o#39;re verntation/memory-barriers.t6t#L1569" id="L1589" on.
a _cmpxchgine" name="L1657">1657        STORE waiter->oation/memo href="Documentation/memo6y-bar6iers.txt#L1590on.
a _txt_"L1672ine" name="L1657">1657        STORE waiter->ist_head w6iters;
1657        STORE waiter->i CPmodifieemory-barriers.txt#L1592"6id="L6592" class="lion.
a _add_"L1672ine" name="L1657">1657        STORE waiter->i new)mply iers.txt#L1593" id="L15936 clas6922" class="lion.
a _sub_"L1672ine" name="L1657">1657        STORE waiter->if the sttuef="Documentation/memory-6arrie6s.txt#L1594" ion.
a _txt_ id_testine" name="L1657">1657        STORE waiter->i
16scost;
1657        STORE waiter->iof waitin6*task;
1657        STORE waiter->iemory-bar6emory-barriers.txt#L1597"6id="L6597" class="lion.
a _add_neg71657        STORE waiter->ire {
1657        STORE waiter->i#39;re ver up_read() or up_write() 6uncti6====
1657        STORE waiter->iation/memoiers.txt#L1600" id="L16006 clas600" id="L1500"test_ id_tion/_bitine" name="L1657">1657        STORE waiter-&g7er from th7s waiter's record to 7now a7L1501" id="L15test_ id_thange_bitine" name="L1657">1657        STORE waiter-&g7e1 from th7smory-barriers.txt#L1592"7riers70"line" name="L1672">1672
1673" class-.txt#" id= class-.txt#" name="L1672">1672
1672
1680
1486LOCKS VS I/O ACCESSES
<7memory-bar7iers.txt#L1607" id="L16077 clas7="line" name="L1607">1607 (4) call wake_up_proce7s() on the7task; and
1607 (4) call wake_up_proce7s8) on the7tup_read() or up_write() 7 clas7="linel wake_uf="Docry-barb5/memory-b Ls="l>1673" cclassclasssid=" class-.txt#" name="L1672">1672
1517
1611In other words, it has 7o perform 7his sequence of events:
<7 href7192" class="lion.
a _setine" name="L1657">1657        STORE waiter-&g7memory-bar7iers.txt#L1613" id="L16137 clas711503" id="L150et_bitine" name="L1657">1657        STORE waiter-&g7list.next;71657        STORE waiter-&g7task;
1657        STORE waiter-&g7;task;
1486LOCKS VS I/O ACCESSES
<7ref="Docum7ntation/memory-barriers.t7t#L1677" id=W="L1674tion/meapentpr6" c " class="3" class="line shref="DocmemorifDof="Docum" name="L1486">1486LOCKS VS I/O ACCESSES
<7r() on the7entation/memory-barriers.7xt#L1718" id href="_ory-barrtion/_bitinry-b Lnumenta)e" name="L1680">1680
1619and if any of these ste7s occur ou7 of order, then the whole7thing71"line" name="L1600">1600 (1) read the next poin7cumentatio7/memory-barriers.txt#L1627" id=7L1621"ref=f="Documenalsofdo4" id="#L1678(4) ca l wake_uf=#L1579"-barss="lin " class=" name="L1600">1600 (1) read the next poin7c perform 7iers.txt#L1622" id="L16227 clas7="line"L1678" class="lu to
1600 (1) read the next poin7cemory-bar7ed the semaphore lock, th7 wait7r doesLnumenta)e" name="L1517">1517
1654        LOAD waiter->7e the reco7d is on the waiter's 7tack,72-barriers.txton.
a _addine" name="L1657">1657        STORE waiter-&g7leared _be7ore_ the next pointer in 7he li72ory-barriers.on.
a _subine" name="L1657">1657        STORE waiter-&g7lef="Docum7the waiter and might clob7er th7297" class="lion.
a _incine" name="L1657">1657        STORE waiter-&g7l() on the7 a chance to read the nex7 poin72/memory-barrion.
a _detine" name="L1657">1657        STORE waiter-&g7lemory-bar7iers.txt#L1629" id="L16297 clas7="line" name="L1629">1629Consider then what migh7 happen to7the above sequence of eve7ts:
<7 href=Ifcumentation/mmemory-b c291607 (4) call wake_up_proce7memory-bar7iers.txt#L1631" id="L16317 clas7="linel wake_uf=unlid=the
1680
1672
1626another CPU might start7          7     down_xxx()
1626another CPU might start7  the reco7     Queue waiter
1678some don't, but the7          7     Sleep
1680
1607 (4) call wake_up_proce7task;
1607 (4) call wake_up_proce7temory-bar7ref="Documentation/memory7barri7rs.txtdotatio8(4) ca" class="l9" idli375pr6mi1607 (4) call wake_up_proce7thappen to7     Woken up by other ev7nt
1680
1611In other words, it has 7          7     Resume processing
1607 (4) call wake_up_proce7          7     down_xxx() returns
<7 href74he barrier
1610
1654        LOAD waiter->7          7     foo() clobbers *wait7r
1517
1486LOCKS VS I/O ACCESSES
<7list.next;71657        STORE waiter-&g7href="Docu7entation/memory-barriers.7xt#L1748" id="L1648"tion/_bitclass="lne" name="L1657">1657        STORE waiter-&g7hemory-bar7iers.txt#L1649" id="L16497 clas7cumentation/me__tion/_bitclass="lne" name="L1657">1657        STORE waiter-&g7hhappen to7semaphore lock, but then 7he do7="line" name="L1550">1550
1586
1586
1570
1654        LOAD waiter->7list.next;71586
1586
1626another CPU might start7;task;
1570
1629Consider then what migh7href="Docu7entation/memory-barriers.7xt#L1760" id="Documentation/meon.
a _opnet mid="L1552" class="line" name="L1552">1552
1661In this case, the barri7r makes a 7uarantee that all memory 7ccess76"line" name="L1672">1672
1672
1672
1565 (*) Atomic operations.7mplete.
1565 (*) Atomic operations.7mist.next;7iers.txt#L1667" id="L16677 clas7="lineriers.0f<3" clasli3s="line1 T37" ntroltclass="ss="lief="Dodr/verarrier59"ocumen" name="L1565">1565 (*) Atomic operations.7mtask;
1680
1569 (*) Interrupts.
1569 (*) Interrupts.
1679kernel.
1679kernel.
1577synchronisation problem7f="Documen7ation/memory-barriers.txt7L167477ation0" 6" id="L13" class="line" name="L1621">1621
1575When there's a syst7memory-bar7iers.txt#L1676" id="L16767 clas7="lineInn/memory-barLinux.txt#L1, I/O.shref="Docd6" c9" clason/meapentpr6" c ref="D-b" name="L1600">1600 (1) read the next poin7lly interp7ocessor interaction consi7erati7ns, at cl73"ocu-7ylass=cuf"bs.txt#547" cl)"Documory="L16hL1613" cklaylass=ef="Doc" name="L1600">1600 (1) read the next poin7ltask;
1600 (1) read the next poin7're ve7y heavily relied on as a 7roup 7hroughmemory-"L1678" class="lu of="Docum,the
1586
1517
16a Any atomic
operation re7t CPmodifi7some ofste in thmory accn7eturn7
1678some don't, but the7r new)mply7ieso SMP k-nsidion/malene7al SM781503" id="79"e lo_ ie_ id="L167dr/verscli37s.shref="Docmemor.txt#miowbs.tm"linbe" name="L1577">1577synchronisation problem7af the stt7allyperation re(th them  7xcepo78riers.txt#issocumpr6oumentlass="mory-barc47"3cs.t"Documee" name="L1621">1621
1575When there's a syst7 of waitin7 processes:
1575When there's a syst7 ly interp7iers.txt#L1587" id="L15877 clas78id="L1657"relaxio8(4) ca"riarritentpertierDo"L165_m.txon.ry_8(4) ca" class="l952" name="L1679">1679kernel.
1621
1569 (*) Interrupts.
1552
16a Any atomic
operation re7i CPmodifi7emory-barriers.txt#L1592"7id="L79"line" name="L1672">1672
1672
1672
1575When there's a syst7iof waitin7*task;
1679kernel.
1600 (1) read the next poin7ire {
1552
1569 (*) Interrupts.
1607 (4) call wake_up_proce8er from th8s waiter's record to 8now a8L1501"L1612oryss="mor),cclassclentatio147"3cs.t and
1586
1586
1600 (1) read the next poin8m3mory-bar8if="Documentation/memory-8href=8Documeilass="liti"linetxt#mittnor8" ation/m651" iutxeriers.curr167eilass="litL1606" i" name="L1600">1600 (1) read the next poin8m4mory-bar8it;
1610
1486LOCKS VS I/O ACCESSES
<8memory-bar8iers.txt#L1607" id="L16078 clas8="lineHmentatioid="L167s="sr/veraument/cumeal"mory- css=ss.txneto158dass="ltaoDosmai" name="L1600">1600 (1) read the next poin8m7mory-bar8iers.txt#L1598" id="L15988tatio8/memoraddrrritregisiers.txta-barriregisiers.txfass="ldr/ver/memoryc552"eal"smentrs.t158d" name="L1600">1600 (1) read the next poin8m8mory-bar8iup_read() or up_write() 8 clas8="lineu to
<"Lass="li-disable>167cemory-bna hDodr/ver/memory-bass="litL1hrlnlary-bnvoky-e" name="L1517">1517
1550
1550
1657        STORE waiter-&g8memory-bar8iers.txt#L1613" id="L16138 clas811503" id="L15547" w(DATA, yne" name="L1657">1657        STORE waiter-&g8m3mory-bar81550
1646        LOAD waiter->8;task;
1657        STORE waiter-&g8memory-bar8ntation/memory-barriers.t8t#L1687" id="L1617" q = id="w(DATAne" name="L1657">1657        STORE waiter-&g8m7mory-bar8entation/memory-barriers.8xt#L1818" id="L1618"646" -bass="liline" name="L1646">1646        LOAD waiter->8;8mory-bar8iers.txt#L1619" id="L16198 clas8="line" name="L1619">1619and if any of these ste8s occur ou8 of order, then the whole8thing819f="Dref=st552mentrs.tbarriregisierory-barriers.t1663" clas"DooL157t552mentrs." name="L1619">1619and if any of these ste8cumentatio8/memory-barriers.txt#L1628" id=8L1621"addrrritregisiersif/memory-barulessf="Dtuffass167iers.taxioe" name="L1517">1517
1622Once it has queued itse8cemory-bar8ed the semaphore lock, th8 wait821503" id="L15id="L1*ADDR = 3,5id="L1*ADDR = 4,5id="L1*DATA = y, q = d="L1*DATA" name="L1622">1622Once it has queued itse8c3mory-bar8 waits for its task point8r to 82"line" name="L1654">1654        LOAD waiter->8e the reco8d is on the waiter's 8tack,82"line" name="L1575">1575When there's a syst8leared _be8ore_ the next pointer in 8he li82ory-bIf/memory-barulessf="Ds.taxioy-barm"linbe he ">1dass="lref="Docud6" ci="L16-bi" name="L1600">1600 (1) read the next poin8lef="Docum8the waiter and might clob8er th8297" c-bass="litdisablef="Documeu="L1ntakriern/memoryi7cemor="L1ilassntave6"L15" name="L1575">1575When there's a syst8l() on the8 a chance to read the nex8 poin82/memoriarriocuxt#L161moriecss=-bass="lit-cemorid="Lversat-cunlid=tmemorss="-b" name="L1600">1600 (1) read the next poin8lemory-bar8iers.txt#L1629" id="L16298 clas8="line" class="rrier
1610
1550
1550
1550
1600 (1) read the next poin8          8     down_xxx()
1680
1575When there's a syst8          8     Sleep
1486LOCKS VS I/O ACCESSES
<8="Document8tion/memory-barriers.txt#81637"83"lineA simientasitu
1600 (1) read the next poin8task;
1600 (1) read the next poin8temory-bar8ref="Documentation/memory8barri8rs.txtlikelyDo"L165"Lass="li-disabl3" cli37s.shref="Docmemor8" L1664" clamemory-be" name="L1621">1621
1550
1611In other words, it has 8          8     Resume processing
1633                       8          8     down_xxx() returns
<8 href84he baKERNEL"I/O.BARRIER EFFECT5" name="L1672">1672
1633                       8  the reco8     foo() clobbers *wait8r
1575When there's a syst8
1600 (1) read the next poin8list.next;81517
1517
1517
1550
1550
1550
1586
1586
1575When there's a syst8m1550
1550
1627stack before the up*() 8memory-bar8ntation/memory-barriers.t8t#L1689" id="L1653" clasmti,a="Doicuent="linersosc ion/mn/ne he
1550
1570
1661In this case, the barri8r makes a 8uarantee that all memory 8ccess8692" class=Aef="Docuentrsry-spa="L="L1579" id=""ynchronousi(are167f386)f="Do" name="L1550">1550
1600 (1) read the next poin8aemory-bar8he system.  It does _not_8guara8632" class=n/nee" name="L1570">1570
1565 (*) Atomic operations.8mplete.
1565 (*) Atomic operations.8mist.next;8iers.txt#L1667" id="L16678 clas8="line" name="L1667">1667On a UP system - where 8mtask;
1586quexy icilock;
peration8aking sure8the compiler emits the in8truct86" id="L1653" clasemorI/O. and
1565 (*) Atomic operations.8mhappen to8ening in the CPU.  Since 8here&86"line" name="L1550">1550
1517
1672
1575When there's a syst8f="Documen8ation/memory-barriers.txt8L16748732" class=l
1575When there's a syst8f the reco8ation/memory-barriers.txt8L167587.txt#L1615  f3"od e load
1575When there's a syst8fplete.
1575When there's a syst8fist.next;8ocessor interaction consi8erati87id="L1657"MTRRtregisierne" name="L1570">1570
1517
1626another CPU might start8tation/mem8ry-barriers.txt#L1680" id8"L168870" id="L16y-bvidmor8mentation/mocusbcion/memo.txtefetcha="li" id="e" name="L1552">1552
16a Any atomic
operation re8t CPmodifi8some ofste in thmory accn8eturn8892" class=Hmentatiobnassmediaca"ha#dwL15/ehlass=cua PCI="ridgn)"="L1indulgerie" name="L1586">1586
1586
1586
1552
1486LOCKS VS I/O ACCESSES
<8 ly interp8iers.txt#L1587" id="L15878 clas88id="L1657"[*] NOTE!"Dttss="mory- cliad eromon/memory-li3s="lis=cu/cum547"tbna 9"-ba" name="L1486">1486LOCKS VS I/O ACCESSES
<8 task;
1600 (1) read the next poin8.#39;re ve8ntation/memory-barriers.t8t#L1589" id="L1589" oexas="le" name="L1552">1552
1550
1550
1552
1673ATOMIC OPERATIONS
1575When there's a syst8i
16sc8st;
1552
1486LOCKS VS I/O ACCESSES
<8iemory-bar8emory-barriers.txt#L1597"8id="L8597" cl(*)5id="X_s.taxio()" name="L1486">1486LOCKS VS I/O ACCESSES
<8itask;
1517
1486LOCKS VS I/O ACCESSES
<8iation/mem8iers.txt#L1600" id="L16008 clas800" id="L15"Do. B="LwL15/clentatireti"liniI/O.id="t="DocumLavails="le" name="L1552">1552
16a Any atomic
operation re9e1 from th9smory-barriers.txt#L1592"9riers901menta(*)5"oid="X(),riow47" X()" name="L1681">16a Any atomic
operation re9e2 from th9sers.txt#L1593" id="L15939 clas90"line" name="L1673">1673ATOMIC OPERATIONS
1673ATOMIC OPERATIONS
1552
1486LOCKS VS I/O ACCESSES
<9memory-bar9iers.txt#L1607" id="L16079 clas9="line" name="L1607">1607 (4) call wake_up_proce9m7mory-bar9iers.txt#L1598" id="L15989tatio9/memor33" id="L1633" class="line3" class="line" name="L1633">1633                       9m8mory-bar9iup_read() or up_write() 9 clas9="lineASSUMED MINIMUM EXECU"lin ORDERING MODEL" name="L1633">1633                       9m9mory-bar9iers.txt#L1600" id="L16009ct.
<90"line33" id="L1633" class="line3" class="line" name="L1633">1633                       9memory-bar9iers.txt#L1611" id="L16119 clas9="line" name="L1611">1611In other words, it has 9m1 from th9his sequence of events:
<9 href9192" cIt"ocumentt#Lhe ">1dass="lbarrienlassrs.t1611In other words, it has 9m2 from th9iers.txt#L1613" id="L16139 clas911503"mainta;son/meapee664"cecoryentgram="linalitycat all
1611In other words, it has 9m3mory-bar91600 (1) read the next poin9m4mory-bar9ef="Documentation/memory-9arrie9s.txt#frv)f=#L1579"ad
1daiern/me" name="L1600">1600 (1) read the next poin9m5mory-bar9ref="Documentation/memory9barri9rs.txtoryrrch-tatiofa hcodle" name="L1552">1552
1607 (4) call wake_up_proce9m7mory-bar9entation/memory-barriers.9xt#L1917xxx()
1607 (4) call wake_up_proce9m8mory-bar9iers.txt#L1619" id="L16199 clas9="line166eam=iecssabe
1600 (1) read the next poin9s occur ou9 of order, then the whole9thing919f="Df"1669" claLriers.t166eam=umenta/memoss=sarline "L1669" claxt"L1650"ao" name="L1550">1550
1575When there's a syst9c perform 9iers.txt#L1622" id="L16229 clas9="line"L1669" cla5may y-bared;Lriementaawe
1575When there's a syst9c2 from th9ed the semaphore lock, th9 wait921503""linalityc1552
1654        LOAD waiter->9e the reco9d is on the waiter's 9tack,92-barri[*] Sobar"L1669" classhave6mbarassaxtmne ementau-7ylass=cuthangmory-ba" name="L1654">1654        LOAD waiter->9e5mory-bar9ore_ the next pointer in 9he li92ory-barrieooL1i cla5codls,uthangmoryregisier="-b ihangmoryaL1678"-cemordifry-bao" name="L1550">1550
1552
1517
1550
1600 (1) read the next poin9memory-bar9iers.txt#L1631" id="L16319 clas9="lineimmedia c valu5/"Laoon/memory-regisier,a hDofirstL="L1579dis158d de" name="L1552">1552
1672
1673ATOMIC OPERATIONS
1dass="liers.txt#ry-baridt#L16"ineeil1669" cla" name="L1607">1607 (4) call wake_up_proce9  the reco9     Queue waiter
1607 (4) call wake_up_proce9 5mory-bar9     Sleep
1552
1607 (4) call wake_up_proce9task;
1517
1633                       9thappen to9     Woken up by other ev9nt
1550
1633                       9          9     Resume processing
1672
1550
1550
1552
1486LOCKS VS I/O ACCESSES
<9list.next;91486LOCKS VS I/O ACCESSES
<9lask;
1486LOCKS VS I/O ACCESSES
<9lemory-bar9iers.txt#L1649" id="L16499 clas9cumentrrier
1486LOCKS VS I/O ACCESSES
<9lhappen to9semaphore lock, but then 9he do9="line(#L1681"rrier
1517
1611In other words, it has 9l         9iers.txt#L1652" id="L16529 clas9592" class="liiiii646"---txt#i---lines="liiiii:"liiiii646"----------- ML1678"-----------line" name="L1646">1646        LOAD waiter->9l         9ert a general SMP memory 9arrie9522" class="liiiiiiiiiiiiiiiiiiiiiiiiiiie" name="L1517">1517
1517
1517
1517
1517
1517
1517
1517
1517
1517
1517
1517
1517
1517
1517
1517
1517
1517
1517
1517
1673ATOMIC OPERATIONS
1486LOCKS VS I/O ACCESSES
<9f the reco9ation/memory-barriers.txt9L167597.txt#xt#i8m="lissocumi7csiarribarm"L1have66" i s61626another CPU might start9fplete.
1626another CPU might start9fist.next;9ocessor interaction consi9erati97id="Lmentaaion/m=rrrienlars dDsiarrirs.t15chi"cohy-bary="Lihanismrerriermigr" c t i" name="L1626">1626another CPU might start9ftask;
1570
1619and if any of these ste9tation/mem9ry-barriers.txt#L1680" id9"L168979f="Dref=xt#ic552"="L1execl7et#l1669" classiecssabe
1619and if any of these ste9memory-bar9iers.txt#L1681" id="L16819 clas9="lineexpntanorentgram="linalityc="Docuumentt#L="inta;s de  Sobarory-bar#l1669" clas" name="L1619">1619and if any of these ste9m makes a 9some ofste in thmory accn9eturn9892" cid="L1tecliad bi157t552m and
1619and if any of these ste9mppen befo9ieso SMP k-nsidion/malene9al SM981503"aef="Docuentbeuxt#L161mo.56" i c552"="L1pla="Ltefs="ie rs.tqueue iecssabe
1619and if any of these ste9m="Documen9allyperation re(th them  9xcepo98riersit5rrshis,m=nd." ntinueLexecl73o iutxeritatisLlasceo88" waimid="Lss=-b1669" cla" name="L1607">1607 (4) call wake_up_proce9r the reco9n/memory-barriers.txt#L1690" id984" id537" rsletee" name="L1570">1570
1486LOCKS VS I/O ACCESSES
<9 ly interp9iers.txt#L1587" id="L15879 clas98id="LWm="l=L1681"rrier
1486LOCKS VS I/O ACCESSES
<9 task;
1678some don't, but the9.#39;re ve9ntation/memory-barriers.t9t#L1599" id=-bare
1678some don't, but the9.ation/mem9 href="Documentation/memo9y-bar989f="Df"ers.tmhref=e" name="L1552">1552
16a Any atomic
operation re9i CPmodifi9emory-barriers.txt#L1592"9id="L9592" c[!]LML1678"rrier
16a Any atomic
operation re9ippen befo9iers.txt#L1593" id="L15939 clas99"liners.iryown9liads bi157t552sid="Lfcumenthadtation/" ciecentgram=remore" name="L1680">1680
1654        LOAD waiter->9i
16sc9st;
1654        LOAD waiter->9iplete.
1600 (1) read the next poin9iemory-bar9emory-barriers.txt#L1597"9id="L9597" cthocmemcoryrny6tation/d" id="LcommuntattclaLri1669" classn/mext#im"L1havee" name="L1680">1680
1517
1569 (*) Interrupts.
1569 (*) Interrupts.
 name="L1569">1569 (*) Interrupts.
20e"line" name="L1672">1672
1626another CPU might star20e3 from t20ef="Documentation/memory20ef=>20e3" id15chiscf="Dexpntanorentbeucohy-bat,the
1626another CPU might star20e4 from t20et;
1626another CPU might star20e5 from t20etask;
1626another CPU might star20e6 from t20emory-barriers.txt#L159720emo>20e97" cbecobara"Dar167eilon/memory-e
1680
1517
1569 (*) Interrupts.
1486LOCKS VS I/O ACCESSES
201r from t20iers.txt#L1611" id="L16120ier>20ie" idh=cua pairyofu="Dtio
lydarri15chisc(1517
1672
1517
20i32" class="liiiiiiiiiiiiieiiiiiiiiiiiiiiiiiiiiiiiiii+--------+" name="L1517">1517
20i42" class="liiiiiiiiiiiiieiiiiii+---------+iiiiiiiii|L1615" i|" name="L1517">1517
20i5txt#L1615" i+--------+#L:L+---line|=C5chiaA |646"-------line|=1615" i|" name="L1517">1517
1517
1517
1517
1517
1517
1517
1517
1517
1517
1517
1517
1517
1517
1517
1517
20i"line" name="L1672">1672
1517
1654        LOAD waiter-&g20i4 from t20     Queue waiter
20i.txt#L(*)5axtmdd-numb67ed615chi"ock,L="L1579in9c5chi A,9c5chi Ct r5barm"L17trie5bi" name="L1626">1626another CPU might star2035 from t20     Sleep
1646        LOAD waiter-&g20i6 from t20tion/memory-barriers.txt20tio>20i"line" name="L1607">1607 (4) call wake_up_proc20i7 from t20ef="Documentation/memory20ef=>20i7txt#L(*)5axtev16-numb67ed615chi"ock,L="L1579in9c5chi B,9c5chi Dt r5barm"L17trie5bi" name="L1626">1626another CPU might star2038 from t20ref="Documentation/memor20ref>20i8txt#L1615re"L1667eilonothere" name="L1646">1646        LOAD waiter-&g20i9 from t20     Woken up by other e20   >20i"line" name="L1550">1550
1550
1550
1646        LOAD waiter-&g2043 from t20     call foo()
20c"line" name="L1654">1654        LOAD waiter-&g2044 from t20     foo() clobbers *wai20   >20c.txt#L(*)5tatioc5chi h=cua queue ry- and
1486LOCKS VS I/O ACCESSES
20c5 from t20ocumentation/memory-barr20ocu>20c5txt#L1615 9"-binta;socohy-bary=at al0" 5re"o"ory-barmhref=e" name="L1646">1646        LOAD waiter-&g2046 from t201607 (4) call wake_up_proc2047 from t20entation/memory-barriers20ent>20c7txt#L(*)5thi"cohy-bary=queue is1ocus"lussnorbytnass=l9liads - cli"ocuslmo="y" name="L1626">1626another CPU might star2048 from t20iers.txt#L1649" id="L16420ier>20c8txt#L1615pre"167eilon/me15chi,tev165thclasobarrienum67rrory-barqueue -ba" name="L1486">1486LOCKS VS I/O ACCESSES
20c9 from t20semaphore lock, but then20sem>20c0" id="L16youm67itati"=mentaursosc liadse" name="L1680">1680
1607 (4) call wake_up_proc2051 from t20iers.txt#L1652" id="L16520ier>20s12" cImagck,xt"L16,a8m="lnwor547" scf="D="memoxt hDofirstLion,sat alai547" "rrier
<" name="L1607">1607 (4) call wake_up_proc2052 from t20ert a general SMP memory20ert>20s27" cbetw" idrs.mr8" L1664" cla8m="ln/eyhrrie1a"Docum8" id=or t attxt#/memoryc5chisrie" name="L1586">1586
1517
20s"line" name="L1565">1565 (*) Atomic operations20s5 from t20ef="Documentation/memory20ef=>20s5txt#L1615" i1565 (*) Atomic operations20s6 from t20ation/memory-barriers.tx20ati>20s6txt#L1615" ie3" class="lineie3" class="lineie3" class="linelass="line3" class="line" name="L1633">1633                      20s7 from t20ref="Documentation/memor20ref>20s72" class="liiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiuie3 0, vie3 1idhreeie3 &u, qie3 &u" name="L1633">1633                      20s8 from t20ntation/memory-barriers.20nta>20s82" class="livie 2e" name="L1646">1646        LOAD waiter-&g2059 from t20entation/memory-barriers20ent>20s92" class="lismp_wmb();iiiiiiiiiiiiiiiiiiiiiiMake tureaihangom8" v is1visi="liby-bar" name="L1646">1646        LOAD waiter-&g206r from t20iers.txt#L1661" id="L16620ier>20ie2" class="liiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiaihangom8" p" name="L1646">1646        LOAD waiter-&g2061 from t20uarantee that all memory20uar>20i92" class="li646"A:modify v=2lines="liiiiiiiiiiiiiiv is1ocw9in9c5chi A exclusiveti" name="L1673">1673ATOMIC OPERATIONS
20i22" class="lieie &ve" name="L1646">1646        LOAD waiter-&g2063 from t20he system.  It does _not20he >20i32" class="li646"B:modify p=&vlines="liiiiiiiiiiiiip is1ocw9in9c5chi B exclusiveti" name="L1673">1673ATOMIC OPERATIONS
20i"line" name="L1565">1565 (*) Atomic operations2065 from t20href="Documentation/memo20hre>20i5e ba" i "47" "=L1681"rrier
1550
1550
1517
1569 (*) Interrupts.
20i9txt#L1615" i1565 (*) Atomic operations207r from t20ring logic will take car20rin>20ritxt#L1615" ie3" class="lineie3" class="lineie3" class="linelass="line3" class="line" name="L1633">1633                      2071 from t20iers.txt#L1672" id="L16720ier>20r92" class="li..e" name="L1680">1680
1646        LOAD waiter-&g2073 from t20ation/memory-barriers.tx20ati>20r32" class="liiiiiiiiiiiiiiiiixie *qe" name="L1646">1646        LOAD waiter-&g2074 from t20ation/memory-barriers.tx20ati>20r"line" name="L1565">1565 (*) Atomic operations2075 from t20iers.txt#L1676" id="L16720ier>20r5e ba" i dbov6 pairyofuid="cu="L1umen failc8" ation/miecbarrexpntanorremor,s=cut i" name="L1626">1626another CPU might star20r6 from t20ocessor interaction cons20oce>20r6" id15chiock,Lholdumeneu="L1getdupdat" ciectimeory-barmeooL1 1626another CPU might star20r7 from t20ome of them imply full m20ome>20r77" cthocmpdat"mentrs.t15chiock,Lholdumenv is1delay" ciecbarrmentaatry-barmeooL1" name="L1626">1626another CPU might star20r8 from t20y heavily relied on as a20y h>20r8txt#xt#/memoryc5chisrby sobaroentaac5chi ev16ee" name="L1517">1517
20r"line" name="L1550">1550
1565 (*) Atomic operations2081 from t20some ofste in thmory acc20som>20i1txt#L1615" ie3" class="lineie3" class="lineie3" class="linelass="line3" class="line" name="L1633">1633                      2082 from t20ieso SMP k-nsidion/malen20ies>20i22" class="liiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiuie3 0, vie3 1idhreeie3 &u, qie3 &u" name="L1633">1633                      2083 from t20allyperation re(th them 20all>20i32" class="livie 2e" name="L1646">1646        LOAD waiter-&g2084 from t20n/memory-barriers.txt#L120n/m>20i42" class="lismp_wmb();" name="L1646">1646        LOAD waiter-&g2085 from t20 processes:
1646        LOAD waiter-&g20i6 from t20iers.txt#L1587" id="L15820ier>20i62" class="liiiiiiiiiiiiiiiii646"C:queue v=2line" name="L1646">1646        LOAD waiter-&g20i7 from t20ef="Documentation/memory20ef=>20i72" class="lieie &veiiiiiiiiiqie pe" name="L1646">1646        LOAD waiter-&g2088 from t20ntation/memory-barriers.20nta>20i82" class="liiiiiiiiiiiiiiiii646"D:ss="e"o"pline" name="L1646">1646        LOAD waiter-&g20i9 from t20 href="Documentation/mem20 hr>20i92" class="li646"B:modify p=&vlines646"D:commit p=&vline" name="L1646">1646        LOAD waiter-&g209r from t20iters;
1646        LOAD waiter-&g2091 from t20emory-barriers.txt#L159220emo>20i92" class="liiiiiiiiiiiiiiiiixie *qe" name="L1646">1646        LOAD waiter-&g2092 from t20iers.txt#L1593" id="L15920ier>20i22" class="liiiiiiiiiiiiiiiii646"C:ss="u*qlines="liRd="cueromov by-baravdupdat" cieci5chi" name="L1486">1486LOCKS VS I/O ACCESSES
2093 from t20ef="Documentation/memory20ef=>20i32" class="liiiiiiiiiiiiiiiii646"C:unbusyline" name="L1646">1646        LOAD waiter-&g2094 from t20st;
1646        LOAD waiter-&g2095 from t20*task;
1486LOCKS VS I/O ACCESSES
20i6 from t20emory-barriers.txt#L159720emo>20i62" cBastation,5wmic
1486LOCKS VS I/O ACCESSES
20i7 from t20iers.txt#L1598" id="L15920ier>20i72" coc L1664" cla8m=",sat aout-bLassv16eilaxt"L1-e
1486LOCKS VS I/O ACCESSES
20i8 from t20 up_read() or up_write()20 up>20i82" casass="liermitt" conlxt#i1e" name="L1680">1680
1550
16a Any atomic
operation r2101 from t21emory-barriers.txt#L159221emo>21e"lineTo-bLassv16e,saelotio88" bLasspol  3Lr"darriumentabary=rrier
16a Any atomic
operation r2102 from t21eers.txt#L1593" id="L15921eer>21e"linerrier
1626another CPU might star21e3 from t21ef="Documentation/memory21ef=>21e3" idqueue by-baray-barn/memo.ny furentaass="e"ore" name="L1517">1517
210"line" name="L1565">1565 (*) Atomic operations21e5 from t21etask;
1565 (*) Atomic operations21e6 from t21emory-barriers.txt#L159721emo>2106txt#L1615" ie3" class="lineie3" class="lineie3" class="linelass="line3" class="line" name="L1633">1633                      21e7 from t21eers.txt#L1598" id="L15921eer>21072" class="liiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiuie3 0, vie3 1idhreeie3 &u, qie3 &u" name="L1633">1633                      21e8 from t21eup_read() or up_write()21eup>21082" class="livie 2e" name="L1646">1646        LOAD waiter-&g21e9 from t21eers.txt#L1600" id="L16021eer>21092" class="lismp_wmb();" name="L1646">1646        LOAD waiter-&g211r from t21iers.txt#L1611" id="L16121ier>21102" class="li646"A:modify v=2lines=646"C:busyline" name="L1646">1646        LOAD waiter-&g21i1 from t21his sequence of events:
21his>21192" class="liiiiiiiiiiiiiiiii646"C:queue v=2line" name="L1646">1646        LOAD waiter-&g2112 from t21iers.txt#L1613" id="L16121ier>21122" class="lieie &veiiiiiiiiiqie pe" name="L1646">1646        LOAD waiter-&g21i3 from t211646        LOAD waiter-&g21i4 from t21ef="Documentation/memory21ef=>21i42" class="li646"B:modify p=&vlines646"D:commit p=&vline" name="L1646">1646        LOAD waiter-&g21i5 from t21ref="Documentation/memor21ref>21i5txt#L1615" iiiiiiiiiiiiiiiii646"D:ss="upline" name="L1646">1646        LOAD waiter-&g21i6 from t21ntation/memory-barriers.21nta>21162" class="liiiiiiiiiiiiiiiiismp_ss="_LOAD wa_umenta/()" name="L1681">16a Any atomic
operation r2117 from t21entation/memory-barriers21ent>21172" class="liiiiiiiiiiiiiiiii646"C:unbusyline" name="L1646">1646        LOAD waiter-&g21i8 from t21iers.txt#L1619" id="L16121ier>21182" class="liiiiiiiiiiiiiiiii646"C:commit v=2line" name="L1646">1646        LOAD waiter-&g21i9 from t21 of order, then the whol21 of>21192" class="liiiiiiiiiiiiiiiiixie *qe" name="L1646">1646        LOAD waiter-&g212r from t21/memory-barriers.txt#L1621/me>21/m2" class="liiiiiiiiiiiiiiiii646"C:ss="u*qlines="liRd="cueromov afassavdupdat" cieci5chi" name="L1486">1486LOCKS VS I/O ACCESSES
2121 from t21iers.txt#L1622" id="L16221ier>212"line" name="L1672">1672
1673ATOMIC OPERATIONS
21/riers" barsoDo"oryy-bblem="lnrs.tbarouLass" conlDEC Alphaay-barn/orss=cut iL1have6a" name="L1673">1673ATOMIC OPERATIONS
21/.txt#splite15chi"5m="limy-bv,s"xt#L1614"cecby=makentabetassamemcoryrs.tdarribuse" name="L1680">1680
1619and if any of these st21/6 from t21the waiter and might clo21the>21/6txt#riarritumenta/memos5re=",1ocusbierdo,579"barm"L1ocusb 5relimorone" name="L1680">1680
1517
1486LOCKS VS I/O ACCESSES
2129 from t21the above sequence of ev21the>21/92" c15chioetree lonass=l9=L1681"riarrioc.56" i se14"ticrrory-barAlphaarL16vecut i" name="L1626">1626another CPU might star213r from t21iers.txt#L1631" id="L16321ier>21ie2" cotio8e locoordin  ilaLriers.tabse"cecory=L1681"rrier
1680
21i"line" name="L1672">1672
1673ATOMIC OPERATIONS
21i"lineCACHE COHERENCY VS DMA" name="L1673">1673ATOMIC OPERATIONS
21i.txt#----------------------" name="L1673">1673ATOMIC OPERATIONS
1486LOCKS VS I/O ACCESSES
21i6 from t21tion/memory-barriers.txt21tio>21i"lineNcusbiermhref=s"-binta;soc5chi"cohy-bary=at all
1586
1586
1586
21i"linehave66" i "47"tn/mbackef="RAM"yea.  Tosdeal=at al0"irDo"L1tapentpria c ="Do"or" name="L1586">1586
21cutxt#"L1tkars lcm"lin"lusst"L1-everlapeentabi7rrorycachicon5tatioxt#i(=nd.""L57" name="L1550">1550
1680
1673ATOMIC OPERATIONS
21c"lineImosd1i cla,yrs.tdarriDMA/memodef="RAM"bylia" id="L="L1579ever"47"tn/mby"dirto" name="L1673">1673ATOMIC OPERATIONS
21c.txt#cachicli"ocubemorya47"tn/mbackef="RAM"eromoa 1486LOCKS VS I/O ACCESSES
21c5 from t21ocumentation/memory-barr21ocu>21c5txt#ri16tio
reftcyown9darr,"-b iachicli"ocupre"167eilon/me1486LOCKS VS I/O ACCESSES
21c6 from t211486LOCKS VS I/O ACCESSES
21c7 from t21entation/memory-barriers21ent>21c7txt#is1dis158d d"eromon/mext#/memoryc5chi and.reload" e56"osdeal=at al0"irDo"L1" name="L1486">1486LOCKS VS I/O ACCESSES
21c8 from t21iers.txt#L1649" id="L16421ier>21c8txt#apentpria c ="Do"or "L1tkars lcm"lin"Lvalid" c t i-everlapeentabi7rrory"L1" name="L1486">1486LOCKS VS I/O ACCESSES
21c9 from t21semaphore lock, but then21sem>21492" c15chicon5tatioxt#e" name="L1680">1680
1607 (4) call wake_up_proc2151 from t21iers.txt#L1652" id="L16521ier>21s12" cSee 607">1607 15chitlbp_pr8e lom552"rnL1614 ilaLonyc5chi m"nage>160e" name="L1680">1680
1673ATOMIC OPERATIONS
1654        LOAD waiter-&g2154 from t211654        LOAD waiter-&g2155 from t21ef="Documentation/memory21ef=>21s5txt#-----------------------" name="L1673">1673ATOMIC OPERATIONS
215"line" name="L1607">1607 (4) call wake_up_proc21s7 from t21ref="Documentation/memor21ref>21s72" cML1681"mtiond I/O usntati"tak s1pla="Lte claso=L1681"li3s1586
21s82" ca"windL16ilon/me1586
21s92" cthocmentalRAM"dirntanorwindL1e" name="L1680">1680
1607 (4) call wake_up_proc2161 from t21uarantee that all memory21uar>21i92" cAmong
1607 (4) call wake_up_proc2162 from t21e all the memory accesse21e a>21i22" cc5chenta16eirely and.go"dirntati"toars.td id="Lbuioc.56" bar=e4"scMMIOtriarrioc" name="L1607">1607 (4) call wake_up_proc2163 from t21he system.  It does _not21he >21i32" cm"L,6iloementa,-evertak  aef="Docuentcachio8(4) ca"um="lwe="Demitt" cearliore" name="L1680">1680
1550
21i5e ba"lussnorbetw" idrs.tcachio8(4) ca""47" "and.rs.tMMIOtriarri"Lfcume8nwora52"rn" name="L1550">1550
1680
1517
1569 (*) Interrupts.
21i9txt#elass="line3" class="line" name="L1633">1633                      217r from t21ring logic will take car21rin>21ritxt#THE THINGSe1654        LOAD waiter-&g2171 from t21iers.txt#L1672" id="L16721ier>21r92" celass="line3" class="line" name="L1633">1633                      2172 from t21iers.txt#L1673" id="L16721ier>217"line" name="L1673">1673ATOMIC OPERATIONS
21732" cAcentgrammtaamight"tak  imid="Lg64" cdL-b="ln/me1619and if any of these st2174 from t21ation/memory-barriers.tx21ati>21r"line and
1626another CPU might star21r5 from t21iers.txt#L1676" id="L16721ier>21r5e bagiv idt i f="Documeneiececorycodi"537execl7ee" name="L1517">1517
1607 (4) call wake_up_proc21r7 from t21ome of them imply full m21ome>21772" class="liaie *Ae" name="L1646">1646        LOAD waiter-&g21r8 from t21y heavily relied on as a21y h>21782" class="li*Bie be" name="L1646">1646        LOAD waiter-&g21r9 from t21ry-barriers.txt#L1680" i21ry->21792" class="licie *Ce" name="L1646">1646        LOAD waiter-&g218r from t21iers.txt#L1681" id="L16821ier>21ietxt#L1615" idie *De" name="L1646">1646        LOAD waiter-&g2181 from t21some ofste in thmory acc21som>21i1txt#L1615" i*Eie ee" name="L1646">1646        LOAD waiter-&g2182 from t21ieso SMP k-nsidion/malen21ies>218"line" name="L1673">1673ATOMIC OPERATIONS
21837" cthoy "ould1umen expntaL-b="ln/me1486LOCKS VS I/O ACCESSES
2184 from t21n/memory-barriers.txt#L121n/m>21i42" cri1669" cla by-baramoventati"toars.tnextctim, leadumenentrcumfin7" "ss="e"cecor" name="L1486">1486LOCKS VS I/O ACCESSES
2185 from t21 processes:
1517
1607 (4) call wake_up_proc21i7 from t21ef="Documentation/memory21ef=>21i72" class="liLOAD *A, STOREi*B,iLOAD *C,iLOAD *D, STOREi*Ee" name="L1680">1680
1569 (*) Interrupts.
1550
21it2" cRealitycirDoorycourhr,cmlassmrn/more  Wt alm.ny ion/m=nd." mpilumeDo"L1tabov6" name="L1550">1550
1517
1673ATOMIC OPERATIONS
1673ATOMIC OPERATIONS
1673ATOMIC OPERATIONS
1646        LOAD waiter-&g21i6 from t21emory-barriers.txt#L159721emo>219"line" name="L1607">1607 (4) call wake_up_proc21i7 from t21iers.txt#L1598" id="L15921ier>21972" cl(*)5liads ="L1579d6" impecuentiveti,land.rs.t52sult1dis158d d"should1iteentv6" name="L1550">1550
1646        LOAD waiter-&g2199 from t21iers.txt#L1600" id="L16021ier>21i"line" name="L1550">1550
1550
1646        LOAD waiter-&g2202 from t22eers.txt#L1593" id="L15922eer>220"line" name="L1673">1673ATOMIC OPERATIONS
1673ATOMIC OPERATIONS
1646        LOAD waiter-&g2205 from t22etask;
1486LOCKS VS I/O ACCESSES
22e6 from t22emory-barriers.txt#L159722emo>2206txt#L(*)5liads bi157t552si="L15 5" rbinio88" bmy-bv,"xt#L1614"cecwmen talkumenen" name="L1486">1486LOCKS VS I/O ACCESSES
22e7 from t22eers.txt#L1598" id="L15922eer>22072" class=#L1681" r I/O h58dware e/="li5i"do batchio"riarriocuoryrdjac167eli3s1626another CPU might star22e8 from t22eup_read() or up_write()22eup>22082" class=thusi"uttentadown9ti"transa" cla setup5" sts (#L1681"ri15PCI"" id="re-ba" name="L1486">1486LOCKS VS I/O ACCESSES
22e9 from t22eers.txt#L1600" id="L16022eer>22092" class=bmencDoca="li" cdol0"ir);line" name="L1678">1678some don't, but th221r from t22iers.txt#L1611" id="L16122ier>221pline" name="L1607">1607 (4) call wake_up_proc22i1 from t22his sequence of events:
22his>22192" cl(*)5"L1-1626another CPU might star2212 from t22iers.txt#L1613" id="L16122ier>22122" class=meihanism/mm"L1all id" c t is - enlaers.tmt552mh=cuacentati"hitdrs.tcachi" name="L1626">1626another CPU might star2213 from t22160mrriers.tentpagat" cie" name="L1626">1626another CPU might star2214 from t22ef="Documentation/memory22ef=>22i42" class=e
1680
221"line" name="L1486">1486LOCKS VS I/O ACCESSES
22i6 from t22ntation/memory-barriers.22nta>22162" cSo.wm="lfnmentaaion, s"L,6might"acentati"tb"Drit"eromon/medbov6 piececorycodi" name="L1486">1486LOCKS VS I/O ACCESSES
22i7 from t22entation/memory-barriers22ent>2217txt#ise" name="L1517">1517
1569 (*) Interrupts.
22192" class="liLOAD *A, ...,iLOAD {*C,*D}, STOREi*E, STOREi*B" name="L1569">1569 (*) Interrupts.
222pline" name="L1607">1607 (4) call wake_up_proc2221 from t22iers.txt#L1622" id="L16222ier>22/92" class="li(Why-b "LOAD {*C,*D}"ris1a5" rbinio8liad)" name="L1681">16a Any atomic
operation r22/2 from t22ed the semaphore lock, t22ed >222"line" name="L1673">1673ATOMIC OPERATIONS
222"line" name="L1654">1654        LOAD waiter-&g2224 from t22d is on the waiter's22d i>22/.txt#HL1ntat,1iteis1L1664" cldL-b="lae1607 (4) call wake_up_proc2225 from t22ore_ the next pointer in22ore>22/5txt#_own_"riarriocua"Docum8" brrierrntati"t1581" ,sat aout-rs.tneio8e loa-"L1678" name="L1619">1619and if any of these st22/6 from t22the waiter and might clo22the>22/6txt#ny of t.  F r5bi16t"cecwt al0" 5f="Documencodie" name="L1517">1517
1517
1646        LOAD waiter-&g2229 from t22the above sequence of ev22the>22/92" class="li*Aie Ve" name="L1646">1646        LOAD waiter-&g223r from t22iers.txt#L1631" id="L16322ier>22ie2" class="li*Aie We" name="L1646">1646        LOAD waiter-&g2231 from t22     CPU 2
1646        LOAD waiter-&g2232 from t22==== ===================22===>22322" class="li*Aie Ye" name="L1646">1646        LOAD waiter-&g2233 from t22     down_xxx()
22332" class="liZie *Ae" name="L1646">1646        LOAD waiter-&g2234 from t22     Queue waiter
223"line" name="L1565">1565 (*) Atomic operations2235 from t22     Sleep
1565 (*) Atomic operations2236 from t22tion/memory-barriers.txt22tio>22397" cthocfintal52sult1rrie1a"Docum8" bie" name="L1517">1517
2238" id" name="L1517">1517
22382" class="liUie=urs1-e
igintalvalu5cory*A" name="L1673">1673ATOMIC OPERATIONS
22392" class="liXiee W" name="L1673">1673ATOMIC OPERATIONS
22402" class="liZiee Y" name="L1673">1673ATOMIC OPERATIONS
22412" class="li*Aiee Y" name="L1673">1673ATOMIC OPERATIONS
224"line" name="L1673">1673ATOMIC OPERATIONS
224riers" eycodi"dbov6 m"L1camemln/me1619and if any of these st2244 from t22     foo() clobbers *wai22   >22c.txt#riarrioce" name="L1517">1517
1486LOCKS VS I/O ACCESSES
22c6 from t221486LOCKS VS I/O ACCESSES
22c7 from t22entation/memory-barriers22ent>2248" id" name="L1517">1517
1619and if any of these st2249 from t22semaphore lock, but then22sem>22492" c1 rbin4 ilaLof ele>160s5" rbinio8 r5dis158d d,eentvided.rs.tentgram/memoryviewcor" name="L1486">1486LOCKS VS I/O ACCESSES
225r from t22spinlock again after bei22spi>225utxt#"L1tworld.re-bins5" nsisum67e" name="L1680">1680
1672
160s5try-barme="e"cecby-bar" name="L1646">1646        LOAD waiter-&g22s3 from t22iers.txt#L1654" id="L16522ier>22s37" cthoc1680
22s"line" name="L1565">1565 (*) Atomic operations2255 from t22ef="Documentation/memory22ef=>22s5txt#F r5bi16t"cee" name="L1517">1517
1607 (4) call wake_up_proc22s7 from t22ref="Documentation/memor22ref>22s72" class="li*Aie Ve" name="L1646">1646        LOAD waiter-&g22s8 from t22ntation/memory-barriers.22nta>22s82" class="li*Aie We" name="L1646">1646        LOAD waiter-&g2259 from t22entation/memory-barriers22ent>225"line" name="L1550">1550
1517
1672
1646        LOAD waiter-&g2263 from t22he system.  It does _not22he >226"line" name="L1654">1654        LOAD waiter-&g22i4 from t22ier will be complete by 22ier>22i"linesi"ce,1"L15out-ai547" "rrier
<,1ite"lnrs.tbarumldL-b="cbarrementauory"L1" name="L1486">1486LOCKS VS I/O ACCESSES
2265 from t22href="Documentation/memo22hre>22i5e bamt55agecorlVh8" *Aiis lo
<.  Similarlye" name="L1517">1517
1607 (4) call wake_up_proc22i7 from t22#39;t be a problem - the22#39>22672" class="li*Aie Ye" name="L1646">1646        LOAD waiter-&g2268 from t22the compiler emits the i22the>22682" class="liZie *Ae" name="L1646">1646        LOAD waiter-&g2269 from t22ening in the CPU.  Since22eni>226"line" name="L1550">1550
1517
1672
1646        LOAD waiter-&g2273 from t22ation/memory-barriers.tx22ati>22732" class="liZie Ye" name="L1646">1646        LOAD waiter-&g2274 from t22ation/memory-barriers.tx22ati>22r"line" name="L1565">1565 (*) Atomic operations22r5 from t22iers.txt#L1676" id="L16722ier>227"lineand.barrLOAD  and
1680
1607 (4) call wake_up_proc22r7 from t22ome of them imply full m22ome>2278" id" name="L1517">1517
1486LOCKS VS I/O ACCESSES
22r9 from t22ry-barriers.txt#L1680" i22ry->22792" c--------------------------" name="L1673">1673ATOMIC OPERATIONS
1607 (4) call wake_up_proc2281 from t22some ofste in thmory acc22som>22i1txt#" eyDEC Alphaa1626another CPU might star2282 from t22ieso SMP k-nsidion/malen22ies>228"linesobarit, a hreory-barAlphaa1626another CPU might star2283 from t22allyperation re(th them 22all>22837" ctwo se14"tictati-relat" ciachicli"ocuupdat" c="lyepad
1626another CPU might star2284 from t22n/memory-barriers.txt#L122n/m>22i42" crs.tdarriumentabary=rrier
1486LOCKS VS I/O ACCESSES
2285 from t22 processes:
1486LOCKS VS I/O ACCESSES
2286 from t22iers.txt#L1587" id="L15822ier>228"lineihangos vcunewtdarrioccursiecbarrright"remore" name="L1486">1486LOCKS VS I/O ACCESSES
2287 from t22ef="Documentation/memory22ef=>2288" id" name="L1517">1517
1486LOCKS VS I/O ACCESSES
2289 from t22 href="Documentation/mem22 hr>228"line" name="L1550">1550
22it2" cSeaers.tmubse" cla la "CachicCohy-bary"rdbov6e" name="L1486">1486LOCKS VS I/O ACCESSES
2291 from t22emory-barriers.txt#L159222emo>229"line" name="L1672">1672
1673ATOMIC OPERATIONS
1633                      2294 from t22st;
1633                      2295 from t22*task;
1633                      2296 from t22emory-barriers.txt#L159722emo>229"line" name="L1607">1607 (4) call wake_up_proc22i7 from t22iers.txt#L1598" id="L15922ier>22972" cCIRCULAR BUFFERS" name="L1633">1633                      2298 from t22 up_read() or up_write()22 up>22982" c----------------" name="L1673">1673ATOMIC OPERATIONS
1550
160 circuenr buffy-moryat aout-rs.tneio" name="L1550">1550
1t.  Seae" name="L1517">1517
1673ATOMIC OPERATIONS
1673Acircuenr-buffy-NS
1673ATOMIC OPERATIONS
1565 (*) Atomic operations2305 from t23etask;
1680
1607 (4) call wake_up_proc23e7 from t23eers.txt#L1598" id="L15923eer>2308" id" name="L1517">1517
1633                      23e9 from t23eers.txt#L1600" id="L16023eer>23092" cREFERENCES" name="L1633">1633                      231r from t23iers.txt#L1611" id="L16123ier>231plinelass="line" name="L1633">1633                      23i1 from t23his sequence of events:
23his>231"line" name="L1672">1672
1626another CPU might star2313 from t2316a Any atomic
operation r2314 from t23ef="Documentation/memory23ef=>23i42" class="liChapassa5.2: Phystati Addrrn/ Spa="LCharacassisticr" name="L1681">16a Any atomic
operation r2315 from t23ref="Documentation/memor23ref>23i5txt#L1615" iChapassa5.4: C5chisrand.W47" "Buffy-N" name="L1681">16a Any atomic
operation r2316 from t23ntation/memory-barriers.23nta>23162" class="liChapassa5.5: DarriSharmor" name="L1681">16a Any atomic
operation r2317 from t23entation/memory-barriers23ent>23172" class="liChapassa5.6:iRd="/W47" "O
16a Any atomic
operation r2318 from t23iers.txt#L1619" id="L16123ier>231"line" name="L1569">1569 (*) Interrupts.
23192" cAMD64 Archite" ure/Pntgrammta/memoryManual Vol">1 2: Shref=/Pntgramment" name="L1681">16a Any atomic
operation r232r from t23/memory-barriers.txt#L1623/me>23/m2" class="liChapassa7.1: ML1681-Aiarri"O
16a Any atomic
operation r2321 from t23iers.txt#L1622" id="L16223ier>23/92" class="liChapassa7.4: Buffy-moryand.C rbinmoryML1681"W47" N" name="L1681">16a Any atomic
operation r23/2 from t23ed the semaphore lock, t23ed >232"line" name="L1673">1673ATOMIC OPERATIONS
232"lineIA-32 Intel Archite" ure/Software Devel and/memoryManual, Vol">1 3e" name="L1517">1517
1486LOCKS VS I/O ACCESSES
2325 from t23ore_ the next pointer in23ore>2325txt#L1615" iChapassa7.1: Li3kio8Atomic Oand
1486LOCKS VS I/O ACCESSES
2326 from t23the waiter and might clo23the>23262" class="liChapassa7.2: ML1681"O
16a Any atomic
operation r2327 from t23 a chance to read the ne23 a >23272" class="liChapassa7.4: Sy-malizent Ii1669" clar" name="L1486">1486LOCKS VS I/O ACCESSES
2328 from t23iers.txt#L1629" id="L16223ier>232"line" name="L1569">1569 (*) Interrupts.
23/92" cTbarSPARC Archite" ure/Manual, Vt, a h 9" name="L1569">1569 (*) Interrupts.
1486LOCKS VS I/O ACCESSES
2331 from t23     CPU 2
1486LOCKS VS I/O ACCESSES
2332 from t23==== ===================23===>23322" class="liApentaix J:/Pntgramment wt al0" 5ML1681"Modelr" name="L1486">1486LOCKS VS I/O ACCESSES
2333 from t23     down_xxx()
233"line" name="L1654">1654        LOAD waiter-&g2334 from t23     Queue waiter
233"lineUltraSPARC Pntgrammta/Refy-bar.tManual" name="L1654">1654        LOAD waiter-&g2335 from t23     Sleep
1654        LOAD waiter-&g2336 from t23tion/memory-barriers.txt23tio>23362" class="liChapassa15: Sparc-V95ML1681"Modelr" name="L1486">1486LOCKS VS I/O ACCESSES
2337 from t23ef="Documentation/memory23ef=>2338" id" name="L1517">1517
23382" cUltraSPARC III Cu Usnd/memoryManual" name="L1517">1517
1486LOCKS VS I/O ACCESSES
234r from t23cumentation/memory-barri23cum>234pline" name="L1607">1607 (4) call wake_up_proc2341 from t23     Resume processing
<23   >23412" cUltraSPARC IIIi Pntarn/or Usnd/memoryManual" name="L1517">1517
1486LOCKS VS I/O ACCESSES
2343 from t23     call foo()
234"line" name="L1654">1654        LOAD waiter-&g2344 from t23     foo() clobbers *wai23   >234"lineUltraSPARC Archite" ure/2005" name="L1654">1654        LOAD waiter-&g2345 from t23ocumentation/memory-barr23ocu>2345txt#L1615" iChapassa9: ML1681" name="L1654">1654        LOAD waiter-&g2346 from t231486LOCKS VS I/O ACCESSES
23c7 from t23entation/memory-barriers23ent>2348" id" name="L1517">1517
160 entrs.tUltraSPARC Archite" ure/2005" name="L1654">1654        LOAD waiter-&g2349 from t23semaphore lock, but then23sem>23492" class="liChapassa8: ML1681"Modelr" name="L1486">1486LOCKS VS I/O ACCESSES
235r from t23spinlock again after bei23spi>23502" class="liApentaix F: C5chisrand.CachicCohy-bary" name="L1486">1486LOCKS VS I/O ACCESSES
2351 from t23iers.txt#L1652" id="L16523ier>235"line" name="L1672">1672
1517
1678some don't, but th2354 from t231678some don't, but th2355 from t23ef="Documentation/memory23ef=>235"line" name="L1486">1486LOCKS VS I/O ACCESSES
23s6 from t23ation/memory-barriers.tx23ati>235"lineUnix Shref=s"f r5ModerncArchite" ures,cSymmttric Multiy-barn/moryand.C5chent" name="L1486">1486LOCKS VS I/O ACCESSES
23s7 from t23ref="Documentation/memor23ref>23s72" cf r5Kars lcPntgrammtace" name="L1517">1517
1486LOCKS VS I/O ACCESSES
2359 from t23entation/memory-barriers23ent>235"line" name="L1550">1550
1 1e" name="L1517">1517
" name="L1678">1678some don't, but th2362 from t23e all the memory accesse23e a>23622" class="liSe" cla 4.4: ML1681"Aiarri" name="L1678">1678some don't, but th2363 from t23he system.  It does _not23he >236"line


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