linux/drivers/gpio/gpio-pch.c
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   1/*
   2 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   3 *
   4 * This program is free software; you can redistribute it and/or modify
   5 * it under the terms of the GNU General Public License as published by
   6 * the Free Software Foundation; version 2 of the License.
   7 *
   8 * This program is distributed in the hope that it will be useful,
   9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 * GNU General Public License for more details.
  12 *
  13 * You should have received a copy of the GNU General Public License
  14 * along with this program; if not, write to the Free Software
  15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  16 */
  17#include <linux/module.h>
  18#include <linux/kernel.h>
  19#include <linux/pci.h>
  20#include <linux/gpio.h>
  21#include <linux/interrupt.h>
  22#include <linux/irq.h>
  23
  24#define PCH_EDGE_FALLING        0
  25#define PCH_EDGE_RISING         BIT(0)
  26#define PCH_LEVEL_L             BIT(1)
  27#define PCH_LEVEL_H             (BIT(0) | BIT(1))
  28#define PCH_EDGE_BOTH           BIT(2)
  29#define PCH_IM_MASK             (BIT(0) | BIT(1) | BIT(2))
  30
  31#define PCH_IRQ_BASE            24
  32
  33struct pch_regs {
  34        u32     ien;
  35        u32     istatus;
  36        u32     idisp;
  37        u32     iclr;
  38        u32     imask;
  39        u32     imaskclr;
  40        u32     po;
  41        u32     pi;
  42        u32     pm;
  43        u32     im0;
  44        u32     im1;
  45        u32     reserved[3];
  46        u32     gpio_use_sel;
  47        u32     reset;
  48};
  49
  50enum pch_type_t {
  51        INTEL_EG20T_PCH,
  52        OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
  53        OKISEMI_ML7223n_IOH  /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
  54};
  55
  56/* Specifies number of GPIO PINS */
  57static int gpio_pins[] = {
  58        [INTEL_EG20T_PCH] = 12,
  59        [OKISEMI_ML7223m_IOH] = 8,
  60        [OKISEMI_ML7223n_IOH] = 8,
  61};
  62
  63/**
  64 * struct pch_gpio_reg_data - The register store data.
  65 * @ien_reg:    To store contents of IEN register.
  66 * @imask_reg:  To store contents of IMASK register.
  67 * @po_reg:     To store contents of PO register.
  68 * @pm_reg:     To store contents of PM register.
  69 * @im0_reg:    To store contents of IM0 register.
  70 * @im1_reg:    To store contents of IM1 register.
  71 * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
  72 *                     (Only ML7223 Bus-n)
  73 */
  74struct pch_gpio_reg_data {
  75        u32 ien_reg;
  76        u32 imask_reg;
  77        u32 po_reg;
  78        u32 pm_reg;
  79        u32 im0_reg;
  80        u32 im1_reg;
  81        u32 gpio_use_sel_reg;
  82};
  83
  84/**
  85 * struct pch_gpio - GPIO private data structure.
  86 * @base:                       PCI base address of Memory mapped I/O register.
  87 * @reg:                        Memory mapped PCH GPIO register list.
  88 * @dev:                        Pointer to device structure.
  89 * @gpio:                       Data for GPIO infrastructure.
  90 * @pch_gpio_reg:               Memory mapped Register data is saved here
  91 *                              when suspend.
  92 * @lock:                       Used for register access protection
  93 * @irq_base:           Save base of IRQ number for interrupt
  94 * @ioh:                IOH ID
  95 * @spinlock:           Used for register access protection
  96 */
  97struct pch_gpio {
  98        void __iomem *base;
  99        struct pch_regs __iomem *reg;
 100        struct device *dev;
 101        struct gpio_chip gpio;
 102        struct pch_gpio_reg_data pch_gpio_reg;
 103        int irq_base;
 104        enum pch_type_t ioh;
 105        spinlock_t spinlock;
 106};
 107
 108static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
 109{
 110        u32 reg_val;
 111        struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
 112        unsigned long flags;
 113
 114        spin_lock_irqsave(&chip->spinlock, flags);
 115        reg_val = ioread32(&chip->reg->po);
 116        if (val)
 117                reg_val |= (1 << nr);
 118        else
 119                reg_val &= ~(1 << nr);
 120
 121        iowrite32(reg_val, &chip->reg->po);
 122        spin_unlock_irqrestore(&chip->spinlock, flags);
 123}
 124
 125static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr)
 126{
 127        struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
 128
 129        return ioread32(&chip->reg->pi) & (1 << nr);
 130}
 131
 132static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
 133                                     int val)
 134{
 135        struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
 136        u32 pm;
 137        u32 reg_val;
 138        unsigned long flags;
 139
 140        spin_lock_irqsave(&chip->spinlock, flags);
 141        pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
 142        pm |= (1 << nr);
 143        iowrite32(pm, &chip->reg->pm);
 144
 145        reg_val = ioread32(&chip->reg->po);
 146        if (val)
 147                reg_val |= (1 << nr);
 148        else
 149                reg_val &= ~(1 << nr);
 150        iowrite32(reg_val, &chip->reg->po);
 151        spin_unlock_irqrestore(&chip->spinlock, flags);
 152
 153        return 0;
 154}
 155
 156static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
 157{
 158        struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
 159        u32 pm;
 160        unsigned long flags;
 161
 162        spin_lock_irqsave(&chip->spinlock, flags);
 163        pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
 164        pm &= ~(1 << nr);
 165        iowrite32(pm, &chip->reg->pm);
 166        spin_unlock_irqrestore(&chip->spinlock, flags);
 167
 168        return 0;
 169}
 170
 171/*
 172 * Save register configuration and disable interrupts.
 173 */
 174static void pch_gpio_save_reg_conf(struct pch_gpio *chip)
 175{
 176        chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
 177        chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
 178        chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
 179        chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
 180        chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
 181        if (chip->ioh == INTEL_EG20T_PCH)
 182                chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
 183        if (chip->ioh == OKISEMI_ML7223n_IOH)
 184                chip->pch_gpio_reg.gpio_use_sel_reg =\
 185                                            ioread32(&chip->reg->gpio_use_sel);
 186}
 187
 188/*
 189 * This function restores the register configuration of the GPIO device.
 190 */
 191static void pch_gpio_restore_reg_conf(struct pch_gpio *chip)
 192{
 193        iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
 194        iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
 195        /* to store contents of PO register */
 196        iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
 197        /* to store contents of PM register */
 198        iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
 199        iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
 200        if (chip->ioh == INTEL_EG20T_PCH)
 201                iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
 202        if (chip->ioh == OKISEMI_ML7223n_IOH)
 203                iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg,
 204                          &chip->reg->gpio_use_sel);
 205}
 206
 207static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
 208{
 209        struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
 210        return chip->irq_base + offset;
 211}
 212
 213static void pch_gpio_setup(struct pch_gpio *chip)
 214{
 215        struct gpio_chip *gpio = &chip->gpio;
 216
 217        gpio->label = dev_name(chip->dev);
 218        gpio->owner = THIS_MODULE;
 219        gpio->direction_input = pch_gpio_direction_input;
 220        gpio->get = pch_gpio_get;
 221        gpio->direction_output = pch_gpio_direction_output;
 222        gpio->set = pch_gpio_set;
 223        gpio->dbg_show = NULL;
 224        gpio->base = -1;
 225        gpio->ngpio = gpio_pins[chip->ioh];
 226        gpio->can_sleep = 0;
 227        gpio->to_irq = pch_gpio_to_irq;
 228}
 229
 230static int pch_irq_type(struct irq_data *d, unsigned int type)
 231{
 232        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 233        struct pch_gpio *chip = gc->private;
 234        u32 im, im_pos, val;
 235        u32 __iomem *im_reg;
 236        unsigned long flags;
 237        int ch, irq = d->irq;
 238
 239        ch = irq - chip->irq_base;
 240        if (irq <= chip->irq_base + 7) {
 241                im_reg = &chip->reg->im0;
 242                im_pos = ch;
 243        } else {
 244                im_reg = &chip->reg->im1;
 245                im_pos = ch - 8;
 246        }
 247        dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d\n",
 248                __func__, irq, type, ch, im_pos);
 249
 250        spin_lock_irqsave(&chip->spinlock, flags);
 251
 252        switch (type) {
 253        case IRQ_TYPE_EDGE_RISING:
 254                val = PCH_EDGE_RISING;
 255                break;
 256        case IRQ_TYPE_EDGE_FALLING:
 257                val = PCH_EDGE_FALLING;
 258                break;
 259        case IRQ_TYPE_EDGE_BOTH:
 260                val = PCH_EDGE_BOTH;
 261                break;
 262        case IRQ_TYPE_LEVEL_HIGH:
 263                val = PCH_LEVEL_H;
 264                break;
 265        case IRQ_TYPE_LEVEL_LOW:
 266                val = PCH_LEVEL_L;
 267                break;
 268        default:
 269                goto unlock;
 270        }
 271
 272        /* Set interrupt mode */
 273        im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
 274        iowrite32(im | (val << (im_pos * 4)), im_reg);
 275
 276        /* And the handler */
 277        if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 278                __irq_set_handler_locked(d->irq, handle_level_irq);
 279        else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 280                __irq_set_handler_locked(d->irq, handle_edge_irq);
 281
 282unlock:
 283        spin_unlock_irqrestore(&chip->spinlock, flags);
 284        return 0;
 285}
 286
 287static void pch_irq_unmask(struct irq_data *d)
 288{
 289        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 290        struct pch_gpio *chip = gc->private;
 291
 292        iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imaskclr);
 293}
 294
 295static void pch_irq_mask(struct irq_data *d)
 296{
 297        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 298        struct pch_gpio *chip = gc->private;
 299
 300        iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imask);
 301}
 302
 303static void pch_irq_ack(struct irq_data *d)
 304{
 305        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 306        struct pch_gpio *chip = gc->private;
 307
 308        iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->iclr);
 309}
 310
 311static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
 312{
 313        struct pch_gpio *chip = dev_id;
 314        u32 reg_val = ioread32(&chip->reg->istatus);
 315        int i, ret = IRQ_NONE;
 316
 317        for (i = 0; i < gpio_pins[chip->ioh]; i++) {
 318                if (reg_val & BIT(i)) {
 319                        dev_dbg(chip->dev, "%s:[%d]:irq=%d  status=0x%x\n",
 320                                __func__, i, irq, reg_val);
 321                        generic_handle_irq(chip->irq_base + i);
 322                        ret = IRQ_HANDLED;
 323                }
 324        }
 325        return ret;
 326}
 327
 328static __devinit void pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
 329                                unsigned int irq_start, unsigned int num)
 330{
 331        struct irq_chip_generic *gc;
 332        struct irq_chip_type *ct;
 333
 334        gc = irq_alloc_generic_chip("pch_gpio", 1, irq_start, chip->base,
 335                                    handle_simple_irq);
 336        gc->private = chip;
 337        ct = gc->chip_types;
 338
 339        ct->chip.irq_ack = pch_irq_ack;
 340        ct->chip.irq_mask = pch_irq_mask;
 341        ct->chip.irq_unmask = pch_irq_unmask;
 342        ct->chip.irq_set_type = pch_irq_type;
 343
 344        irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
 345                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 346}
 347
 348static int __devinit pch_gpio_probe(struct pci_dev *pdev,
 349                                    const struct pci_device_id *id)
 350{
 351        s32 ret;
 352        struct pch_gpio *chip;
 353        int irq_base;
 354        u32 msk;
 355
 356        chip = kzalloc(sizeof(*chip), GFP_KERNEL);
 357        if (chip == NULL)
 358                return -ENOMEM;
 359
 360        chip->dev = &pdev->dev;
 361        ret = pci_enable_device(pdev);
 362        if (ret) {
 363                dev_err(&pdev->dev, "%s : pci_enable_device FAILED", __func__);
 364                goto err_pci_enable;
 365        }
 366
 367        ret = pci_request_regions(pdev, KBUILD_MODNAME);
 368        if (ret) {
 369                dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
 370                goto err_request_regions;
 371        }
 372
 373        chip->base = pci_iomap(pdev, 1, 0);
 374        if (!chip->base) {
 375                dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
 376                ret = -ENOMEM;
 377                goto err_iomap;
 378        }
 379
 380        if (pdev->device == 0x8803)
 381                chip->ioh = INTEL_EG20T_PCH;
 382        else if (pdev->device == 0x8014)
 383                chip->ioh = OKISEMI_ML7223m_IOH;
 384        else if (pdev->device == 0x8043)
 385                chip->ioh = OKISEMI_ML7223n_IOH;
 386
 387        chip->reg = chip->base;
 388        pci_set_drvdata(pdev, chip);
 389        spin_lock_init(&chip->spinlock);
 390        pch_gpio_setup(chip);
 391        ret = gpiochip_add(&chip->gpio);
 392        if (ret) {
 393                dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
 394                goto err_gpiochip_add;
 395        }
 396
 397        irq_base = irq_alloc_descs(-1, 0, gpio_pins[chip->ioh], NUMA_NO_NODE);
 398        if (irq_base < 0) {
 399                dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n");
 400                chip->irq_base = -1;
 401                goto end;
 402        }
 403        chip->irq_base = irq_base;
 404
 405        /* Mask all interrupts, but enable them */
 406        msk = (1 << gpio_pins[chip->ioh]) - 1;
 407        iowrite32(msk, &chip->reg->imask);
 408        iowrite32(msk, &chip->reg->ien);
 409
 410        ret = request_irq(pdev->irq, pch_gpio_handler,
 411                          IRQF_SHARED, KBUILD_MODNAME, chip);
 412        if (ret != 0) {
 413                dev_err(&pdev->dev,
 414                        "%s request_irq failed\n", __func__);
 415                goto err_request_irq;
 416        }
 417
 418        pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
 419
 420end:
 421        return 0;
 422
 423err_request_irq:
 424        irq_free_descs(irq_base, gpio_pins[chip->ioh]);
 425
 426        ret = gpiochip_remove(&chip->gpio);
 427        if (ret)
 428                dev_err(&pdev->dev, "%s gpiochip_remove failed\n", __func__);
 429
 430err_gpiochip_add:
 431        pci_iounmap(pdev, chip->base);
 432
 433err_iomap:
 434        pci_release_regions(pdev);
 435
 436err_request_regions:
 437        pci_disable_device(pdev);
 438
 439err_pci_enable:
 440        kfree(chip);
 441        dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
 442        return ret;
 443}
 444
 445static void __devexit pch_gpio_remove(struct pci_dev *pdev)
 446{
 447        int err;
 448        struct pch_gpio *chip = pci_get_drvdata(pdev);
 449
 450        if (chip->irq_base != -1) {
 451                free_irq(pdev->irq, chip);
 452
 453                irq_free_descs(chip->irq_base, gpio_pins[chip->ioh]);
 454        }
 455
 456        err = gpiochip_remove(&chip->gpio);
 457        if (err)
 458                dev_err(&pdev->dev, "Failed gpiochip_remove\n");
 459
 460        pci_iounmap(pdev, chip->base);
 461        pci_release_regions(pdev);
 462        pci_disable_device(pdev);
 463        kfree(chip);
 464}
 465
 466#ifdef CONFIG_PM
 467static int pch_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
 468{
 469        s32 ret;
 470        struct pch_gpio *chip = pci_get_drvdata(pdev);
 471        unsigned long flags;
 472
 473        spin_lock_irqsave(&chip->spinlock, flags);
 474        pch_gpio_save_reg_conf(chip);
 475        spin_unlock_irqrestore(&chip->spinlock, flags);
 476
 477        ret = pci_save_state(pdev);
 478        if (ret) {
 479                dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
 480                return ret;
 481        }
 482        pci_disable_device(pdev);
 483        pci_set_power_state(pdev, PCI_D0);
 484        ret = pci_enable_wake(pdev, PCI_D0, 1);
 485        if (ret)
 486                dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
 487
 488        return 0;
 489}
 490
 491static int pch_gpio_resume(struct pci_dev *pdev)
 492{
 493        s32 ret;
 494        struct pch_gpio *chip = pci_get_drvdata(pdev);
 495        unsigned long flags;
 496
 497        ret = pci_enable_wake(pdev, PCI_D0, 0);
 498
 499        pci_set_power_state(pdev, PCI_D0);
 500        ret = pci_enable_device(pdev);
 501        if (ret) {
 502                dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
 503                return ret;
 504        }
 505        pci_restore_state(pdev);
 506
 507        spin_lock_irqsave(&chip->spinlock, flags);
 508        iowrite32(0x01, &chip->reg->reset);
 509        iowrite32(0x00, &chip->reg->reset);
 510        pch_gpio_restore_reg_conf(chip);
 511        spin_unlock_irqrestore(&chip->spinlock, flags);
 512
 513        return 0;
 514}
 515#else
 516#define pch_gpio_suspend NULL
 517#define pch_gpio_resume NULL
 518#endif
 519
 520#define PCI_VENDOR_ID_ROHM             0x10DB
 521static DEFINE_PCI_DEVICE_TABLE(pch_gpio_pcidev_id) = {
 522        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
 523        { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
 524        { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) },
 525        { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803) },
 526        { 0, }
 527};
 528MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
 529
 530static struct pci_driver pch_gpio_driver = {
 531        .name = "pch_gpio",
 532        .id_table = pch_gpio_pcidev_id,
 533        .probe = pch_gpio_probe,
 534        .remove = __devexit_p(pch_gpio_remove),
 535        .suspend = pch_gpio_suspend,
 536        .resume = pch_gpio_resume
 537};
 538
 539module_pci_driver(pch_gpio_driver);
 540
 541MODULE_DESCRIPTION("PCH GPIO PCI Driver");
 542MODULE_LICENSE("GPL");
 543
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