linux/drivers/gpio/gpio-mvebu.c
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   1/*
   2 * GPIO driver for Marvell SoCs
   3 *
   4 * Copyright (C) 2012 Marvell
   5 *
   6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   7 * Andrew Lunn <andrew@lunn.ch>
   8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
   9 *
  10 * This file is licensed under the terms of the GNU General Public
  11 * License version 2.  This program is licensed "as is" without any
  12 * warranty of any kind, whether express or implied.
  13 *
  14 * This driver is a fairly straightforward GPIO driver for the
  15 * complete family of Marvell EBU SoC platforms (Orion, Dove,
  16 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
  17 * driver is the different register layout that exists between the
  18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
  19 * platforms (MV78200 from the Discovery family and the Armada
  20 * XP). Therefore, this driver handles three variants of the GPIO
  21 * block:
  22 * - the basic variant, called "orion-gpio", with the simplest
  23 *   register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
  24 *   non-SMP Discovery systems
  25 * - the mv78200 variant for MV78200 Discovery systems. This variant
  26 *   turns the edge mask and level mask registers into CPU0 edge
  27 *   mask/level mask registers, and adds CPU1 edge mask/level mask
  28 *   registers.
  29 * - the armadaxp variant for Armada XP systems. This variant keeps
  30 *   the normal cause/edge mask/level mask registers when the global
  31 *   interrupts are used, but adds per-CPU cause/edge mask/level mask
  32 *   registers n a separate memory area for the per-CPU GPIO
  33 *   interrupts.
  34 */
  35
  36#include <linux/module.h>
  37#include <linux/gpio.h>
  38#include <linux/irq.h>
  39#include <linux/slab.h>
  40#include <linux/irqdomain.h>
  41#include <linux/io.h>
  42#include <linux/of_irq.h>
  43#include <linux/of_device.h>
  44#include <linux/platform_device.h>
  45#include <linux/pinctrl/consumer.h>
  46
  47/*
  48 * GPIO unit register offsets.
  49 */
  50#define GPIO_OUT_OFF            0x0000
  51#define GPIO_IO_CONF_OFF        0x0004
  52#define GPIO_BLINK_EN_OFF       0x0008
  53#define GPIO_IN_POL_OFF         0x000c
  54#define GPIO_DATA_IN_OFF        0x0010
  55#define GPIO_EDGE_CAUSE_OFF     0x0014
  56#define GPIO_EDGE_MASK_OFF      0x0018
  57#define GPIO_LEVEL_MASK_OFF     0x001c
  58
  59/* The MV78200 has per-CPU registers for edge mask and level mask */
  60#define GPIO_EDGE_MASK_MV78200_OFF(cpu)   ((cpu) ? 0x30 : 0x18)
  61#define GPIO_LEVEL_MASK_MV78200_OFF(cpu)  ((cpu) ? 0x34 : 0x1C)
  62
  63/* The Armada XP has per-CPU registers for interrupt cause, interrupt
  64 * mask and interrupt level mask. Those are relative to the
  65 * percpu_membase. */
  66#define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
  67#define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu)  (0x10 + (cpu) * 0x4)
  68#define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
  69
  70#define MVEBU_GPIO_SOC_VARIANT_ORION    0x1
  71#define MVEBU_GPIO_SOC_VARIANT_MV78200  0x2
  72#define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
  73
  74#define MVEBU_MAX_GPIO_PER_BANK         32
  75
  76struct mvebu_gpio_chip {
  77        struct gpio_chip   chip;
  78        spinlock_t         lock;
  79        void __iomem      *membase;
  80        void __iomem      *percpu_membase;
  81        unsigned int       irqbase;
  82        struct irq_domain *domain;
  83        int                soc_variant;
  84};
  85
  86/*
  87 * Functions returning addresses of individual registers for a given
  88 * GPIO controller.
  89 */
  90static inline void __iomem *mvebu_gpioreg_out(struct mvebu_gpio_chip *mvchip)
  91{
  92        return mvchip->membase + GPIO_OUT_OFF;
  93}
  94
  95static inline void __iomem *mvebu_gpioreg_blink(struct mvebu_gpio_chip *mvchip)
  96{
  97        return mvchip->membase + GPIO_BLINK_EN_OFF;
  98}
  99
 100static inline void __iomem *mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip)
 101{
 102        return mvchip->membase + GPIO_IO_CONF_OFF;
 103}
 104
 105static inline void __iomem *mvebu_gpioreg_in_pol(struct mvebu_gpio_chip *mvchip)
 106{
 107        return mvchip->membase + GPIO_IN_POL_OFF;
 108}
 109
 110static inline void __iomem *mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip)
 111{
 112        return mvchip->membase + GPIO_DATA_IN_OFF;
 113}
 114
 115static inline void __iomem *mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip)
 116{
 117        int cpu;
 118
 119        switch(mvchip->soc_variant) {
 120        case MVEBU_GPIO_SOC_VARIANT_ORION:
 121        case MVEBU_GPIO_SOC_VARIANT_MV78200:
 122                return mvchip->membase + GPIO_EDGE_CAUSE_OFF;
 123        case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
 124                cpu = smp_processor_id();
 125                return mvchip->percpu_membase + GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
 126        default:
 127                BUG();
 128        }
 129}
 130
 131static inline void __iomem *mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip)
 132{
 133        int cpu;
 134
 135        switch(mvchip->soc_variant) {
 136        case MVEBU_GPIO_SOC_VARIANT_ORION:
 137                return mvchip->membase + GPIO_EDGE_MASK_OFF;
 138        case MVEBU_GPIO_SOC_VARIANT_MV78200:
 139                cpu = smp_processor_id();
 140                return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu);
 141        case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
 142                cpu = smp_processor_id();
 143                return mvchip->percpu_membase + GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
 144        default:
 145                BUG();
 146        }
 147}
 148
 149static void __iomem *mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip)
 150{
 151        int cpu;
 152
 153        switch(mvchip->soc_variant) {
 154        case MVEBU_GPIO_SOC_VARIANT_ORION:
 155                return mvchip->membase + GPIO_LEVEL_MASK_OFF;
 156        case MVEBU_GPIO_SOC_VARIANT_MV78200:
 157                cpu = smp_processor_id();
 158                return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu);
 159        case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
 160                cpu = smp_processor_id();
 161                return mvchip->percpu_membase + GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
 162        default:
 163                BUG();
 164        }
 165}
 166
 167/*
 168 * Functions implementing the gpio_chip methods
 169 */
 170
 171int mvebu_gpio_request(struct gpio_chip *chip, unsigned pin)
 172{
 173        return pinctrl_request_gpio(chip->base + pin);
 174}
 175
 176void mvebu_gpio_free(struct gpio_chip *chip, unsigned pin)
 177{
 178        pinctrl_free_gpio(chip->base + pin);
 179}
 180
 181static void mvebu_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
 182{
 183        struct mvebu_gpio_chip *mvchip =
 184                container_of(chip, struct mvebu_gpio_chip, chip);
 185        unsigned long flags;
 186        u32 u;
 187
 188        spin_lock_irqsave(&mvchip->lock, flags);
 189        u = readl_relaxed(mvebu_gpioreg_out(mvchip));
 190        if (value)
 191                u |= 1 << pin;
 192        else
 193                u &= ~(1 << pin);
 194        writel_relaxed(u, mvebu_gpioreg_out(mvchip));
 195        spin_unlock_irqrestore(&mvchip->lock, flags);
 196}
 197
 198static int mvebu_gpio_get(struct gpio_chip *chip, unsigned pin)
 199{
 200        struct mvebu_gpio_chip *mvchip =
 201                container_of(chip, struct mvebu_gpio_chip, chip);
 202        u32 u;
 203
 204        if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin)) {
 205                u = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) ^
 206                        readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
 207        } else {
 208                u = readl_relaxed(mvebu_gpioreg_out(mvchip));
 209        }
 210
 211        return (u >> pin) & 1;
 212}
 213
 214static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned pin, int value)
 215{
 216        struct mvebu_gpio_chip *mvchip =
 217                container_of(chip, struct mvebu_gpio_chip, chip);
 218        unsigned long flags;
 219        u32 u;
 220
 221        spin_lock_irqsave(&mvchip->lock, flags);
 222        u = readl_relaxed(mvebu_gpioreg_blink(mvchip));
 223        if (value)
 224                u |= 1 << pin;
 225        else
 226                u &= ~(1 << pin);
 227        writel_relaxed(u, mvebu_gpioreg_blink(mvchip));
 228        spin_unlock_irqrestore(&mvchip->lock, flags);
 229}
 230
 231static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
 232{
 233        struct mvebu_gpio_chip *mvchip =
 234                container_of(chip, struct mvebu_gpio_chip, chip);
 235        unsigned long flags;
 236        int ret;
 237        u32 u;
 238
 239        /* Check with the pinctrl driver whether this pin is usable as
 240         * an input GPIO */
 241        ret = pinctrl_gpio_direction_input(chip->base + pin);
 242        if (ret)
 243                return ret;
 244
 245        spin_lock_irqsave(&mvchip->lock, flags);
 246        u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
 247        u |= 1 << pin;
 248        writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
 249        spin_unlock_irqrestore(&mvchip->lock, flags);
 250
 251        return 0;
 252}
 253
 254static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned pin,
 255                                       int value)
 256{
 257        struct mvebu_gpio_chip *mvchip =
 258                container_of(chip, struct mvebu_gpio_chip, chip);
 259        unsigned long flags;
 260        int ret;
 261        u32 u;
 262
 263        /* Check with the pinctrl driver whether this pin is usable as
 264         * an output GPIO */
 265        ret = pinctrl_gpio_direction_output(chip->base + pin);
 266        if (ret)
 267                return ret;
 268
 269        mvebu_gpio_blink(chip, pin, 0);
 270        mvebu_gpio_set(chip, pin, value);
 271
 272        spin_lock_irqsave(&mvchip->lock, flags);
 273        u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
 274        u &= ~(1 << pin);
 275        writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
 276        spin_unlock_irqrestore(&mvchip->lock, flags);
 277
 278        return 0;
 279}
 280
 281static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
 282{
 283        struct mvebu_gpio_chip *mvchip =
 284                container_of(chip, struct mvebu_gpio_chip, chip);
 285        return irq_create_mapping(mvchip->domain, pin);
 286}
 287
 288/*
 289 * Functions implementing the irq_chip methods
 290 */
 291static void mvebu_gpio_irq_ack(struct irq_data *d)
 292{
 293        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 294        struct mvebu_gpio_chip *mvchip = gc->private;
 295        u32 mask = ~(1 << (d->irq - gc->irq_base));
 296
 297        irq_gc_lock(gc);
 298        writel_relaxed(mask, mvebu_gpioreg_edge_cause(mvchip));
 299        irq_gc_unlock(gc);
 300}
 301
 302static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
 303{
 304        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 305        struct mvebu_gpio_chip *mvchip = gc->private;
 306        u32 mask = 1 << (d->irq - gc->irq_base);
 307
 308        irq_gc_lock(gc);
 309        gc->mask_cache &= ~mask;
 310        writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip));
 311        irq_gc_unlock(gc);
 312}
 313
 314static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
 315{
 316        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 317        struct mvebu_gpio_chip *mvchip = gc->private;
 318        u32 mask = 1 << (d->irq - gc->irq_base);
 319
 320        irq_gc_lock(gc);
 321        gc->mask_cache |= mask;
 322        writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip));
 323        irq_gc_unlock(gc);
 324}
 325
 326static void mvebu_gpio_level_irq_mask(struct irq_data *d)
 327{
 328        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 329        struct mvebu_gpio_chip *mvchip = gc->private;
 330        u32 mask = 1 << (d->irq - gc->irq_base);
 331
 332        irq_gc_lock(gc);
 333        gc->mask_cache &= ~mask;
 334        writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip));
 335        irq_gc_unlock(gc);
 336}
 337
 338static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
 339{
 340        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 341        struct mvebu_gpio_chip *mvchip = gc->private;
 342        u32 mask = 1 << (d->irq - gc->irq_base);
 343
 344        irq_gc_lock(gc);
 345        gc->mask_cache |= mask;
 346        writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip));
 347        irq_gc_unlock(gc);
 348}
 349
 350/*****************************************************************************
 351 * MVEBU GPIO IRQ
 352 *
 353 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
 354 * value of the line or the opposite value.
 355 *
 356 * Level IRQ handlers: DATA_IN is used directly as cause register.
 357 *                     Interrupt are masked by LEVEL_MASK registers.
 358 * Edge IRQ handlers:  Change in DATA_IN are latched in EDGE_CAUSE.
 359 *                     Interrupt are masked by EDGE_MASK registers.
 360 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
 361 *                     the polarity to catch the next line transaction.
 362 *                     This is a race condition that might not perfectly
 363 *                     work on some use cases.
 364 *
 365 * Every eight GPIO lines are grouped (OR'ed) before going up to main
 366 * cause register.
 367 *
 368 *                    EDGE  cause    mask
 369 *        data-in   /--------| |-----| |----\
 370 *     -----| |-----                         ---- to main cause reg
 371 *           X      \----------------| |----/
 372 *        polarity    LEVEL          mask
 373 *
 374 ****************************************************************************/
 375
 376static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 377{
 378        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 379        struct irq_chip_type *ct = irq_data_get_chip_type(d);
 380        struct mvebu_gpio_chip *mvchip = gc->private;
 381        int pin;
 382        u32 u;
 383
 384        pin = d->hwirq;
 385
 386        u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin);
 387        if (!u) {
 388                return -EINVAL;
 389        }
 390
 391        type &= IRQ_TYPE_SENSE_MASK;
 392        if (type == IRQ_TYPE_NONE)
 393                return -EINVAL;
 394
 395        /* Check if we need to change chip and handler */
 396        if (!(ct->type & type))
 397                if (irq_setup_alt_chip(d, type))
 398                        return -EINVAL;
 399
 400        /*
 401         * Configure interrupt polarity.
 402         */
 403        switch(type) {
 404        case IRQ_TYPE_EDGE_RISING:
 405        case IRQ_TYPE_LEVEL_HIGH:
 406                u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
 407                u &= ~(1 << pin);
 408                writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
 409                break;
 410        case IRQ_TYPE_EDGE_FALLING:
 411        case IRQ_TYPE_LEVEL_LOW:
 412                u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
 413                u |= 1 << pin;
 414                writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
 415                break;
 416        case IRQ_TYPE_EDGE_BOTH: {
 417                u32 v;
 418
 419                v = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)) ^
 420                        readl_relaxed(mvebu_gpioreg_data_in(mvchip));
 421
 422                /*
 423                 * set initial polarity based on current input level
 424                 */
 425                u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
 426                if (v & (1 << pin))
 427                        u |= 1 << pin;          /* falling */
 428                else
 429                        u &= ~(1 << pin);       /* rising */
 430                writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
 431                break;
 432        }
 433        }
 434        return 0;
 435}
 436
 437static void mvebu_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 438{
 439        struct mvebu_gpio_chip *mvchip = irq_get_handler_data(irq);
 440        u32 cause, type;
 441        int i;
 442
 443        if (mvchip == NULL)
 444                return;
 445
 446        cause = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) &
 447                readl_relaxed(mvebu_gpioreg_level_mask(mvchip));
 448        cause |= readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)) &
 449                readl_relaxed(mvebu_gpioreg_edge_mask(mvchip));
 450
 451        for (i = 0; i < mvchip->chip.ngpio; i++) {
 452                int irq;
 453
 454                irq = mvchip->irqbase + i;
 455
 456                if (!(cause & (1 << i)))
 457                        continue;
 458
 459                type = irqd_get_trigger_type(irq_get_irq_data(irq));
 460                if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
 461                        /* Swap polarity (race with GPIO line) */
 462                        u32 polarity;
 463
 464                        polarity = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
 465                        polarity ^= 1 << i;
 466                        writel_relaxed(polarity, mvebu_gpioreg_in_pol(mvchip));
 467                }
 468                generic_handle_irq(irq);
 469        }
 470}
 471
 472static struct platform_device_id mvebu_gpio_ids[] = {
 473        {
 474                .name = "orion-gpio",
 475        }, {
 476                .name = "mv78200-gpio",
 477        }, {
 478                .name = "armadaxp-gpio",
 479        }, {
 480                /* sentinel */
 481        },
 482};
 483MODULE_DEVICE_TABLE(platform, mvebu_gpio_ids);
 484
 485static struct of_device_id mvebu_gpio_of_match[] __devinitdata = {
 486        {
 487                .compatible = "marvell,orion-gpio",
 488                .data       = (void*) MVEBU_GPIO_SOC_VARIANT_ORION,
 489        },
 490        {
 491                .compatible = "marvell,mv78200-gpio",
 492                .data       = (void*) MVEBU_GPIO_SOC_VARIANT_MV78200,
 493        },
 494        {
 495                .compatible = "marvell,armadaxp-gpio",
 496                .data       = (void*) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
 497        },
 498        {
 499                /* sentinel */
 500        },
 501};
 502MODULE_DEVICE_TABLE(of, mvebu_gpio_of_match);
 503
 504static int __devinit mvebu_gpio_probe(struct platform_device *pdev)
 505{
 506        struct mvebu_gpio_chip *mvchip;
 507        const struct of_device_id *match;
 508        struct device_node *np = pdev->dev.of_node;
 509        struct resource *res;
 510        struct irq_chip_generic *gc;
 511        struct irq_chip_type *ct;
 512        unsigned int ngpios;
 513        int soc_variant;
 514        int i, cpu, id;
 515
 516        match = of_match_device(mvebu_gpio_of_match, &pdev->dev);
 517        if (match)
 518                soc_variant = (int) match->data;
 519        else
 520                soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
 521
 522        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 523        if (! res) {
 524                dev_err(&pdev->dev, "Cannot get memory resource\n");
 525                return -ENODEV;
 526        }
 527
 528        mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), GFP_KERNEL);
 529        if (! mvchip){
 530                dev_err(&pdev->dev, "Cannot allocate memory\n");
 531                return -ENOMEM;
 532        }
 533
 534        if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
 535                dev_err(&pdev->dev, "Missing ngpios OF property\n");
 536                return -ENODEV;
 537        }
 538
 539        id = of_alias_get_id(pdev->dev.of_node, "gpio");
 540        if (id < 0) {
 541                dev_err(&pdev->dev, "Couldn't get OF id\n");
 542                return id;
 543        }
 544
 545        mvchip->soc_variant = soc_variant;
 546        mvchip->chip.label = dev_name(&pdev->dev);
 547        mvchip->chip.dev = &pdev->dev;
 548        mvchip->chip.request = mvebu_gpio_request;
 549        mvchip->chip.direction_input = mvebu_gpio_direction_input;
 550        mvchip->chip.get = mvebu_gpio_get;
 551        mvchip->chip.direction_output = mvebu_gpio_direction_output;
 552        mvchip->chip.set = mvebu_gpio_set;
 553        mvchip->chip.to_irq = mvebu_gpio_to_irq;
 554        mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
 555        mvchip->chip.ngpio = ngpios;
 556        mvchip->chip.can_sleep = 0;
 557#ifdef CONFIG_OF
 558        mvchip->chip.of_node = np;
 559#endif
 560
 561        spin_lock_init(&mvchip->lock);
 562        mvchip->membase = devm_request_and_ioremap(&pdev->dev, res);
 563        if (! mvchip->membase) {
 564                dev_err(&pdev->dev, "Cannot ioremap\n");
 565                kfree(mvchip->chip.label);
 566                return -ENOMEM;
 567        }
 568
 569        /* The Armada XP has a second range of registers for the
 570         * per-CPU registers */
 571        if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
 572                res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 573                if (! res) {
 574                        dev_err(&pdev->dev, "Cannot get memory resource\n");
 575                        kfree(mvchip->chip.label);
 576                        return -ENODEV;
 577                }
 578
 579                mvchip->percpu_membase = devm_request_and_ioremap(&pdev->dev, res);
 580                if (! mvchip->percpu_membase) {
 581                        dev_err(&pdev->dev, "Cannot ioremap\n");
 582                        kfree(mvchip->chip.label);
 583                        return -ENOMEM;
 584                }
 585        }
 586
 587        /*
 588         * Mask and clear GPIO interrupts.
 589         */
 590        switch(soc_variant) {
 591        case MVEBU_GPIO_SOC_VARIANT_ORION:
 592                writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
 593                writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
 594                writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
 595                break;
 596        case MVEBU_GPIO_SOC_VARIANT_MV78200:
 597                writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
 598                for (cpu = 0; cpu < 2; cpu++) {
 599                        writel_relaxed(0, mvchip->membase +
 600                                       GPIO_EDGE_MASK_MV78200_OFF(cpu));
 601                        writel_relaxed(0, mvchip->membase +
 602                                       GPIO_LEVEL_MASK_MV78200_OFF(cpu));
 603                }
 604                break;
 605        case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
 606                writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
 607                writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
 608                writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
 609                for (cpu = 0; cpu < 4; cpu++) {
 610                        writel_relaxed(0, mvchip->percpu_membase +
 611                                       GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu));
 612                        writel_relaxed(0, mvchip->percpu_membase +
 613                                       GPIO_EDGE_MASK_ARMADAXP_OFF(cpu));
 614                        writel_relaxed(0, mvchip->percpu_membase +
 615                                       GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu));
 616                }
 617                break;
 618        default:
 619                BUG();
 620        }
 621
 622        gpiochip_add(&mvchip->chip);
 623
 624        /* Some gpio controllers do not provide irq support */
 625        if (!of_irq_count(np))
 626                return 0;
 627
 628        /* Setup the interrupt handlers. Each chip can have up to 4
 629         * interrupt handlers, with each handler dealing with 8 GPIO
 630         * pins. */
 631        for (i = 0; i < 4; i++) {
 632                int irq;
 633                irq = platform_get_irq(pdev, i);
 634                if (irq < 0)
 635                        continue;
 636                irq_set_handler_data(irq, mvchip);
 637                irq_set_chained_handler(irq, mvebu_gpio_irq_handler);
 638        }
 639
 640        mvchip->irqbase = irq_alloc_descs(-1, 0, ngpios, -1);
 641        if (mvchip->irqbase < 0) {
 642                dev_err(&pdev->dev, "no irqs\n");
 643                kfree(mvchip->chip.label);
 644                return -ENOMEM;
 645        }
 646
 647        gc = irq_alloc_generic_chip("mvebu_gpio_irq", 2, mvchip->irqbase,
 648                                    mvchip->membase, handle_level_irq);
 649        if (! gc) {
 650                dev_err(&pdev->dev, "Cannot allocate generic irq_chip\n");
 651                kfree(mvchip->chip.label);
 652                return -ENOMEM;
 653        }
 654
 655        gc->private = mvchip;
 656        ct = &gc->chip_types[0];
 657        ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
 658        ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
 659        ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
 660        ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
 661        ct->chip.name = mvchip->chip.label;
 662
 663        ct = &gc->chip_types[1];
 664        ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 665        ct->chip.irq_ack = mvebu_gpio_irq_ack;
 666        ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
 667        ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
 668        ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
 669        ct->handler = handle_edge_irq;
 670        ct->chip.name = mvchip->chip.label;
 671
 672        irq_setup_generic_chip(gc, IRQ_MSK(ngpios), 0,
 673                               IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
 674
 675        /* Setup irq domain on top of the generic chip. */
 676        mvchip->domain = irq_domain_add_legacy(np, mvchip->chip.ngpio,
 677                                               mvchip->irqbase, 0,
 678                                               &irq_domain_simple_ops,
 679                                               mvchip);
 680        if (!mvchip->domain) {
 681                dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
 682                        mvchip->chip.label);
 683                irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST,
 684                                        IRQ_LEVEL | IRQ_NOPROBE);
 685                kfree(gc);
 686                kfree(mvchip->chip.label);
 687                return -ENODEV;
 688        }
 689
 690        return 0;
 691}
 692
 693static struct platform_driver mvebu_gpio_driver = {
 694        .driver         = {
 695                .name           = "mvebu-gpio",
 696                .owner          = THIS_MODULE,
 697                .of_match_table = mvebu_gpio_of_match,
 698        },
 699        .probe          = mvebu_gpio_probe,
 700        .id_table       = mvebu_gpio_ids,
 701};
 702
 703static int __init mvebu_gpio_init(void)
 704{
 705        return platform_driver_register(&mvebu_gpio_driver);
 706}
 707postcore_initcall(mvebu_gpio_init);
 708
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