linux/drivers/spi/spi-s3c24xx.c
<<
v3.3.4/spalue 3.4/formue 3.4a v3.3. href="../linux+v3.7.9/drivers/spi/spi-s3c24xx.c"> v3.3.4img src="../.static/gfx/right.png" alt=">>"> v4/spalue v4spal class="lxr_search"> v3. v3.3.4input typ v3hidden" nam v3navtarget" > v3"> v3.3.4input typ v3text" nam v3search" idv3search"> v3.3.4butt typ v3submit">Search v3.3.Prefse 3.4/a> v4/spalue3.3. .4/divue3.3. .4form ac val="ajax+*" method="post" onsubmit="return false;"> v4input typ v3hidden" nam v3ajax_lookup" idv3ajax_lookup" > v3"> 3.3. .4/formue 3.3. .4div class="headingbott m">e 4div idv3file_contents"u
. .14/a>4spal class="comment">/*4/spalue. .24/a>4spal class="comment"> * Copyright (c) 2006 Ben Dooks4/spalue. .34/a>4spal class="comment"> * Copyright 2006-2009 Simtec Electronics4/spalue. .44/a>4spal class="comment"> *      Ben Dooks <ben@simtec.co.uk>4/spalue. .54/a>4spal class="comment"> *4/spalue. .64/a>4spal class="comment"> * This program is free software; you cal redistribute it and/or modify4/spalue. .74/a>4spal class="comment"> * it under the terms of the GNU General Public License vers"
	 2 as4/spalue. .84/a>4spal class="comment"> * published by the Free Software Founda val.4/spalue. .94/a>4spal class="comment"> *4/spalue. >
  a>4spal class="comment">*/4/spalue. 114/a>e. 124/a>#include <linux/init.h4/a>>e. 134/a>#include <linux/spinlock.h4/a>>e. 144/a>#include <linux/workqueue.h4/a>>e. 154/a>#include <linux/interrupt.h4/a>>e. 164/a>#include <linux/delay.h4/a>>e. 174/a>#include <linux/errno.h4/a>>e. 184/a>#include <linux/err.h4/a>>e. 194/a>#include <linux/clk.h4/a>>e. 204/a>#include <linux/platform_device.h4/a>>e. 214/a>#include <linux/gpio.h4/a>>e. 224/a>#include <linux/io.h4/a>>e. 234/a>#include <linux/slab.h4/a>>e. 244/a>e. 254/a>#include <linux/spi/spi.h4/a>>e. 264/a>#include <linux/spi/spi_bitbang.h4/a>>e. 274/a>#include <linux/spi/s3c24xx.h4/a>>e. 284/a>#include <linux/module.h4/a>>e. 294/a>e. 304/a>#include <plat/regs-spi.h4/a>>e. 314/a>e. 324/a>#include <plat/fiq.h4/a>>e. 334/a>#include <asm/fiq.h4/a>>e. 344/a>e. 354/a>#include "spi-s3c24xx-fiq.h4/a>"e. 364/a>e. 374/a>4spal class="comment">/**4/spalue. 384/a>4spal class="comment"> * s3c24xx_spi_devstate - per device data4/spalue. 394/a>4spal class="comment"> * @hz: Last frequency calculated for @sppre field.4/spalue. 4
  a>4spal class="comment"> * @mode: Last mode setting for the @spcon field.4/spalue. 414/a>4spal class="comment"> * @spcon: V>
   to writ  to the SPCON register.4/spalue. 424/a>4spal class="comment"> * @sppre: V>
   to writ  to the SPPRE register.4/spalue. 434/a>4spal class="comment"> */4/spalue. 444/a>struct.4a href="+code=s3c24xx_spi_devstate" class="sref">s3c24xx_spi_devstate4/a> {e. 454/a>        unsigned int3. .4a href="+code=hz" class="sref">hz4/a>;e. 464/a>        unsigned int3. .4a href="+code=mode" class="sref">mode4/a>;e. 474/a>        4a href="+code=u8" class="sref">u84/a>              4a href="+code=spcon" class="sref">spcon4/a>;e. 484/a>        4a href="+code=u8" class="sref">u84/a>              4a href="+code=sppre" class="sref">sppre4/a>;e. 494/a>};e. 504/a>e. 514/a>enum 4a href="+code=spi_fiq_mode" class="sref">spi_fiq_mode4/a> {e. 524/a>        4a href="+code=FIQ_MODE_NONE" class="sref">FIQ_MODE_NONE4/a>   = 0,e. 534/a>        4a href="+code=FIQ_MODE_TX" class="sref">FIQ_MODE_TX4/a>     = 1,e. 544/a>        4a href="+code=FIQ_MODE_RX" class="sref">FIQ_MODE_RX4/a>     = 2,e. 554/a>        4a href="+code=FIQ_MODE_TXRX" class="sref">FIQ_MODE_TXRX4/a>   = 3,e. 564/a>};e. 574/a>e. 584/a>struct.4a href="+code=s3c24xx_spi" class="sref">s3c24xx_spi4/a> {e. 594/a>        4spal class="comment">/* bitbang has to be first */4/spalue. 604/a>        struct.4a href="+code=spi_bitbang" class="sref">spi_bitbang4/a>       4a href="+code=bitbang" class="sref">bitbang4/a>;e. 614/a>        struct.4a href="+code=comple val" class="sref">comple val4/a>        4a href="+code=done" class="sref">done4/a>;e. 624/a>e. 634/a>        void 4a href="+code=__iomem" class="sref">__iomem4/a>            *4a href="+code=regs" class="sref">regs4/a>;e. 644/a>        int3. ...................4a href="+code=irq" class="sref">irq4/a>;e. 654/a>        int3. ...................4a href="+code=lel" class="sref">lel4/a>;e. 664/a>        int3. ...................4a href="+code=count" class="sref">count4/a>;e. 674/a>e. 684/a>        struct.4a href="+code=fiq_handler" class="sref">fiq_handler4/a>       4a href="+code=fiq_handler" class="sref">fiq_handler4/a>;e. 694/a>        enum 4a href="+code=spi_fiq_mode" class="sref">spi_fiq_mode4/a>        4a href="+code=fiq_mode" class="sref">fiq_mode4/a>;e. 704/a>        unsigned char............4a href="+code=fiq_inuse" class="sref">fiq_inuse4/a>;e. 714/a>        unsigned char............4a href="+code=fiq_claimed" class="sref">fiq_claimed4/a>;e. 724/a>e. 734/a>        void                    (*4a href="+code=set_cs" class="sref">set_cs4/a>)(struct.4a href="+code=s3c2410_spi_info" class="sref">s3c2410_spi_info4/a> *4a href="+code=spi" class="sref">spi4/a>,e. 744/a>                                          int34a href="+code=cs" class="sref">cs4/a>, int34a href="+code=pol" class="sref">pol4/a>);e. 754/a>e. 764/a>        4spal class="comment">/* data buffers */4/spalue. 774/a>        const unsigned char.....*4a href="+code=tx" class="sref">tx4/a>;e. 784/a>        unsigned char...........*4a href="+code=rx" class="sref">rx4/a>;e. 794/a>e. 804/a>        struct.4a href="+code=clk" class="sref">clk4/a>              *4a href="+code=clk" class="sref">clk4/a>;e. 814/a>        struct.4a href="+code=resource" class="sref">resource4/a>         *4a href="+code=ioarea" class="sref">ioarea4/a>;e. 824/a>        struct.4a href="+code=spi_master" class="sref">spi_master4/a>       *4a href="+code=master" class="sref">master4/a>;e. 834/a>        struct.4a href="+code=spi_device" class="sref">spi_device4/a>       *4a href="+code=curdev" class="sref">curdev4/a>;e. 844/a>        struct.4a href="+code=device" class="sref">device4/a>           *4a href="+code=dev" class="sref">dev4/a>;e. 854/a>        struct.4a href="+code=s3c2410_spi_info" class="sref">s3c2410_spi_info4/a> *4a href="+code=pdata" class="sref">pdata4/a>;e. 864/a>};e. 874/a>e. 884/a>e. 894/a>#define.4a href="+code=SPCON_DEFAULT" class="sref">SPCON_DEFAULT4/a> (4a href="+code=S3C2410_SPCON_MSTR" class="sref">S3C2410_SPCON_MSTR4/a> |.4a href="+code=S3C2410_SPCON_SMOD_INT" class="sref">S3C2410_SPCON_SMOD_INT4/a>)e. 904/a>#define.4a href="+code=SPPIN_DEFAULT" class="sref">SPPIN_DEFAULT4/a> (4a href="+code=S3C2410_SPPIN_KEEP" class="sref">S3C2410_SPPIN_KEEP4/a>)e. 914/a>e. 924/a>static.4a href="+code=inline" class="sref">inline4/a> struct.4a href="+code=s3c24xx_spi" class="sref">s3c24xx_spi4/a> *4a href="+code=to_hw" class="sref">to_hw4/a>(struct.4a href="+code=spi_device" class="sref">spi_device4/a> *4a href="+code=sdev" class="sref">sdev4/a>)e. 934/a>{e. 944/a>        return 4a href="+code=spi_master_get_devdata" class="sref">spi_master_get_devdata4/a>(4a href="+code=sdev" class="sref">sdev4/a>->4a href="+code=master" class="sref">master4/a>);e. 954/a>}e. 964/a>e. 974/a>static.void 4a href="+code=s3c24xx_spi_gpiocs" class="sref">s3c24xx_spi_gpiocs4/a>(struct.4a href="+code=s3c2410_spi_info" class="sref">s3c2410_spi_info4/a> *4a href="+code=spi" class="sref">spi4/a>, int34a href="+code=cs" class="sref">cs4/a>, int34a href="+code=pol" class="sref">pol4/a>)e. 984/a>{e. 994/a>        4a href="+code=gpio_set_ >
  " class="sref">gpio_set_ >
  4/a>(4a href="+code=spi" class="sref">spi4/a>->4a href="+code=pin_cs" class="sref">pin_cs4/a>, 4a href="+code=pol" class="sref">pol4/a>);e.1004/a>}e.1014/a>e.1024/a>static.void 4a href="+code=s3c24xx_spi_chipsel" class="sref">s3c24xx_spi_chipsel4/a>(struct.4a href="+code=spi_device" class="sref">spi_device4/a> *4a href="+code=spi" class="sref">spi4/a>, int34a href="+code= >
  " class="sref"> >
  4/a>)e.1034/a>{e.1044/a>        struct.4a href="+code=s3c24xx_spi_devstate" class="sref">s3c24xx_spi_devstate4/a> *4a href="+code=cs" class="sref">cs4/a> =.4a href="+code=spi" class="sref">spi4/a>->4a href="+code=controller_state" class="sref">controller_state4/a>;e.1054/a>        struct.4a href="+code=s3c24xx_spi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" class="sref">hw4/a> =.4a href="+code=to_hw" class="sref">to_hw4/a>(4a href="+code=spi" class="sref">spi4/a>);e.1064/a>        unsigned int34a href="+code=cspol" class="sref">cspol4/a> =.4a href="+code=spi" class="sref">spi4/a>->4a href="+code=mode" class="sref">mode4/a> &.4a href="+code=SPI_CS_HIGH" class="sref">SPI_CS_HIGH4/a> ? 1 : 0;e.1074/a>e.1084/a>        4spal class="comment">/* change the chipselect.state and the state of the spi engine.clock */4/spalue.1094/a>e.1104/a>        switch (4a href="+code= >
  " class="sref"> >
  4/a>) {e.1114/a>        case.4a href="+code=BITBANG_CS_INACTIVE" class="sref">BITBANG_CS_INACTIVE4/a>:e.1124/a>                4a href="+code=hw" class="sref">hw4/a>->4a href="+code=set_cs" class="sref">set_cs4/a>(4a href="+code=hw" class="sref">hw4/a>->4a href="+code=pdata" class="sref">pdata4/a>, 4a href="+code=spi" class="sref">spi4/a>->4a href="+code=chip_select" class="sref">chip_select4/a>, 4a href="+code=cspol" class="sref">cspol4/a>^1);e.1134/a>                4a href="+code=writ b" class="sref">writ b4/a>(4a href="+code=cs" class="sref">cs4/a>->4a href="+code=spcon" class="sref">spcon4/a>, 4a href="+code=hw" class="sref">hw4/a>->4a href="+code=regs" class="sref">regs4/a> +.4a href="+code=S3C2410_SPCON" class="sref">S3C2410_SPCON4/a>);e.1144/a>                break;e.1154/a>e.1164/a>        case.4a href="+code=BITBANG_CS_ACTIVE" class="sref">BITBANG_CS_ACTIVE4/a>:e.1174/a>                4a href="+code=writ b" class="sref">writ b4/a>(4a href="+code=cs" class="sref">cs4/a>->4a href="+code=spcon" class="sref">spcon4/a> |.4a href="+code=S3C2410_SPCON_ENSCK" class="sref">S3C2410_SPCON_ENSCK4/a>,e.1184/a>                       4a href="+code=hw" class="sref">hw4/a>->4a href="+code=regs" class="sref">regs4/a> +.4a href="+code=S3C2410_SPCON" class="sref">S3C2410_SPCON4/a>);e.1194/a>                4a href="+code=hw" class="sref">hw4/a>->4a href="+code=set_cs" class="sref">set_cs4/a>(4a href="+code=hw" class="sref">hw4/a>->4a href="+code=pdata" class="sref">pdata4/a>, 4a href="+code=spi" class="sref">spi4/a>->4a href="+code=chip_select" class="sref">chip_select4/a>, 4a href="+code=cspol" class="sref">cspol4/a>);e.1204/a>                break;e.1214/a>        }e.1224/a>}e.1234/a>e.1244/a>static.int34a href="+code=s3c24xx_spi_update_state" class="sref">s3c24xx_spi_update_state4/a>(struct.4a href="+code=spi_device" class="sref">spi_device4/a> *4a href="+code=spi" class="sref">spi4/a>,e.1254/a>                                    struct.4a href="+code=spi_transfer" class="sref">spi_transfer4/a> *4a href="+code=t" class="sref">t4/a>)e.1264/a>{e.1274/a>        struct.4a href="+code=s3c24xx_spi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" class="sref">hw4/a> =.4a href="+code=to_hw" class="sref">to_hw4/a>(4a href="+code=spi" class="sref">spi4/a>);e.1284/a>        struct.4a href="+code=s3c24xx_spi_devstate" class="sref">s3c24xx_spi_devstate4/a> *4a href="+code=cs" class="sref">cs4/a> =.4a href="+code=spi" class="sref">spi4/a>->4a href="+code=controller_state" class="sref">controller_state4/a>;e.1294/a>        unsigned int34a href="+code=bpw" class="sref">bpw4/a>;e.1304/a>        unsigned int34a href="+code=hz" class="sref">hz4/a>;e.1314/a>        unsigned int34a href="+code=div" class="sref">div4/a>;e.1324/a>        unsigned long.4a href="+code=clk" class="sref">clk4/a>;e.1334/a>e.1344/a>        4a href="+code=bpw" class="sref">bpw4/a> =.4a href="+code=t" class="sref">t4/a> ?.4a href="+code=t" class="sref">t4/a>->4a href="+code=bits_per_word" class="sref">bits_per_word4/a> :.4a href="+code=spi" class="sref">spi4/a>->4a href="+code=bits_per_word" class="sref">bits_per_word4/a>;e.1354/a>        4a href="+code=hz" class="sref">hz4/a>  =.4a href="+code=t" class="sref">t4/a> ?.4a href="+code=t" class="sref">t4/a>->4a href="+code=speed_hz" class="sref">speed_hz4/a> :.4a href="+code=spi" class="sref">spi4/a>->4a href="+code=max_speed_hz" class="sref">max_speed_hz4/a>;e.1364/a>e.1374/a>        if (!4a href="+code=bpw" class="sref">bpw4/a>)e.1384/a>                4a href="+code=bpw" class="sref">bpw4/a> =.8;e.1394/a>e.1404/a>        if (!4a href="+code=hz" class="sref">hz4/a>)e.1414/a>                4a href="+code=hz" class="sref">hz4/a> =.4a href="+code=spi" class="sref">spi4/a>->4a href="+code=max_speed_hz" class="sref">max_speed_hz4/a>;e.1424/a>e.1434/a>        if (4a href="+code=bpw" class="sref">bpw4/a> !=.8) {e.1444/a>                4a href="+code=dev_err" class="sref">dev_err4/a>(&4a href="+code=spi" class="sref">spi4/a>->4a href="+code=dev" class="sref">dev4/a>, 4spal class="string">"invalid bits-per-word (%d)\n"bpw4/a>);e.1454/a>                return -4a href="+code=EINVAL" class="sref">EINVAL4/a>;e.1464/a>        }e.1474/a>e.1484/a>        if (4a href="+code=spi" class="sref">spi4/a>->4a href="+code=mode" class="sref">mode4/a> !=.4a href="+code=cs" class="sref">cs4/a>->4a href="+code=mode" class="sref">mode4/a>) {e.1494/a>                4a href="+code=u8" class="sref">u84/a> 4a href="+code=spcon" class="sref">spcon4/a> =.4a href="+code=SPCON_DEFAULT" class="sref">SPCON_DEFAULT4/a> |.4a href="+code=S3C2410_SPCON_ENSCK" class="sref">S3C2410_SPCON_ENSCK4/a>;e.1504/a>e.1514/a>                if (4a href="+code=spi" class="sref">spi4/a>->4a href="+code=mode" class="sref">mode4/a> &.4a href="+code=SPI_CPHA" class="sref">SPI_CPHA4/a>)e.1524/a>                        4a href="+code=spcon" class="sref">spcon4/a> |=.4a href="+code=S3C2410_SPCON_CPHA_FMTB" class="sref">S3C2410_SPCON_CPHA_FMTB4/a>;e.1534/a>e.1544/a>                if (4a href="+code=spi" class="sref">spi4/a>->4a href="+code=mode" class="sref">mode4/a> &.4a href="+code=SPI_CPOL" class="sref">SPI_CPOL4/a>)e.1554/a>                        4a href="+code=spcon" class="sref">spcon4/a> |=.4a href="+code=S3C2410_SPCON_CPOL_HIGH" class="sref">S3C2410_SPCON_CPOL_HIGH4/a>;e.1564/a>e.1574/a>                4a href="+code=cs" class="sref">cs4/a>->4a href="+code=mode" class="sref">mode4/a> =.4a href="+code=spi" class="sref">spi4/a>->4a href="+code=mode" class="sref">mode4/a>;e.1584/a>                4a href="+code=cs" class="sref">cs4/a>->4a href="+code=spcon" class="sref">spcon4/a> =.4a href="+code=spcon" class="sref">spcon4/a>;e.1594/a>        }e.1604/a>e.1614/a>        if (4a href="+code=cs" class="sref">cs4/a>->4a href="+code=hz" class="sref">hz4/a> !=.4a href="+code=hz" class="sref">hz4/a>) {e.1624/a>                4a href="+code=clk" class="sref">clk4/a> =.4a href="+code=clk_get_rate" class="sref">clk_get_rate4/a>(4a href="+code=hw" class="sref">hw4/a>->4a href="+code=clk" class="sref">clk4/a>);e.1634/a>                4a href="+code=div" class="sref">div4/a> =.4a href="+code=DIV_ROUND_UP" class="sref">DIV_ROUND_UP4/a>(4a href="+code=clk" class="sref">clk4/a>, 4a href="+code=hz" class="sref">hz4/a> * 2) - 1;e.1644/a>e.1654/a>                if (4a href="+code=div" class="sref">div4/a> > 255)e.1664/a>                        4a href="+code=div" class="sref">div4/a> =.255;e.1674/a>e.1684/a>                4a href="+code=dev_dbg" class="sref">dev_dbg4/a>(&4a href="+code=spi" class="sref">spi4/a>->4a href="+code=dev" class="sref">dev4/a>, 4spal class="string">"pre-scaler=%d (wanted %d, got %ld)\n".1694/a>                        4a href="+code=div" class="sref">div4/a>, 4a href="+code=hz" class="sref">hz4/a>, 4a href="+code=clk" class="sref">clk4/a> / (2 * (4a href="+code=div" class="sref">div4/a> + 1)));e.1704/a>e.1714/a>                4a href="+code=cs" class="sref">cs4/a>->4a href="+code=hz" class="sref">hz4/a> =.4a href="+code=hz" class="sref">hz4/a>;e.1724/a>                4a href="+code=cs" class="sref">cs4/a>->4a href="+code=sppre" class="sref">sppre4/a> =.4a href="+code=div" class="sref">div4/a>;e.1734/a>        }e.1744/a>e.1754/a>        return 0;e.1764/a>}e.1774/a>e.1784/a>static.int34a href="+code=s3c24xx_spi_setupxfer" class="sref">s3c24xx_spi_setupxfer4/a>(struct.4a href="+code=spi_device" class="sref">spi_device4/a> *4a href="+code=spi" class="sref">spi4/a>,e.1794/a>                                 struct.4a href="+code=spi_transfer" class="sref">spi_transfer4/a> *4a href="+code=t" class="sref">t4/a>)e.1804/a>{e.1814/a>        struct.4a href="+code=s3c24xx_spi_devstate" class="sref">s3c24xx_spi_devstate4/a> *4a href="+code=cs" class="sref">cs4/a> =.4a href="+code=spi" class="sref">spi4/a>->4a href="+code=controller_state" class="sref">controller_state4/a>;e.1824/a>        struct.4a href="+code=s3c24xx_spi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" class="sref">hw4/a> =.4a href="+code=to_hw" class="sref">to_hw4/a>(4a href="+code=spi" class="sref">spi4/a>);e.1834/a>        int34a href="+code=ret" class="sref">ret4/a>;e.1844/a>e.1854/a>        4a href="+code=ret" class="sref">ret4/a> =.4a href="+code=s3c24xx_spi_update_state" class="sref">s3c24xx_spi_update_state4/a>(4a href="+code=spi" class="sref">spi4/a>,.4a href="+code=t" class="sref">t4/a>);e.1864/a>        if (!4a href="+code=ret" class="sref">ret4/a>)e.1874/a>                4a href="+code=writ b" class="sref">writ b4/a>(4a href="+code=cs" class="sref">cs4/a>->4a href="+code=sppre" class="sref">sppre4/a>, 4a href="+code=hw" class="sref">hw4/a>->4a href="+code=regs" class="sref">regs4/a> +.4a href="+code=S3C2410_SPPRE" class="sref">S3C2410_SPPRE4/a>);e.1884/a>e.1894/a>        return 4a href="+code=ret" class="sref">ret4/a>;e.1904/a>}e.1914/a>e.1924/a>static.int34a href="+code=s3c24xx_spi_setup" class="sref">s3c24xx_spi_setup4/a>(struct.4a href="+code=spi_device" class="sref">spi_device4/a> *4a href="+code=spi" class="sref">spi4/a>)e.1934/a>{e.1944/a>        struct.4a href="+code=s3c24xx_spi_devstate" class="sref">s3c24xx_spi_devstate4/a> *4a href="+code=cs" class="sref">cs4/a> =.4a href="+code=spi" class="sref">spi4/a>->4a href="+code=controller_state" class="sref">controller_state4/a>;e.1954/a>        struct.4a href="+code=s3c24xx_spi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" class="sref">hw4/a> =.4a href="+code=to_hw" class="sref">to_hw4/a>(4a href="+code=spi" class="sref">spi4/a>);e.1964/a>        int34a href="+code=ret" class="sref">ret4/a>;e.1974/a>e.1984/a>        4spal class="comment">/* allocate settings on the first call */4/spalue.1994/a>        if (!4a href="+code=cs" class="sref">cs4/a>) {e.2004/a>                4a href="+code=cs" class="sref">cs4/a> =.4a href="+code=kzalloc" class="sref">kzalloc4/a>(sizeof(struct.4a href="+code=s3c24xx_spi_devstate" class="sref">s3c24xx_spi_devstate4/a>), 4a href="+code=GFP_KERNEL" class="sref">GFP_KERNEL4/a>);e.2014/a>                if (!4a href="+code=cs" class="sref">cs4/a>) {e.2024/a>                        4a href="+code=dev_err" class="sref">dev_err4/a>(&4a href="+code=spi" class="sref">spi4/a>->4a href="+code=dev" class="sref">dev4/a>, 4spal class="string">"no memory for controller state\n".2034/a>                        return -4a href="+code=ENOMEM" class="sref">ENOMEM4/a>;e.2044/a>                }e.2054/a>e.2064/a>                4a href="+code=cs" class="sref">cs4/a>->4a href="+code=spcon" class="sref">spcon4/a> =.4a href="+code=SPCON_DEFAULT" class="sref">SPCON_DEFAULT4/a>;e.2074/a>                4a href="+code=cs" class="sref">cs4/a>->4a href="+code=hz" class="sref">hz4/a> =.-1;e.2084/a>                4a href="+code=spi" class="sref">spi4/a>->4a href="+code=controller_state" class="sref">controller_state4/a> =.4a href="+code=cs" class="sref">cs4/a>;e.2094/a>        }e.2104/a>e.2114/a>        4spal class="comment">/* initialise the state from the device */4/spalue.2124/a>        4a href="+code=ret" class="sref">ret4/a> =.4a href="+code=s3c24xx_spi_update_state" class="sref">s3c24xx_spi_update_state4/a>(4a href="+code=spi" class="sref">spi4/a>,.4a href="+code=NULL" class="sref">NULL4/a>);e.2134/a>        if (4a href="+code=ret" class="sref">ret4/a>)e.2144/a>                return 4a href="+code=ret" class="sref">ret4/a>;e.2154/a>e.2164/a>        4a href="+code=spin_lock" class="sref">spin_lock4/a>(&4a href="+code=hw" class="sref">hw4/a>->4a href="+code=bitbang" class="sref">bitbang4/a>.4a href="+code=lock" class="sref">lock4/a>);e.2174/a>        if (!4a href="+code=hw" class="sref">hw4/a>->4a href="+code=bitbang" class="sref">bitbang4/a>.4a href="+code=busy" class="sref">busy4/a>) {e.2184/a>                4a href="+code=hw" class="sref">hw4/a>->4a href="+code=bitbang" class="sref">bitbang4/a>.4a href="+code=chipselect" class="sref">chipselect4/a>(4a href="+code=spi" class="sref">spi4/a>,.4a href="+code=BITBANG_CS_INACTIVE" class="sref">BITBANG_CS_INACTIVE4/a>);e.2194/a>                4spal class="comment">/* need to ndelay for 0.5 clocktick ? */4/spalue.2204/a>        }e.2214/a>        4a href="+code=spin_unlock" class="sref">spin_unlock4/a>(&4a href="+code=hw" class="sref">hw4/a>->4a href="+code=bitbang" class="sref">bitbang4/a>.4a href="+code=lock" class="sref">lock4/a>);e.2224/a>e.2234/a>        return 0;e.2244/a>}e.2254/a>e.2264/a>static.void 4a href="+code=s3c24xx_spi_cleanup" class="sref">s3c24xx_spi_cleanup4/a>(struct.4a href="+code=spi_device" class="sref">spi_device4/a> *4a href="+code=spi" class="sref">spi4/a>)e.2274/a>{e.2284/a>        4a href="+code=kfree" class="sref">kfree4/a>(4a href="+code=spi" class="sref">spi4/a>->4a href="+code=controller_state" class="sref">controller_state4/a>);e.2294/a>}e.2304/a>e.2314/a>static.4a href="+code=inline" class="sref">inline4/a> unsigned int34a href="+code=hw_txbyte" class="sref">hw_txbyte4/a>(struct.4a href="+code=s3c24xx_spi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" class="sref">hw4/a>, int34a href="+code=count" class="sref">count4/a>)e.2324/a>{e.2334/a>        return 4a href="+code=hw" class="sref">hw4/a>->4a href="+code=tx" class="sref">tx4/a> ?.4a href="+code=hw" class="sref">hw4/a>->4a href="+code=tx" class="sref">tx4/a>[4a href="+code=count" class="sref">count4/a>] : 0;e.2344/a>}e.2354/a>e.2364/a>#ifdef.4a href="+code=CONFIG_SPI_S3C24XX_FIQ" class="sref">CONFIG_SPI_S3C24XX_FIQ4/a>e.2374/a>4spal class="comment">/* Support for FIQ based pseudo-DMA to improve the transfer speed.4/spalue.2384/a>4spal class="comment"> *4/spalue.2394/a>4spal class="comment"> * This code uses the assembly helper in spi_s3c24xx_spi.S which is4/spalue.2404/a>4spal class="comment"> * used by the FIQ core to move data between main memory and the peripheral4/spalue.2414/a>4spal class="comment"> * block. Since this is code running on the processor, there is no problem4/spalue.2424/a>4spal class="comment"> * with cache coherency of the buffers, so we cal use any buffer we like.4/spalue.2434/a>4spal class="comment"> */4/spalue.2444/a>e.2454/a>4spal class="comment">/**4/spalue.2464/a>4spal class="comment"> * struct.spi_fiq_code - FIQ code and header4/spalue.2474/a>4spal class="comment"> * @length: The length of the code fragment, excluding this header.4/spalue.2484/a>4spal class="comment"> * @ack_offset: The offset from @data to the word to place the IRQ ACK bit at.4/spalue.2494/a>4spal class="comment"> * @data: The code itself to install as a FIQ handler.4/spalue.2504/a>4spal class="comment"> */4/spalue.2514/a>struct.4a href="+code=spi_fiq_code" class="sref">spi_fiq_code4/a> {e.2524/a>        4a href="+code=u32" class="sref">u324/a>     4a href="+code=length" class="sref">length4/a>;e.2534/a>        4a href="+code=u32" class="sref">u324/a>     4a href="+code=ack_offset" class="sref">ack_offset4/a>;e.2544/a>        4a href="+code=u8" class="sref">u84/a>      4a href="+code=data" class="sref">data4/a>[0];e.2554/a>};e.2564/a>e.2574/a>extern struct.4a href="+code=spi_fiq_code" class="sref">spi_fiq_code4/a> 4a href="+code=s3c24xx_spi_fiq_txrx" class="sref">s3c24xx_spi_fiq_txrx4/a>;e.2584/a>extern struct.4a href="+code=spi_fiq_code" class="sref">spi_fiq_code4/a> 4a href="+code=s3c24xx_spi_fiq_tx" class="sref">s3c24xx_spi_fiq_tx4/a>;e.2594/a>extern struct.4a href="+code=spi_fiq_code" class="sref">spi_fiq_code4/a> 4a href="+code=s3c24xx_spi_fiq_rx" class="sref">s3c24xx_spi_fiq_rx4/a>;e.2604/a>e.2614/a>4spal class="comment">/**4/spalue.2624/a>4spal class="comment"> * ack_bit - turn IRQ into IRQ acknowledgement bit4/spalue.2634/a>4spal class="comment"> * @irq: The interrupt number4/spalue.2644/a>4spal class="comment"> *4/spalue.2654/a>4spal class="comment"> * Returns the bit to writ  to the interrupt acknowledge register.4/spalue.2664/a>4spal class="comment"> */4/spalue.2674/a>static.4a href="+code=inline" class="sref">inline4/a> 4a href="+code=u32" class="sref">u324/a> 4a href="+code=ack_bit" class="sref">ack_bit4/a>(unsigned int34a href="+code=irq" class="sref">irq4/a>)e.2684/a>{e.2694/a>        return 1 << (4a href="+code=irq" class="sref">irq4/a> - 4a href="+code=IRQ_EINT0" class="sref">IRQ_EINT04/a>);e.2704/a>}e.2714/a>e.2724/a>4spal class="comment">/**4/spalue.2734/a>4spal class="comment"> * s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer4/spalue.2744/a>4spal class="comment"> * @hw: The hardware state.4/spalue.2754/a>4spal class="comment"> *4/spalue.2764/a>4spal class="comment"> * Claim the FIQ handler (only one cal be active at any one time) and4/spalue.2774/a>4spal class="comment"> * then setup the correct.transfer code for this transfer.4/spalue.2784/a>4spal class="comment"> *4/spalue.2794/a>4spal class="comment"> * This call updates all the necessary state information if successful,4/spalue.2804/a>4spal class="comment"> * so the caller does not need to do anything more than start the transfer4/spalue.2814/a>4spal class="comment"> * as normal, since the IRQ will have been re-routed to the FIQ handler.4/spalue.2824/a>4spal class="comment">*/4/spalue.2834/a>void 4a href="+code=s3c24xx_spi_tryfiq" class="sref">s3c24xx_spi_tryfiq4/a>(struct.4a href="+code=s3c24xx_spi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" class="sref">hw4/a>)e.2844/a>{e.2854/a>        struct.4a href="+code=pt_regs" class="sref">pt_regs4/a> 4a href="+code=regs" class="sref">regs4/a>;e.2864/a>        enum.4a href="+code=spi_fiq_mode" class="sref">spi_fiq_mode4/a> 4a href="+code=mode" class="sref">mode4/a>;e.2874/a>        struct.4a href="+code=spi_fiq_code" class="sref">spi_fiq_code4/a> *4a href="+code=code" class="sref">code4/a>;e.2884/a>        int34a href="+code=ret" class="sref">ret4/a>;e.2894/a>e.2904/a>        if (!4a href="+code=hw" class="sref">hw4/a>->4a href="+code=fiq_claimed" class="sref">fiq_claimed4/a>) {e.2914/a>                4spal class="comment">/* try and claim fiq if we haven't got it, and if not4/spalue.2924/a>4spal class="comment">                 * then return and simply use another.transfer method */4/spalue.2934/a>e.2944/a>                4a href="+code=ret" class="sref">ret4/a> =.4a href="+code=claim_fiq" class="sref">claim_fiq4/a>(&4a href="+code=hw" class="sref">hw4/a>->4a href="+code=fiq_handler" class="sref">fiq_handler4/a>);e.2954/a>                if (4a href="+code=ret" class="sref">ret4/a>)e.2964/a>                        return;e.2974/a>        }e.2984/a>e.2994/a>        if (4a href="+code=hw" class="sref">hw4/a>->4a href="+code=tx" class="sref">tx4/a> &&.!4a href="+code=hw" class="sref">hw4/a>->4a href="+code=rx" class="sref">rx4/a>)e.3004/a>                4a href="+code=mode" class="sref">mode4/a> =.4a href="+code=FIQ_MODE_TX" class="sref">FIQ_MODE_TX4/a>;e.3014/a>        else if (4a href="+code=hw" class="sref">hw4/a>->4a href="+code=rx" class="sref">rx4/a> &&.!4a href="+code=hw" class="sref">hw4/a>->4a href="+code=tx" class="sref">tx4/a>)e.3024/a>                4a href="+code=mode" class="sref">mode4/a> =.4a href="+code=FIQ_MODE_RX" class="sref">FIQ_MODE_RX4/a>;e.3034/a>        elsee.3044/a>                4a href="+code=mode" class="sref">mode4/a> =.4a href="+code=FIQ_MODE_TXRX" class="sref">FIQ_MODE_TXRX4/a>;e.3054/a>e.3064/a>        4a href="+code=regs" class="sref">regs4/a>.4a href="+code=uregs" class="sref">uregs4/a>[4a href="+code=fiq_rspi" class="sref">fiq_rspi4/a>] = (long)4a href="+code=hw" class="sref">hw4/a>->4a href="+code=regs" class="sref">regs4/a>;e.3074/a>        4a href="+code=regs" class="sref">regs4/a>.4a href="+code=uregs" class="sref">uregs4/a>[4a href="+code=fiq_rrx" class="sref">fiq_rrx4/a>]  = (long)4a href="+code=hw" class="sref">hw4/a>->4a href="+code=rx" class="sref">rx4/a>;e.3084/a>        4a href="+code=regs" class="sref">regs4/a>.4a href="+code=uregs" class="sref">uregs4/a>[4a href="+code=fiq_rtx" class="sref">fiq_rtx4/a>]  = (long)4a href="+code=hw" class="sref">hw4/a>->4a href="+code=tx" class="sref">tx4/a> + 1;e.3094/a>        4a href="+code=regs" class="sref">regs4/a>.4a href="+code=uregs" class="sref">uregs4/a>[4a href="+code=fiq_rcount" class="sref">fiq_rcount4/a>] = 4a href="+code=hw" class="sref">hw4/a>->4a href="+code=len" class="sref">len4/a> - 1;e.3104/a>        4a href="+code=regs" class="sref">regs4/a>.4a href="+code=uregs" class="sref">uregs4/a>[4a href="+code=fiq_rirq" class="sref">fiq_rirq4/a>] = (long)4a href="+code=S3C24XX_VA_IRQ" class="sref">S3C24XX_VA_IRQ4/a>;e.3114/a>e.3124/a>        4a href="+code=set_fiq_regs" class="sref">set_fiq_regs4/a>(&4a href="+code=regs" class="sref">regs4/a>);e.3134/a>e.3144/a>        if (4a href="+code=hw" class="sref">hw4/a>->4a href="+code=fiq_mode" class="sref">fiq_mode4/a> !=.4a href="+code=mode" class="sref">mode4/a>) {e.3154/a>                4a href="+code=u32" class="sref">u324/a> *4a href="+code=ack_ptr" class="sref">ack_ptr4/a>;e.3164/a>e.3174/a>                4a href="+code=hw" class="sref">hw4/a>->4a href="+code=fiq_mode" class="sref">fiq_mode4/a>              4spal class="commen(3L199">.1994/a>f="+code=spi" class="srref="drivers/sp 1313L298" class="line" nam v3L298">.2984/a>e<3 href="dr3vers/spi/spi-s3c24xx.c#L319" i3v3L219" class="line" nswitchine" nam v3L314">ef">fiq_mode4/a> !=.4a href="+code=mode" class="sref">mode4/a>) {emode4/a> =.4a href="+code=FIQ_MO:code=mode" class="sref">mode4/a>) {e.317">spi_fiq_code4/a> *4a hreffiq=dev_err" class="sref">spi_fiq_code4/a> 4a href="+code=s3c24xx_spi_fiq_tx" class="sref">s3c24xx_spi_fiq_tx4/a>;e<3 href="dr3vers/spi/spi-s3c24xx.c#L322" i323L202" class="line" nam v3L20breakclass="sref">s3c24xx_spi_fiq_tx4/a>;e<3 href="drivers/spi/spi-s3c24xx.c#L323" i323L203" class="line" ncainecode=mode" class="sref">mode4/a> =.4a href="+code=FIQ_MO:code=mode" class="sref">mode4/a>) {e.317">spi_fiq_code4/a> *4a hreffiq=dev_err" class="sref">spi_fiq_code4/a> 4a href="+code=s3c24xx_spi_fiq_rx" class="sref">s3c24xx_spi_fiq_rx4/a>;e<3 href="dr3vers/spi/spi-s3c24xx.c#L325" i323L155" class="line" nam v3L15breakclass="sref">s3c24xx_spi_fiq_tx4/a>;e<3 href="drivers/spi/spi-s3c24xx.c#L326" i323L296" class="line" ncainecode=mode" class="sref">mode4/a> =.4a href="+code=FIQ_MODE_T:code=mode" class="sref">mode4/a>) {e.317">spi_fiq_code4/a> *4a hreffiq=dev_err" class="sref">spi_fiq_code4/a> 4a href="+code=s3c24xx_spi_fiq_txrx" class="sref">s3c24xx_spi_fiq_txrx4/a>;e<3 href="dr3vers/spi/spi-s3c24xx.c#L328" i3v3L228" class="line" nam v3L15breakclass="sref">s3c24xx_spi_fiq_tx4/a>;e<3 href="dr3vers/spi/spi-s3c24xx.c#L329" i323L219" class="line" ndefault:code=mode" class="sref">mode4/a>) {e.317">spi_fiq_code4/a> *4a hreffiqam v3L317">.317ass="sref">spi4/a>,.4a hrefclass="sref">s3c24xx_spi_fiq_tx4/a>;e<3 href="dr3vers/spi/spi-s3c24xx.c#L331" i333L291" class="line" n"line" nam v3L297">.2974/a>        }e<3 href="dr3vers/spi/spi-s3c24xx.c#L332" i333L222" class="line" nam v3L222">.2224/a>e<3 href="dr3vers/spi/spi-s3c24xx.c#L333" i333L203" class="line" nam v3L317">.317BUG_ON"sref">spi4/a>,BUG_ONfiq_r3L201">.2014/a>  >spi_fiq_code4/a> *4a href="+code=regs" class="sref">regs4/a>);e.2444/a>e<3 href="dr3vers/spi/spi-s3c24xx.c#L335" i333L315" class="line" nam v3L315">.315ass="sref">u324/a> *4a href="+codiq_ram v3L315">.3154/a>                4a href)=dev_err" class="sre >spi_fiq_code4/a> *4a hrefef="+code=spi" class="sref">u84/a>      4a href=err" class="sre >spi_fiq_code4/a> *4a hrefef="+code=spi" class="sref">u324/a>     4a href="+code=ack_+code=data" class="sref">data4/a>[0];e<3 href="dr3vers/spi/spi-s3c24xx.c#L336" i333L296" class="line" nf="+code=u32" class="sref">u324/a> *4a href="+codfiqam v3L317">.317lass="sref">u324/a> 4a href="+codeam v3L317">.3174/a>                4a href="+code=hw" clasit4/a>(unsigned int34a hrecode=data" class="sref">data4/a>[0];e<3 href="drivers/spi/spi-s3c24xx.c#L337" i333L197" class="line" nam v3L197">.1974/a>e<3 href="dr3vers/spi/spi-s3c24xx.c#L338" i333L208" class="line" nam v3L208">.2084"+code=ref">hw4/a>->4a hre4"+code=ref">hwfiq_regs" class="sref">se >spi_fiq_code4/a> *4a hrefef="+code=spi" class="sref">u84/a>      4a hrefhref="+code=hz" cl>spi_fiq_code4/a> *4a hrefef="+code=spi" class="sref">u324/a>     4a href="+cecode=data" class="sref">data4/a>[0];e<3 href="dr3vers/spi/spi-s3c24xx.c#L339" i333L209" class="line" nam v3L209">.2094/a>        }e<3 href="dr3vers/spi/spi-s3c24xx.c#L340" i343L260" class="line" nam v3L260">.2604/a>e<3 href="dr3vers/spi/spi-s3c24xx.c#L341" i343L221" class="line" nam v3L223c24xx_s"+code4a href="+code=s3c24xx_s"+code+codeam v3L317">.3174/a>                4a href="+code=hw" clasit4/a>(unsigned int34a href="+code=spi" clarupi_fiq_code4/a> arup="+cecode=data" class="sref">data4/a>[0];e<3 href="dr3vers/spi/spi-s3c24xx.c#L342" i343L222" class="line" nam v3L222">.2224/a>e<3 href="dr3vers/spi/spi-s3c24xx.c#L343" i343L253" class="line" nam v3L24/a>                4a href="+code=hw" class="sref">hw4/a>->4a href="+code=fiq_mode" class="sref">fiq_mode4/a>              4spal class="commen(3L199">.1994/a> href="dr3vers/spi/spi-s3c24xx.c#L344" i343L254" class="line" nam v3L24/a>                4a href="+code=hw" class="sinus">hw4/a>->4a hrefinus"ode=fiq"+code=len" class="sref">len4/a> - 1;e.2094/a>        }e<3 href="dr3vers/spi/spi-s3c24xx.c#L346" i343L316" class="line" nam v3L316">.3164/a>e.2724/a>4spal class="comment">/**4/spalue<3 href="dr3vers/spi/spi-s3c24xx.c#L348" i3v3L248" class="line" nam v3L248s3c24xx_spi_fiqopss="commer>4spal /a>4baa hr.2724/a>4spal class="comment">/**4/spalue<3 href="dr3vers/spi/spi-s3c24xx.c#L349" i3v3L249" class="line" nam v3L249"pw: D> * writ  toed2">.24t4/a>4f">hwfi.2724/a>4spal class="comment">/**4/spalue<3 href="dr3vers/spi/spi-s3c24xx.c#L350" i3v3L250" class="line" nam v3L25 @releain: Whe   * tl class* wrleain ors* wr>.29e been re-routed to the FIQ handler.4/spalue<3 href="dr3vers/spi/spi-s3c24xx.c#L351" i353L281" class="line" nam v3L28 been re-routed to the FIQ handler.4/spalue<3 href="dr3vers/spi/spi-s3c24xx.c#L352" i353L262" class="line" nam v3L262Ca>4s2404/a>4spal clal wlass      *    ull wantsce tu  4spalpalwith been re-routed to the FIQ handler.4/spalue<3 href="dr3vers/spi/spi-s3c24xx.c#L353" i353L273" class="line" nam v3L273="commewhe   * we l clcurrm v     length oforsss="e to mon>4spal  ouwfi.2724/a>4spal class="comment">/**4/spalue<3 href="dr3vers/spi/spi-s3c24xx.c#L354" i353L274" class="line" nam v3L274 * Renallass="comment"> * @hw: The hardware state.4/spalue<3 href="dr3vers/spi/spi-s3c24xx.c#L355" i353L275" class="line" nam v3L27imply use another.transfer method */4/spalue<3 href="dr3vers/spi/spi-s3c24xx.c#L356" i353L226" class="line" nam v3L192">.1924/a>stafiqop4a href="+code=s3c24xx_spi_fiqoup" cl" claf="+code=u32" clp/a>             p *4a href="+code=hw" classwrleainq_regs4/a>(&4leain="+cee another.transfer method */4/spalue<3 href="dr3vers/spi/spi-s3c24xx.c#L357" i353L227" class="line" nam v3L227">.2274/a>{e<3 href="dr3vers/spi/spi-s3c24xx.c#L358" i353L208" class="line" nam v3L195">.1954/a>        struct.4a href="+code=s3c24xx_spi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" clp/a>             p *4a +code=len" class="sref">len4/a> - 1;e.2884/a>        int34a hrhree=count" class="sref">count4/a>] : 0;e<3 href="dr3vers/spi/spi-s3c24xx.c#L360" i3v3L260" class="line" nam v3L260">.2604/a>e<3 href="dr3vers/spi/spi-s3c24xx.c#L361" i363L221" class=am v3L295">.2954/a>  leainq_regs4/a>(&4leain="+ce"+code=mode" class="sref">mode4/a>) {e.3144/a>        if (4a href="+code=hw" class="sinus">hw4/a>->4a hrefinus"ode=ee another.transfer method */4/spalue<3 href="dr3vers/spi/spi-s3c24xx.c#L363" i363L203" class="line" nam v3L20e" nam v3L288">.2884/a>        int34a hrhre4/a>             BUSY84/a>        in BUSY*4a +code=len" class="sref">len4/a> - 1;e.2444/a>e<3 href="dr3vers/spi/spi-s3c24xx.c#L365" i363L315" class="line" nam v3L219">.2194/a>       ote, we doass="comment"unl, si4spalpalwias4spalpalmply use another.transfer method */4/spalue<3 href="dr3vers/spi/spi-s3c24xx.c#L366" i3v3L266" class="line" nam v3L2" class="line" nf vectal cldnt">al, siclaent">ck_bas="come tos="chen retu7imply use another.transfer method */4/spalue<3 href="dr3vers/spi/spi-s3c24xx.c#L367" i363L197" class="line" nam v3L197">.1974/a>e<3 href="dr3vers/spi/spi-s3c24xx.c#L368" i363L218" class="line" nam v3L218">.2184/a>                4a href="+code=hw" class="sref">hw4/a>->4a href="+code=fiq_mode" class="s"+code=FINONE4/a> =.4a href="+code=FINONE*4a +code=len" class="sref">len4/a> - 1;e.2184/a>                4a href="+code=hw" class="scef">hw4/a>->4a href="+code=fiq_clhree=count" class="sref">count4/a>] : 0;e<3 href="dr3vers/spi/spi-s3c24xx.c#L370" i373L220" class="="line+code=mode" class="sref">mode4/a>) {e.2184/a>                4a href="+code=hw" class="scef">hw4/a>->4a href="+code=fiq_clhre"+code=len" class="sref">len4/a> - 1;e.2094/a>        }e<3 href="dr3vers/spi/spi-s3c24xx.c#L373" i373L313" class="line" nam v3L313">.3134/a>e.2144/a>                return 4a href="+code=ret" class="sref">ret4/a>;e<3 href="dr3vers/spi/spi-s3c24xx.c#L375" i373L245"line" nam v3L209">.2094/a>        }e<3 href="dr3vers/spi/spi-s3c24xx.c#L376" i373L316" class="line" nam v3L316">.3164/a>e.2724/a>4spal class="comment">/**4/spalue<3 href="dr3vers/spi/spi-s3c24xx.c#L378" i3v3L278" class="line" nam v3L278s3c24xx_spi_a>   class74/a>4spalll updates aen set4spal clas">.2724/a>4spal class="comment">/**4/spalue<3 href="dr3vers/spi/spi-s3c24xx.c#L379" i3v3L279" class="line" nam v3L279">.2744/a>4spal class="comment"> * @hw: The hardware state.4/spalue<3 href="dr3vers/spi/spi-s3c24xx.c#L380" i3v3L280" class="line" nam v3L28omment"> * @hw: The hardware state.4/spalue<3 href="dr3vers/spi/spi-s3c24xx.c#L381" i3v3L281" class="line" nam v3L281S4/a>4spalode=ref">hw1">.24: The"lice the IRQ wclascomment"> * @hw: The hardware state.4/spalue<3 href="dr3vers/spi/spi-s3c24xx.c#L382" i3v3L282" class="line" nam v3Lu7imply use another.transfer method */4/spalue<3 href="dr3vers/spi/spi-s3c24xx.c#L383" i3v3L283" class="line" nam v3L267">.2674/a>static.4a href="+co" class="line" nam v3L283">.2834a>   cl4a href="+code=s3c24xx_spi_a>   clp" cllass="sref">s3c24xx_spi_tryfiq4/a>(struct.4a href="+code=s3c24xx_spi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" class="sref">hw4/a>)e<3 href="dr3vers/spi/spi-s3c24xx.c#L384" i3v3L284" class="line" nam v3L284">.2844/a>{e<3 href="dr3vers/spi/spi-s3c24xx.c#L385" i3v3L285" class=am v3L218">.2184/a>                4a href="+code=hw" class="sref">hw4/a>->4a href="+code=fiq_ha="+code=regs" cl hreiw4/a>->4a hre hreiwode=fiq_mode" class="s4/a>                4a ef="+code=ret" class="sref">ret4/a>;e<3 href="dr3vers/spi/spi-s3c24xx.c#L386" i383L306" class="line" nam v3L34/a>                4a href="+code=hw" class="sref">hw4/a>->4a href="+code=fiq_ha="+code=regs" cl4xx.4/a>->4a hre4xx.ode=fiq_mode" class="s hre4xx.4/a>->4a hre hre4xx.+codeam v3L317">.3174/a>                4a href="+code=hw" clas="sref">spi4/a>->4a hrecode=data" class="sref">data4/a>[0];e<3 href="dr3vers/spi/spi-s3c24xx.c#L387" i383L307" class="line" nam v3L34/a>                4a href="+code=hw" class="sref">hw4/a>->4a href="+code=fiq_ha="+code=regs" clf="+op4a href="+code=f="+opode=fiq_mode" class="s>.1924/a>stafiqop4a href="+code=s3c24xx_spi_fiqoup" ccode=data" class="sref">data4/a>[0];e<3 href="dr3vers/spi/spi-s3c24xx.c#L388" i3v3L288"line" nam v3L209">.2094/a>        }e<3 href="dr3vers/spi/spi-s3c24xx.c#L389" i3v3L289" class="line" nam v3L289">.2894/a>e<3 href="dr3vers/spi/spi-s3c24xx.c#L390" i393L280" class="line" nam v3L272">.2724/a>4spal class="comment">/**4/spalue<3 href="dr3vers/spi/spi-s3c24xx.c#L391" i393L281" class="line" nam v3L281s3c24xx_spi_use classam v3L2ass="cshouldClai  lengRQ comment"> * @hw: The hardware state.4/spalue<3 href="dr3vers/spi/spi-s3c24xx.c#L392" i3v3L292" class="line" nam v3L279">.2744/a>4spal class="comment"> * @hw: The hardware state.4/spalue<3 href="dr3vers/spi/spi-s3c24xx.c#L393" i393L273" class="line" nam v3L27omment"> * @hw: The hardware state.4/spalue<3 href="dr3vers/spi/spi-s3c24xx.c#L394" i393L274" class="line" nam v3L274">.265 arup2assock. lat updnt"> *specifiesewhe   * th ofccodnely helper in spi_s3c24xx_spi.S which is4/spalue<3 href="dr3vers/spi/spi-s3c24xx.c#L395" i393L265" class="line" nam v3L265allowmment"u  4spalpalcomment"> * @hw: The hardware state.4/spalue<3 href="dr3vers/spi/spi-s3c24xx.c#L396" i393L266" class="line" nam v3L266">.2664/a>4spal class="comment"> */4/spalue<3 href="dr3vers/spi/spi-s3c24xx.c#L397" i393L267" class="line" nam v3L267">.2674/a>static.4a href="+code=inline" clasbool2674/a>static.4bool="+code=inline" class3c24xx_spi_use cl4a href="+code=s3c24xx_spi_use clp" cllass="sref">s3c24xx_spi_tryfiq4/a>(struct.4a href="+code=s3c24xx_spi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" class="sref">hw4/a>)e<3 href="dr3vers/spi/spi-s3c24xx.c#L398" i393L268" class="line" nam v3L268">.2684/a>{e<3 href="dr3vers/spi/spi-s3c24xx.c#L399" i393L269" class="line" "line" nam v3L34/a>                4a href="+code=hw" clasp="sref">u84/a>     p 4a hrefhref="+code=hw" clasusecode4a href="+code=usecodep" ccode=data" class="sref">data4/a>[0];e<4 href="dr4vers/spi/spi-s3c24xx.c#L400" i403L270" class="line" nam v3L270">.2704/a>}e<4 href="dr4vers/spi/spi-s3c24xx.c#L401" i403L311" class="line" nam v3L311">.3114/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L402" i403L272" class="line" nam v3L272">.2724/a>4spal class="comment">/**4/spalue<4 href="dr4vers/spi/spi-s3c24xx.c#L403" i403L273" class="line" nam v3L273">.2734/a>4s  len classam v3L2assccodnely hi  lengRQ ">.2724/a>4spal class="comment">/**4/spalue<4 4ref="dr4vers/spi/spi-s3c24xx.c#L404" i403L274" class="line" nam v3L274"t">2744/a>4spal class="comment"> * @hw: The hardware state.4/spalue<4 href="dr4vers/spi/spi-s3c24xx.c#L405" i403L275" class="line" nam v3L275">.2754/a>4spal class="comment"> *4/spalue<4 href="dr4vers/spi/spi-s3c24xx.c#L406" i403L276" class="line" nam v3L276R"commewhe   * 2804/codnely hicurrm v     length IRQ w(separlass="co5">.2754/a>4spal class="comment"> *4/spalue<4 7ref="dr4vers/spi/spi-s3c24xx.c#L407" i403L277" class="line" nam v3L277whe   * 2804RQ w hicode=fi)comment"> * @hw: The hardware state.4/spalue<4 8ref="dr4vers/spi/spi-s3c24xx.c#L408" i403L278" class="line" nam v3L276">.2664/a>4spal class="comment"> */4/spalue<4 href="dr4vers/spi/spi-s3c24xx.c#L409" i4v3L309" class="line" nam v3L267">.2674/a>static.4a href="+code=inline" clasbool2674/a>static.4bool="+code=inline" class3c24xx_spi_uslen cl4a href="+code=s3c24xx_spi_uslen clp" cllass="sref">s3c24xx_spi_tryfiq4/a>(struct.4a href="+code=s3c24xx_spi" class="sre4/a>(struct.4a href*4a href="+code=spi" class="sref">spi4/a>)e<4 href="dr4vers/spi/spi-s3c24xx.c#L410" i4v3L310" class="line" nam v3L268">.2684/a>{e<4 href="dr4vers/spi/spi-s3c24xx.c#L411" i411L269" class="line" "line" nam v3L34/a>(struct.4a href*4a hrhref="+code=hw" class="sinus">hw4/a>->4a hrefinus"ode=code=data" class="sref">data4/a>[0];e<4 href="dr4vers/spi/spi-s3c24xx.c#L412" i4v3L312" class="line" nam v3L270">.2704/a>}e<4 href="dr4vers/spi/spi-s3c24xx.c#L413" i4v3L313#"line" nam v3L303">.3034/a>        elsee<4 href="dr4vers/spi/spi-s3c24xx.c#L414" i413L244" class="line" nam v3L244">.2444/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L415" i4v3L315" class="line" nam v3L267">.2674/a>static.4a href="+co" class="line" nam v3L283">.2834a>   cl4a href="+code=s3c24xx_spi_a>   clp" cllass="sref">s3c24xx_spi_tryfiq4/a>(struct.4a href="+code=s3c24xx_spi" class="sre>        4a href=="+ce"+="line" nam v3L209">.2094/a>        }e<4 href="dr4vers/spi/spi-s3c24xx.c#L416" i416L315" class="line" nam v3L267">.2674/a>static.4a href="+co" class="line" nam v3L283">.2834/a>void 4a href="+code=s3c24xx_spi_tryfiq" class="sref">s3c24xx_spi_tryfiq4/a>(struct.4a href="+code=s3c24xx_spi" class="sre>        4a href=="+ce"+="line" nam v3L209">.2094/a>        }e<4 7ref="dr4vers/spi/spi-s3c24xx.c#L417" i413L267" class="line" nam v3L267">.2674/a>static.4a href="+code=inline" clasbool2674/a>static.4bool="+code=inline" class3c24xx_spi_use cl4a href="+code=s3c24xx_spi_use clp" cllass="sref">s3c24xx_spi_tryfiq4/a>(struct.4a href="+code=s3c24xx_spi" class="sre>        4a href=="+ce"+="line" "line" nam v3L3fals">hw4/a>->4a hals"ode=c="line" nam v3L209">.2094/a>        }e<4 8ref="dr4pi" class="srref="driver4/sp 1413L298" class="line" nam v3L267">.2674/a>static.4a href="+code=inline" clasbool2674/a>static.4bool="+code=inline" class3c24xx_spi_uslen cl4a href="+code=s3c24xx_spi_uslen clp" cllass="sref">s3c24xx_spi_tryfiq4/a>(struct.4a href="+code=s3c24xx_spi" class="sre4        4a href=="+ce"+="line" "line" nam v3L3fals">hw4/a>->4a hals"ode=c="line" nam v3L209">.2094/a>        }e<4 href="dr4vers/spi/spi-s3c24xx.c#L419" i413L289" class="line" nam v3L289">.2894/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L420" i423L300#endassam v3L219">.2194/a>      NFIG_SPI_S3C24XX_FIQ" 276">.2664/a>4spal class="comment"> */4/spalue<4 href="dr4vers/spi/spi-s3c24xx.c#L421" i423L311" class="line" nam v3L311">.3114/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L422" i423L202" class="line" nam v3L192">.1924/a>sta/a> 4a href="+code=s3c24xx_spi_txrx" clllass="sref">s3c24xx_spipi_devic">hw4/a>->4a ipi_devic"c24xx_spi" class="sre4/a>(struct.4a href*4a hr,="line" nam v3L287">.2874/achen ret>hw4/a>->4a ipi_to do anyt4xx_spi" class="sre           retur4a href="+code=ret" class="sref">ret4/a>)e<4 href="dr4vers/spi/spi-s3c24xx.c#L423" i423L203" class="line" nam v3L268">.2684/a>{e<4 href="dr4vers/spi/spi-s3c24xx.c#L424" i423L304" class="line" nam v3L195">.1954/a>        struct.4a href="+code=s3c24xx_spi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" clto_f">s3c24xx_spi4/ato_f"+codeam v3L317">.3174/a>(struct.4a href*4a hrecode=data" class="sref">data4/a>[0];e<4 href="dr4vers/spi/spi-s3c24xx.c#L425" i423L305" class="line" nam v3L305">.3054/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L426" i423L306" class="line" nam v3L34/a>                4a href="+code=hw" class="sref">hw4/a>->4a href="+code=hw" clt          retur4a hrhref="+code=hw" class=_buf"sref">hw4/a>->_bufode=code=data" class="sref">data4/a>[0];e<4 href="dr4vers/spi/spi-s3c24xx.c#L427" i423L307" class="line" nam v3L34/a>                4a href="+code=hw" class="sref">hw4/a>->4a href="+code=hw" clt          retur4a hrhref="+code=hw" clasr=_buf"sref">hw4/a>-&rt_bufode=code=data" class="sref">data4/a>[0];e<4 8ref="dr4vers/spi/spi-s3c24xx.c#L428" i423L308" class="line" nam v3L3">fiq_rcount4/a>] = 4a href="+code=hw" class="sref">hw4/a>->4a hreref="+code=hw" clt          retur4a hrhref="+code=hw" class="sref">hw4/a>->4a hrcode=data" class="sref">data4/a>[0];e<4 href="dr4vers/spi/spi-s3c24xx.c#L429" i423L309" class="line" nam v3L3">fiq_rcount4/a>] = 4a href="+code=hw" clasref">uregs4/a>[4a hrcode=fiq_hree=count" class="sref">count4/a>] : 0;e<4 href="dr4vers/spi/spi-s3c24xx.c#L430" i433L260" class="line" nam v3L260">.2604/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L431" i433L221" class="line" nam v3L2a>  _194pletes 2674/a>static.4a   _194pletes +codeim_fiq" class="sref">claim_fiq4/a>(&4a href="+code=hw" clasdo>.2674/a>static.4do>.a hrecode=data" class="sref">data4/a>[0];e<4 href="dr4vers/spi/spi-s3c24xx.c#L432" i433L222" class="line" nam v3L222">.2224/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L433" i433L253" class="line" nam v3L24/a>                4a href="+code=hw" class="sinus">hw4/a>->4a hrefinus"ode=fiqe=count" class="sref">count4/a>] : 0;e<4 href="dr4vers/spi/spi-s3c24xx.c#L434" i433L314" class="line" nam v3L314">s3c24xx_spi_use cl4a href="+code=s3c24xx_spi_use clp" clspi" class="sref">s3c24xx_spi4/a> *4a hhref="+code=f="+code=hw" clt          retur4a hrhref="+code=hw" class="sref">hw4/a>->4a hr ref== 3ef="+code=ret" class="sref">ret4/a>)e<4 href="dr4vers/spi/spi-s3c24xx.c#L435" i433L315" class="line" nam v3L315">.3153L283">.2834/a>void 4a href="+code=s3c24xx_spi_tryfiq" cspi" class="sref">s3c24xx_spi4/a> *4a h=count" class="sref">count4/a>] : 0;e<4 href="dr4vers/spi/spi-s3c24xx.c#L436" i433L316" class="line" nam v3L316">.3164/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L437" i433L307" class="m v3L219">.2194/a>      se to mo first byte276">.2664/a>4spal class="comment"> */4/spalue<4 href="dr4vers/spi/spi-s3c24xx.c#L438" i433L308" class="line" nam v3L3ss="cb>s3c24xx_spi4/ass="cbiq" cspi" class="sref"_txbyte>s3c24xx_spi4/a> _txbyteiq" cspi" class="sref">s3c24xx_spi4/a> *4a , 0)ef="+code=spi" clq_rspi4/a>] = (long)4a href="+code=hw" class="sref">hw4/a>->4a href +f="+code=spi" clC24XX10PI_TDATref">hw4/a>->C24XX10PI_TDAT*4a h=count" class="sref">count4/a>] : 0;e<4 href="dr4vers/spi/spi-s3c24xx.c#L439" i433L289" class="line" nam v3L289">.2894/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L440" i443L310" class="line" nam v3L3wa  _for_194pletes 2674/a>static.4wa  _for_194pletes +codeim_fiq" class="sref">claim_fiq4/a>(&4a href="+code=hw" clasdo>.2674/a>static.4do>.a hrecode=data" class="sref">data4/a>[0];e<4 href="dr4vers/spi/spi-s3c24xx.c#L441" i441L269" class="line" "line" nam v3L3">fiq_rcount4/a>] = 4a href="+code=hw" clasref">uregs4/a>[4a hrcode=fiq_code=data" class="sref">data4/a>[0];e<4 href="dr4vers/spi/spi-s3c24xx.c#L442" i443L312" class="line" nam v3L270">.2704/a>}e<4 href="dr4vers/spi/spi-s3c24xx.c#L443" i443L313" class="line" nam v3L313">.3134/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L444" i443L254" class="line" nam v3L2rq"line"_>uregs4/a>[4a hr2rq"line"_>="+code=inline" class3c24xx_spi_it4/a>(unsigned ins3c24xx_spi_it4+code class="sref">ack_bit4/a>(unsigned int34a hr, " claf="+code=u32" cl="sref">spi4/a>->4a hre" class="line" nam v3L313">.3134/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L445" i4v3L245" class="line" nam v3L268">.2684/a>{e<4 href="dr4vers/spi/spi-s3c24xx.c#L446" i443L306" class="line" nam v3L195">.1954/a>        struct.4a href="+code=s3c24xx_spi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" cl="sref">spi4/a>->4a hrcode=data" class="sref">data4/a>[0];e<4 href="dr4vers/spi/spi-s3c24xx.c#L447" i443L307" class==ack_bit" class="sref">ack_bspssref">u84/a>     spssr*4a href="+code=hw" clreadb>s3c24xx_spi4/areadbiq" cspi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" class="sref">hw4/a>->4a href +f="+code=spi" clC24XX10PI_STAref">hw4/a>->C24XX10PI_STAa hrecode=data" class="sref">data4/a>[0];e<4 href="dr4vers/spi/spi-s3c24xx.c#L448" i448L307" class==ack_bit" class="sref">ack_bref">uregs4/a>[4a hrcode=fiq_hre"line" nam v3L3">fiq_rcount4/a>] = 4a href="+code=hw" clasref">uregs4/a>[4a hrcode=fiq_code=data" class="sref">data4/a>[0];e<4 href="dr4vers/spi/spi-s3c24xx.c#L449" i443L289" class="line" nam v3L289">.2894/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L450" i453L290" class="linss="sref">ack_bspssref">u84/a>     spssr*4a h+code=f="+code=hw" clC24XX10PI_STA_DCO="sref">spi4/a>,C24XX10PI_STA_DCO=="+ce"+" class="line" nam v3L289">.2894/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L451" i453L291" class="line" nam v3L218">.218 hredbgref">spi4/a>->4edbgiq" cspi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" clas="sref">spi4/a>->4a hr,="m v3L219">.2"liing">" 4a -collises \n"">.2664ecode=data" class="sref">data4/a>[0];e<4 href="dr4vers/spi/spi-s3c24xx.c#L452" i453L302" class="line" nam v3L302">.302194plet.2674/a>static.4194plet.+codeim_fiq" class="sref">claim_fiq4/a>(&4a href="+code=hw" clasdo>.2674/a>static.4do>.a hrecode=data" class="sref">data4/a>[0];e<4 href="dr4vers/spi/spi-s3c24xx.c#L453" i453L203" class="line" ngotoass="sref">ack_bit4_do>.2674/a>static.4it4_do>.fiq_code=data" class="sref">data4/a>[0];e<4 href="dr4vers/spi/spi-s3c24xx.c#L454" i453L314" class=" class="line" nam v3L270">.2704/a>}e<4 href="dr4vers/spi/spi-s3c24xx.c#L455" i453L305" class="line" nam v3L305">.3054/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L456" i456L290" class="lin!nss="sref">ack_bspssref">u84/a>     spssr*4a h+code=f="+code=hw" clC24XX10PI_STA_READY84/a>        inC24XX10PI_STA_READYa hree"+" class="line" nam v3L289">.2894/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L457" i453L317" class="line" nam v3L317">.317 hredbgref">spi4/a>->4edbgiq" cspi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" clas="sref">spi4/a>->4a hr,="m v3L219">.2"liing">"289ass="readyaen sex?\n"">.2664ecode=data" class="sref">data4/a>[0];e<4 href="dr4vers/spi/spi-s3c24xx.c#L458" i453L218" class="line" nam v3L218">.218194plet.2674/a>static.4194plet.+codeim_fiq" class="sref">claim_fiq4/a>(&4a href="+code=hw" clasdo>.2674/a>static.4do>.a hrecode=data" class="sref">data4/a>[0];e<4 href="dr4vers/spi/spi-s3c24xx.c#L459" i453L219" class="line" ngotoass="sref">ack_bit4_do>.2674/a>static.4it4_do>.fiq_code=data" class="sref">data4/a>[0];e<4 href="dr4vers/spi/spi-s3c24xx.c#L460" i460L314" class=" class="line" nam v3L270">.2704/a>}e<4 href="dr4vers/spi/spi-s3c24xx.c#L461" i463L311" class="line" nam v3L311">.3114/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L462" i463L202" class="line" nam v3L290">.s3c24xx_spi_uslen cl4a href="+code=s3c24xx_spi_uslen clp" clspi" class="sref">s3c24xx_spi4/a> *4a he"+" class="line" nam v3L289">.2894/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L463" i463L203" class="line" n"line" nam v3L3">fiq_rcount4/a>] = 4a href="+code=hw" clasref">uregs4/a>[4a hrcode=fiq_++code=data" class="sref">data4/a>[0];e<4 href="dr4vers/spi/spi-s3c24xx.c#L464" i463L244" class="line" nam v3L244">.2444/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L465" i463L315" class="line" n" nam v3L301">.3014/a>        else if (4a href="+code=hw" class="sref">hw4/a>->4a e" class="line" nam v3L313">.3134/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L466" i463L296" class="line" nam v3L29m v3L301">.3014/a>        else if (4a href="+code=hw" class="sref">hw4/a>->4a =err" class="sre >f">uregs4/a>[4a hrcode=fiq_rcount" class="srefreadb>s3c24xx_spi4/areadbiq" cspi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" class="sref">hw4/a>->4a href +f="+code=spi" clC24XX10PI_RDATref">hw4/a>->C24XX10PI_RDAT*4a h=count" class="sref">count4/a>] : 0;e<4 href="dr4vers/spi/spi-s3c24xx.c#L467" i463L197" class="line" nam v3L197">.1974/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L468" i463L218" class="line" nam v3L218">.218ref">uregs4/a>[4a hrcode=fiq_++code=data" class="sref">data4/a>[0];e<4 href="dr4vers/spi/spi-s3c24xx.c#L469" i463L289" class="line" nam v3L289">.2894/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L470" i473L300" class="line" n" nam v3L301">.3014ref">uregs4/a>[4a hrcode=fiq_h<e=f="+code=hw" cl">fiq_rcount4/a>] = 4a href="+code=hw" class="sref">hw4/a>->4a hre" class="line" nam v3L313">.3134/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L471" i473L291" class="line" n"line" nam v3L218">.218ss="cb>s3c24xx_spi4/ass="cbiq" cspi" class="sref"_txbyte>s3c24xx_spi4/a> _txbyteiq" cspi" class="sref">s3c24xx_spi4/a> *4a , m v3L301">.3014ref">uregs4/a>[4a hrcode=fiq_)ef="+code=spi" clq_rspi4/a>] = (long)4a href="+code=hw" class="sref">hw4/a>->4a href +f="+code=spi" clC24XX10PI_TDATref">hw4/a>->C24XX10PI_TDAT*4a h=count" class="sref">count4/a>] : 0;e<4 href="dr4vers/spi/spi-s3c24xx.c#L472" i473L302" class="line" n"line" nam v3L303">.3034/a>        elsee<4 href="dr4vers/spi/spi-s3c24xx.c#L473" i473L203" class="line" nam v3L20e" nam v3L288">194plet.2674/a>static.4194plet.+codeim_fiq" class="sref">claim_fiq4/a>(&4a href="+code=hw" clasdo>.2674/a>static.4do>.a hrecode=data" class="sref">data4/a>[0];e<4 href="dr4vers/spi/spi-s3c24xx.c#L474" i473L254" class="="line+code=mode" class="sref">mode4/a>) {e<4 href="dr4vers/spi/spi-s3c24xx.c#L475" i473L315" class="line" nam v3L315">.315">fiq_rcount4/a>] = 4a href="+code=hw" clasref">uregs4/a>[4a hrcode=fiq_href="+code=hw" cl">fiq_rcount4/a>] = 4a href="+code=hw" class="sref">hw4/a>->4a hrcode=data" class="sref">data4/a>[0];e<4 href="dr4vers/spi/spi-s3c24xx.c#L476" i473L296" class="line" n"line" nam v3L24/a>                4a href="+code=hw" class="sinus">hw4/a>->4a hrefinus"ode=fiqe=count" class="sref">count4/a>] : 0;e<4 href="dr4vers/spi/spi-s3c24xx.c#L477" i473L197" class="line" nam v3L197">.1974/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L478" i473L218" class="line" n" nam v3L301">.3014/a>        else if (4a href="+code=hw" class="sref">hw4/a>->4a e" class="line" nam v3L313">.3134/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L479" i473L219" class="line" n"line" n"line" nam v3L24/a>                4a href="+code=hw" class="sref">hw4/a>->4a =err" class="sre">fiq_rcount4/a>] = 4a href="+code=hw" class="sref">hw4/a>->4a hr-1rcount" class="srefreadb>s3c24xx_spi4/areadbiq" cspi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" class="sref">hw4/a>->4a href +f="+code=spi" clC24XX10PI_RDATref">hw4/a>->C24XX10PI_RDAT*4a h=count" class="sref">count4/a>] : 0;e<4 href="dr4vers/spi/spi-s3c24xx.c#L480" i483L260" class="line" nam v3L260">.2604/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L481" i483L291" class="line" nam v3L218">.218194plet.2674/a>static.4194plet.+codeim_fiq" class="sref">claim_fiq4/a>(&4a href="+code=hw" clasdo>.2674/a>static.4do>.a hrecode=data" class="sref">data4/a>[0];e<4 href="dr4vers/spi/spi-s3c24xx.c#L482" i483L202" class="line" nam v3L209">.2094/a>        }e<4 href="dr4vers/spi/spi-s3c24xx.c#L483" i483L313" class="line" nam v3L313">.3134/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L484" i4v3L284ass="sref">ack_bit4_do>.2674/a>static.4it4_do>.fiq_:code=mode" class="sref">mode4/a>) {e<4 href="dr4vers/spi/spi-s3c24xx.c#L485" i4v3L285" class="line" "line" nam v3L3IRQ_HANDLED2674/a>static.4IRQ_HANDLEDa hrcode=data" class="sref">data4/a>[0];e<4 href="dr4vers/spi/spi-s3c24xx.c#L486" i483L306"line" nam v3L209">.2094/a>        }e<4 href="dr4vers/spi/spi-s3c24xx.c#L487" i483L197" class="line" nam v3L197">.1974/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L488" i483L298" class" class="line" nam v3L283">.2834a>  ials"tup4a href="+code=s3c24xx_spi_a>  ials"tup+codelass="sref">s3c24xx_spi_tryfiq4/a>(struct.4a href="+code=s3c24xx_spi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" class="sref">hw4/a>)e<4 href="dr4vers/spi/spi-s3c24xx.c#L489" i4v3L289+code=mode" class="sref">mode4/a>) {e<4 href="dr4vers/spi/spi-s3c24xx.c#L490" i493L310" class="m v3L219">.2194/a>      en set4smo/a> , permanm v   enabl 4spalc>.24:76">.2664/a>4spal class="comment"> */4/spalue<4 href="dr4vers/spi/spi-s3c24xx.c#L491" i493L311" class="line" nam v3L311">.3114/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L492" i493L312" class="line" nam v3L3clk_enabl 2674/a>static.41lk_enabl iq" cspi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" clas1lk2674/a>static.41lka hrecode=data" class="sref">data4/a>[0];e<4 href="dr4vers/spi/spi-s3c24xx.c#L493" i493L313" class="line" nam v3L313">.3134/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L494" i494L310" class="m v3L219">.2194/a>      programndefaults" cl the Iwrit  tos:76">.2664/a>4spal class="comment"> */4/spalue<4 href="dr4vers/spi/spi-s3c24xx.c#L495" i493L305" class="line" nam v3L305">.3054/a>e<4 href="dr4vers/spi/spi-s3c24xx.c#L496" i493L306" class="line" nam v3L3ss="cb>s3c24xx_spi4/ass="cbiq" c0xffef="+code=spi" clq_rspi4/a>] = (long)4a href="+code=hw" class="sref">hw4/a>->4a href +f="+code=spi" clC24XX10PI_PREref">hw4/a>->C24XX10PI_PREa hrecode=data" class="sref">data4/a>[0];e<4 href="dr4vers/spi/spi-s3c24xx.c#L497" i493L307" class="line" nam v3L3ss="cb>s3c24xx_spi4/ass="cbiq" cspi" class="sreI_PIN_DEFAULTref">hw4/a>->C_PIN_DEFAULT*4a , m v3L301">.3014q_rspi4/a>] = (long)4a href="+code=hw" class="sref">hw4/a>->4a href +f="+code=spi" clC24XX10PI_PIN"sref">spi4/a>,C24XX10PI_PINa hrecode=data" class="sref">data4/a>[0];e<4 href="dr4vers/spi/spi-s3c24xx.c#L498" i493L308" class="line" nam v3L3ss="cb>s3c24xx_spi4/ass="cbiq" cspi" class="sreSPCON_DEFAULTref">hw4/a>->C_CON_DEFAULT*4a , m v3L301">.3014q_rspi4/a>] = (long)4a href="+code=hw" class="sref">hw4/a>->4a href +f="+code=spi" clC24XX10PI_CON"sref">spi4/a>,C24XX10PI_CONa hrecode=data" class="sref">data4/a>[0];e<4 href="dr4vers/spi/spi-s3c24xx.c#L499" i493L289" class="line" nam v3L289">.2894/a>e<5 href="dr5vers/spi/spi-s3c24xx.c#L500" i503L290" class="linss="sref">ack_b4/a>                4a href="+code=hw" clasp="sref">u84/a>     p 4a hrefe"+" class="line" nam v3L289">.2894/a>e<5 href="dr5vers/spi/spi-s3c24xx.c#L501" i503L291" class="line" n"linss="sref">ack_b4/a>                4a href="+code=hw" class"+cc4        4a href="+cc4ode=fiiq_mode" class="s>.1924/a>stagpioc4        4a href=.1924/a>stagpioc4*4a href="+code=hw" class="sref">hw4/a>)e<5 href="dr5vers/spi/spi-s3c24xx.c#L502" i503L202" class="line" nam v3L20_mode" class="sgpio_directes _outpu>uregs4/a>[4a hrgpio_directes _outpu>iq" cspi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" clasp="sref">u84/a>     p 4a hrefhref="+code=hw" claspincc4        4a hrefpincc4*4a , 1ecode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L503" i503L313" class="line" nam v3L313">.3134/a>e<5 4ref="dr5vers/spi/spi-s3c24xx.c#L504" i503L304" class="line" n"linss="sref">ack_b4/a>                4a href="+code=hw" clasp="sref">u84/a>     p 4a hrefhref="+code=hw" clasgpio_s"tup4a href="+code=gpio_s"tup*4a href="+code=hw" class="sref">hw4/a>)e<5 5ref="dr5vers/spi/spi-s3c24xx.c#L505" i503L155" class="line" nam v3L15ss="sref">ack_b4/a>                4a href="+code=hw" clasp="sref">u84/a>     p 4a hrefhref="+code=hw" clasgpio_s"tup4a href="+code=gpio_s"tup*4a nss="sref">ack_b4/a>                4a href="+code=hw" clasp="sref">u84/a>     p 4a href, 1ecode=data" class="sref">data4/a>[0];e<5 6ref="dr5vers/spi/spi-s3c24xx.c#L506" i503L306" class="line" nam v3L209">.2094/a>        }e<5 7ref="dr5vers/spi/spi-s3c24xx.c#L507" i503L277"line" nam v3L209">.2094/a>        }e<5 8ref="dr5vers/spi/spi-s3c24xx.c#L508" i503L278line" nam v3L209">.2094/a>        }e<5 9ref="dr5vers/spi/spi-s3c24xx.c#L509" i5v3L309" class class="sref">ack_b__devin"sref">u324/a> 4a__devin"sL284ass="sref">ack_b=.1924/a>staprob">hw4/a>->4a i.1924/a>staprob"+codelass="sref">s3c24xx_sp lat upd_devic">hw4/a>->4a  lat upd_devic"c24xx_spi" class="srep="sref">spi4/a>-&gpt;4a hre" class="line" nam v3L313">.3134/a>e<5 href="dr5vers/spi/spi-s3c24xx.c#L510" i5v3L310" class="line" nam v3L268">.2684/a>{e<5 href="dr5vers/spi/spi-s3c24xx.c#L511" i511L269" class=lass="sref">s3c24xx_spi_try10Pspi_a>fo>hw4/a>->4a i.19210Pspi_a>foc24xx_spi" class="srep="sref">u84/a>     p 4a hrefcode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L512" i512L269" class=lass="sref">s3c24xx_spi_tryfiq4/a>(struct.4a href="+code=s3c24xx_spi" class="sref">s3c24xx_spi4/a> *4a code=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L513" i513L269" class=lass="sref">s3c24xx_spipi_ma  to>(struct.4a hrefpi_ma  toc24xx_spi" class="srema  to>(struct.4a hrema  toc24xcode=data" class="sref">data4/a>[0];e<5 4ref="dr5vers/spi/spi-s3c24xx.c#L514" i513L304" class="line" nam v3L195">.19resourc">hw4/a>->4a resourc"c24xx_spi" class="sreres>hw4/a>->4a resc24xcode=data" class="sref">data4/a>[0];e<5 5ref="dr5vers/spi/spi-s3c24xx.c#L515" i513L155" class= class="sref">ack_bero>(struct.4a hreeroode=fiqe=count" class="sref">count4/a>] : 0;e<5 href="dr5vers/spi/spi-s3c24xx.c#L516" i513L316" class="line" nam v3L316">.3164/a>e<5 7ref="dr5vers/spi/spi-s3c24xx.c#L517" i513L307" class="line" nam v3L3ma  to>(struct.4a hrema  toc24xfiq_mode" class="s>pi_alloc_ma  to>(struct.4a hrefpi_alloc_ma  to+codeim_fiq" class="sref"p="sref">spi4/a>-&gpt;4a hrhref="+code=hw" clas="sref">spi4/a>->4a hr,=sizeofelass="sref">s3c24xx_spi_tryfiq4/a>(struct.4a href="+code=s3c24x)ecode=data" class="sref">data4/a>[0];e<5 8ref="dr5pi" class="srref="driver5/sp 1513L308" class="linss="sref">ack_bma  to>(struct.4a hrema  toc24xfiiq_mode" class="sNUL="sref">spi4/a>,NUL=hrefe"+" class="line" nam v3L289">.2894/a>e<5 href="dr5vers/spi/spi-s3c24xx.c#L519" i513L219" class="line" nam v3L218">.218t;4eero>(struct.4a hret;4eero+codeim_fiq" class="sref"p="sref">spi4/a>-&gpt;4a hrhref="+code=hw" clas="sref">spi4/a>->4a hr,="m v3L219">.2"liing">"No memoryaen sfpi_ma  to\n"">.2664ecode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L520" i523L300" class="line" nss="sref">ack_bero>(struct.4a hreeroode=fiq4/a>             NOMEM>(struct.4a hre NOMEMc24xcode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L521" i523L291" class="line" ngotoass="sref">ack_bero_nomem>(struct.4a hreero_nomemc24xcode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L522" i523L202" class="line" nam v3L209">.2094/a>        }e<5 href="dr5vers/spi/spi-s3c24xx.c#L523" i523L313" class="line" nam v3L313">.3134/a>e<5 href="dr5vers/spi/spi-s3c24xx.c#L524" i523L304" class=spi" class="sref">s3c24xx_spi4/a> *4a fiq_mode" class="s>pi_ma  to_get_dev="sref">u84/a>     >pi_ma  to_get_dev="sr*4a nss="sref">ack_bma  to>(struct.4a hrema  toc24xecode=data" class="sref">data4/a>[0];e<5 5ref="dr5vers/spi/spi-s3c24xx.c#L525" i523L285" class=am v3L218">.218mems            returmems  *4a nss="sref">ack_b4/a>                4a , 0,=sizeofelass="sref">s3c24xx_spi_tryfiq4/a>(struct.4a href="+code=s3c24x)ecode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L526" i523L316" class="line" nam v3L316">.3164/a>e<5 href="dr5vers/spi/spi-s3c24xx.c#L527" i523L307" class="line" nam v3L34/a>                4a href="+code=hw" clasma  to>(struct.4a hrema  toc24xfiq_mode" class="s>pi_ma  to_getef">u84/a>     >pi_ma  to_get*4a nss="sref">ack_bma  to>(struct.4a hrema  toc24xecode=data" class="sref">data4/a>[0];e<5 8ref="dr5vers/spi/spi-s3c24xx.c#L528" i523L308" class="line" nam v3L3">fiq_rcount4/a>] = 4a href="+code=hw" clasp="sref">u84/a>     p 4a hrefhref="+code=hw" clp="sref">u84/a>     p 4a hrefhref="+code=hw" clp="sref">spi4/a>-&gpt;4a hrhref="+code=hw" clas="sref">spi4/a>->4a hr="+code=regs" cl lat upd_d"sref">u84/a>     plat upd_d"src24xcode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L529" i523L309" class="line" nam v3L3">fiq_rcount4/a>] = 4a href="+code=hw" clas="sref">spi4/a>->4a hrhreim_fiq" class="sref"p="sref">spi4/a>-&gpt;4a hrhref="+code=hw" clas="sref">spi4/a>->4a hrcode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L530" i533L260" class="line" nam v3L260">.2604/a>e<5 href="dr5vers/spi/spi-s3c24xx.c#L531" i533L221" class="linss="sref">ack_bp="sref">u84/a>     p 4a hrefhriq_mode" class="sNUL="sref">spi4/a>,NUL=hrefe"+" class="line" nam v3L289">.2894/a>e<5 href="dr5vers/spi/spi-s3c24xx.c#L532" i533L302" class="line" nam v3L302">.302t;4eero>(struct.4a hret;4eero+codeim_fiq" class="sref"p="sref">spi4/a>-&gpt;4a hrhref="+code=hw" clas="sref">spi4/a>->4a hr,="m v3L219">.2"liing">"No  lat updnt"> *supplied\n"">.2664ecode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L533" i533L203" class="line" n"line" nam v3L3ero>(struct.4a hreeroode=fiq4/a>             NOENTref">hw4/a>-> NOENTa hrcode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L534" i533L304" class="line" ngotoass="sref">ack_bero_no_p="sref">u84/a>     ero_no_p="sra hrcode=data" class="sref">data4/a>[0];e<5 5ref="dr5vers/spi/spi-s3c24xx.c#L535" i533L315" class="line" nam v3L209">.2094/a>        }e<5 href="dr5vers/spi/spi-s3c24xx.c#L536" i533L316" class="line" nam v3L316">.3164/a>e<5 href="dr5vers/spi/spi-s3c24xx.c#L537" i533L307" class="line" nam v3L3plat upd_="+cdrv="sref">u84/a>     plat upd_="+cdrv="sr*4a nss="sref">ack_bp="sref">spi4/a>-&gpt;4a hr, m v3L301">.3014q_rspi4/a>] = (long)4a ecode=data" class="sref">data4/a>[0];e<5 8ref="dr5vers/spi/spi-s3c24xx.c#L538" i533L308" class="line" nam v3L3a>  _194pletes 2674/a>static.4a   _194pletes +codeim_fiq" class="sref">claim_fiq4/a>(&4a href="+code=hw" clasdo>.2674/a>static.4do>.a hrecode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L539" i533L289" class="line" nam v3L289">.2894/a>e<5 href="dr5vers/spi/spi-s3c24xx.c#L540" i543L310" class="m v3L219">.2194/a>      a>  ialisalode ref">hw176">.2664/a>4spal class="comment"> */4/spalue<5 href="dr5vers/spi/spi-s3c24xx.c#L541" i543L311" class="line" nam v3L311">.3114/a>e<5 href="dr5vers/spi/spi-s3c24xx.c#L542" i543L312" class="line" nam v3L3s3c24xx_spi_a>   cl4a href="+code=s3c24xx_spi_a>   clp" clm v3L301">.3014q_rspi4/a>] = (long)4a ecode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L543" i543L313" class="line" nam v3L313">.3134/a>e<5 href="dr5vers/spi/spi-s3c24xx.c#L544" i544L310" class="m v3L219">.2194/a>      74/a>4spalma  tolass="c176">.2664/a>4spal class="comment"> */4/spalue<5 5ref="dr5vers/spi/spi-s3c24xx.c#L545" i543L305" class="line" nam v3L305">.3054/a>e<5 href="dr5vers/spi/spi-s3c24xx.c#L546" i543L306" class="m v3L219">.2194/a>      spal305"ref=m301 bits und natood by th ofine" n:176">.2664/a>4spal class="comment"> */4/spalue<5 href="dr5vers/spi/spi-s3c24xx.c#L547" i543L307" class="line" nam v3L3ma  to>(struct.4a hrema  toc24xhref="+code=hw" clasmcla_bits>(struct.4a hremcla_bitshrefhref="+code=hw" clI_S3CPO="sref">spi4/a>,C_S3CPO=hrefh|ef="+code=hw" clI_S3CPHAref">hw4/a>->C_S3CPHAhrefh|ef="+code=hw" clI_S3CS_HIGHref">hw4/a>->C_S3CS_HIGHa hrcode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L548" i543L278line" nam v3L209">.2094/a>        }e<5 href="dr5vers/spi/spi-s3c24xx.c#L549" i543L309" class="line" nam v3L3ma  to>(struct.4a hrema  toc24xhref="+code=hw" clasnum_chipselectef">u84/a>     num_chipselecthrefhref="+code=hw" cl4/a>                4a href="+code=hw" clasp="sref">u84/a>     p 4a hrefhref="+code=hw" clasnum_cs>(struct.4a hrenum_csa hrcode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L550" i553L310" class="line" nam v3L3ma  to>(struct.4a hrema  toc24xhref="+code=hw" clasbus_num>(struct.4a hrebus_numhrefhref="+code=hw" clp="sref">u84/a>     p 4a hrefhref="+code=hw" clasbus_num>(struct.4a hrebus_numhrefcode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L551" i553L311" class="line" nam v3L311">.3114/a>e<5 href="dr5vers/spi/spi-s3c24xx.c#L552" i553L302" class="m v3L219">.2194/a>      74/a>4spalass=" en set4sbitbangfine" n176">.2664/a>4spal class="comment"> */4/spalue<5 href="dr5vers/spi/spi-s3c24xx.c#L553" i553L313" class="line" nam v3L313">.3134/a>e<5 href="dr5vers/spi/spi-s3c24xx.c#L554" i553L304" class=spi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" clasbitbang>(struct.4a hrebitbanga hr="+code=regs" clma  to>(struct.4a hrema  toc24xfffffffffref="+code=hw" cl4/a>                4a href="+code=hw" clasma  to>(struct.4a hrema  toc24xcode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L555" i553L285" class=am v3L218">.2184/a>                4a href="+code=hw" clasbitbang>(struct.4a hrebitbanga hr="+code=regs" cl74/a>achen ret>hw4/a>->4a i4/a>achen retc24xfiq_mode" class="s>3c24xx_spi_i4/a>xret>hw4/a>->4a i3c24xx_spi_i4/a>xretc24xcode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L556" i553L306" class="line" nam v3L34/a>                4a href="+code=hw" clasbitbang>(struct.4a hrebitbanga hr="+code=regs" clchipselectef">u84/a>     chipselecthrefhffffref="+code=hw" cli3c24xx_spi_chipsel>hw4/a>->4a i3c24xx_spi_chipselc24xcode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L557" i553L307" class="line" nam v3L34/a>                4a href="+code=hw" clasbitbang>(struct.4a hrebitbanga hr="+code=regs" cltxrx_bufs>(struct.4a hretxrx_bufsL307" clasref="+code=hw" cli3c24xx_spi_/a> 4a href="+code=s3c24xx_spi_txrx" clcode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L558" i553L278line" nam v3L209">.2094/a>        }e<5 href="dr5vers/spi/spi-s3c24xx.c#L559" i553L309" class="line" nam v3L3">fiq_rcount4/a>] = 4a href="+code=hw" clasma  to>(struct.4a hrema  toc24xhref="+code=hw" class"tup4a href="+code=s"tup*4a asref="+code=hw" cli3c24xx_spi_s"tup4a href="+code=s3c24xx_spi_s"tup*4a code=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L560" i563L310" class="line" nam v3L3">fiq_rcount4/a>] = 4a href="+code=hw" clasma  to>(struct.4a hrema  toc24xhref="+code=hw" clascleanup4a href="+code=cleanupc24xfiq_mode" class="s>3c24xx_spi_cleanup4a href="+code=>3c24xx_spi_cleanup*4a code=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L561" i563L311" class="line" nam v3L311">.3114/a>e<5 href="dr5vers/spi/spi-s3c24xx.c#L562" i563L312" class="line" nam v3L3 hredbgref">spi4/a>->4edbgiq" cspi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" clas="sref">spi4/a>->4a hr,="m v3L219">.2"liing">"bitbangfat %p\n"">.2664,eim_fiq" class="sref"4/a>                4a href="+code=hw" clasbitbang>(struct.4a hrebitbanga hrecode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L563" i563L313" class="line" nam v3L313">.3134/a>e<5 href="dr5vers/spi/spi-s3c24xx.c#L564" i564L310" class="m v3L219">.2194/a>      find and map our resourc"s:76">.2664/a>4spal class="comment"> */4/spalue<5 href="dr5vers/spi/spi-s3c24xx.c#L565" i563L305" class="line" nam v3L305">.3054/a>e<5 href="dr5vers/spi/spi-s3c24xx.c#L566" i563L306" class="line" nam v3L3res>hw4/a>->4a resc24xhref="+code=hw" clplat upd_get_resourc">hw4/a>->4a plat upd_get_resourc"*4a nss="sref">ack_bp="sref">spi4/a>-&gpt;4a hr, m v3L301">.3014IORESOURCE_MEM>(struct.4a hreIORESOURCE_MEM 4a , 0ecode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L567" i563L307" class="linss="sref">ack_bres>hw4/a>->4a resc24xhriq_mode" class="sNUL="sref">spi4/a>,NUL=hrefe"+" class="line" nam v3L289">.2894/a>e<5 href="dr5vers/spi/spi-s3c24xx.c#L568" i563L218" class="line" nam v3L218">.218t;4eero>(struct.4a hret;4eero+codeim_fiq" class="sref"p="sref">spi4/a>-&gpt;4a hrhref="+code=hw" clas="sref">spi4/a>->4a hr,="m v3L219">.2"liing">"Canss="get IORESOURCE_MEM\n"">.2664ecode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L569" i563L219" class="line" nam v3L218">.218ero>(struct.4a hreeroode=fiq4/a>             NOENTref">hw4/a>-> NOENTa hrcode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L570" i573L300" class="line" ngotoass="sref">ack_bero_no_iores>hw4/a>->4a ero_no_ioresa hrcode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L571" i573L291" class="line" nam v3L209">.2094/a>        }e<5 href="dr5vers/spi/spi-s3c24xx.c#L572" i573L222" class="line" nam v3L222">.2224/a>e<5 href="dr5vers/spi/spi-s3c24xx.c#L573" i573L253" class="line" nam v3L24/a>                4a href="+code=hw" clasioareref">u84/a>     ioarerc24xhref="+code=hw" clrequest_mem_writs 2674/a>static.4request_mem_writs *4a nss="sref">ack_bres>hw4/a>->4a resc24xhref="+code=hw" classtartef">u84/a>     >tarta hr, m v3L301">.3014resourc"_size>hw4/a>->4a resourc"_size*4a nss="sref">ack_bres>hw4/a>->4a resc24x)," class="line" nam v3L222">.2224/a>e<5 href="dr5vers/spi/spi-s3c24xx.c#L574" i573L304" class="line" nnnnnnnnnnnnnnnnnnnnnnnnnq" class="sref"p="sref">spi4/a>-&gpt;4a hrhref="+code=hw" clas4xx.>(struct.4a hrenxx.a hrecode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L575" i573L305" class="line" nam v3L305">.3054/a>e<5 href="dr5vers/spi/spi-s3c24xx.c#L576" i576L290" class="lin"line" nam v3L24/a>                4a href="+code=hw" clasioareref">u84/a>     ioarerc24xhriq_mode" class="sNUL="sref">spi4/a>,NUL=hrefe"+" class="line" nam v3L289">.2894/a>e<5 href="dr5vers/spi/spi-s3c24xx.c#L577" i573L317" class="line" nam v3L317">.317 hreero>(struct.4a hret;4eero+codeim_fiq" class="sref"p="sref">spi4/a>-&gpt;4a hrhref="+code=hw" clas="sref">spi4/a>->4a hr,="m v3L219">.2"liing">"Canss="reserv Iwrits \n"">.2664ecode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L578" i573L218" class="line" nam v3L218">.218ero>(struct.4a hreeroode=fiq4/a>             NXIOref">hw4/a>-> NXIOa hrcode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L579" i573L219" class="line" ngotoass="sref">ack_bero_no_iores>hw4/a>->4a ero_no_ioresa hrcode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L580" i580L314" class=" class="line" nam v3L270">.2704/a>}e<5 href="dr5vers/spi/spi-s3c24xx.c#L581" i583L311" class="line" nam v3L311">.3114/a>e<5 href="dr5vers/spi/spi-s3c24xx.c#L582" i583L312" class="line" nam v3L3q_rspi4/a>] = (long)4a href="+code=hw" class="sref">hw4/a>->4a href iq_mode" class="sioremapef">u84/a>     ioremap*4a nss="sref">ack_bres>hw4/a>->4a resc24xhref="+code=hw" classtartef">u84/a>     >tarta hr, m v3L301">.3014resourc"_size>hw4/a>->4a resourc"_size*4a nss="sref">ack_bres>hw4/a>->4a resc24x)ecode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L583" i583L290" class="lin"line" nam v3L24/a>                4a href="+code=hw" class="sref">hw4/a>->4a href iiq_mode" class="sNUL="sref">spi4/a>,NUL=hrefe"+" class="line" nam v3L289">.2894/a>e<5 href="dr5vers/spi/spi-s3c24xx.c#L584" i583L304" class="line" nam v3L317">.317 hreero>(struct.4a hret;4eero+codeim_fiq" class="sref"p="sref">spi4/a>-&gpt;4a hrhref="+code=hw" clas="sref">spi4/a>->4a hr,="m v3L219">.2"liing">"Canss="map IO\n"">.2664ecode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L585" i583L315" class="line" nam v3L315">.315ero>(struct.4a hreeroode=fiq4/a>             NXIOref">hw4/a>-> NXIOa hrcode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L586" i583L296" class="line" ngotoass="sref">ack_bero_no_iomapef">u84/a>     ero_no_iomapa hrcode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L587" i587L314" class=" class="line" nam v3L270">.2704/a>}e<5 href="dr5vers/spi/spi-s3c24xx.c#L588" i583L278line" nam v3L209">.2094/a>        }e<5 href="dr5vers/spi/spi-s3c24xx.c#L589" i583L309" class="line" nam v3L3">fiq_rcount4/a>] = 4a href="+code=hw" clasit4/a>(unsigned int34a hrhref="+code=hw" clplat upd_get_it4/a>(unsigned inplat upd_get_it4*4a nss="sref">ack_bp="sref">spi4/a>-&gpt;4a hr, 0ecode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L590" i593L290" class="linss="sref">ack_b4/a>                4a href="+code=hw" clasit4/a>(unsigned int34a hrh<e=0e"+" class="line" nam v3L289">.2894/a>e<5 href="dr5vers/spi/spi-s3c24xx.c#L591" i593L291" class="line" nam v3L218">.218 hreero>(struct.4a hret;4eero+codeim_fiq" class="sref"p="sref">spi4/a>-&gpt;4a hrhref="+code=hw" clas="sref">spi4/a>->4a hr,="m v3L219">.2"liing">"No IRQ specified\n"">.2664ecode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L592" i593L302" class="line" nam v3L302">.302ero>(struct.4a hreeroode=fiq4/a>             NOENTref">hw4/a>-> NOENTa hrcode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L593" i593L203" class="line" ngotoass="sref">ack_bero_no_it4/a>(unsigned inero_no_it4a hrcode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L594" i594L310" class=" class="line" nam v3L270">.2704/a>}e<5 href="dr5vers/spi/spi-s3c24xx.c#L595" i593L305" class="line" nam v3L305">.3054/a>e<5 href="dr5vers/spi/spi-s3c24xx.c#L596" i593L306" class="line" nam v3L3ero>(struct.4a hreeroode=fiqf="+code=hw" clrequest_it4/a>(unsigned inrequest_it4iq" cspi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" clasit4/a>(unsigned int34a hr, _mode" class="s>3c24xx_spi_it4/a>(unsigned ins3c24xx_spi_it4+cod, 0,=q" class="sref"p="sref">spi4/a>-&gpt;4a hrhref="+code=hw" clas4xx.>(struct.4a hrenxx.a hr, m v3L301">.3014q_rspi4/a>] = (long)4a ecode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L597" i593L307" class="linss="sref">ack_bero>(struct.4a hreeroode=e"+" class="line" nam v3L289">.2894/a>e<5 href="dr5vers/spi/spi-s3c24xx.c#L598" i593L218" class="line" nam v3L218">.218t;4eero>(struct.4a hret;4eero+codeim_fiq" class="sref"p="sref">spi4/a>-&gpt;4a hrhref="+code=hw" clas="sref">spi4/a>->4a hr,="m v3L219">.2"liing">"Canss="219im IRQ\n"">.2664ecode=data" class="sref">data4/a>[0];e<5 href="dr5vers/spi/spi-s3c24xx.c#L599" i593L219" class="line" ngotoass="sref">ack_bero_no_it4/a>(unsigned inero_no_it4a hrcode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L600" i600L314" class=" class="line" nam v3L270">.2704/a>}e<6 href="dr6vers/spi/spi-s3c24xx.c#L601" i603L311" class="line" nam v3L311">.3114/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L602" i603L312" class="line" nam v3L3q_rspi4/a>] = (long)4a href="+code=hw" clas1lk2674/a>static.41lka hrfiqf="+code=hw" cl1lk_getef">u84/a>     1lk_get+codeim_fiq" class="sref"p="sref">spi4/a>-&gpt;4a hrhref="+code=hw" clas="sref">spi4/a>->4a hr,="m v3L219">.2"liing">"311"">.2664ecode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L603" i603L290" class="lin"line" nam v3L2IS_ERR>(struct.4a hreIS_ERRiq" cspi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" clas1lk2674/a>static.41lka hree"+" class="line" nam v3L289">.2894/a>e<6 4ref="dr6vers/spi/spi-s3c24xx.c#L604" i603L304" class="line" nam v3L218">.218t;4eero>(struct.4a hret;4eero+codeim_fiq" class="sref"p="sref">spi4/a>-&gpt;4a hrhref="+code=hw" clas="sref">spi4/a>->4a hr,="m v3L219">.2"liing">"No c>.24:en sdevic"\n"">.2664ecode=data" class="sref">data4/a>[0];e<6 5ref="dr6vers/spi/spi-s3c24xx.c#L605" i603L155" class="line" n"line" nam v3L3ero>(struct.4a hreeroode=fiqf="+code=hw" clPTR_ERR>(struct.4a hrePTR_ERRiq" cspi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" clas1lk2674/a>static.41lka hrecode=data" class="sref">data4/a>[0];e<6 6ref="dr6vers/spi/spi-s3c24xx.c#L606" i603L296" class="line" ngotoass="sref">ack_bero_no_1lk2674/a>static.4ero_no_1lka hrcode=data" class="sref">data4/a>[0];e<6 7ref="dr6vers/spi/spi-s3c24xx.c#L607" i607L314" class=" class="line" nam v3L270">.2704/a>}e<6 8ref="dr6vers/spi/spi-s3c24xx.c#L608" i603L278line" nam v3L209">.2094/a>        }e<6 9ref="dr6vers/spi/spi-s3c24xx.c#L609" i603L309" class="m v3L219">.2194/a>      74/a>4any gpio we cv3L76">.2664/a>4spal class="comment"> */4/spalue<6 href="dr6vers/spi/spi-s3c24xx.c#L610" i613L260" class="line" nam v3L260">.2604/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L611" i613L221" class="line" nam v3L290">.p="sref">u84/a>     p 4a hrefhref="+code=hw" class"+cc4        4a href="+cc4ode=e"+" class="line" nam v3L289">.2894/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L612" i613L302" class="line" n"linss="sref">ack_bp="sref">u84/a>     p 4a hrefhref="+code=hw" claspincc4        4a hrefpincc4*4a h<e=0e"+" class="line" nam v3L289">.2894/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L613" i613L203" class="line" n"line" nam v3L218">.218t;4eero>(struct.4a hret;4eero+codeim_fiq" class="sref"p="sref">spi4/a>-&gpt;4a hrhref="+code=hw" clas="sref">spi4/a>->4a hr,="m v3L219">.2"liing">"No chipselect pin\n"">.2664ecode=data" class="sref">data4/a>[0];e<6 4ref="dr6vers/spi/spi-s3c24xx.c#L614" i613L304" class="line" nnnnnnnnnam v3L302">.302ero>(struct.4a hreeroode=fiq4/a>             INVA="sref">spi4/a>, INVA=a hrcode=data" class="sref">data4/a>[0];e<6 5ref="dr6vers/spi/spi-s3c24xx.c#L615" i613L155" class="line" nam v3L15gotoass="sref">ack_bero_writ  to2674/a>static.4ero_writ  toa hrcode=data" class="sref">data4/a>[0];e<6 6ref="dr6vers/spi/spi-s3c24xx.c#L616" i613L296" class="line" n" class="line" nam v3L270">.2704/a>}e<6 7ref="dr6vers/spi/spi-s3c24xx.c#L617" i613L197" class="line" nam v3L197">.1974/a>e<6 8ref="dr6pi" class="srref="driver6/sp 1613L218" class="line" nam v3L218">.218ero>(struct.4a hreeroode=fiqam v3L218">.218gpio_request>(struct.4a hregpio_request*4a nss="sref">ack_bp="sref">u84/a>     p 4a hrefhref="+code=hw" claspincc4        4a hrefpincc4*4a , am v3L218">.218t;4e4xx.>(struct.4a hret;4e4xx.+codeim_fiq" class="sref"p="sref">spi4/a>-&gpt;4a hrhref="+code=hw" clas="sref">spi4/a>->4a hr)ecode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L619" i613L219" class="line" n"linss="sref">ack_bero>(struct.4a hreeroode=e"+" class="line" nam v3L289">.2894/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L620" i623L300" class="line" n"line" nam v3L218">.218t;4eero>(struct.4a hret;4eero+codeim_fiq" class="sref"p="sref">spi4/a>-&gpt;4a hrhref="+code=hw" clas="sref">spi4/a>->4a hr,="m v3L219">.2"liing">"Failed toaget gpio en scs\n"">.2664ecode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L621" i623L291" class="line" nam v3L15gotoass="sref">ack_bero_writ  to2674/a>static.4ero_writ  toa hrcode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L622" i623L302" class="line" n" class="line" nam v3L270">.2704/a>}e<6 href="dr6vers/spi/spi-s3c24xx.c#L623" i623L313" class="line" nam v3L313">.3134/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L624" i623L304" class="line" nam v3L218">.2184/a>                4a href="+code=hw" class"+cc4        4a href="+cc4ode=fiq_mode" class="s>.1924/a>stagpioc4        4a href=.1924/a>stagpioc4*4a code=data" class="sref">data4/a>[0];e<6 5ref="dr6vers/spi/spi-s3c24xx.c#L625" i623L155" class="line" n"line" nam v3L3gpio_directes _outpu>uregs4/a>[4a hrgpio_directes _outpu>iq" cspi" class="srep="sref">u84/a>     p 4a hrefhref="+code=hw" claspincc4        4a hrefpincc4*4a , 1ecode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L626" i623L306" class="n"line" nam v3L303">.3034/a>        elsee<6 href="dr6vers/spi/spi-s3c24xx.c#L627" i623L317" class="line" nam v3L317">.3174/a>                4a href="+code=hw" class"+cc4        4a href="+cc4ode=fiq_mode" class="sp="sref">u84/a>     p 4a hrefhref="+code=hw" class"+cc4        4a href="+cc4ode=code=data" class="sref">data4/a>[0];e<6 8ref="dr6vers/spi/spi-s3c24xx.c#L628" i623L278line" nam v3L209">.2094/a>        }e<6 href="dr6vers/spi/spi-s3c24xx.c#L629" i623L309" class="line" nam v3L3s3c24xx_spi_a>  ials"tup4a href="+code=s3c24xx_spi_a>  ials"tup+codem v3L301">.3014q_rspi4/a>] = (long)4a ecode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L630" i633L260" class="line" nam v3L260">.2604/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L631" i633L221" class="m v3L219">.2194/a>      writ  to our 260 control>hw176">.2664/a>4spal class="comment"> */4/spalue<6 href="dr6vers/spi/spi-s3c24xx.c#L632" i633L222" class="line" nam v3L222">.2224/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L633" i633L253" class="line" nam v3L2ero>(struct.4a hreeroode=fiqam v3L218">.218spi_bitbang_startef">u84/a>     >pi_bitbang_start+codeim_fiq" class="sref"4/a>                4a href="+code=hw" clasbitbang>(struct.4a hrebitbanga hrecode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L634" i633L304" class="linss="sref">ack_bero>(struct.4a hreeroode=e"+" class="line" nam v3L289">.2894/a>e<6 5ref="dr6vers/spi/spi-s3c24xx.c#L635" i633L155" class="line" n"line" nam v3L3t;4eero>(struct.4a hret;4eero+codeim_fiq" class="sref"p="sref">spi4/a>-&gpt;4a hrhref="+code=hw" clas="sref">spi4/a>->4a hr,="m v3L219">.2"liing">"Failed toawrit  to SPI ma  to\n"">.2664ecode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L636" i633L296" class="line" ngotoass="sref">ack_bero_writ  to2674/a>static.4ero_writ  toa hrcode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L637" i637L314" class=" class="line" nam v3L270">.2704/a>}e<6 8ref="dr6vers/spi/spi-s3c24xx.c#L638" i633L278line" nam v3L209">.2094/a>        }e<6 href="dr6vers/spi/spi-s3c24xx.c#L639" i633L309" class="line" e=count" class="sref">count4/a>] : 0;e<6 href="dr6vers/spi/spi-s3c24xx.c#L640" i643L260" class="line" nam v3L260">.2604/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L641" i643L311ass="sref">ack_bero_writ  to2674/a>static.4ero_writ  toa hr:code=mode" class="sref">mode4/a>) {e<6 href="dr6vers/spi/spi-s3c24xx.c#L642" i643L312" class="linss="sref">ack_b4/a>                4a href="+code=hw" class"+cc4        4a href="+cc4ode=fiiq_mode" class="s>.1924/a>stagpioc4        4a href=.1924/a>stagpioc4*4a href="+code=hw" class="sref">hw4/a>)e<6 href="dr6vers/spi/spi-s3c24xx.c#L643" i643L203" class="line" n"line" nam v3L3gpio_fre.>(struct.4a hregpio_fre.iq" cspi" class="srep="sref">u84/a>     p 4a hrefhref="+code=hw" claspincc4        4a hrefpincc4*4a ecode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L644" i644L310ode=data" class="sref">data4/a>[0];e<6 5ref="dr6vers/spi/spi-s3c24xx.c#L645" i643L285" class=am v3L218">.2181lk_disabl 2674/a>static.41lk_disabl iq" cspi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" clas1lk2674/a>static.41lka hrecode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L646" i643L306" class="line" nam v3L31lk_pu>uregs4/a>[4a hr1lk_pu>iq" cspi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" clas1lk2674/a>static.41lka hrecode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L647" i643L197" class="line" nam v3L197">.1974/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L648" i643L278ass="sref">ack_bero_no_1lk2674/a>static.4ero_no_1lka hr:code=mode" class="sref">mode4/a>) {e<6 href="dr6vers/spi/spi-s3c24xx.c#L649" i643L309" class="line" nam v3L3fre._it4/a>(unsigned infre._it4iq" cspi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" clasit4/a>(unsigned int34a hr, _mode" class="sq_rspi4/a>] = (long)4a ecode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L650" i653L260" class="line" nam v3L260">.2604/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L651" i653L311ass="sref">ack_bero_no_it4/a>(unsigned inero_no_it4a hr:code=mode" class="sref">mode4/a>) {e<6 href="dr6vers/spi/spi-s3c24xx.c#L652" i653L312" class="line" nam v3L3iounmapef">u84/a>     iounmapiq" cspi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" class="sref">hw4/a>->4a hrefecode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L653" i653L313" class="line" nam v3L313">.3134/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L654" i653L284ass="sref">ack_bero_no_iomapef">u84/a>     ero_no_iomapa hr:code=mode" class="sref">mode4/a>) {e<6 5ref="dr6vers/spi/spi-s3c24xx.c#L655" i653L285" class=am v3L218">.218release_resourc">hw4/a>->4a release_resourc"iq" cspi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" clasioareref">u84/a>     ioarerc24xecode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L656" i653L306" class="line" nam v3L3kfre.>(struct.4a hrekfre.iq" cspi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" clasioareref">u84/a>     ioarerc24xecode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L657" i653L197" class="line" nam v3L197">.1974/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L658" i653L278ass="sref">ack_bero_no_iores>hw4/a>->4a ero_no_ioresa hr:code=mode" class="sref">mode4/a>) {e<6 href="dr6vers/spi/spi-s3c24xx.c#L659" i653L309"ss="sref">ack_bero_no_p="sref">u84/a>     ero_no_p="sra hr:code=mode" class="sref">mode4/a>) {e<6 href="dr6vers/spi/spi-s3c24xx.c#L660" i663L310" class="line" nam v3L3spi_ma  to_pu>uregs4/a>[4a hrspi_ma  to_pu>iq" cspi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" clasma  to>(struct.4a hrema  toc24xecode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L661" i663L311" class="line" nam v3L311">.3114/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L662" i663L312"ss="sref">ack_bero_nomem>(struct.4a hreero_nomemc24x:code=mode" class="sref">mode4/a>) {e<6 href="dr6vers/spi/spi-s3c24xx.c#L663" i663L203" class="line" ss="sref">ack_bero>(struct.4a hreeroode=code=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L664" i664L310" class="line" nam v3L270">.2704/a>}e<6 href="dr6vers/spi/spi-s3c24xx.c#L665" i663L305" class="line" nam v3L305">.3054/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L666" i663L306" class class="sref">ack_b__devex"sref">u324/a> 4a__devex"sL312"ss="sref">ack_b=.1924/a>staremov.>(struct.4a hre=.1924/a>staremov.iq" class="sref">s3c24xx_sp lat upd_devic">hw4/a>->4a  lat upd_devic"c24xx_spi" class="sre="sref">spi4/a>->4a hr)" class="line" nam v3L305">.3054/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L667" i663L307+" class="line" nam v3L289">.2894/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L668" i663L218" class=lass="sref">s3c24xx_spi_tryfiq4/a>(struct.4a href="+code=s3c24xx_spi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" clplat upd_get_drv="sref">u84/a>     plat upd_g"+cdrv="sr*4a nss="sref">ack_b="sref">spi4/a>->4a hr)code=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L669" i663L289" class="line" nam v3L289">.2894/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L670" i673L310" class="line" nam v3L3plat upd_="+cdrv="sref">u84/a>     plat upd_="+cdrv="sr*4a nss="sref">ack_b="sref">spi4/a>->4a hr,="s="sref">ack_bNUL="sref">spi4/a>,NUL=hrefecode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L671" i673L311" class="line" nam v3L311">.3114/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L672" i673L312" class="line" nam v3L3spi_bitbang_stop4a href="+code=spi_bitbang_stop+codeim_fiq" class="sref"4/a>                4a href="+code=hw" clasbitbang>(struct.4a hrebitbanga hrecode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L673" i673L313" class="line" nam v3L313">.3134/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L674" i673L304" class=spi" class="sre1lk_disabl 2674/a>static.41lk_disabl iq" cspi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" clas1lk2674/a>static.41lka hrecode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L675" i673L285" class=am v3L218">.2181lk_pu>uregs4/a>[4a hr1lk_pu>iq" cspi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" clas1lk2674/a>static.41lka hrecode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L676" i673L316" class="line" nam v3L316">.3164/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L677" i673L317" class="line" nam v3L3fre._it4/a>(unsigned infre._it4iq" cspi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" clasit4/a>(unsigned int34a hr, _mode" class="sq_rspi4/a>] = (long)4a ecode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L678" i673L308" class="line" nam v3L3aounmapef">u84/a>     iounmapiq" cspi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" class="sref">hw4/a>->4a hrefecode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L679" i673L289" class="line" nam v3L289">.2894/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L680" i683L290" class="linss="sref">ack_b4/a>                4a href="+code=hw" class"+cc4        4a href="+cc4ode=fiiq_mode" class="s>.1924/a>stagpioc4        4a href=.1924/a>stagpioc4*4a href="+code=hw" class="sref">hw4/a>)e<6 href="dr6vers/spi/spi-s3c24xx.c#L681" i683L291" class="line" nam v3L218">.218gpio_fre.>(struct.4a hregpio_fre.iq" cspi" class="sre4/a>                4a href="+code=hw" clasp="sref">u84/a>     p 4a hrefhref="+code=hw" claspincc4        4a hrefpincc4*4a ecode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L682" i683L222" class="line" nam v3L222">.2224/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L683" i683L253" class="line" nam v3L2release_resourc">hw4/a>->4a release_resourc"iq" cspi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" clasioareref">u84/a>     ioarerc24xecode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L684" i683L304" class=spi" class="srekfre.>(struct.4a hrekfre.iq" cspi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" clasioareref">u84/a>     ioarerc24xecode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L685" i683L305" class="line" nam v3L305">.3054/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L686" i683L306" class="line" nam v3L3spi_ma  to_pu>uregs4/a>[4a hrspi_ma  to_pu>iq" cspi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" clasma  to>(struct.4a hrema  toc24xecode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L687" i687L314" class="line" e=count" class="sref">count4/a>] : 0;e<6 href="dr6vers/spi/spi-s3c24xx.c#L688" i683L278" class="line" nam v3L270">.2704/a>}e<6 href="dr6vers/spi/spi-s3c24xx.c#L689" i683L289" class="line" nam v3L289">.2894/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L690" i693L260" class="line" nam v3L260">.2604/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L691" i693L291#ifdef="line" nam v3L3CONFIG_PM>(struct.4a hreCONFIG_PML260" class="line" nam v3L260">.2604/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L692" i693L222" class="line" nam v3L222">.2224/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L693" i693L203" class class="sref">ack_b=.1924/a>stasuspend        4a href=.1924/a>stasuspendiq" class="sref">s3c24xx_spdevic">hw4/a>->4a devic"c24xx_spi" class="sre="sref">spi4/a>->4a hr)" class="line" nam v3L305">.3054/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L694" i694L310+" class="line" nam v3L289">.2894/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L695" i693L285" class=lass="sref">s3c24xx_spi_tryfiq4/a>(struct.4a href="+code=s3c24xx_spi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" clplat upd_get_drv="sref">u84/a>     plat upd_g"+cdrv="sr*4a nss="sref">ack_bto_ lat upd_devic">hw4/a>->4a to_ lat upd_devic"*4a nss="sref">ack_b="sref">spi4/a>->4a hr)ecode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L696" i693L316" class="line" nam v3L316">.3164/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L697" i693L307" class="linss="sref">ack_b">fiq_rcount4/a>] = 4a href="+code=hw" clasp="sref">u84/a>     p 4a hrefhim_fiim_fief="+code=hw" cl4/a>                4a href="+code=hw" clasp="sref">u84/a>     p 4a hrefhref="+code=hw" clasgpio_s"tup4a href="+code=gpio_s"tupa hr)" class="line" nam v3L305">.3054/a>e<6 href="dr6vers/spi/spi-s3c24xx.c#L698" i693L218" class="line" nam v3L218">.2184/a>                4a href="+code=hw" clasp="sref">u84/a>     p 4a hrefhref="+code=hw" clasgpio_s"tup4a href="+code=gpio_s"tupa hrnss="sref">ack_b">fiq_rcount4/a>] = 4a href="+code=hw" clasp="sref">u84/a>     p 4a href, 0ecode=data" class="sref">data4/a>[0];e<6 href="dr6vers/spi/spi-s3c24xx.c#L699" i693L289" class="line" nam v3L289">.2894/a>e<7 href="dr7vers/spi/spi-s3c24xx.c#L700" i703L310" class="line" nam v3L31lk_disabl 2674/a>static.41lk_disabl iq" cspi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" clas1lk2674/a>static.41lka hrecode=data" class="sref">data4/a>[0];e<7 href="dr7vers/spi/spi-s3c24xx.c#L701" i703L291" class="line" e=count" class="sref">count4/a>] : 0;e<7 href="dr7vers/spi/spi-s3c24xx.c#L702" i703L312" class="line" nam v3L270">.2704/a>}e<7 href="dr7vers/spi/spi-s3c24xx.c#L703" i703L313" class="line" nam v3L313">.3134/a>e<7 4ref="dr7vers/spi/spi-s3c24xx.c#L704" i703L304" class class="sref">ack_b=.1924/a>staresux.>(struct.4a hre=.1924/a>staresux.iq" class="sref">s3c24xx_spdevic">hw4/a>->4a devic"c24xx_spi" class="sre="sref">spi4/a>->4a hr)" class="line" nam v3L305">.3054/a>e<7 5ref="dr7vers/spi/spi-s3c24xx.c#L705" i703L155+" class="line" nam v3L289">.2894/a>e<7 6ref="dr7vers/spi/spi-s3c24xx.c#L706" i703L296" class=lass="sref">s3c24xx_spi_tryfiq4/a>(struct.4a href="+code=s3c24xx_spi" class="sref">s3c24xx_spi4/a> *4a href="+code=hw" clplat upd_get_drv="sref">u84/a>     plat upd_g"+cdrv="sr*4a nss="sref">ack_bto_ lat upd_devic">hw4/a>->4a to_ lat upd_devic"*4a nss="sref">ack_b="sref">spi4/a>->4a hr)ecode=data" class="sref">data4/a>[0];e<7 7ref="dr7vers/spi/spi-s3c24xx.c#L707" i703L197" class="line" nam v3L197">.1974/a>e<7 8ref="dr7vers/spi/spi-s3c24xx.c#L708" i703L308" class="line" nam v3L3s3c24xx_spi_a>  ials"tup4a href="+code=s3c24xx_spi_a>  ials"tup+codem v3L301">.3014q_rspi4/a>] = (long)4a ecode=data" class="sref">data4/a>[0];e<7 9ref="dr7vers/spi/spi-s3c24xx.c#L709" i703L309" class="line" e=count" class="sref">count4/a>] : 0;e<7 href="dr7vers/spi/spi-s3c24xx.c#L710" i713L260" class="line" nam v3L270">.2704/a>}e<7 href="dr7vers/spi/spi-s3c24xx.c#L711" i713L311" class="line" nam v3L311">.3114/a>e<7 href="dr7vers/spi/spi-s3c24xx.c#L712" i713L302" classconst=lass="sref">s3c24xx_spt;4epm_op4        4a hreft;4epm_op4L312"ss="sref">ack_b=.1924/a>stapmop4        4a href=.1924/a>stapmop4*4a hre+" class="line" nam v3L289">.2894/a>e<7 href="dr7vers/spi/spi-s3c24xx.c#L713" i713L203" class=="+code=regs" cl7uspend        4a href=uspendiq" " class=ref="+code=hw" cli3c24xx_spi_suspend        4a href=.1924/a>stasuspendiq" ," class="line" nam v3L222">.2224/a>e<7 4ref="dr7vers/spi/spi-s3c24xx.c#L714" i713L304" class=="+code=regs" clresux.>(struct.4a hreresux.iq"  " class=ref="+code=hw" cli3c24xx_spi_resux.>(struct.4a hre=.1924/a>staresux.iq" ," class="line" nam v3L222">.2224/a>e<7 5ref="dr7vers/spi/spi-s3c24xx.c#L715" i713L155}=count" class="sref">count4/a>] : 0;e<7 6ref="dr7vers/spi/spi-s3c24xx.c#L716" i713L316" class="line" nam v3L316">.3164/a>e<7 7ref="dr7vers/spi/spi-s3c24xx.c#L717" i713L197#def-s3ef="+code=hw" clS3C24XX_C_S3PMOPS>(struct.4a hreS3C24XX_C_S3PMOPShrefhim_fiss="sref">ack_b=.1924/a>stapmop4        4a href=.1924/a>stapmop4*4a " class="line" nam v3L316">.3164/a>e<7 8ref="dr7pi" class="srref="driver7/sp 1713L218#"line" nam v3L303">.3034/a>        elsee<7 href="dr7vers/spi/spi-s3c24xx.c#L719" i713L219#def-s3ef="+code=hw" clS3C24XX_C_S3PMOPS>(struct.4a hreS3C24XX_C_S3PMOPShrefh"s="sref">ack_bNUL="sref">spi4/a>,NUL=hrefe" nam v3L303">.3034/a>        elsee<7 href="dr7vers/spi/spi-s3c24xx.c#L720" i723L300#end"li"m v3L219">.2194/a>      CONFIG_PM176">.2664/a>4spal class="comment"> */4/spalue<7 href="dr7vers/spi/spi-s3c24xx.c#L721" i723L311" class="line" nam v3L311">.3114/a>e<7 href="dr7vers/spi/spi-s3c24xx.c#L722" i723L302"s="sref">ack_bMODULE_ALIAS>(struct.4a hreMODULE_ALIAS+codemm v3L219">.2"liing">" lat upd:>.31110-s11"">.2664ecode=data" class="sref">data4/a>[0];e<7 href="dr7vers/spi/spi-s3c24xx.c#L723" i723L203" classlass="sref">s3c24xx_sp lat upd_dlass=ef">u84/a>     plat upd_dlass=L312"ss="sref">ack_b=.1924/a>stadlass=ef">u84/a>     =.1924/a>stadlass=*4a hre+" class="line" nam v3L289">.2894/a>e<7 href="dr7vers/spi/spi-s3c24xx.c#L724" i723L304" class=="+code=regs" clprob">hw4/a>->4a  rob"L218" class="lref="+code=hw" cli3c24xx_spi_prob">hw4/a>->4a i3c24xx_spi_prob"iq" ," class="line" nam v3L222">.2224/a>e<7 5ref="dr7vers/spi/spi-s3c24xx.c#L725" i723L155" class=="+code=regs" clremov.>(struct.4a hreremov.iq"  class="lref="+code=hw" cl__devex"s_p4a href="+code=__devex"s_p+codem v3L301">.3014=.1924/a>staremov.>(struct.4a hre=.1924/a>staremov.iq" )," class="line" nam v3L222">.2224/a>e<7 href="dr7vers/spi/spi-s3c24xx.c#L726" i723L306" class=="+code=regs" cldlass=ef">u84/a>     dlass=*4a hclass="lre+" class="line" nam v3L289">.2894/a>e<7 7ref="dr7vers/spi/spi-s3c24xx.c#L727" i723L317" class="line" n="+code=regs" cl4xx.>(struct.4a hre4xx.+cod="lrefm v3L219">.2"liing">"3.31110-s11"">.2664," class="line" nam v3L222">.2224/a>e<7 8ref="dr7vers/spi/spi-s3c24xx.c#L728" i723L218" class="line" n="+code=regs" clowns=ef">u84/a>     owns=L218" ref="+code=hw" clTHIS_MODULEef">u84/a>     THIS_MODULEiq" ," class="line" nam v3L222">.2224/a>e<7 href="dr7vers/spi/spi-s3c24xx.c#L729" i723L219" class="line" n="+code=regs" clpm>(struct.4a hrepmL219" claref="+code=hw" clS3C24XX_C_S3PMOPS>(struct.4a hreS3C24XX_C_S3PMOPShref," class="line" nam v3L222">.2224/a>e<7 href="dr7vers/spi/spi-s3c24xx.c#L730" i730L314" class="," class="line" nam v3L222">.2224/a>e<7 href="dr7vers/spi/spi-s3c24xx.c#L731" i733L221}=count" class="sref">count4/a>] : 0;e<7 href="dr7vers/spi/spi-s3c24xx.c#L732" i733L302"s="sref">ack_bmodule_ lat upd_dlass=ef">u84/a>     module_ lat upd_dlass=+codem v3L301">.3014=.1924/a>stadlass=ef">u84/a>     =.1924/a>stadlass=*4a ecode=data" class="sref">data4/a>[0];e<7 href="dr7vers/spi/spi-s3c24xx.c#L733" i733L313" class="line" nam v3L313">.3134/a>e<7 href="dr7vers/spi/spi-s3c24xx.c#L734" i733L304"s="sref">ack_bMODULE_DESCRIPTION>(struct.4a hreMODULE_DESCRIPTION+codemm v3L219">.2"liing">"S3C24XX SPI Dne" n"">.2664ecode=data" class="sref">data4/a>[0];e<7 5ref="dr7vers/spi/spi-s3c24xx.c#L735" i733L155"s="sref">ack_bMODULE_AUTHOR>(struct.4a hreMODULE_AUTHOR+codemm v3L219">.2"liing">"Ben Dooks,h<eben@simtec.co.ukref="">.2664ecode=data" class="sref">data4/a>[0];e<7 href="dr7vers/spi/spi-s3c24xx.c#L736" i733L296"s="sref">ack_bMODULE_LICENSEef">u84/a>     MODULE_LICENSE+codemm v3L219">.2"liing">"GPL"">.2664ecode=data" class="sref">data4/a>[0];e<7 7ref="dr7vers/spi/spi-s3c24xx.c#L737" i737L314


> The original LXR software by th3ef="+code=http://sourc" upge.net/projects/lxo>>LXR 194/unityhref, this experi/a> al ss="ion by f="+code=mailto:lxo@i-sux.no">lxo@i-sux.nohref.
> lxo.i-sux.no kindly hosted by f="+code=http://www.redpill-i-spro.no">Redpill L-spro AS+cod, providto of L-suxsconsultingfand operates s servic"s:since 1995.