linux/drivers/ide/piix.c
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   1/*
   2 *  Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
   3 *  Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
   4 *  Copyright (C) 2003 Red Hat
   5 *  Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
   6 *
   7 *  May be copied or modified under the terms of the GNU General Public License
   8 *
   9 * Documentation:
  10 *
  11 *      Publicly available from Intel web site. Errata documentation
  12 * is also publicly available. As an aide to anyone hacking on this
  13 * driver the list of errata that are relevant is below.going back to
  14 * PIIX4. Older device documentation is now a bit tricky to find.
  15 *
  16 * Errata of note:
  17 *
  18 * Unfixable
  19 *      PIIX4    errata #9      - Only on ultra obscure hw
  20 *      ICH3     errata #13     - Not observed to affect real hw
  21 *                                by Intel
  22 *
  23 * Things we must deal with
  24 *      PIIX4   errata #10      - BM IDE hang with non UDMA
  25 *                                (must stop/start dma to recover)
  26 *      440MX   errata #15      - As PIIX4 errata #10
  27 *      PIIX4   errata #15      - Must not read control registers
  28 *                                during a PIO transfer
  29 *      440MX   errata #13      - As PIIX4 errata #15
  30 *      ICH2    errata #21      - DMA mode 0 doesn't work right
  31 *      ICH0/1  errata #55      - As ICH2 errata #21
  32 *      ICH2    spec c #9       - Extra operations needed to handle
  33 *                                drive hotswap [NOT YET SUPPORTED]
  34 *      ICH2    spec c #20      - IDE PRD must not cross a 64K boundary
  35 *                                and must be dword aligned
  36 *      ICH2    spec c #24      - UDMA mode 4,5 t85/86 should be 6ns not 3.3
  37 *
  38 * Should have been BIOS fixed:
  39 *      450NX:  errata #19      - DMA hangs on old 450NX
  40 *      450NX:  errata #20      - DMA hangs on old 450NX
  41 *      450NX:  errata #25      - Corruption with DMA on old 450NX
  42 *      ICH3    errata #15      - IDE deadlock under high load
  43 *                                (BIOS must set dev 31 fn 0 bit 23)
  44 *      ICH3    errata #18      - Don't use native mode
  45 */
  46
  47#include <linux/types.h>
  48#include <linux/module.h>
  49#include <linux/kernel.h>
  50#include <linux/pci.h>
  51#include <linux/ide.h>
  52#include <linux/init.h>
  53
  54#include <asm/io.h>
  55
  56#define DRV_NAME "piix"
  57
  58static int no_piix_dma;
  59
  60/**
  61 *      piix_set_pio_mode       -       set host controller for PIO mode
  62 *      @port: port
  63 *      @drive: drive
  64 *
  65 *      Set the interface PIO mode based upon the settings done by AMI BIOS.
  66 */
  67
  68static void piix_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  69{
  70        struct pci_dev *dev     = to_pci_dev(hwif->dev);
  71        int is_slave            = drive->dn & 1;
  72        int master_port         = hwif->channel ? 0x42 : 0x40;
  73        int slave_port          = 0x44;
  74        unsigned long flags;
  75        u16 master_data;
  76        u8 slave_data;
  77        static DEFINE_SPINLOCK(tune_lock);
  78        int control = 0;
  79        const u8 pio = drive->pio_mode - XFER_PIO_0;
  80
  81                                     /* ISP  RTC */
  82        static const u8 timings[][2]= {
  83                                        { 0, 0 },
  84                                        { 0, 0 },
  85                                        { 1, 0 },
  86                                        { 2, 1 },
  87                                        { 2, 3 }, };
  88
  89        /*
  90         * Master vs slave is synchronized above us but the slave register is
  91         * shared by the two hwifs so the corner case of two slave timeouts in
  92         * parallel must be locked.
  93         */
  94        spin_lock_irqsave(&tune_lock, flags);
  95        pci_read_config_word(dev, master_port, &master_data);
  96
  97        if (pio > 1)
  98                control |= 1;   /* Programmable timing on */
  99        if (drive->media == ide_disk)
 100                control |= 4;   /* Prefetch, post write */
 101        if (ide_pio_need_iordy(drive, pio))
 102                control |= 2;   /* IORDY */
 103        if (is_slave) {
 104                master_data |=  0x4000;
 105                master_data &= ~0x0070;
 106                if (pio > 1) {
 107                        /* Set PPE, IE and TIME */
 108                        master_data |= control << 4;
 109                }
 110                pci_read_config_byte(dev, slave_port, &slave_data);
 111                slave_data &= hwif->channel ? 0x0f : 0xf0;
 112                slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
 113                               (hwif->channel ? 4 : 0);
 114        } else {
 115                master_data &= ~0x3307;
 116                if (pio > 1) {
 117                        /* enable PPE, IE and TIME */
 118                        master_data |= control;
 119                }
 120                master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
 121        }
 122        pci_write_config_word(dev, master_port, master_data);
 123        if (is_slave)
 124                pci_write_config_byte(dev, slave_port, slave_data);
 125        spin_unlock_irqrestore(&tune_lock, flags);
 126}
 127
 128/**
 129 *      piix_set_dma_mode       -       set host controller for DMA mode
 130 *      @hwif: port
 131 *      @drive: drive
 132 *
 133 *      Set a PIIX host controller to the desired DMA mode.  This involves
 134 *      programming the right timing data into the PCI configuration space.
 135 */
 136
 137static void piix_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
 138{
 139        struct pci_dev *dev     = to_pci_dev(hwif->dev);
 140        u8 maslave              = hwif->channel ? 0x42 : 0x40;
 141        int a_speed             = 3 << (drive->dn * 4);
 142        int u_flag              = 1 << drive->dn;
 143        int v_flag              = 0x01 << drive->dn;
 144        int w_flag              = 0x10 << drive->dn;
 145        int u_speed             = 0;
 146        int                     sitre;
 147        u16                     reg4042, reg4a;
 148        u8                      reg48, reg54, reg55;
 149        const u8 speed          = drive->dma_mode;
 150
 151        pci_read_config_word(dev, maslave, &reg4042);
 152        sitre = (reg4042 & 0x4000) ? 1 : 0;
 153        pci_read_config_byte(dev, 0x48, &reg48);
 154        pci_read_config_word(dev, 0x4a, &reg4a);
 155        pci_read_config_byte(dev, 0x54, &reg54);
 156        pci_read_config_byte(dev, 0x55, &reg55);
 157
 158        if (speed >= XFER_UDMA_0) {
 159                u8 udma = speed - XFER_UDMA_0;
 160
 161                u_speed = min_t(u8, 2 - (udma & 1), udma) << (drive->dn * 4);
 162
 163                if (!(reg48 & u_flag))
 164                        pci_write_config_byte(dev, 0x48, reg48 | u_flag);
 165                if (speed == XFER_UDMA_5) {
 166                        pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
 167                } else {
 168                        pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
 169                }
 170                if ((reg4a & a_speed) != u_speed)
 171                        pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
 172                if (speed > XFER_UDMA_2) {
 173                        if (!(reg54 & v_flag))
 174                                pci_write_config_byte(dev, 0x54, reg54 | v_flag);
 175                } else
 176                        pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
 177        } else {
 178                const u8 mwdma_to_pio[] = { 0, 3, 4 };
 179
 180                if (reg48 & u_flag)
 181                        pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
 182                if (reg4a & a_speed)
 183                        pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
 184                if (reg54 & v_flag)
 185                        pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
 186                if (reg55 & w_flag)
 187                        pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
 188
 189                if (speed >= XFER_MW_DMA_0)
 190                        drive->pio_mode =
 191                                mwdma_to_pio[speed - XFER_MW_DMA_0] + XFER_PIO_0;
 192                else
 193                        drive->pio_mode = XFER_PIO_2; /* for SWDMA2 */
 194
 195                piix_set_pio_mode(hwif, drive);
 196        }
 197}
 198
 199/**
 200 *      init_chipset_ich        -       set up the ICH chipset
 201 *      @dev: PCI device to set up
 202 *
 203 *      Initialize the PCI device as required.  For the ICH this turns
 204 *      out to be nice and simple.
 205 */
 206
 207static int init_chipset_ich(struct pci_dev *dev)
 208{
 209        u32 extra = 0;
 210
 211        pci_read_config_dword(dev, 0x54, &extra);
 212        pci_write_config_dword(dev, 0x54, extra | 0x400);
 213
 214        return 0;
 215}
 216
 217/**
 218 *      ich_clear_irq   -       clear BMDMA status
 219 *      @drive: IDE drive
 220 *
 221 *      ICHx contollers set DMA INTR no matter DMA or PIO.
 222 *      BMDMA status might need to be cleared even for
 223 *      PIO interrupts to prevent spurious/lost IRQ.
 224 */
 225static void ich_clear_irq(ide_drive_t *drive)
 226{
 227        ide_hwif_t *hwif = drive->hwif;
 228        u8 dma_stat;
 229
 230        /*
 231         * ide_dma_end() needs BMDMA status for error checking.
 232         * So, skip clearing BMDMA status here and leave it
 233         * to ide_dma_end() if this is DMA interrupt.
 234         */
 235        if (drive->waiting_for_dma || hwif->dma_base == 0)
 236                return;
 237
 238        /* clear the INTR & ERROR bits */
 239        dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
 240        /* Should we force the bit as well ? */
 241        outb(dma_stat, hwif->dma_base + ATA_DMA_STATUS);
 242}
 243
 244struct ich_laptop {
 245        u16 device;
 246        u16 subvendor;
 247        u16 subdevice;
 248};
 249
 250/*
 251 *      List of laptops that use short cables rather than 80 wire
 252 */
 253
 254static const struct ich_laptop ich_laptop[] = {
 255        /* devid, subvendor, subdev */
 256        { 0x27DF, 0x1025, 0x0102 },     /* ICH7 on Acer 5602aWLMi */
 257        { 0x27DF, 0x0005, 0x0280 },     /* ICH7 on Acer 5602WLMi */
 258        { 0x27DF, 0x1025, 0x0110 },     /* ICH7 on Acer 3682WLMi */
 259        { 0x27DF, 0x1043, 0x1267 },     /* ICH7 on Asus W5F */
 260        { 0x27DF, 0x103C, 0x30A1 },     /* ICH7 on HP Compaq nc2400 */
 261        { 0x27DF, 0x1071, 0xD221 },     /* ICH7 on Hercules EC-900 */
 262        { 0x24CA, 0x1025, 0x0061 },     /* ICH4 on Acer Aspire 2023WLMi */
 263        { 0x24CA, 0x1025, 0x003d },     /* ICH4 on ACER TM290 */
 264        { 0x266F, 0x1025, 0x0066 },     /* ICH6 on ACER Aspire 1694WLMi */
 265        { 0x2653, 0x1043, 0x82D8 },     /* ICH6M on Asus Eee 701 */
 266        { 0x27df, 0x104d, 0x900e },     /* ICH7 on Sony TZ-90 */
 267        /* end marker */
 268        { 0, }
 269};
 270
 271static u8 piix_cable_detect(ide_hwif_t *hwif)
 272{
 273        struct pci_dev *pdev = to_pci_dev(hwif->dev);
 274        const struct ich_laptop *lap = &ich_laptop[0];
 275        u8 reg54h = 0, mask = hwif->channel ? 0xc0 : 0x30;
 276
 277        /* check for specials */
 278        while (lap->device) {
 279                if (lap->device == pdev->device &&
 280                    lap->subvendor == pdev->subsystem_vendor &&
 281                    lap->subdevice == pdev->subsystem_device) {
 282                        return ATA_CBL_PATA40_SHORT;
 283                }
 284                lap++;
 285        }
 286
 287        pci_read_config_byte(pdev, 0x54, &reg54h);
 288
 289        return (reg54h & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 290}
 291
 292/**
 293 *      init_hwif_piix          -       fill in the hwif for the PIIX
 294 *      @hwif: IDE interface
 295 *
 296 *      Set up the ide_hwif_t for the PIIX interface according to the
 297 *      capabilities of the hardware.
 298 */
 299
 300static void __devinit init_hwif_piix(ide_hwif_t *hwif)
 301{
 302        if (!hwif->dma_base)
 303                return;
 304
 305        if (no_piix_dma)
 306                hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0;
 307}
 308
 309static const struct ide_port_ops piix_port_ops = {
 310        .set_pio_mode           = piix_set_pio_mode,
 311        .set_dma_mode           = piix_set_dma_mode,
 312        .cable_detect           = piix_cable_detect,
 313};
 314
 315static const struct ide_port_ops ich_port_ops = {
 316        .set_pio_mode           = piix_set_pio_mode,
 317        .set_dma_mode           = piix_set_dma_mode,
 318        .clear_irq              = ich_clear_irq,
 319        .cable_detect           = piix_cable_detect,
 320};
 321
 322#define DECLARE_PIIX_DEV(udma) \
 323        {                                               \
 324                .name           = DRV_NAME,             \
 325                .init_hwif      = init_hwif_piix,       \
 326                .enablebits     = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
 327                .port_ops       = &piix_port_ops,       \
 328                .pio_mask       = ATA_PIO4,             \
 329                .swdma_mask     = ATA_SWDMA2_ONLY,      \
 330                .mwdma_mask     = ATA_MWDMA12_ONLY,     \
 331                .udma_mask      = udma,                 \
 332        }
 333
 334#define DECLARE_ICH_DEV(mwdma, udma) \
 335        { \
 336                .name           = DRV_NAME, \
 337                .init_chipset   = init_chipset_ich, \
 338                .init_hwif      = init_hwif_piix, \
 339                .enablebits     = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
 340                .port_ops       = &ich_port_ops, \
 341                .pio_mask       = ATA_PIO4, \
 342                .swdma_mask     = ATA_SWDMA2_ONLY, \
 343                .mwdma_mask     = mwdma, \
 344                .udma_mask      = udma, \
 345        }
 346
 347static const struct ide_port_info piix_pci_info[] __devinitconst = {
 348        /* 0: MPIIX */
 349        {       /*
 350                 * MPIIX actually has only a single IDE channel mapped to
 351                 * the primary or secondary ports depending on the value
 352                 * of the bit 14 of the IDETIM register at offset 0x6c
 353                 */
 354                .name           = DRV_NAME,
 355                .enablebits     = {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}},
 356                .host_flags     = IDE_HFLAG_ISA_PORTS | IDE_HFLAG_NO_DMA,
 357                .pio_mask       = ATA_PIO4,
 358                /* This is a painful system best to let it self tune for now */
 359        },
 360        /* 1: PIIXa/PIIXb/PIIX3 */
 361        DECLARE_PIIX_DEV(0x00), /* no udma */
 362        /* 2: PIIX4 */
 363        DECLARE_PIIX_DEV(ATA_UDMA2),
 364        /* 3: ICH0 */
 365        DECLARE_ICH_DEV(ATA_MWDMA12_ONLY, ATA_UDMA2),
 366        /* 4: ICH */
 367        DECLARE_ICH_DEV(ATA_MWDMA12_ONLY, ATA_UDMA4),
 368        /* 5: PIIX4 */
 369        DECLARE_PIIX_DEV(ATA_UDMA4),
 370        /* 6: ICH[2-6]/ICH[2-3]M/C-ICH/ICH5-SATA/ESB2/ICH8M */
 371        DECLARE_ICH_DEV(ATA_MWDMA12_ONLY, ATA_UDMA5),
 372        /* 7: ICH7/7-R, no MWDMA1 */
 373        DECLARE_ICH_DEV(ATA_MWDMA2_ONLY, ATA_UDMA5),
 374};
 375
 376/**
 377 *      piix_init_one   -       called when a PIIX is found
 378 *      @dev: the piix device
 379 *      @id: the matching pci id
 380 *
 381 *      Called when the PCI registration layer (or the IDE initialization)
 382 *      finds a device matching our IDE device tables.
 383 */
 384 
 385static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 386{
 387        return ide_pci_init_one(dev, &piix_pci_info[id->driver_data], NULL);
 388}
 389
 390/**
 391 *      piix_check_450nx        -       Check for problem 450NX setup
 392 *      
 393 *      Check for the present of 450NX errata #19 and errata #25. If
 394 *      they are found, disable use of DMA IDE
 395 */
 396
 397static void __devinit piix_check_450nx(void)
 398{
 399        struct pci_dev *pdev = NULL;
 400        u16 cfg;
 401        while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
 402        {
 403                /* Look for 450NX PXB. Check for problem configurations
 404                   A PCI quirk checks bit 6 already */
 405                pci_read_config_word(pdev, 0x41, &cfg);
 406                /* Only on the original revision: IDE DMA can hang */
 407                if (pdev->revision == 0x00)
 408                        no_piix_dma = 1;
 409                /* On all revisions below 5 PXB bus lock must be disabled for IDE */
 410                else if (cfg & (1<<14) && pdev->revision < 5)
 411                        no_piix_dma = 2;
 412        }
 413        if(no_piix_dma)
 414                printk(KERN_WARNING DRV_NAME ": 450NX errata present, disabling IDE DMA.\n");
 415        if(no_piix_dma == 2)
 416                printk(KERN_WARNING DRV_NAME ": A BIOS update may resolve this.\n");
 417}               
 418
 419static const struct pci_device_id piix_pci_tbl[] = {
 420        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_0),  1 },
 421        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_1),  1 },
 422        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX),    0 },
 423        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371SB_1),  1 },
 424        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371AB),    2 },
 425        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AB_1),  3 },
 426        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82443MX_1),  2 },
 427        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AA_1),  4 },
 428        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82372FB_1),  5 },
 429        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82451NX),    2 },
 430        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_9),  6 },
 431        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_8),  6 },
 432        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_10), 6 },
 433        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_11), 6 },
 434        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_11), 6 },
 435        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_11), 6 },
 436        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801E_11),  6 },
 437        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_10), 6 },
 438#ifdef CONFIG_BLK_DEV_IDE_SATA
 439        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_1),  6 },
 440#endif
 441        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB_2),      6 },
 442        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH6_19),    6 },
 443        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH7_21),    7 },
 444        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_1),  6 },
 445        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB2_18),    7 },
 446        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH8_6),     6 },
 447        { 0, },
 448};
 449MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
 450
 451static struct pci_driver piix_pci_driver = {
 452        .name           = "PIIX_IDE",
 453        .id_table       = piix_pci_tbl,
 454        .probe          = piix_init_one,
 455        .remove         = ide_pci_remove,
 456        .suspend        = ide_pci_suspend,
 457        .resume         = ide_pci_resume,
 458};
 459
 460static int __init piix_ide_init(void)
 461{
 462        piix_check_450nx();
 463        return ide_pci_register_driver(&piix_pci_driver);
 464}
 465
 466static void __exit piix_ide_exit(void)
 467{
 468        pci_unregister_driver(&piix_pci_driver);
 469}
 470
 471module_init(piix_ide_init);
 472module_exit(piix_ide_exit);
 473
 474MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
 475MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
 476MODULE_LICENSE("GPL");
 477
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