linux/drivers/gpio/gpio-omap.c
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   1/*
   2 * Support functions for OMAP GPIO
   3 *
   4 * Copyright (C) 2003-2005 Nokia Corporation
   5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
   6 *
   7 * Copyright (C) 2009 Texas Instruments
   8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
   9 *
  10 * This program is free software; you can redistribute it and/or modify
  11 * it under the terms of the GNU General Public License version 2 as
  12 * published by the Free Software Foundation.
  13 */
  14
  15#include <linux/init.h>
  16#include <linux/module.h>
  17#include <linux/interrupt.h>
  18#include <linux/syscore_ops.h>
  19#include <linux/err.h>
  20#include <linux/clk.h>
  21#include <linux/io.h>
  22#include <linux/device.h>
  23#include <linux/pm_runtime.h>
  24#include <linux/pm.h>
  25#include <linux/of.h>
  26#include <linux/of_device.h>
  27#include <linux/irqdomain.h>
  28#include <linux/gpio.h>
  29#include <linux/platform_data/gpio-omap.h>
  30
  31#include <asm/mach/irq.h>
  32
  33#define OFF_MODE        1
  34
  35static LIST_HEAD(omap_gpio_list);
  36
  37struct gpio_regs {
  38        u32 irqenable1;
  39        u32 irqenable2;
  40        u32 wake_en;
  41        u32 ctrl;
  42        u32 oe;
  43        u32 leveldetect0;
  44        u32 leveldetect1;
  45        u32 risingdetect;
  46        u32 fallingdetect;
  47        u32 dataout;
  48        u32 debounce;
  49        u32 debounce_en;
  50};
  51
  52struct gpio_bank {
  53        struct list_head node;
  54        void __iomem *base;
  55        u16 irq;
  56        int irq_base;
  57        struct irq_domain *domain;
  58        u32 non_wakeup_gpios;
  59        u32 enabled_non_wakeup_gpios;
  60        struct gpio_regs context;
  61        u32 saved_datain;
  62        u32 level_mask;
  63        u32 toggle_mask;
  64        spinlock_t lock;
  65        struct gpio_chip chip;
  66        struct clk *dbck;
  67        u32 mod_usage;
  68        u32 dbck_enable_mask;
  69        bool dbck_enabled;
  70        struct device *dev;
  71        bool is_mpuio;
  72        bool dbck_flag;
  73        bool loses_context;
  74        int stride;
  75        u32 width;
  76        int context_loss_count;
  77        int power_mode;
  78        bool workaround_enabled;
  79
  80        void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
  81        int (*get_context_loss_count)(struct device *dev);
  82
  83        struct omap_gpio_reg_offs *regs;
  84};
  85
  86#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
  87#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
  88#define GPIO_MOD_CTRL_BIT       BIT(0)
  89
  90static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)
  91{
  92        return gpio_irq - bank->irq_base + bank->chip.base;
  93}
  94
  95static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
  96{
  97        void __iomem *reg = bank->base;
  98        u32 l;
  99
 100        reg += bank->regs->direction;
 101        l = __raw_readl(reg);
 102        if (is_input)
 103                l |= 1 << gpio;
 104        else
 105                l &= ~(1 << gpio);
 106        __raw_writel(l, reg);
 107        bank->context.oe = l;
 108}
 109
 110
 111/* set data out value using dedicate set/clear register */
 112static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
 113{
 114        void __iomem *reg = bank->base;
 115        u32 l = GPIO_BIT(bank, gpio);
 116
 117        if (enable) {
 118                reg += bank->regs->set_dataout;
 119                bank->context.dataout |= l;
 120        } else {
 121                reg += bank->regs->clr_dataout;
 122                bank->context.dataout &= ~l;
 123        }
 124
 125        __raw_writel(l, reg);
 126}
 127
 128/* set data out value using mask register */
 129static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
 130{
 131        void __iomem *reg = bank->base + bank->regs->dataout;
 132        u32 gpio_bit = GPIO_BIT(bank, gpio);
 133        u32 l;
 134
 135        l = __raw_readl(reg);
 136        if (enable)
 137                l |= gpio_bit;
 138        else
 139                l &= ~gpio_bit;
 140        __raw_writel(l, reg);
 141        bank->context.dataout = l;
 142}
 143
 144static int _get_gpio_datain(struct gpio_bank *bank, int offset)
 145{
 146        void __iomem *reg = bank->base + bank->regs->datain;
 147
 148        return (__raw_readl(reg) & (1 << offset)) != 0;
 149}
 150
 151static int _get_gpio_dataout(struct gpio_bank *bank, int offset)
 152{
 153        void __iomem *reg = bank->base + bank->regs->dataout;
 154
 155        return (__raw_readl(reg) & (1 << offset)) != 0;
 156}
 157
 158static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
 159{
 160        int l = __raw_readl(base + reg);
 161
 162        if (set)
 163                l |= mask;
 164        else
 165                l &= ~mask;
 166
 167        __raw_writel(l, base + reg);
 168}
 169
 170static inline void _gpio_dbck_enable(struct gpio_bank *bank)
 171{
 172        if (bank->dbck_enable_mask && !bank->dbck_enabled) {
 173                clk_enable(bank->dbck);
 174                bank->dbck_enabled = true;
 175
 176                __raw_writel(bank->dbck_enable_mask,
 177                             bank->base + bank->regs->debounce_en);
 178        }
 179}
 180
 181static inline void _gpio_dbck_disable(struct gpio_bank *bank)
 182{
 183        if (bank->dbck_enable_mask && bank->dbck_enabled) {
 184                /*
 185                 * Disable debounce before cutting it's clock. If debounce is
 186                 * enabled but the clock is not, GPIO module seems to be unable
 187                 * to detect events and generate interrupts at least on OMAP3.
 188                 */
 189                __raw_writel(0, bank->base + bank->regs->debounce_en);
 190
 191                clk_disable(bank->dbck);
 192                bank->dbck_enabled = false;
 193        }
 194}
 195
 196/**
 197 * _set_gpio_debounce - low level gpio debounce time
 198 * @bank: the gpio bank we're acting upon
 199 * @gpio: the gpio number on this @gpio
 200 * @debounce: debounce time to use
 201 *
 202 * OMAP's debounce time is in 31us steps so we need
 203 * to convert and round up to the closest unit.
 204 */
 205static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
 206                unsigned debounce)
 207{
 208        void __iomem            *reg;
 209        u32                     val;
 210        u32                     l;
 211
 212        if (!bank->dbck_flag)
 213                return;
 214
 215        if (debounce < 32)
 216                debounce = 0x01;
 217        else if (debounce > 7936)
 218                debounce = 0xff;
 219        else
 220                debounce = (debounce / 0x1f) - 1;
 221
 222        l = GPIO_BIT(bank, gpio);
 223
 224        clk_enable(bank->dbck);
 225        reg = bank->base + bank->regs->debounce;
 226        __raw_writel(debounce, reg);
 227
 228        reg = bank->base + bank->regs->debounce_en;
 229        val = __raw_readl(reg);
 230
 231        if (debounce)
 232                val |= l;
 233        else
 234                val &= ~l;
 235        bank->dbck_enable_mask = val;
 236
 237        __raw_writel(val, reg);
 238        clk_disable(bank->dbck);
 239        /*
 240         * Enable debounce clock per module.
 241         * This call is mandatory because in omap_gpio_request() when
 242         * *_runtime_get_sync() is called,  _gpio_dbck_enable() within
 243         * runtime callbck fails to turn on dbck because dbck_enable_mask
 244         * used within _gpio_dbck_enable() is still not initialized at
 245         * that point. Therefore we have to enable dbck here.
 246         */
 247        _gpio_dbck_enable(bank);
 248        if (bank->dbck_enable_mask) {
 249                bank->context.debounce = debounce;
 250                bank->context.debounce_en = val;
 251        }
 252}
 253
 254/**
 255 * _clear_gpio_debounce - clear debounce settings for a gpio
 256 * @bank: the gpio bank we're acting upon
 257 * @gpio: the gpio number on this @gpio
 258 *
 259 * If a gpio is using debounce, then clear the debounce enable bit and if
 260 * this is the only gpio in this bank using debounce, then clear the debounce
 261 * time too. The debounce clock will also be disabled when calling this function
 262 * if this is the only gpio in the bank using debounce.
 263 */
 264static void _clear_gpio_debounce(struct gpio_bank *bank, unsigned gpio)
 265{
 266        u32 gpio_bit = GPIO_BIT(bank, gpio);
 267
 268        if (!bank->dbck_flag)
 269                return;
 270
 271        if (!(bank->dbck_enable_mask & gpio_bit))
 272                return;
 273
 274        bank->dbck_enable_mask &= ~gpio_bit;
 275        bank->context.debounce_en &= ~gpio_bit;
 276        __raw_writel(bank->context.debounce_en,
 277                     bank->base + bank->regs->debounce_en);
 278
 279        if (!bank->dbck_enable_mask) {
 280                bank->context.debounce = 0;
 281                __raw_writel(bank->context.debounce, bank->base +
 282                             bank->regs->debounce);
 283                clk_disable(bank->dbck);
 284                bank->dbck_enabled = false;
 285        }
 286}
 287
 288static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
 289                                                unsigned trigger)
 290{
 291        void __iomem *base = bank->base;
 292        u32 gpio_bit = 1 << gpio;
 293
 294        _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
 295                  trigger & IRQ_TYPE_LEVEL_LOW);
 296        _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
 297                  trigger & IRQ_TYPE_LEVEL_HIGH);
 298        _gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
 299                  trigger & IRQ_TYPE_EDGE_RISING);
 300        _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
 301                  trigger & IRQ_TYPE_EDGE_FALLING);
 302
 303        bank->context.leveldetect0 =
 304                        __raw_readl(bank->base + bank->regs->leveldetect0);
 305        bank->context.leveldetect1 =
 306                        __raw_readl(bank->base + bank->regs->leveldetect1);
 307        bank->context.risingdetect =
 308                        __raw_readl(bank->base + bank->regs->risingdetect);
 309        bank->context.fallingdetect =
 310                        __raw_readl(bank->base + bank->regs->fallingdetect);
 311
 312        if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
 313                _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
 314                bank->context.wake_en =
 315                        __raw_readl(bank->base + bank->regs->wkup_en);
 316        }
 317
 318        /* This part needs to be executed always for OMAP{34xx, 44xx} */
 319        if (!bank->regs->irqctrl) {
 320                /* On omap24xx proceed only when valid GPIO bit is set */
 321                if (bank->non_wakeup_gpios) {
 322                        if (!(bank->non_wakeup_gpios & gpio_bit))
 323                                goto exit;
 324                }
 325
 326                /*
 327                 * Log the edge gpio and manually trigger the IRQ
 328                 * after resume if the input level changes
 329                 * to avoid irq lost during PER RET/OFF mode
 330                 * Applies for omap2 non-wakeup gpio and all omap3 gpios
 331                 */
 332                if (trigger & IRQ_TYPE_EDGE_BOTH)
 333                        bank->enabled_non_wakeup_gpios |= gpio_bit;
 334                else
 335                        bank->enabled_non_wakeup_gpios &= ~gpio_bit;
 336        }
 337
 338exit:
 339        bank->level_mask =
 340                __raw_readl(bank->base + bank->regs->leveldetect0) |
 341                __raw_readl(bank->base + bank->regs->leveldetect1);
 342}
 343
 344#ifdef CONFIG_ARCH_OMAP1
 345/*
 346 * This only applies to chips that can't do both rising and falling edge
 347 * detection at once.  For all other chips, this function is a noop.
 348 */
 349static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
 350{
 351        void __iomem *reg = bank->base;
 352        u32 l = 0;
 353
 354        if (!bank->regs->irqctrl)
 355                return;
 356
 357        reg += bank->regs->irqctrl;
 358
 359        l = __raw_readl(reg);
 360        if ((l >> gpio) & 1)
 361                l &= ~(1 << gpio);
 362        else
 363                l |= 1 << gpio;
 364
 365        __raw_writel(l, reg);
 366}
 367#else
 368static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
 369#endif
 370
 371static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
 372                                                        unsigned trigger)
 373{
 374        void __iomem *reg = bank->base;
 375        void __iomem *base = bank->base;
 376        u32 l = 0;
 377
 378        if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
 379                set_gpio_trigger(bank, gpio, trigger);
 380        } else if (bank->regs->irqctrl) {
 381                reg += bank->regs->irqctrl;
 382
 383                l = __raw_readl(reg);
 384                if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
 385                        bank->toggle_mask |= 1 << gpio;
 386                if (trigger & IRQ_TYPE_EDGE_RISING)
 387                        l |= 1 << gpio;
 388                else if (trigger & IRQ_TYPE_EDGE_FALLING)
 389                        l &= ~(1 << gpio);
 390                else
 391                        return -EINVAL;
 392
 393                __raw_writel(l, reg);
 394        } else if (bank->regs->edgectrl1) {
 395                if (gpio & 0x08)
 396                        reg += bank->regs->edgectrl2;
 397                else
 398                        reg += bank->regs->edgectrl1;
 399
 400                gpio &= 0x07;
 401                l = __raw_readl(reg);
 402                l &= ~(3 << (gpio << 1));
 403                if (trigger & IRQ_TYPE_EDGE_RISING)
 404                        l |= 2 << (gpio << 1);
 405                if (trigger & IRQ_TYPE_EDGE_FALLING)
 406                        l |= 1 << (gpio << 1);
 407
 408                /* Enable wake-up during idle for dynamic tick */
 409                _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
 410                bank->context.wake_en =
 411                        __raw_readl(bank->base + bank->regs->wkup_en);
 412                __raw_writel(l, reg);
 413        }
 414        return 0;
 415}
 416
 417static int gpio_irq_type(struct irq_data *d, unsigned type)
 418{
 419        struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
 420        unsigned gpio = 0;
 421        int retval;
 422        unsigned long flags;
 423
 424#ifdef CONFIG_ARCH_OMAP1
 425        if (d->irq > IH_MPUIO_BASE)
 426                gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
 427#endif
 428
 429        if (!gpio)
 430                gpio = irq_to_gpio(bank, d->irq);
 431
 432        if (type & ~IRQ_TYPE_SENSE_MASK)
 433                return -EINVAL;
 434
 435        if (!bank->regs->leveldetect0 &&
 436                (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
 437                return -EINVAL;
 438
 439        spin_lock_irqsave(&bank->lock, flags);
 440        retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
 441        spin_unlock_irqrestore(&bank->lock, flags);
 442
 443        if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 444                __irq_set_handler_locked(d->irq, handle_level_irq);
 445        else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 446                __irq_set_handler_locked(d->irq, handle_edge_irq);
 447
 448        return retval;
 449}
 450
 451static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 452{
 453        void __iomem *reg = bank->base;
 454
 455        reg += bank->regs->irqstatus;
 456        __raw_writel(gpio_mask, reg);
 457
 458        /* Workaround for clearing DSP GPIO interrupts to allow retention */
 459        if (bank->regs->irqstatus2) {
 460                reg = bank->base + bank->regs->irqstatus2;
 461                __raw_writel(gpio_mask, reg);
 462        }
 463
 464        /* Flush posted write for the irq status to avoid spurious interrupts */
 465        __raw_readl(reg);
 466}
 467
 468static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
 469{
 470        _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
 471}
 472
 473static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
 474{
 475        void __iomem *reg = bank->base;
 476        u32 l;
 477        u32 mask = (1 << bank->width) - 1;
 478
 479        reg += bank->regs->irqenable;
 480        l = __raw_readl(reg);
 481        if (bank->regs->irqenable_inv)
 482                l = ~l;
 483        l &= mask;
 484        return l;
 485}
 486
 487static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 488{
 489        void __iomem *reg = bank->base;
 490        u32 l;
 491
 492        if (bank->regs->set_irqenable) {
 493                reg += bank->regs->set_irqenable;
 494                l = gpio_mask;
 495                bank->context.irqenable1 |= gpio_mask;
 496        } else {
 497                reg += bank->regs->irqenable;
 498                l = __raw_readl(reg);
 499                if (bank->regs->irqenable_inv)
 500                        l &= ~gpio_mask;
 501                else
 502                        l |= gpio_mask;
 503                bank->context.irqenable1 = l;
 504        }
 505
 506        __raw_writel(l, reg);
 507}
 508
 509static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 510{
 511        void __iomem *reg = bank->base;
 512        u32 l;
 513
 514        if (bank->regs->clr_irqenable) {
 515                reg += bank->regs->clr_irqenable;
 516                l = gpio_mask;
 517                bank->context.irqenable1 &= ~gpio_mask;
 518        } else {
 519                reg += bank->regs->irqenable;
 520                l = __raw_readl(reg);
 521                if (bank->regs->irqenable_inv)
 522                        l |= gpio_mask;
 523                else
 524                        l &= ~gpio_mask;
 525                bank->context.irqenable1 = l;
 526        }
 527
 528        __raw_writel(l, reg);
 529}
 530
 531static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
 532{
 533        if (enable)
 534                _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
 535        else
 536                _disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
 537}
 538
 539/*
 540 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
 541 * 1510 does not seem to have a wake-up register. If JTAG is connected
 542 * to the target, system will wake up always on GPIO events. While
 543 * system is running all registered GPIO interrupts need to have wake-up
 544 * enabled. When system is suspended, only selected GPIO interrupts need
 545 * to have wake-up enabled.
 546 */
 547static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
 548{
 549        u32 gpio_bit = GPIO_BIT(bank, gpio);
 550        unsigned long flags;
 551
 552        if (bank->non_wakeup_gpios & gpio_bit) {
 553                dev_err(bank->dev,
 554                        "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
 555                return -EINVAL;
 556        }
 557
 558        spin_lock_irqsave(&bank->lock, flags);
 559        if (enable)
 560                bank->context.wake_en |= gpio_bit;
 561        else
 562                bank->context.wake_en &= ~gpio_bit;
 563
 564        __raw_writel(bank->context.wake_en, bank->base + bank->regs->wkup_en);
 565        spin_unlock_irqrestore(&bank->lock, flags);
 566
 567        return 0;
 568}
 569
 570static void _reset_gpio(struct gpio_bank *bank, int gpio)
 571{
 572        _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
 573        _set_gpio_irqenable(bank, gpio, 0);
 574        _clear_gpio_irqstatus(bank, gpio);
 575        _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
 576        _clear_gpio_debounce(bank, gpio);
 577}
 578
 579/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
 580static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
 581{
 582        struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
 583        unsigned int gpio = irq_to_gpio(bank, d->irq);
 584
 585        return _set_gpio_wakeup(bank, gpio, enable);
 586}
 587
 588static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
 589{
 590        struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
 591        unsigned long flags;
 592
 593        /*
 594         * If this is the first gpio_request for the bank,
 595         * enable the bank module.
 596         */
 597        if (!bank->mod_usage)
 598                pm_runtime_get_sync(bank->dev);
 599
 600        spin_lock_irqsave(&bank->lock, flags);
 601        /* Set trigger to none. You need to enable the desired trigger with
 602         * request_irq() or set_irq_type().
 603         */
 604        _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
 605
 606        if (bank->regs->pinctrl) {
 607                void __iomem *reg = bank->base + bank->regs->pinctrl;
 608
 609                /* Claim the pin for MPU */
 610                __raw_writel(__raw_readl(reg) | (1 << offset), reg);
 611        }
 612
 613        if (bank->regs->ctrl && !bank->mod_usage) {
 614                void __iomem *reg = bank->base + bank->regs->ctrl;
 615                u32 ctrl;
 616
 617                ctrl = __raw_readl(reg);
 618                /* Module is enabled, clocks are not gated */
 619                ctrl &= ~GPIO_MOD_CTRL_BIT;
 620                __raw_writel(ctrl, reg);
 621                bank->context.ctrl = ctrl;
 622        }
 623
 624        bank->mod_usage |= 1 << offset;
 625
 626        spin_unlock_irqrestore(&bank->lock, flags);
 627
 628        return 0;
 629}
 630
 631static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
 632{
 633        struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
 634        void __iomem *base = bank->base;
 635        unsigned long flags;
 636
 637        spin_lock_irqsave(&bank->lock, flags);
 638
 639        if (bank->regs->wkup_en) {
 640                /* Disable wake-up during idle for dynamic tick */
 641                _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
 642                bank->context.wake_en =
 643                        __raw_readl(bank->base + bank->regs->wkup_en);
 644        }
 645
 646        bank->mod_usage &= ~(1 << offset);
 647
 648        if (bank->regs->ctrl && !bank->mod_usage) {
 649                void __iomem *reg = bank->base + bank->regs->ctrl;
 650                u32 ctrl;
 651
 652                ctrl = __raw_readl(reg);
 653                /* Module is disabled, clocks are gated */
 654                ctrl |= GPIO_MOD_CTRL_BIT;
 655                __raw_writel(ctrl, reg);
 656                bank->context.ctrl = ctrl;
 657        }
 658
 659        _reset_gpio(bank, bank->chip.base + offset);
 660        spin_unlock_irqrestore(&bank->lock, flags);
 661
 662        /*
 663         * If this is the last gpio to be freed in the bank,
 664         * disable the bank module.
 665         */
 666        if (!bank->mod_usage)
 667                pm_runtime_put(bank->dev);
 668}
 669
 670/*
 671 * We need to unmask the GPIO bank interrupt as soon as possible to
 672 * avoid missing GPIO interrupts for other lines in the bank.
 673 * Then we need to mask-read-clear-unmask the triggered GPIO lines
 674 * in the bank to avoid missing nested interrupts for a GPIO line.
 675 * If we wait to unmask individual GPIO lines in the bank after the
 676 * line's interrupt handler has been run, we may miss some nested
 677 * interrupts.
 678 */
 679static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 680{
 681        void __iomem *isr_reg = NULL;
 682        u32 isr;
 683        unsigned int gpio_irq, gpio_index;
 684        struct gpio_bank *bank;
 685        int unmasked = 0;
 686        struct irq_chip *chip = irq_desc_get_chip(desc);
 687
 688        chained_irq_enter(chip, desc);
 689
 690        bank = irq_get_handler_data(irq);
 691        isr_reg = bank->base + bank->regs->irqstatus;
 692        pm_runtime_get_sync(bank->dev);
 693
 694        if (WARN_ON(!isr_reg))
 695                goto exit;
 696
 697        while(1) {
 698                u32 isr_saved, level_mask = 0;
 699                u32 enabled;
 700
 701                enabled = _get_gpio_irqbank_mask(bank);
 702                isr_saved = isr = __raw_readl(isr_reg) & enabled;
 703
 704                if (bank->level_mask)
 705                        level_mask = bank->level_mask & enabled;
 706
 707                /* clear edge sensitive interrupts before handler(s) are
 708                called so that we don't miss any interrupt occurred while
 709                executing them */
 710                _disable_gpio_irqbank(bank, isr_saved & ~level_mask);
 711                _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
 712                _enable_gpio_irqbank(bank, isr_saved & ~level_mask);
 713
 714                /* if there is only edge sensitive GPIO pin interrupts
 715                configured, we could unmask GPIO bank interrupt immediately */
 716                if (!level_mask && !unmasked) {
 717                        unmasked = 1;
 718                        chained_irq_exit(chip, desc);
 719                }
 720
 721                if (!isr)
 722                        break;
 723
 724                gpio_irq = bank->irq_base;
 725                for (; isr != 0; isr >>= 1, gpio_irq++) {
 726                        int gpio = irq_to_gpio(bank, gpio_irq);
 727
 728                        if (!(isr & 1))
 729                                continue;
 730
 731                        gpio_index = GPIO_INDEX(bank, gpio);
 732
 733                        /*
 734                         * Some chips can't respond to both rising and falling
 735                         * at the same time.  If this irq was requested with
 736                         * both flags, we need to flip the ICR data for the IRQ
 737                         * to respond to the IRQ for the opposite direction.
 738                         * This will be indicated in the bank toggle_mask.
 739                         */
 740                        if (bank->toggle_mask & (1 << gpio_index))
 741                                _toggle_gpio_edge_triggering(bank, gpio_index);
 742
 743                        generic_handle_irq(gpio_irq);
 744                }
 745        }
 746        /* if bank has any level sensitive GPIO pin interrupt
 747        configured, we must unmask the bank interrupt only after
 748        handler(s) are executed in order to avoid spurious bank
 749        interrupt */
 750exit:
 751        if (!unmasked)
 752                chained_irq_exit(chip, desc);
 753        pm_runtime_put(bank->dev);
 754}
 755
 756static void gpio_irq_shutdown(struct irq_data *d)
 757{
 758        struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
 759        unsigned int gpio = irq_to_gpio(bank, d->irq);
 760        unsigned long flags;
 761
 762        spin_lock_irqsave(&bank->lock, flags);
 763        _reset_gpio(bank, gpio);
 764        spin_unlock_irqrestore(&bank->lock, flags);
 765}
 766
 767static void gpio_ack_irq(struct irq_data *d)
 768{
 769        struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
 770        unsigned int gpio = irq_to_gpio(bank, d->irq);
 771
 772        _clear_gpio_irqstatus(bank, gpio);
 773}
 774
 775static void gpio_mask_irq(struct irq_data *d)
 776{
 777        struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
 778        unsigned int gpio = irq_to_gpio(bank, d->irq);
 779        unsigned long flags;
 780
 781        spin_lock_irqsave(&bank->lock, flags);
 782        _set_gpio_irqenable(bank, gpio, 0);
 783        _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
 784        spin_unlock_irqrestore(&bank->lock, flags);
 785}
 786
 787static void gpio_unmask_irq(struct irq_data *d)
 788{
 789        struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
 790        unsigned int gpio = irq_to_gpio(bank, d->irq);
 791        unsigned int irq_mask = GPIO_BIT(bank, gpio);
 792        u32 trigger = irqd_get_trigger_type(d);
 793        unsigned long flags;
 794
 795        spin_lock_irqsave(&bank->lock, flags);
 796        if (trigger)
 797                _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
 798
 799        /* For level-triggered GPIOs, the clearing must be done after
 800         * the HW source is cleared, thus after the handler has run */
 801        if (bank->level_mask & irq_mask) {
 802                _set_gpio_irqenable(bank, gpio, 0);
 803                _clear_gpio_irqstatus(bank, gpio);
 804        }
 805
 806        _set_gpio_irqenable(bank, gpio, 1);
 807        spin_unlock_irqrestore(&bank->lock, flags);
 808}
 809
 810static struct irq_chip gpio_irq_chip = {
 811        .name           = "GPIO",
 812        .irq_shutdown   = gpio_irq_shutdown,
 813        .irq_ack        = gpio_ack_irq,
 814        .irq_mask       = gpio_mask_irq,
 815        .irq_unmask     = gpio_unmask_irq,
 816        .irq_set_type   = gpio_irq_type,
 817        .irq_set_wake   = gpio_wake_enable,
 818};
 819
 820/*---------------------------------------------------------------------*/
 821
 822static int omap_mpuio_suspend_noirq(struct device *dev)
 823{
 824        struct platform_device *pdev = to_platform_device(dev);
 825        struct gpio_bank        *bank = platform_get_drvdata(pdev);
 826        void __iomem            *mask_reg = bank->base +
 827                                        OMAP_MPUIO_GPIO_MASKIT / bank->stride;
 828        unsigned long           flags;
 829
 830        spin_lock_irqsave(&bank->lock, flags);
 831        __raw_writel(0xffff & ~bank->context.wake_en, mask_reg);
 832        spin_unlock_irqrestore(&bank->lock, flags);
 833
 834        return 0;
 835}
 836
 837static int omap_mpuio_resume_noirq(struct device *dev)
 838{
 839        struct platform_device *pdev = to_platform_device(dev);
 840        struct gpio_bank        *bank = platform_get_drvdata(pdev);
 841        void __iomem            *mask_reg = bank->base +
 842                                        OMAP_MPUIO_GPIO_MASKIT / bank->stride;
 843        unsigned long           flags;
 844
 845        spin_lock_irqsave(&bank->lock, flags);
 846        __raw_writel(bank->context.wake_en, mask_reg);
 847        spin_unlock_irqrestore(&bank->lock, flags);
 848
 849        return 0;
 850}
 851
 852static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
 853        .suspend_noirq = omap_mpuio_suspend_noirq,
 854        .resume_noirq = omap_mpuio_resume_noirq,
 855};
 856
 857/* use platform_driver for this. */
 858static struct platform_driver omap_mpuio_driver = {
 859        .driver         = {
 860                .name   = "mpuio",
 861                .pm     = &omap_mpuio_dev_pm_ops,
 862        },
 863};
 864
 865static struct platform_device omap_mpuio_device = {
 866        .name           = "mpuio",
 867        .id             = -1,
 868        .dev = {
 869                .driver = &omap_mpuio_driver.driver,
 870        }
 871        /* could list the /proc/iomem resources */
 872};
 873
 874static inline void mpuio_init(struct gpio_bank *bank)
 875{
 876        platform_set_drvdata(&omap_mpuio_device, bank);
 877
 878        if (platform_driver_register(&omap_mpuio_driver) == 0)
 879                (void) platform_device_register(&omap_mpuio_device);
 880}
 881
 882/*---------------------------------------------------------------------*/
 883
 884static int gpio_input(struct gpio_chip *chip, unsigned offset)
 885{
 886        struct gpio_bank *bank;
 887        unsigned long flags;
 888
 889        bank = container_of(chip, struct gpio_bank, chip);
 890        spin_lock_irqsave(&bank->lock, flags);
 891        _set_gpio_direction(bank, offset, 1);
 892        spin_unlock_irqrestore(&bank->lock, flags);
 893        return 0;
 894}
 895
 896static int gpio_is_input(struct gpio_bank *bank, int mask)
 897{
 898        void __iomem *reg = bank->base + bank->regs->direction;
 899
 900        return __raw_readl(reg) & mask;
 901}
 902
 903static int gpio_get(struct gpio_chip *chip, unsigned offset)
 904{
 905        struct gpio_bank *bank;
 906        u32 mask;
 907
 908        bank = container_of(chip, struct gpio_bank, chip);
 909        mask = (1 << offset);
 910
 911        if (gpio_is_input(bank, mask))
 912                return _get_gpio_datain(bank, offset);
 913        else
 914                return _get_gpio_dataout(bank, offset);
 915}
 916
 917static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
 918{
 919        struct gpio_bank *bank;
 920        unsigned long flags;
 921
 922        bank = container_of(chip, struct gpio_bank, chip);
 923        spin_lock_irqsave(&bank->lock, flags);
 924        bank->set_dataout(bank, offset, value);
 925        _set_gpio_direction(bank, offset, 0);
 926        spin_unlock_irqrestore(&bank->lock, flags);
 927        return 0;
 928}
 929
 930static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
 931                unsigned debounce)
 932{
 933        struct gpio_bank *bank;
 934        unsigned long flags;
 935
 936        bank = container_of(chip, struct gpio_bank, chip);
 937
 938        spin_lock_irqsave(&bank->lock, flags);
 939        _set_gpio_debounce(bank, offset, debounce);
 940        spin_unlock_irqrestore(&bank->lock, flags);
 941
 942        return 0;
 943}
 944
 945static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 946{
 947        struct gpio_bank *bank;
 948        unsigned long flags;
 949
 950        bank = container_of(chip, struct gpio_bank, chip);
 951        spin_lock_irqsave(&bank->lock, flags);
 952        bank->set_dataout(bank, offset, value);
 953        spin_unlock_irqrestore(&bank->lock, flags);
 954}
 955
 956static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
 957{
 958        struct gpio_bank *bank;
 959
 960        bank = container_of(chip, struct gpio_bank, chip);
 961        return bank->irq_base + offset;
 962}
 963
 964/*---------------------------------------------------------------------*/
 965
 966static void __init omap_gpio_show_rev(struct gpio_bank *bank)
 967{
 968        static bool called;
 969        u32 rev;
 970
 971        if (called || bank->regs->revision == USHRT_MAX)
 972                return;
 973
 974        rev = __raw_readw(bank->base + bank->regs->revision);
 975        pr_info("OMAP GPIO hardware version %d.%d\n",
 976                (rev >> 4) & 0x0f, rev & 0x0f);
 977
 978        called = true;
 979}
 980
 981/* This lock class tells lockdep that GPIO irqs are in a different
 982 * category than their parents, so it won't report false recursion.
 983 */
 984static struct lock_class_key gpio_lock_class;
 985
 986static void omap_gpio_mod_init(struct gpio_bank *bank)
 987{
 988        void __iomem *base = bank->base;
 989        u32 l = 0xffffffff;
 990
 991        if (bank->width == 16)
 992                l = 0xffff;
 993
 994        if (bank->is_mpuio) {
 995                __raw_writel(l, bank->base + bank->regs->irqenable);
 996                return;
 997        }
 998
 999        _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
1000        _gpio_rmw(base, bank->regs->irqstatus, l, !bank->regs->irqenable_inv);
1001        if (bank->regs->debounce_en)
1002                __raw_writel(0, base + bank->regs->debounce_en);
1003
1004        /* Save OE default value (0xffffffff) in the context */
1005        bank->context.oe = __raw_readl(bank->base + bank->regs->direction);
1006         /* Initialize interface clk ungated, module enabled */
1007        if (bank->regs->ctrl)
1008                __raw_writel(0, base + bank->regs->ctrl);
1009
1010        bank->dbck = clk_get(bank->dev, "dbclk");
1011        if (IS_ERR(bank->dbck))
1012                dev_err(bank->dev, "Could not get gpio dbck\n");
1013}
1014
1015static __devinit void
1016omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
1017                    unsigned int num)
1018{
1019        struct irq_chip_generic *gc;
1020        struct irq_chip_type *ct;
1021
1022        gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
1023                                    handle_simple_irq);
1024        if (!gc) {
1025                dev_err(bank->dev, "Memory alloc failed for gc\n");
1026                return;
1027        }
1028
1029        ct = gc->chip_types;
1030
1031        /* NOTE: No ack required, reading IRQ status clears it. */
1032        ct->chip.irq_mask = irq_gc_mask_set_bit;
1033        ct->chip.irq_unmask = irq_gc_mask_clr_bit;
1034        ct->chip.irq_set_type = gpio_irq_type;
1035
1036        if (bank->regs->wkup_en)
1037                ct->chip.irq_set_wake = gpio_wake_enable,
1038
1039        ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
1040        irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
1041                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
1042}
1043
1044static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1045{
1046        int j;
1047        static int gpio;
1048
1049        /*
1050         * REVISIT eventually switch from OMAP-specific gpio structs
1051         * over to the generic ones
1052         */
1053        bank->chip.request = omap_gpio_request;
1054        bank->chip.free = omap_gpio_free;
1055        bank->chip.direction_input = gpio_input;
1056        bank->chip.get = gpio_get;
1057        bank->chip.direction_output = gpio_output;
1058        bank->chip.set_debounce = gpio_debounce;
1059        bank->chip.set = gpio_set;
1060        bank->chip.to_irq = gpio_2irq;
1061        if (bank->is_mpuio) {
1062                bank->chip.label = "mpuio";
1063                if (bank->regs->wkup_en)
1064                        bank->chip.dev = &omap_mpuio_device.dev;
1065                bank->chip.base = OMAP_MPUIO(0);
1066        } else {
1067                bank->chip.label = "gpio";
1068                bank->chip.base = gpio;
1069                gpio += bank->width;
1070        }
1071        bank->chip.ngpio = bank->width;
1072
1073        gpiochip_add(&bank->chip);
1074
1075        for (j = bank->irq_base; j < bank->irq_base + bank->width; j++) {
1076                irq_set_lockdep_class(j, &gpio_lock_class);
1077                irq_set_chip_data(j, bank);
1078                if (bank->is_mpuio) {
1079                        omap_mpuio_alloc_gc(bank, j, bank->width);
1080                } else {
1081                        irq_set_chip(j, &gpio_irq_chip);
1082                        irq_set_handler(j, handle_simple_irq);
1083                        set_irq_flags(j, IRQF_VALID);
1084                }
1085        }
1086        irq_set_chained_handler(bank->irq, gpio_irq_handler);
1087        irq_set_handler_data(bank->irq, bank);
1088}
1089
1090static const struct of_device_id omap_gpio_match[];
1091
1092static int __devinit omap_gpio_probe(struct platform_device *pdev)
1093{
1094        struct device *dev = &pdev->dev;
1095        struct device_node *node = dev->of_node;
1096        const struct of_device_id *match;
1097        const struct omap_gpio_platform_data *pdata;
1098        struct resource *res;
1099        struct gpio_bank *bank;
1100        int ret = 0;
1101
1102        match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1103
1104        pdata = match ? match->data : dev->platform_data;
1105        if (!pdata)
1106                return -EINVAL;
1107
1108        bank = devm_kzalloc(&pdev->dev, sizeof(struct gpio_bank), GFP_KERNEL);
1109        if (!bank) {
1110                dev_err(dev, "Memory alloc failed\n");
1111                return -ENOMEM;
1112        }
1113
1114        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1115        if (unlikely(!res)) {
1116                dev_err(dev, "Invalid IRQ resource\n");
1117                return -ENODEV;
1118        }
1119
1120        bank->irq = res->start;
1121        bank->dev = dev;
1122        bank->dbck_flag = pdata->dbck_flag;
1123        bank->stride = pdata->bank_stride;
1124        bank->width = pdata->bank_width;
1125        bank->is_mpuio = pdata->is_mpuio;
1126        bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1127        bank->loses_context = pdata->loses_context;
1128        bank->regs = pdata->regs;
1129#ifdef CONFIG_OF_GPIO
1130        bank->chip.of_node = of_node_get(node);
1131#endif
1132
1133        bank->irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1134        if (bank->irq_base < 0) {
1135                dev_err(dev, "Couldn't allocate IRQ numbers\n");
1136                return -ENODEV;
1137        }
1138
1139        bank->domain = irq_domain_add_legacy(node, bank->width, bank->irq_base,
1140                                             0, &irq_domain_simple_ops, NULL);
1141
1142        if (bank->regs->set_dataout && bank->regs->clr_dataout)
1143                bank->set_dataout = _set_gpio_dataout_reg;
1144        else
1145                bank->set_dataout = _set_gpio_dataout_mask;
1146
1147        spin_lock_init(&bank->lock);
1148
1149        /* Static mapping, never released */
1150        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1151        if (unlikely(!res)) {
1152                dev_err(dev, "Invalid mem resource\n");
1153                return -ENODEV;
1154        }
1155
1156        if (!devm_request_mem_region(dev, res->start, resource_size(res),
1157                                     pdev->name)) {
1158                dev_err(dev, "Region already claimed\n");
1159                return -EBUSY;
1160        }
1161
1162        bank->base = devm_ioremap(dev, res->start, resource_size(res));
1163        if (!bank->base) {
1164                dev_err(dev, "Could not ioremap\n");
1165                return -ENOMEM;
1166        }
1167
1168        platform_set_drvdata(pdev, bank);
1169
1170        pm_runtime_enable(bank->dev);
1171        pm_runtime_irq_safe(bank->dev);
1172        pm_runtime_get_sync(bank->dev);
1173
1174        if (bank->is_mpuio)
1175                mpuio_init(bank);
1176
1177        omap_gpio_mod_init(bank);
1178        omap_gpio_chip_init(bank);
1179        omap_gpio_show_rev(bank);
1180
1181        if (bank->loses_context)
1182                bank->get_context_loss_count = pdata->get_context_loss_count;
1183
1184        pm_runtime_put(bank->dev);
1185
1186        list_add_tail(&bank->node, &omap_gpio_list);
1187
1188        return ret;
1189}
1190
1191#ifdef CONFIG_ARCH_OMAP2PLUS
1192
1193#if defined(CONFIG_PM_RUNTIME)
1194static void omap_gpio_restore_context(struct gpio_bank *bank);
1195
1196static int omap_gpio_runtime_suspend(struct device *dev)
1197{
1198        struct platform_device *pdev = to_platform_device(dev);
1199        struct gpio_bank *bank = platform_get_drvdata(pdev);
1200        u32 l1 = 0, l2 = 0;
1201        unsigned long flags;
1202        u32 wake_low, wake_hi;
1203
1204        spin_lock_irqsave(&bank->lock, flags);
1205
1206        /*
1207         * Only edges can generate a wakeup event to the PRCM.
1208         *
1209         * Therefore, ensure any wake-up capable GPIOs have
1210         * edge-detection enabled before going idle to ensure a wakeup
1211         * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1212         * NDA TRM 25.5.3.1)
1213         *
1214         * The normal values will be restored upon ->runtime_resume()
1215         * by writing back the values saved in bank->context.
1216         */
1217        wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1218        if (wake_low)
1219                __raw_writel(wake_low | bank->context.fallingdetect,
1220                             bank->base + bank->regs->fallingdetect);
1221        wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1222        if (wake_hi)
1223                __raw_writel(wake_hi | bank->context.risingdetect,
1224                             bank->base + bank->regs->risingdetect);
1225
1226        if (!bank->enabled_non_wakeup_gpios)
1227                goto update_gpio_context_count;
1228
1229        if (bank->power_mode != OFF_MODE) {
1230                bank->power_mode = 0;
1231                goto update_gpio_context_count;
1232        }
1233        /*
1234         * If going to OFF, remove triggering for all
1235         * non-wakeup GPIOs.  Otherwise spurious IRQs will be
1236         * generated.  See OMAP2420 Errata item 1.101.
1237         */
1238        bank->saved_datain = __raw_readl(bank->base +
1239                                                bank->regs->datain);
1240        l1 = bank->context.fallingdetect;
1241        l2 = bank->context.risingdetect;
1242
1243        l1 &= ~bank->enabled_non_wakeup_gpios;
1244        l2 &= ~bank->enabled_non_wakeup_gpios;
1245
1246        __raw_writel(l1, bank->base + bank->regs->fallingdetect);
1247        __raw_writel(l2, bank->base + bank->regs->risingdetect);
1248
1249        bank->workaround_enabled = true;
1250
1251update_gpio_context_count:
1252        if (bank->get_context_loss_count)
1253                bank->context_loss_count =
1254                                bank->get_context_loss_count(bank->dev);
1255
1256        _gpio_dbck_disable(bank);
1257        spin_unlock_irqrestore(&bank->lock, flags);
1258
1259        return 0;
1260}
1261
1262static int omap_gpio_runtime_resume(struct device *dev)
1263{
1264        struct platform_device *pdev = to_platform_device(dev);
1265        struct gpio_bank *bank = platform_get_drvdata(pdev);
1266        int context_lost_cnt_after;
1267        u32 l = 0, gen, gen0, gen1;
1268        unsigned long flags;
1269
1270        spin_lock_irqsave(&bank->lock, flags);
1271        _gpio_dbck_enable(bank);
1272
1273        /*
1274         * In ->runtime_suspend(), level-triggered, wakeup-enabled
1275         * GPIOs were set to edge trigger also in order to be able to
1276         * generate a PRCM wakeup.  Here we restore the
1277         * pre-runtime_suspend() values for edge triggering.
1278         */
1279        __raw_writel(bank->context.fallingdetect,
1280                     bank->base + bank->regs->fallingdetect);
1281        __raw_writel(bank->context.risingdetect,
1282                     bank->base + bank->regs->risingdetect);
1283
1284        if (bank->get_context_loss_count) {
1285                context_lost_cnt_after =
1286                        bank->get_context_loss_count(bank->dev);
1287                if (context_lost_cnt_after != bank->context_loss_count) {
1288                        omap_gpio_restore_context(bank);
1289                } else {
1290                        spin_unlock_irqrestore(&bank->lock, flags);
1291                        return 0;
1292                }
1293        }
1294
1295        if (!bank->workaround_enabled) {
1296                spin_unlock_irqrestore(&bank->lock, flags);
1297                return 0;
1298        }
1299
1300        __raw_writel(bank->context.fallingdetect,
1301                        bank->base + bank->regs->fallingdetect);
1302        __raw_writel(bank->context.risingdetect,
1303                        bank->base + bank->regs->risingdetect);
1304        l = __raw_readl(bank->base + bank->regs->datain);
1305
1306        /*
1307         * Check if any of the non-wakeup interrupt GPIOs have changed
1308         * state.  If so, generate an IRQ by software.  This is
1309         * horribly racy, but it's the best we can do to work around
1310         * this silicon bug.
1311         */
1312        l ^= bank->saved_datain;
1313        l &= bank->enabled_non_wakeup_gpios;
1314
1315        /*
1316         * No need to generate IRQs for the rising edge for gpio IRQs
1317         * configured with falling edge only; and vice versa.
1318         */
1319        gen0 = l & bank->context.fallingdetect;
1320        gen0 &= bank->saved_datain;
1321
1322        gen1 = l & bank->context.risingdetect;
1323        gen1 &= ~(bank->saved_datain);
1324
1325        /* FIXME: Consider GPIO IRQs with level detections properly! */
1326        gen = l & (~(bank->context.fallingdetect) &
1327                                         ~(bank->context.risingdetect));
1328        /* Consider all GPIO IRQs needed to be updated */
1329        gen |= gen0 | gen1;
1330
1331        if (gen) {
1332                u32 old0, old1;
1333
1334                old0 = __raw_readl(bank->base + bank->regs->leveldetect0);
1335                old1 = __raw_readl(bank->base + bank->regs->leveldetect1);
1336
1337                if (!bank->regs->irqstatus_raw0) {
1338                        __raw_writel(old0 | gen, bank->base +
1339                                                bank->regs->leveldetect0);
1340                        __raw_writel(old1 | gen, bank->base +
1341                                                bank->regs->leveldetect1);
1342                }
1343
1344                if (bank->regs->irqstatus_raw0) {
1345                        __raw_writel(old0 | l, bank->base +
1346                                                bank->regs->leveldetect0);
1347                        __raw_writel(old1 | l, bank->base +
1348                                                bank->regs->leveldetect1);
1349                }
1350                __raw_writel(old0, bank->base + bank->regs->leveldetect0);
1351                __raw_writel(old1, bank->base + bank->regs->leveldetect1);
1352        }
1353
1354        bank->workaround_enabled = false;
1355        spin_unlock_irqrestore(&bank->lock, flags);
1356
1357        return 0;
1358}
1359#endif /* CONFIG_PM_RUNTIME */
1360
1361void omap2_gpio_prepare_for_idle(int pwr_mode)
1362{
1363        struct gpio_bank *bank;
1364
1365        list_for_each_entry(bank, &omap_gpio_list, node) {
1366                if (!bank->mod_usage || !bank->loses_context)
1367                        continue;
1368
1369                bank->power_mode = pwr_mode;
1370
1371                pm_runtime_put_sync_suspend(bank->dev);
1372        }
1373}
1374
1375void omap2_gpio_resume_after_idle(void)
1376{
1377        struct gpio_bank *bank;
1378
1379        list_for_each_entry(bank, &omap_gpio_list, node) {
1380                if (!bank->mod_usage || !bank->loses_context)
1381                        continue;
1382
1383                pm_runtime_get_sync(bank->dev);
1384        }
1385}
1386
1387#if defined(CONFIG_PM_RUNTIME)
1388static void omap_gpio_restore_context(struct gpio_bank *bank)
1389{
1390        __raw_writel(bank->context.wake_en,
1391                                bank->base + bank->regs->wkup_en);
1392        __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
1393        __raw_writel(bank->context.leveldetect0,
1394                                bank->base + bank->regs->leveldetect0);
1395        __raw_writel(bank->context.leveldetect1,
1396                                bank->base + bank->regs->leveldetect1);
1397        __raw_writel(bank->context.risingdetect,
1398                                bank->base + bank->regs->risingdetect);
1399        __raw_writel(bank->context.fallingdetect,
1400                                bank->base + bank->regs->fallingdetect);
1401        if (bank->regs->set_dataout && bank->regs->clr_dataout)
1402                __raw_writel(bank->context.dataout,
1403                                bank->base + bank->regs->set_dataout);
1404        else
1405                __raw_writel(bank->context.dataout,
1406                                bank->base + bank->regs->dataout);
1407        __raw_writel(bank->context.oe, bank->base + bank->regs->direction);
1408
1409        if (bank->dbck_enable_mask) {
1410                __raw_writel(bank->context.debounce, bank->base +
1411                                        bank->regs->debounce);
1412                __raw_writel(bank->context.debounce_en,
1413                                        bank->base + bank->regs->debounce_en);
1414        }
1415
1416        __raw_writel(bank->context.irqenable1,
1417                                bank->base + bank->regs->irqenable);
1418        __raw_writel(bank->context.irqenable2,
1419                                bank->base + bank->regs->irqenable2);
1420}
1421#endif /* CONFIG_PM_RUNTIME */
1422#else
1423#define omap_gpio_runtime_suspend NULL
1424#define omap_gpio_runtime_resume NULL
1425#endif
1426
1427static const struct dev_pm_ops gpio_pm_ops = {
1428        SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1429                                                                        NULL)
1430};
1431
1432#if defined(CONFIG_OF)
1433static struct omap_gpio_reg_offs omap2_gpio_regs = {
1434        .revision =             OMAP24XX_GPIO_REVISION,
1435        .direction =            OMAP24XX_GPIO_OE,
1436        .datain =               OMAP24XX_GPIO_DATAIN,
1437        .dataout =              OMAP24XX_GPIO_DATAOUT,
1438        .set_dataout =          OMAP24XX_GPIO_SETDATAOUT,
1439        .clr_dataout =          OMAP24XX_GPIO_CLEARDATAOUT,
1440        .irqstatus =            OMAP24XX_GPIO_IRQSTATUS1,
1441        .irqstatus2 =           OMAP24XX_GPIO_IRQSTATUS2,
1442        .irqenable =            OMAP24XX_GPIO_IRQENABLE1,
1443        .irqenable2 =           OMAP24XX_GPIO_IRQENABLE2,
1444        .set_irqenable =        OMAP24XX_GPIO_SETIRQENABLE1,
1445        .clr_irqenable =        OMAP24XX_GPIO_CLEARIRQENABLE1,
1446        .debounce =             OMAP24XX_GPIO_DEBOUNCE_VAL,
1447        .debounce_en =          OMAP24XX_GPIO_DEBOUNCE_EN,
1448        .ctrl =                 OMAP24XX_GPIO_CTRL,
1449        .wkup_en =              OMAP24XX_GPIO_WAKE_EN,
1450        .leveldetect0 =         OMAP24XX_GPIO_LEVELDETECT0,
1451        .leveldetect1 =         OMAP24XX_GPIO_LEVELDETECT1,
1452        .risingdetect =         OMAP24XX_GPIO_RISINGDETECT,
1453        .fallingdetect =        OMAP24XX_GPIO_FALLINGDETECT,
1454};
1455
1456static struct omap_gpio_reg_offs omap4_gpio_regs = {
1457        .revision =             OMAP4_GPIO_REVISION,
1458        .direction =            OMAP4_GPIO_OE,
1459        .datain =               OMAP4_GPIO_DATAIN,
1460        .dataout =              OMAP4_GPIO_DATAOUT,
1461        .set_dataout =          OMAP4_GPIO_SETDATAOUT,
1462        .clr_dataout =          OMAP4_GPIO_CLEARDATAOUT,
1463        .irqstatus =            OMAP4_GPIO_IRQSTATUS0,
1464        .irqstatus2 =           OMAP4_GPIO_IRQSTATUS1,
1465        .irqenable =            OMAP4_GPIO_IRQSTATUSSET0,
1466        .irqenable2 =           OMAP4_GPIO_IRQSTATUSSET1,
1467        .set_irqenable =        OMAP4_GPIO_IRQSTATUSSET0,
1468        .clr_irqenable =        OMAP4_GPIO_IRQSTATUSCLR0,
1469        .debounce =             OMAP4_GPIO_DEBOUNCINGTIME,
1470        .debounce_en =          OMAP4_GPIO_DEBOUNCENABLE,
1471        .ctrl =                 OMAP4_GPIO_CTRL,
1472        .wkup_en =              OMAP4_GPIO_IRQWAKEN0,
1473        .leveldetect0 =         OMAP4_GPIO_LEVELDETECT0,
1474        .leveldetect1 =         OMAP4_GPIO_LEVELDETECT1,
1475        .risingdetect =         OMAP4_GPIO_RISINGDETECT,
1476        .fallingdetect =        OMAP4_GPIO_FALLINGDETECT,
1477};
1478
1479const static struct omap_gpio_platform_data omap2_pdata = {
1480        .regs = &omap2_gpio_regs,
1481        .bank_width = 32,
1482        .dbck_flag = false,
1483};
1484
1485const static struct omap_gpio_platform_data omap3_pdata = {
1486        .regs = &omap2_gpio_regs,
1487        .bank_width = 32,
1488        .dbck_flag = true,
1489};
1490
1491const static struct omap_gpio_platform_data omap4_pdata = {
1492        .regs = &omap4_gpio_regs,
1493        .bank_width = 32,
1494        .dbck_flag = true,
1495};
1496
1497static const struct of_device_id omap_gpio_match[] = {
1498        {
1499                .compatible = "ti,omap4-gpio",
1500                .data = &omap4_pdata,
1501        },
1502        {
1503                .compatible = "ti,omap3-gpio",
1504                .data = &omap3_pdata,
1505        },
1506        {
1507                .compatible = "ti,omap2-gpio",
1508                .data = &omap2_pdata,
1509        },
1510        { },
1511};
1512MODULE_DEVICE_TABLE(of, omap_gpio_match);
1513#endif
1514
1515static struct platform_driver omap_gpio_driver = {
1516        .probe          = omap_gpio_probe,
1517        .driver         = {
1518                .name   = "omap_gpio",
1519                .pm     = &gpio_pm_ops,
1520                .of_match_table = of_match_ptr(omap_gpio_match),
1521        },
1522};
1523
1524/*
1525 * gpio driver register needs to be done before
1526 * machine_init functions access gpio APIs.
1527 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1528 */
1529static int __init omap_gpio_drv_reg(void)
1530{
1531        return platform_driver_register(&omap_gpio_driver);
1532}
1533postcore_initcall(omap_gpio_drv_reg);
1534
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