linux/drivers/ata/pata_pdc2027x.c
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   1/*
   2 *  Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277.
   3 *
   4 *  This program is free software; you can redistribute it and/or
   5 *  modify it under the terms of the GNU General Public License
   6 *  as published by the Free Software Foundation; either version
   7 *  2 of the License, or (at your option) any later version.
   8 *
   9 *  Ported to libata by:
  10 *  Albert Lee <albertcc@tw.ibm.com> IBM Corporation
  11 *
  12 *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
  13 *  Portions Copyright (C) 1999 Promise Technology, Inc.
  14 *
  15 *  Author: Frank Tiernan (frankt@promise.com)
  16 *  Released under terms of General Public License
  17 *
  18 *
  19 *  libata documentation is available via 'make {ps|pdf}docs',
  20 *  as Documentation/DocBook/libata.*
  21 *
  22 *  Hardware information only available under NDA.
  23 *
  24 */
  25#include <linux/kernel.h>
  26#include <linux/module.h>
  27#include <linux/pci.h>
  28#include <linux/init.h>
  29#include <linux/blkdev.h>
  30#include <linux/delay.h>
  31#include <linux/device.h>
  32#include <scsi/scsi.h>
  33#include <scsi/scsi_host.h>
  34#include <scsi/scsi_cmnd.h>
  35#include <linux/libata.h>
  36
  37#define DRV_NAME        "pata_pdc2027x"
  38#define DRV_VERSION     "1.0"
  39#undef PDC_DEBUG
  40
  41#ifdef PDC_DEBUG
  42#define PDPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
  43#else
  44#define PDPRINTK(fmt, args...)
  45#endif
  46
  47enum {
  48        PDC_MMIO_BAR            = 5,
  49
  50        PDC_UDMA_100            = 0,
  51        PDC_UDMA_133            = 1,
  52
  53        PDC_100_MHZ             = 100000000,
  54        PDC_133_MHZ             = 133333333,
  55
  56        PDC_SYS_CTL             = 0x1100,
  57        PDC_ATA_CTL             = 0x1104,
  58        PDC_GLOBAL_CTL          = 0x1108,
  59        PDC_CTCR0               = 0x110C,
  60        PDC_CTCR1               = 0x1110,
  61        PDC_BYTE_COUNT          = 0x1120,
  62        PDC_PLL_CTL             = 0x1202,
  63};
  64
  65static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
  66static int pdc2027x_reinit_one(struct pci_dev *pdev);
  67static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline);
  68static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev);
  69static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev);
  70static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc);
  71static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask);
  72static int pdc2027x_cable_detect(struct ata_port *ap);
  73static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed);
  74
  75/*
  76 * ATA Timing Tables based on 133MHz controller clock.
  77 * These tables are only used when the controller is in 133MHz clock.
  78 * If the controller is in 100MHz clock, the ASIC hardware will
  79 * set the timing registers automatically when "set feature" command
  80 * is issued to the device. However, if the controller clock is 133MHz,
  81 * the following tables must be used.
  82 */
  83static struct pdc2027x_pio_timing {
  84        u8 value0, value1, value2;
  85} pdc2027x_pio_timing_tbl [] = {
  86        { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
  87        { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
  88        { 0x23, 0x26, 0x64 }, /* PIO mode 2 */
  89        { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
  90        { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
  91};
  92
  93static struct pdc2027x_mdma_timing {
  94        u8 value0, value1;
  95} pdc2027x_mdma_timing_tbl [] = {
  96        { 0xdf, 0x5f }, /* MDMA mode 0 */
  97        { 0x6b, 0x27 }, /* MDMA mode 1 */
  98        { 0x69, 0x25 }, /* MDMA mode 2 */
  99};
 100
 101static struct pdc2027x_udma_timing {
 102        u8 value0, value1, value2;
 103} pdc2027x_udma_timing_tbl [] = {
 104        { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
 105        { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
 106        { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
 107        { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
 108        { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
 109        { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
 110        { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
 111};
 112
 113static const struct pci_device_id pdc2027x_pci_tbl[] = {
 114        { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), PDC_UDMA_100 },
 115        { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), PDC_UDMA_133 },
 116        { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), PDC_UDMA_100 },
 117        { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), PDC_UDMA_133 },
 118        { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), PDC_UDMA_133 },
 119        { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), PDC_UDMA_133 },
 120        { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), PDC_UDMA_133 },
 121
 122        { }     /* terminate list */
 123};
 124
 125static struct pci_driver pdc2027x_pci_driver = {
 126        .name                   = DRV_NAME,
 127        .id_table               = pdc2027x_pci_tbl,
 128        .probe                  = pdc2027x_init_one,
 129        .remove                 = ata_pci_remove_one,
 130#ifdef CONFIG_PM
 131        .suspend                = ata_pci_device_suspend,
 132        .resume                 = pdc2027x_reinit_one,
 133#endif
 134};
 135
 136static struct scsi_host_template pdc2027x_sht = {
 137        ATA_BMDMA_SHT(DRV_NAME),
 138};
 139
 140static struct ata_port_operations pdc2027x_pata100_ops = {
 141        .inherits               = &ata_bmdma_port_ops,
 142        .check_atapi_dma        = pdc2027x_check_atapi_dma,
 143        .cable_detect           = pdc2027x_cable_detect,
 144        .prereset               = pdc2027x_prereset,
 145};
 146
 147static struct ata_port_operations pdc2027x_pata133_ops = {
 148        .inherits               = &pdc2027x_pata100_ops,
 149        .mode_filter            = pdc2027x_mode_filter,
 150        .set_piomode            = pdc2027x_set_piomode,
 151        .set_dmamode            = pdc2027x_set_dmamode,
 152        .set_mode               = pdc2027x_set_mode,
 153};
 154
 155static struct ata_port_info pdc2027x_port_info[] = {
 156        /* PDC_UDMA_100 */
 157        {
 158                .flags          = ATA_FLAG_SLAVE_POSS,
 159                .pio_mask       = ATA_PIO4,
 160                .mwdma_mask     = ATA_MWDMA2,
 161                .udma_mask      = ATA_UDMA5,
 162                .port_ops       = &pdc2027x_pata100_ops,
 163        },
 164        /* PDC_UDMA_133 */
 165        {
 166                .flags          = ATA_FLAG_SLAVE_POSS,
 167                .pio_mask       = ATA_PIO4,
 168                .mwdma_mask     = ATA_MWDMA2,
 169                .udma_mask      = ATA_UDMA6,
 170                .port_ops       = &pdc2027x_pata133_ops,
 171        },
 172};
 173
 174MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee");
 175MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277");
 176MODULE_LICENSE("GPL");
 177MODULE_VERSION(DRV_VERSION);
 178MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl);
 179
 180/**
 181 *      port_mmio - Get the MMIO address of PDC2027x extended registers
 182 *      @ap: Port
 183 *      @offset: offset from mmio base
 184 */
 185static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset)
 186{
 187        return ap->host->iomap[PDC_MMIO_BAR] + ap->port_no * 0x100 + offset;
 188}
 189
 190/**
 191 *      dev_mmio - Get the MMIO address of PDC2027x extended registers
 192 *      @ap: Port
 193 *      @adev: device
 194 *      @offset: offset from mmio base
 195 */
 196static inline void __iomem *dev_mmio(struct ata_port *ap, struct ata_device *adev, unsigned int offset)
 197{
 198        u8 adj = (adev->devno) ? 0x08 : 0x00;
 199        return port_mmio(ap, offset) + adj;
 200}
 201
 202/**
 203 *      pdc2027x_pata_cable_detect - Probe host controller cable detect info
 204 *      @ap: Port for which cable detect info is desired
 205 *
 206 *      Read 80c cable indicator from Promise extended register.
 207 *      This register is latched when the system is reset.
 208 *
 209 *      LOCKING:
 210 *      None (inherited from caller).
 211 */
 212static int pdc2027x_cable_detect(struct ata_port *ap)
 213{
 214        u32 cgcr;
 215
 216        /* check cable detect results */
 217        cgcr = ioread32(port_mmio(ap, PDC_GLOBAL_CTL));
 218        if (cgcr & (1 << 26))
 219                goto cbl40;
 220
 221        PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no);
 222
 223        return ATA_CBL_PATA80;
 224cbl40:
 225        printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no);
 226        return ATA_CBL_PATA40;
 227}
 228
 229/**
 230 * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled.
 231 * @ap: Port to check
 232 */
 233static inline int pdc2027x_port_enabled(struct ata_port *ap)
 234{
 235        return ioread8(port_mmio(ap, PDC_ATA_CTL)) & 0x02;
 236}
 237
 238/**
 239 *      pdc2027x_prereset - prereset for PATA host controller
 240 *      @link: Target link
 241 *      @deadline: deadline jiffies for the operation
 242 *
 243 *      Probeinit including cable detection.
 244 *
 245 *      LOCKING:
 246 *      None (inherited from caller).
 247 */
 248
 249static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline)
 250{
 251        /* Check whether port enabled */
 252        if (!pdc2027x_port_enabled(link->ap))
 253                return -ENOENT;
 254        return ata_sff_prereset(link, deadline);
 255}
 256
 257/**
 258 *      pdc2720x_mode_filter    -       mode selection filter
 259 *      @adev: ATA device
 260 *      @mask: list of modes proposed
 261 *
 262 *      Block UDMA on devices that cause trouble with this controller.
 263 */
 264
 265static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask)
 266{
 267        unsigned char model_num[ATA_ID_PROD_LEN + 1];
 268        struct ata_device *pair = ata_dev_pair(adev);
 269
 270        if (adev->class != ATA_DEV_ATA || adev->devno == 0 || pair == NULL)
 271                return mask;
 272
 273        /* Check for slave of a Maxtor at UDMA6 */
 274        ata_id_c_string(pair->id, model_num, ATA_ID_PROD,
 275                          ATA_ID_PROD_LEN + 1);
 276        /* If the master is a maxtor in UDMA6 then the slave should not use UDMA 6 */
 277        if (strstr(model_num, "Maxtor") == NULL && pair->dma_mode == XFER_UDMA_6)
 278                mask &= ~ (1 << (6 + ATA_SHIFT_UDMA));
 279
 280        return mask;
 281}
 282
 283/**
 284 *      pdc2027x_set_piomode - Initialize host controller PATA PIO timings
 285 *      @ap: Port to configure
 286 *      @adev: um
 287 *
 288 *      Set PIO mode for device.
 289 *
 290 *      LOCKING:
 291 *      None (inherited from caller).
 292 */
 293
 294static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev)
 295{
 296        unsigned int pio = adev->pio_mode - XFER_PIO_0;
 297        u32 ctcr0, ctcr1;
 298
 299        PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode);
 300
 301        /* Sanity check */
 302        if (pio > 4) {
 303                printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio);
 304                return;
 305
 306        }
 307
 308        /* Set the PIO timing registers using value table for 133MHz */
 309        PDPRINTK("Set pio regs... \n");
 310
 311        ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0));
 312        ctcr0 &= 0xffff0000;
 313        ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 |
 314                (pdc2027x_pio_timing_tbl[pio].value1 << 8);
 315        iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
 316
 317        ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
 318        ctcr1 &= 0x00ffffff;
 319        ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24);
 320        iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
 321
 322        PDPRINTK("Set pio regs done\n");
 323
 324        PDPRINTK("Set to pio mode[%u] \n", pio);
 325}
 326
 327/**
 328 *      pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings
 329 *      @ap: Port to configure
 330 *      @adev: um
 331 *
 332 *      Set UDMA mode for device.
 333 *
 334 *      LOCKING:
 335 *      None (inherited from caller).
 336 */
 337static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 338{
 339        unsigned int dma_mode = adev->dma_mode;
 340        u32 ctcr0, ctcr1;
 341
 342        if ((dma_mode >= XFER_UDMA_0) &&
 343           (dma_mode <= XFER_UDMA_6)) {
 344                /* Set the UDMA timing registers with value table for 133MHz */
 345                unsigned int udma_mode = dma_mode & 0x07;
 346
 347                if (dma_mode == XFER_UDMA_2) {
 348                        /*
 349                         * Turn off tHOLD.
 350                         * If tHOLD is '1', the hardware will add half clock for data hold time.
 351                         * This code segment seems to be no effect. tHOLD will be overwritten below.
 352                         */
 353                        ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
 354                        iowrite32(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1));
 355                }
 356
 357                PDPRINTK("Set udma regs... \n");
 358
 359                ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
 360                ctcr1 &= 0xff000000;
 361                ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 |
 362                        (pdc2027x_udma_timing_tbl[udma_mode].value1 << 8) |
 363                        (pdc2027x_udma_timing_tbl[udma_mode].value2 << 16);
 364                iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
 365
 366                PDPRINTK("Set udma regs done\n");
 367
 368                PDPRINTK("Set to udma mode[%u] \n", udma_mode);
 369
 370        } else  if ((dma_mode >= XFER_MW_DMA_0) &&
 371                   (dma_mode <= XFER_MW_DMA_2)) {
 372                /* Set the MDMA timing registers with value table for 133MHz */
 373                unsigned int mdma_mode = dma_mode & 0x07;
 374
 375                PDPRINTK("Set mdma regs... \n");
 376                ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0));
 377
 378                ctcr0 &= 0x0000ffff;
 379                ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) |
 380                        (pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24);
 381
 382                iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
 383                PDPRINTK("Set mdma regs done\n");
 384
 385                PDPRINTK("Set to mdma mode[%u] \n", mdma_mode);
mask;

mask;

mask;

mask;
 382 373              span class="string">"Set to mdma mode[="driversL287" class="line" name=3L287"38377" class="l>PDC_CTCR1));
 288PDC_CTCR1));
);
 290 *      LOCK6"> 326
 293                         * 292" id="3292" class="line" name="3292">39242 *

 *ata_device *      LOCKINta/pata_pdc2027x.c#L329" id="L329" class="line"f%u] \ata/pata_pdc2027x.c#L2953 id="39> *      @ap: Port to configure -  *      @adev: re                         * 2="drivers class="sref">ctcr0,3/**s/atae" nssiblyeindrrrect" id="s pataby50" id="L350" 51" iddrrrectspan class="comment">                         * 2me="L2883/ata/pata_pdc2027x.c#L293" id=39st controller PATA UDMA timinname="L372"> 372                adev-> 248
"L249" class="line" name="L249"> 249static int pdc20027x_set_dmamode(struct  372                 290mdma_mode);
 301        <4pan c4ass="comment">class="line" name="L337"> 337static void pdpdc2027x.c#L376" i_prereset" class="sref">pdc!"Set to mdma mod4me="L302"4 302        if ((struct ata_port">ctcr0, "Set to mdma mod4m4="L302"4 ata/pata_pdc2027x.c#L294>,  rcref="+code=ata_rc+codpan class="string">"Set to mdma mod4m5="L302"4 ss="sref">ata_device 304                return;
 rcref="+code=ata_rc+cod268        struct 
pdc20"+code=pdc2027xr_failedref="+code=ata_r_failed    span class="string">"Set to mdma mod4m7"driver4/io_mode -  372                ctcr0,4" id=40377" class="line" namine" name="L279"> 279"Set to mdma mod4m9"driver4/ata/pata_pdc2027x.c#L294ister40dma_mode" class="sref">udma_mode);
PD4RINTK(dmamodelas_each_">ctcr0, c6"> 376            tcr0, pdc20"+code=pdc2027xENABLE;mdma_mode);
ctcr1 &= 0xff00000="L380" cL337f="drivers/ata/pata_pdc2027x.c#L294" id="L294" s="sref">iowrite32("Set to mdma mod4" class="4ref">adev,  281}
 3124       2) {
pio].pio]. *      LOCKI""""""""""""""""*name="L372"> 372                adev,  346
, static void xfer_shif<+cod26"L270"> 270         static void        mdma_mode);
mask;
 &= 0xff00000_mode;
 359                ctcr1 = , dev_mmio(ap, adev, XFER_UDMA_/ata/pata_pdc2027xa href="drivers/ata/pata_pdc20           25" class="sref">ap, ctcr0 &FER_UDMA_/ata/pata_pdc2);
 364                iowrite32(dev_mmio(ap, pio].adev, XFER_MW_DMA_0
mdma_mode);
PDP4INTK(42nt">                         */

iowrite32("Set to mdma mod4f="driver4/ata/pata_pdc2027x.c#L324" id=42 class="sref">value2<>PDC_CTCR1));
 360PDC_CTCR1));
42uot;Set udma regs... \n");
 326
 329 *      @ap: Port to configure
 3304span 4lass="comment"> *      @adev: re 350> *ocia/driL262" askfil" 51"f="dr_pdc2027x.c#L260" id="L260" class="line" name=4 ="driver4L331" class="line" name=4L331"4 331_pdc2027x.c#L260" id="L260" class="line" name=4 ref">PDP4 3324*      Set UDMA mode for devicre
 *
 334 *      LOCKIN_pdc2027x.c#L335" id="L335" class="line" name=4" class="443ass="comment"> *      @adev: reata_device/name="L372"> 372                 248
"L249" class="line" name="queued_cmdref="+code=ata_me="queued_cmds="sref">ata_portqcref="+code=ata_qc    s72"> 372                adev->mdma_mode);
ctcr0,4XFER"L249" class="line" nascsi_cmndref="+code=ata_scsi_cmnds="sref">ata_portcmdref="+code=ata_cmds="srdc2027x.c#L359" iqcref="+code=ata_qc    !"Set to mdma mod4f="driver4/ata/pata_pdc2027x.c#L344" id=44321" class="line" name="L321u8ref="+code=ata_u8s="sref">ata_portscsicmdref="+code=ata_scsicmd+codrdc2027x.c#L359" icmdref="+code=ata_cmds="s!"Set to mdma mod4fref">PDP4= XFline" name="L248"> rcref="+code=ata_rc+codrdc1;R_MW_DMA_2)) {
/name="L372"> 372                dma_mode4/a> <= 2) {
udma_mo4e =  *      @adev:eeeeeeeeerIf    PI /ataiscuseaivor"L2mmanasass="iL276"_pdc2027x.c#L335" id="L335" class="line" name=4fevice" c4ode == eeeeeeeeerfollowta_pwh="d list, say MODE_SENSE ane=REQUEST_SENSE,_pdc2027x.c#L335" id="L335" class="line" name=4f"drivers4"L348"> 348         4     4        /* 3494span class="comment">   4     4               * Turn off tHOLD. 372                XFER"L26ch"L346"> 346
mdma_mode);
 READ_1dev_mmio(mdma_mode);
PDP4L352"> 352         casee" name="L248"> WRITE_1dev_mmio(mdma_mode);
adev,  READ_1ef="drivers/ata/READ_1e21" :">mdma_mode);
adev,  WRITE_1ef="drivers/ata/WRITE_1e21" :">mdma_mode);
 READ_line" name="L343READ_l21" :">mdma_mode);
 WRITE_line" name="L343WRITE_l21" :">mdma_mode);
(45856" class="lcasee0xad:R_MW_DMA_2)) {
 372                 372                adev, MW_DMA_2)) {
ctcr1 &= 0xff00000rcref="+code=ata_rc+codrdcid="L360" class="line" name="L360"> 360udma_mode]. 360PDP4mode].mdma_mode);
udma4mode].value2 360adev,  355                }
PDPR4NTK(&46356" class="line" name="L279"> 279"Set to mdma mod4f="driver4/ata/pata_pdc2027x.c#L364" id=4L367" >PDC_CTCR1));
, udma_mode);
 326
 *      @adev: r_pd_e="L_counter - R="Lo0" ictr"L2unter 326
ref">PDP4/* Set the MDMA timing r4giste47      Set UDMA mode for devicers/ata/pata_pdc2027x.c#L301" id="L301" class="4">mdma_mo4e = dma_mode & 0x07;
 248_e="L_counterers/ata/pata_pdc20_e="L_counter4"L249" class="line" name="027xref="+code=ata_me="027x 3"sref">ata_port027xref="+code=ata_027x 3"ss72"> 372                PDP4INTK(4quot;Sf">mdma_mode);
adev,  */<__iomemref="+code=ata___iomem 3"sref">ata_porte32"_baseref="+code=ata_e32"_base+codrdc2027x.c#L359" i027xref="+code=ata_027x 3"s!;
"Set to mdma mod4f="driver4/ata/pata_pdc2027x.c#L374" id=4L377" class="lloa_p" name="L248"> counterers/ata/pata_pdcounter4"Set to mdma mod4f"drivers4       ctcline" name="L248"> retryref="+code=ata_retry+codrdc1;an class="string">"Set to mdma mod4ef">mdma_4ode].dma_mode;
"Set to mdma mod4ref">mdma4mode].value1 << 24);
 retryref="+code=ata_retry+cod:">mdma_mode);
adev, ctcr0 &= 0bccr2027x.c#L380" idbccr2ode=pdc2027x.c#L359" id="L359" class="line" name="L359"> 359         e32"_baseref="+code=ata_e32"_base+codr+0"+code=pdc2027x="srBYTE_COUNTsk;
 378PDPR4NTK(&48323" class="line" name="L323bccrh027x.c#L380" idbccrhode=pdc2027x.c#L359" id="L359" class="line" name="L359"> 359         e32"_baseref="+code=ata_e32"_base+codr+0"+code=pdc2027x="srBYTE_COUNTsk;
 378 304                return;
, )) {
 359         e32"_baseref="+code=ata_e32"_base+codr+0"+code=pdc2027x="srBYTE_COUNTsk;
 378PDC_CTbccrh tcr0,  359         e32"_baseref="+code=ata_e32"_base+codr+0"+code=pdc2027x="srBYTE_COUNTsk;
 378 288udma_mode);
dmacounterers/ata/pata_pdcounter4 &= 0bccr2027x.c#L380" idbccr2ode=d="L378" class="line" name="L378"> 378 290value1 << 24);
 294 321
  &= 0bccr2027x.c#L380" idbccr2ode=span class="string">"Set to mdma mod4292" id="4292" class="line" name="4292">49ss="sref">ctcr0 &= 0"> 321
 , "Set to mdma mod42ef">PDPR4/ata/pata_pdc2027x.c#L294" id=49 class="sref">dma_mode & 0x07;
ata_device2) {
 *      @ap: Port to configgggggggg*pTne"30-bit dece="sta_pcounter 50" e="Ltby 2 piec"sspan class="comment">                         *4fta_pdc204pio_mode -  *      @adev:gggggggg*pIndrrrect" id=" may1                         *4f="driver4 class="sref">ctcr0,4gggggggg*pEx. When 7900 dece="s" 51"78FF, wroa_p id=" 7800 mightnamee="Lspan class="comment">                         *4f"drivers4/ata/pata_pdc2027x.c#L294" id=49st controller PATA UDMA timigggggggg*ers/ata/pata_pdc2027x.c#L301" id="L301" class="5" class="5ref">adev-> 270  bccrh tcr0, , mdma_mode);
 290ctcr1 &= 0xff00000retryref="+code=ata_retry+cod--pan class="string">"Set to mdma mod5ine" name5"L301"> 301        <5pan c50381" class="line" name="L381"> 381 321
        if (                 go51"amp;= 0xff00000retryref="+code=ata_retry+cod        , PDC_CTCR1));
ata_device 304                return;
 counterers/ata/pata_pdcounter4"Set to mdma mod5m7"driver5/io_mode - PDC_CTCR1));
ctcr0,5" id=50uot;Set udma regs... \n");
 326
PD5RINTK( *      @ap: Port to configuradjust_pll - Adjusto0" iPLL input ame="Lin Hzspan class="comment">                         *5f="driver5/ata/pata_pdc2027x.c#L315" id=51ass="comment"> *      @adev: pan class="comment">                         *5fne" name5ref">adev,                          *5fe="L302"5       
pio].
pio]. *      LOCKI*ers/ata/pata_pdc2027x.c#L301" id="L301" class="5" class="5ref">adev,  */"L249" class="line" name="027xref="+code=ata_me="027x 3"sref">ata_port027xref="+code=ata_027x 3"s,"loa_p" name="L248"> 2ll_ame="ers/ata/pata_pdcll_ame=" 3"s," 133MHz */
 372                f">mdma_mode);
adev,  */<__iomemref="+code=ata___iomem 3"sref">ata_porte32"_baseref="+code=ata_e32"_base+codrdc2027x.c#L359" i027xref="+code=ata_027x 3"s!;
"Set to mdma mod5"9"driver5       ctclass="sref">dma_1line" name="L343u1uot;Se" name="L248"> 2ll_atlers/ata/pata_pdcll_atl4"Set to mdma mod5ass="sref5>pio]. 2ll_ame="_khzers/ata/pata_pdcll_ame="_khz+codrdc2027x.c#L359" i2ll_ame="ers/ata/pata_pdcll_ame=" 3"s / 1" id="L360" class="line" name="L360"> 360adev, XFERloa_p" name="L248"> 2out_requiredref="+code=ata_2out_required+codrdc2027x.c#L359" iboard_idxtcr0, ;
;
"Set to mdma mod5ane" name5/ata/pata_pdc2027x.c#L325" id=52381" class="lloa_p" name="L248"> ra258ref="+code=ata_ra258+codrdc2027x.c#L359" i2out_requiredref="+code=ata_2out_required+codr/p" name="L248"> 2ll_ame="_khzers/ata/pata_pdcll_ame="_khz+codpan class="string">"Set to mdma mod5ae="L302"5INTK(52ass="sref">XFline" name="L248"> Fers/ata/pata_pdF+codctcr0" class="sreask;
"Set to mdma mod5aode=pio"5/ata/pata_pdc2027x.c#L325" id=52 class="sref">dma_mode & 0x07;
, 2) {
 359         2ll_ame="_khzers/ata/pata_pdcll_ame="_khz+codrtimin5" iL ||cr0 &= 02ll_ame="_khzers/ata/pata_pdcll_ame="_khz+codrtg    #L37Ls (f">mdma_mode);
mask;

mask;

mask;

mask;
 38252377" class="line" namine" n        ctc>PDC_CTCR1));
 329 3305span 5lass="#ifdef0"+code=pdc2027x="srDEBUGsk;
 321
 PDP5 3325*            2) {
 334 *      LOCKIIIIIIIII* (maybe ale="Ly"drivers/adaby50" ifirm350")rs/ata/pata_pdc2027x.c#L301" id="L301" class="5" class="553316" class="line" name="L3162ll_atlers/ata/pata_pdcll_atl4 359         e32"_baseref="+code=ata_e32"_base+codr+0"+code=pdc2027x="srPLL_CTLsk;
ata_device);
ctclass="sref">dma"> 321
 adev->ctcr0,5value1 << 24);
PDP5=  <=  *      LOCKIIIIIIIII*ers/ata/pata_pdc2027x.c#L301" id="L301" class="5">udma_mo5e = 2) {
mask;
) {
 372                 ==  377;
 348         5     54ss="sref">ctc>s="sre not use UDMA 6 */2) {
   5     55C_CTCR1" class="sref">MW_DMA_2)) {
ctcr1 &= 0xff00000ask;
PDP5L352"> 3522) {
adev, value2;
adev, s="sre not use UDMA 6 */2) {
 360mdma_mode);
(55377" class="line" name2) {
ctcr0 &= 0x0000fffdas="sref">mask;

mask;

mask;
 382 up!RR adev, ctc>PDC_CTCR1));
udma_mode]. 281}
PDP5mode].ctcr0 &= 0Fers/ata/pata_pdF+cod c2027x.c#L379" id=ra258ref="+code=ata_ra258+codr*2027x.c#L379" id=ask;
].dma_mode & 0x07;
adev,  359         Fers/ata/pata_pdF+cod timin0 ||cr0 &= 0Fers/ata/pata_pdF+cod tgmin127s (f">mdma_mode);
) {
PDPR5NTK(&56ref">mask;

mask;

mask;

mask;
 382 , ctc>PDC_CTCR1));
);
 >= <5 href="+code=XFER_MW_DMA50" cl571s="sref">ctcr0 &= 0"> 321
  281}
ref">PDP5/* Set the MDMA timing r5giste57ss="sref">ctcr0 &= 02ll_atlers/ata/pata_pdcll_atl4;
 &= 0Fers/ata/pata_pdF+cod         = dma_mode & 0x07;
ctcr0 &= 0"> 321
 PDP5INTK(57 name="L355"> 355                }
adev,  359         2ll_atlers/ata/pata_pdcll_atl4;
PDC_CTd="L351line" name="L343d="L351l9"> 359         e32"_baseref="+code=ata_e32"_base+codr+0"+code=pdc2027x="srPLL_CTLsk;
udma_mode);
mdma_5ode].) {
mdma5mode].ctcr0 &= 0mdelayref="+code=ata_mdelay9"> 330          281}
adev, ;
PDPR5NTK(&584with value t>2) {
 *      LOCKIIIIIIIII*  Showo0" icurr="d ame="L id=" ofiPLL controapdc2027x.rs/ata/pata_pdc2027x.c#L301" id="L301" class="5[%u] 5n",  *      @ap: Port to configgggggggg*p(maybe drivers/adaby50" ifirm350")rs/ata/pata_pdc2027x.c#L301" id="L301" class="5ata_pdc2057x.c#L3827x.c#L22="com" 5lass=58ass="comment"> *      @adev:gggggggg*ers/ata/pata_pdc2027x.c#L301" id="L301" class="5r="driver5L287" class="line" name=5L287"58C_CTCR1" class="sref">PDC_CT2ll_atlers/ata/pata_pdcll_atl4 359         e32"_baseref="+code=ata_e32"_base+codr+0"+code=pdc2027x="srPLL_CTLsk;
 288udma_mode);
dma"> 321
  290 295 281}
59ss="sref">ctcine" n        PDPR5/ata/pata_pdc2027x.c#L295" id=59 clas>PDC_CTCR1));
ata_device 304                return;
 326
 *      @adev:* detect_pll_input_ame=" - Detecto0" iPLL input ame="Lin Hzspan class="comment">                         *5f="driver5 class="sref">ctcr0,5cr@027x: targetf   2027x 326
                         *6" class="6ref">adev->                         *6"1class="6rne" name="L290"> 290 *      @adev: ers/ata/pata_pdc2027x.c#L301" id="L301" class="6ine" name6"L301"> 301        <6pan c60381" class="loa_p" name="L248"> 248_detect_pll_input_ame="ers/ata/pata_pdc48_detect_pll_input_ame="/pata"L249" class="line" name="027xref="+code=ata_me="027x 3"sref">ata_port027xref="+code=ata_027x 3"ss72"> 372                        if ( f">mdma_mode);
,  */<__iomemref="+code=ata___iomem 3"sref">ata_porte32"_baseref="+code=ata_e32"_base+codrdc2027x.c#L359" i027xref="+code=ata_027x 3"s!;
"Set to mdma mod6m5="L302"6 ss="sref">ata_devicectcr0 &= 0_mode;
 clart_counters/ata/pata_pdslart_count4 - ctcr0,6" id=60377" class="lloa_p" name="L248"> 2ll_ame="ers/ata/pata_pdcll_ame=" 3"s,"r0 &= 0_sec_elapsedref="+code=ata__sec_elapsed+cod        udma_mode);
PD6RINTK() {
ctcr0 &= 0scrers/ata/pata_pdscr+codpdc2027x.c#L359" id="L359" class="line" name="L359"> 359         e32"_baseref="+code=ata_e32"_base+codr+0"+code=pdc2027x="srSYS_CTLsk;
adev,  321
 ctcr0 &= 0d=ta_pd9" class="line" namta_pd9"9"> 359         scrers/ata/pata_pdscr+codp| (.c#1pdma_timing4)"+code=DRV_NAME" e32"_baseref="+code=ata_e32"_base+codr+0"+code=pdc2027x="srSYS_CTLsk;
pio]. 359         e32"_baseref="+code=ata_e32"_base+codr+0"+code=pdc2027x="srSYS_CTLsk;
pio]. 304                return;
adev, )) {
f">ata_port027xref="+code=ata_027x 3"ss        adev, PDC_CTdo_gettimeofdayref="+code=ata_do_gettimeofday4ref="s/ata/pata_pdc2slart_timeers/ata/pata_pdslart_time4udma_mode);
) {
adev, ctcr0 &= 0mdelayref="+code=ata_mdelay9"> 3100          281}
(62ass="sref">XF_MW_DMA_2)) {
f">ata_port027xref="+code=ata_027x 3"ss        ctcr0 &= 0do_gettimeofdayref="+code=ata_do_gettimeofday4ref="s/ata/pata_pdc2end_timeers/ata/pata_pdend_time+cods         355                }
maskl2) {
62C_CTCR1" class="sref">PDC_CTscrers/ata/pata_pdscr+codpdc2027x.c#L359" id="L359" class="line" name="L359"> 359         e32"_baseref="+code=ata_e32"_base+codr+0"+code=pdc2027x="srSYS_CTLsk;
ctclass="sref">dma"> 321
  329dmad=ta_pd9" class="line" namta_pd9"9"> 359         scrers/ata/pata_pdscr+codpref=" ~(.c#1pdma_timing4)"+code=DRV_NAME" e32"_baseref="+code=ata_e32"_base+codr+0"+code=pdc2027x="srSYS_CTLsk;
 3306span 631s="sref">ctcr0 &= 0d="L359" class="line" name="L359"> 359         e32"_baseref="+code=ata_e32"_base+codr+0"+code=pdc2027x="srSYS_CTLsk;
 281}
PDP6 33263ass="sref">XF_MW_DMA_2)) {
 334ctccccccccc027x.c#L379" id=end_timeers/ata/pata_pdend_time+cod.class="line" natv_usecers/ata/pata_pdtv_usec+codp-rs/ata/pata_pdc2slart_timeers/ata/pata_pdslart_time4 355                }
63316" class="line" name="L3162ll_ame="ers/ata/pata_pdcll_ame=" 3"s dc0359         slart_counters/ata/pata_pdslart_count4 355                }
ata_device _sec_elapsedref="+code=ata__sec_elapsed+cod         udma_mode);
adev->dma"> 321
 ctcr0,6ctcr0 &= 0"> 321
 281}
PDP6= ctcine" n+code=DRV_NAME" 2ll_ame="ers/ata/pata_pdcll_ame=" 3"s         <=  304                return;
udma_mo6e =  326
 *      @adev:* c20_hard350"_initr-rInitializeriverhard350"span class="comment">                         *6fevice" c6ode == cr@027x: targetf   2027x 326
 348         6     64st controller PATA UDMA timi*p@board_idx: boardrivA tifix.rs/ata/pata_pdc2027x.c#L301" id="L301" class="6> 3496span class="comment">   6     65> *      @ap: Port to configuers/ata/pata_pdc2027x.c#L301" id="L301" class="6>class="l639;1', the hardware 6ill a65ss="sclass="line" name="L248"> c20_hard350"_initers/ata/pata_pdc20_hard350"_init/pata"L249" class="line" name="027xref="+code=ata_me="027x 3"sref">ata_port027xref="+code=ata_027x 3"s," 133MHz */
 372                mdma_mode);
PDP6L352"> 352 2ll_ame="ers/ata/pata_pdcll_ame=" 3"s        adev, dma_mode & 0x07;
adev, 2) {
                         *6T="driver6/ata/pata_pdc2027x.c#L356" id=65ass="comment"> *      @adev:gggggggg*pOn some system,twhere PCI busiis runnta_pat non-clandardrame="Lratespan class="comment">                         *6Tevice" c6INTK(6527gggggggg*pEx. 25MHz or 40MHz, werhav" 51"adjusto0" icycle_timespan class="comment">                         *6T"drivers6/ata/pata_pdc2027x.c#L356" id=65st controller PATA UDMA timigggggggg*pTne"_pdc2025 controa/pa employsiPLL circuito01"help drrrect"timta_pdc2027x.s settia_span class="comment">                         *6" class="6ref">adev, ctcr0 &= 02ll_ame="ers/ata/pata_pdcll_ame=" 3"s dc" name="L248"> c20_detect_pll_input_ame="ers/ata/pata_pdc48_detect_pll_input_ame="/pataf">ata_port027xref="+code=ata_027x 3"ss        udma_mode]. 281}
PDP6mode].ctcr0 &= 0dev_inforef="+code=ata_dev_info/pataf">ata_port027xref="+code=ata_027x 3"s!].dma_mode & 0x07;
adev, 2) {
 c20_adjust_pllers/ata/pata_pdc20_adjust_pll4f">ata_port027xref="+code=ata_027x 3"s,"code=DRV_NAME" 2ll_ame="ers/ata/pata_pdcll_ame=" 3"sctcr0" class="sreboard_idxtcr0, (&66ref">        360, PDC_CTCR1));
);
 >= <6 href="+code=XFER_MW_DMA60" cl67ass="comment"> *      @adev6"> 326

PDP6/* Set the MDMA timing r6giste67      Set UDMA mode for devicr@port:pata ioportso01"setup 326
 = 
 *      LOCKI*ers/ata/pata_pdc2027x.c#L301" id="L301" class="6sref">PDP6INTK(67uot;S> */ata_portporters/ata/pata_pdcort/pat,iclass="comment"> */<__iomemref="+code=ata___iomem 3"sref">ata_portbaseref="+code=ata_base+cods72"> 372                adev, f">mdma_mode);
PDC_CTporters/ata/pata_pdcort/pat!mdma_mode);
ctclass="sref">dmaporters/ata/pata_pdcort/pat! 360mdma_6ode].dmaporters/ata/pata_pdcort/pat!mdma_mode);
mdma6mode].ctcr0 &= 0porters/ata/pata_pdcort/pat!ctcdc2027x.c#L359" ibaseref="+code=ata_base+cod +x.c#5d="L360" class="line" name="L360"> 360ctcdc2027x.c#L359" ibaseref="+code=ata_base+cod +x.c#ad="L360" class="line" name="L360"> 360PDP6ref">adev, ctcr0 &= 02orters/ata/pata_pdcort/pat! 360(&68323" class="line" name="L3232orters/ata/pata_pdcort/pat! 360ctcr0 &= 02orters/ata/pata_pdcort/pat! 360PDP6n",  corters/ata/pata_pdcort/pat! 360mdma_mode);
PDC_CT2orters/ata/pata_pdcort/pat! 360 288ctclass="sref">dmaporters/ata/pata_pdcort/pat!dma2orters/ata/pata_pdcort/pat! 360 290PDC_CTCR1));
 296 281}
69      Set UDMA mode for dev6"> 326
PDPR6/ata/pata_pdc2027x.c#L296" id=69333
ata_device *      LOCKI* Calledtwhen mmeinclanc" ofiPCI adap7x.giseincertedspan class="comment">                         *6f%u] 6ata/pata_pdc2027x.c#L2956 id="69> *      @ap: Port to config*pTnisefunction"f="drstwhethx.giverhard350"gisesupcorted,pan class="comment">                         *6f class="6pio_mode -  *      @adev:* initializerhard350"gane=dc2027x.gmmeinclanc" ofime="027x topan class="comment">                         *6f="driver6 class="sref">ctcr0,6crlib   .  (implemmensl"L249" pci_t">   .probe() )rs/ata/pata_pdc2027x.c#L301" id="L301" class="6f"drivers6/ata/pata_pdc2027x.c#L296" id=69st controller PATA UDMA timi*rs/ata/pata_pdc2027x.c#L301" id="L301" class="7" class="7ref">adev-> 290 *      @adev:  @@ad:  matchta_p@adryLin iverid_tbl[]rs/ata/pata_pdc2027x.c#L301" id="L301" class="7"2class="7r/a>        if ( class="line" name="L248"> __teviniters/ata/pata_pd__tevinit+cod ="comment"> */ata_portptevers/ata/pata_pdcdev4ata_portenters/ata/pata_pdenx 3"ss72"> 372                , mdma_mode);
ata_devicectcclass="concll 133MHz *loa_p" name="L248"> cmd_offseters/ata/pata_pdcmd_offsets="s[]n=c{x.c17c0,x.c15c0 }d="L360" class="line" name="L360"> 360 bmdma_offseters/ata/pata_pdbmdma_offsets="s[]n=c{x.c1000,x.c1008 }d="L360" class="line" name="L360"> 360 - ,  360ctcr0,7" id=70377" class="lconcll"L249" class="line" name="Lort_inforef="+code=ata_me="Lort_info 3"sref">ata_portppiref="+code=ata_2pis="s[]n=="L360" class="line" name="L360"> 360ctcr0 &{ ref="s/ata/pata_pdc2c20c2027_Lort_inforef="+code=ata_c20c2027_Lort_infos="s[pan>
 360PD7RINTK(ata_port027xref="+code=ata_027x 3"sd="L360" class="line" name="L360"> 360ctcclass="comment"> */<__iomemref="+code=ata___iomem 3"sref">ata_porte32"_baseref="+code=ata_e32"_base+codd="L360" class="line" name="L360"> 360adev,  360pio].pio]. 304                return;
adev, )) {
adev,  372                ctcr0 &ine" n+-ine" name="L316ENOMEMref="+code=ata_ENOMEM+codd="L360" class="line" name="L360"> 360pio].adev, ctcrMW_DMA_2)) {
 ccim_en"L25_teviceref="+code=ata_2cim_en"L25_tevice/patas/ata/pata_pdc2c2evers/ata/pata_pdcdev4(72ass="sref">XF not use UDMA 6 */ 372                 360,  304                return;
 rcers/ata/pata_pdrc+cod dc" name="L248"> ccim_iome3_dc20oncref="+code=ata_2cim_iome3_dc20onc/patas/ata/pata_pdc2c2evers/ata/pata_pdcdev4;
mask not use UDMA 6 */ 372                72377" class="line" namine" n+cr0" class="srercers/ata/pata_pdrc+codd="L360" class="line" name="L360"> 360ctclass="sref">dma027xref="+code=ata_027x 3"s! ccim_iome3_t"L25ref="+code=ata_2cim_iome3_t"L25/patas/ata/pata_pdc2c2evers/ata/pata_pdcdev4 329 3307span 731s="sref">ctcr0 &= 0rcers/ata/pata_pdrc+cod dc" name="L248"> cciaset_dma_mas"ers/ata/pata_pdcciaset_dma_mas"/patas/ata/pata_pdc2c2evers/ata/pata_pdcdev4
mask not use UDMA 6 */ 372                PDP7 33273ass="sref">XFine" namine" n+cr0" class="srercers/ata/pata_pdrc+codd="L360" class="line" name="L360"> 360dma_mode & 0x07;
 334ctcr0 &= 0rcers/ata/pata_pdrc+cod dc" name="L248"> cciaset_conc027xnt_dma_mas"ers/ata/pata_pdcciaset_conc027xnt_dma_mas"/patas/ata/pata_pdc2c2evers/ata/pata_pdcdev4
mask not use UDMA 6 */ 372                73ref">mask;
 360ata_device 360ctclass="sref">dmae32"_baseref="+code=ata_e32"_base+codrdc2027x.c#L359" i027xref="+code=ata_027x 3"s!;
"Set to mdma mod7v" class=7sref">adev->ctcr0,7ctcvor"t use UDMA 6 */mdma_mode);
mask;
ata_porte32( 027xref="+code=ata_027x 3"s!"Set to mdma mod7vref">PDP7=  <= (ctcccccccccs/ata/pata_pdc2e32( e32"_baseref="+code=ata_e32"_base+codr+0"+code=pdc2027xbmdma_offseters/ata/pata_pdbmdma_offsets="s["+code=pdc2027xiref="+code=ata_i 3"s]pan class="string">"Set to mdma mod7v class="7e =  355                }
mask;
(;
  == (;
  348         7     74ss="sref">ctc>PDC_CTCR1));
   7     75quot;Set pio regs... \n");
class="l739;1', the hardware 7ill a751s="sref">ctcrMW_DMA_2)) {
 281}
ref">PDP7L352"> 352)) {
adev,  027xref="+code=ata_027x 3"sctcr0" class="sreboard_idxtcr0,  372                adev, ctcccccccccine" n+-ine" name="L316EIOref="+code=ata_EIO+codd="L360" class="line" name="L360"> 360>udma_mo7x.c#L355" id="L355" clas7="lin75 name="L355"> 355                }
(75377" class="line" n+2027x.c#L359" ime="027x_activateref="+code=ata_DPRI027x_activate/pata" name="L248"> 027xref="+code=ata_027x 3"sctcr0" class="srec2evers/ata/pata_pdcdev4ctcr0 &&&&&&&&&&&&&&&&&&cr0" class="sreIRQF_SHAREDref="+code=ata_IRQF_SHARED 3"sctref="s/ata/pata_pdc2c20c2027_shters/ata/pata_pdc20c2027_sht4adev,         7       his code7"sref">udma_mode].));
PDP7mode]. class="line" name="L248"> c20c2027_reinit_oneers/ata/pata_pdc20c2027_reinit_one/pata"L249" class="line" napci_tevers/ata/pata_pdcci_tev 3"sref">ata_portptevers/ata/pata_pdcdev4 372                ].mdma_mode);
adev, ctccl249" class="line" name="027xref="+code=ata_me="027x 3"sref">ata_port027xref="+code=ata_027x 3"s dc" name="L248"> dev_get_drvdef=ers/ata/pata_pddev_get_drvdef=/pataref="s/ata/pata_pdc2c2evers/ata/pata_pdcdev4udma_mo7/ata/pata_pdc2027x.c#L367" id=76uot;Set mdma  133MHz */
(&76ref">mask 
 360 360, ctclass="sref">dmarcers/ata/pata_pdrc+cod dc" name="L248"> me="Lci_tevice"do_resumeers/ata/pata_pdme="Lci_tevice"do_resume/patas/ata/pata_pdc2c2evers/ata/pata_pdcdev4 372                 >= <7 href="+code=XFER_MW_DMA70" cl771s="sref">ctcr0 &ine" n+cr0" class="srercers/ata/pata_pdrc+codd="L360" class="line" name="L360"> 360e" class7<=  281}
ref">PDP7/* Set the MDMA timing r7giste77ass="sref">XF not use UDMA 6 */ PCI_DEVICE_ID_PROMISE_a>}/ata/pata_pa hre4=CI_DEVICE_ID_PROMISE_a>}/a/pat ||lass="line" name="L281"> 281}
ode=pio"7e =  PCI_DEVICE_ID_PROMISE_a>}/ata/pata_pa hre4=CI_DEVICE_ID_PROMISE_a>}7e=dmas72"> 372                comment"7/ata/pata_pdc2027x.c#L377" id=775s="sref">ctcccccccccs/ata/pata_pdc2board_idxtcr0,  360>udma_mo7INTK(77uot;Set mdma else="L360" class="line" name="L360"> 360="driver7ref">adev, mask;
,  360evice" c7/ata/pata_pdc2027x.c#L377" id=77377" ="L360" class="line" name="L360"> 360ctc not use UDMA 6 */ 027xref="+code=ata_027x 3"sctcr0" class="sreboard_idxtcr0,  372                mdma_7ode]. &ine" n+-ine" name="L316EIOref="+code=ata_EIO+codd="L360" class="line" name="L360"> 360mdma7mode].));
 027xref="+code=ata_027x 3"ss        PDP7ref">adev, ctcine" n+id="L360" class="line" name="L360"> 360(&78 clas>PDC_CTCR1));
));
 355                }
 eodule_pci_t">   ref="+code=ata_eodule_pci_t">   /patas/ata/pata_pdc2c20c2027_Lci_t">   ref="+code=ata_c20c2027_Lci_t">    3"ss        


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