linux/sound/mips/hal2.h
<<
>>
Prefs
   1#ifndef __HAL2_H
   2#define __HAL2_H
   3
   4/*
   5 *  Driver for HAL2 sound processors
   6 *  Copyright (c) 1999 Ulf Carlsson <ulfc@bun.falkenberg.se>
   7 *  Copyright (c) 2001, 2002, 2003 Ladislav Michl <ladis@linux-mips.org>
   8 *
   9 *  This program is free software; you can redistribute it and/or modify
  10 *  it under the terms of the GNU General Public License version 2 as
  11 *  published by the Free Software Foundation.
  12 *
  13 *  This program is distributed in the hope that it will be useful,
  14 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 *  GNU General Public License for more details.
  17 *
  18 *  You should have received a copy of the GNU General Public License
  19 *  along with this program; if not, write to the Free Software
  20 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21 *
  22 */
  23
  24#include <linux/types.h>
  25
  26/* Indirect status register */
  27
  28#define H2_ISR_TSTATUS          0x01    /* RO: transaction status 1=busy */
  29#define H2_ISR_USTATUS          0x02    /* RO: utime status bit 1=armed */
  30#define H2_ISR_QUAD_MODE        0x04    /* codec mode 0=indigo 1=quad */
  31#define H2_ISR_GLOBAL_RESET_N   0x08    /* chip global reset 0=reset */
  32#define H2_ISR_CODEC_RESET_N    0x10    /* codec/synth reset 0=reset  */
  33
  34/* Revision register */
  35
  36#define H2_REV_AUDIO_PRESENT    0x8000  /* RO: audio present 0=present */
  37#define H2_REV_BOARD_M          0x7000  /* RO: bits 14:12, board revision */
  38#define H2_REV_MAJOR_CHIP_M     0x00F0  /* RO: bits 7:4, major chip revision */
  39#define H2_REV_MINOR_CHIP_M     0x000F  /* RO: bits 3:0, minor chip revision */
  40
  41/* Indirect address register */
  42
  43/*
  44 * Address of indirect internal register to be accessed. A write to this
  45 * register initiates read or write access to the indirect registers in the
  46 * HAL2. Note that there af four indirect data registers for write access to
  47 * registers larger than 16 byte.
  48 */
  49
  50#define H2_IAR_TYPE_M           0xF000  /* bits 15:12, type of functional */
  51                                        /* block the register resides in */
  52                                        /* 1=DMA Port */
  53                                        /* 9=Global DMA Control */
  54                                        /* 2=Bresenham */
  55                                        /* 3=Unix Timer */
  56#define H2_IAR_NUM_M            0x0F00  /* bits 11:8 instance of the */
  57                                        /* blockin which the indirect */
  58                                        /* register resides */
  59                                        /* If IAR_TYPE_M=DMA Port: */
  60                                        /* 1=Synth In */
  61                                        /* 2=AES In */
  62                                        /* 3=AES Out */
  63                                        /* 4=DAC Out */
  64                                        /* 5=ADC Out */
  65                                        /* 6=Synth Control */
  66                                        /* If IAR_TYPE_M=Global DMA Control: */
  67                                        /* 1=Control */
  68                                        /* If IAR_TYPE_M=Bresenham: */
  69                                        /* 1=Bresenham Clock Gen 1 */
  70                                        /* 2=Bresenham Clock Gen 2 */
  71                                        /* 3=Bresenham Clock Gen 3 */
  72                                        /* If IAR_TYPE_M=Unix Timer: */
  73                                        /* 1=Unix Timer */
  74#define H2_IAR_ACCESS_SELECT    0x0080  /* 1=read 0=write */
  75#define H2_IAR_PARAM            0x000C  /* Parameter Select */
  76#define H2_IAR_RB_INDEX_M       0x0003  /* Read Back Index */
  77                                        /* 00:word0 */
  78                                        /* 01:word1 */
  79                                        /* 10:word2 */
  80                                        /* 11:word3 */
  81/*
  82 * HAL2 internal addressing
  83 *
  84 * The HAL2 has "indirect registers" (idr) which are accessed by writing to the
  85 * Indirect Data registers. Write the address to the Indirect Address register
  86 * to transfer the data.
  87 *
  88 * We define the H2IR_* to the read address and H2IW_* to the write address and
  89 * H2I_* to be fields in whatever register is referred to.
  90 *
  91 * When we write to indirect registers which are larger than one word (16 bit)
  92 * we have to fill more than one indirect register before writing. When we read
  93 * back however we have to read several times, each time with different Read
  94 * Back Indexes (there are defs for doing this easily).
  95 */
  96
  97/*
  98 * Relay Control
  99 */
 100#define H2I_RELAY_C             0x9100
 101#define H2I_RELAY_C_STATE       0x01            /* state of RELAY pin signal */
 102
 103/* DMA port enable */
 104
 105#define H2I_DMA_PORT_EN         0x9104
 106#define H2I_DMA_PORT_EN_SY_IN   0x01            /* Synth_in DMA port */
 107#define H2I_DMA_PORT_EN_AESRX   0x02            /* AES receiver DMA port */
 108#define H2I_DMA_PORT_EN_AESTX   0x04            /* AES transmitter DMA port */
 109#define H2I_DMA_PORT_EN_CODECTX 0x08            /* CODEC transmit DMA port */
 110#define H2I_DMA_PORT_EN_CODECR  0x10            /* CODEC receive DMA port */
 111
 112#define H2I_DMA_END             0x9108          /* global dma endian select */
 113#define H2I_DMA_END_SY_IN       0x01            /* Synth_in DMA port */
 114#define H2I_DMA_END_AESRX       0x02            /* AES receiver DMA port */
 115#define H2I_DMA_END_AESTX       0x04            /* AES transmitter DMA port */
 116#define H2I_DMA_END_CODECTX     0x08            /* CODEC transmit DMA port */
 117#define H2I_DMA_END_CODECR      0x10            /* CODEC receive DMA port */
 118                                                /* 0=b_end 1=l_end */
 119
 120#define H2I_DMA_DRV             0x910C          /* global PBUS DMA enable */
 121
 122#define H2I_SYNTH_C             0x1104          /* Synth DMA control */
 123
 124#define H2I_AESRX_C             0x1204          /* AES RX dma control */
 125
 126#define H2I_C_TS_EN             0x20            /* Timestamp enable */
 127#define H2I_C_TS_FRMT           0x40            /* Timestamp format */
 128#define H2I_C_NAUDIO            0x80            /* Sign extend */
 129
 130/* AESRX CTL, 16 bit */
 131
 132#define H2I_AESTX_C             0x1304          /* AES TX DMA control */
 133#define H2I_AESTX_C_CLKID_SHIFT 3               /* Bresenham Clock Gen 1-3 */
 134#define H2I_AESTX_C_CLKID_M     0x18
 135#define H2I_AESTX_C_DATAT_SHIFT 8               /* 1=mono 2=stereo (3=quad) */
 136#define H2I_AESTX_C_DATAT_M     0x300
 137
 138/* CODEC registers */
 139
 140#define H2I_DAC_C1              0x1404          /* DAC DMA control, 16 bit */
 141#define H2I_DAC_C2              0x1408          /* DAC DMA control, 32 bit */
 142#define H2I_ADC_C1              0x1504          /* ADC DMA control, 16 bit */
 143#define H2I_ADC_C2              0x1508          /* ADC DMA control, 32 bit */
 144
 145/* Bits in CTL1 register */
 146
 147#define H2I_C1_DMA_SHIFT        0               /* DMA channel */
 148#define H2I_C1_DMA_M            0x7
 149#define H2I_C1_CLKID_SHIFT      3               /* Bresenham Clock Gen 1-3 */
 150#define H2I_C1_CLKID_M          0x18
 151#define H2I_C1_DATAT_SHIFT      8               /* 1=mono 2=stereo (3=quad) */
 152#define H2I_C1_DATAT_M          0x300
 153
 154/* Bits in CTL2 register */
 155
 156#define H2I_C2_R_GAIN_SHIFT     0               /* right a/d input gain */
 157#define H2I_C2_R_GAIN_M         0xf
 158#define H2I_C2_L_GAIN_SHIFT     4               /* left a/d input gain */
 159#define H2I_C2_L_GAIN_M         0xf0
 160#define H2I_C2_R_SEL            0x100           /* right input select */
 161#define H2I_C2_L_SEL            0x200           /* left input select */
 162#define H2I_C2_MUTE             0x400           /* mute */
 163#define H2I_C2_DO1              0x00010000      /* digital output port bit 0 */
 164#define H2I_C2_DO2              0x00020000      /* digital output port bit 1 */
 165#define H2I_C2_R_ATT_SHIFT      18              /* right d/a output - */
 166#define H2I_C2_R_ATT_M          0x007c0000      /* attenuation */
 167#define H2I_C2_L_ATT_SHIFT      23              /* left d/a output - */
 168#define H2I_C2_L_ATT_M          0x0f800000      /* attenuation */
 169
 170#define H2I_SYNTH_MAP_C         0x1104          /* synth dma handshake ctrl */
 171
 172/* Clock generator CTL 1, 16 bit */
 173
 174#define H2I_BRES1_C1            0x2104
 175#define H2I_BRES2_C1            0x2204
 176#define H2I_BRES3_C1            0x2304
 177
 178#define H2I_BRES_C1_SHIFT       0               /* 0=48.0 1=44.1 2=aes_rx */
 179#define H2I_BRES_C1_M           0x03
 180
 181/* Clock generator CTL 2, 32 bit */
 182
 183#define H2I_BRES1_C2            0x2108
 184#define H2I_BRES2_C2            0x2208
 185#define H2I_BRES3_C2            0x2308
 186
 187#define H2I_BRES_C2_INC_SHIFT   0               /* increment value */
 188#define H2I_BRES_C2_INC_M       0xffff
 189#define H2I_BRES_C2_MOD_SHIFT   16              /* modcontrol value */
 190#define H2I_BRES_C2_MOD_M       0xffff0000      /* modctrl=0xffff&(modinc-1) */
 191
 192/* Unix timer, 64 bit */
 193
 194#define H2I_UTIME               0x3104
 195#define H2I_UTIME_0_LD          0xffff          /* microseconds, LSB's */
 196#define H2I_UTIME_1_LD0         0x0f            /* microseconds, MSB's */
 197#define H2I_UTIME_1_LD1         0xf0            /* tenths of microseconds */
 198#define H2I_UTIME_2_LD          0xffff          /* seconds, LSB's */
 199#define H2I_UTIME_3_LD          0xffff          /* seconds, MSB's */
 200
 201struct hal2_ctl_regs {
 202        u32 _unused0[4];
 203        u32 isr;                /* 0x10 Status Register */
 204        u32 _unused1[3];
 205        u32 rev;                /* 0x20 Revision Register */
 206        u32 _unused2[3];
 207        u32 iar;                /* 0x30 Indirect Address Register */
 208        u32 _unused3[3];
 209        u32 idr0;               /* 0x40 Indirect Data Register 0 */
 210        u32 _unused4[3];
 211        u32 idr1;               /* 0x50 Indirect Data Register 1 */
 212        u32 _unused5[3];
 213        u32 idr2;               /* 0x60 Indirect Data Register 2 */
 214        u32 _unused6[3];
 215        u32 idr3;               /* 0x70 Indirect Data Register 3 */
 216};
 217
 218struct hal2_aes_regs {
 219        u32 rx_stat[2]; /* Status registers */
 220        u32 rx_cr[2];           /* Control registers */
 221        u32 rx_ud[4];           /* User data window */
 222        u32 rx_st[24];          /* Channel status data */
 223
 224        u32 tx_stat[1]; /* Status register */
 225        u32 tx_cr[3];           /* Control registers */
 226        u32 tx_ud[4];           /* User data window */
 227        u32 tx_st[24];          /* Channel status data */
 228};
 229
 230struct hal2_vol_regs {
 231        u32 right;              /* Right volume */
 232        u32 left;               /* Left volume */
 233};
 234
 235struct hal2_syn_regs {
 236        u32 _unused0[2];
 237        u32 page;               /* DOC Page register */
 238        u32 regsel;             /* DOC Register selection */
 239        u32 dlow;               /* DOC Data low */
 240        u32 dhigh;              /* DOC Data high */
 241        u32 irq;                /* IRQ Status */
 242        u32 dram;               /* DRAM Access */
 243};
 244
 245#endif  /* __HAL2_H */
 246
lxr.linux.no kindly hosted by Redpill Linpro AS, provider of Linux consulting and operations services since 1995.