linux/Documentation/pinctrl.txt
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   1PINCTRL (PIN CONTROL) subsystem
   2This document outlines the pin control subsystem in Linux
   3
   4This subsystem deals with:
   5
   6- Enumerating and naming controllable pins
   7
   8- Multiplexing of pins, pads, fingers (etc) see below for details
   9
  10- Configuration of pins, pads, fingers (etc), such as software-controlled
  11  biasing and driving mode specific pins, such as pull-up/down, open drain,
  12  load capacitance etc.
  13
  14Top-level interface
  15===================
  16
  17Definition of PIN CONTROLLER:
  18
  19- A pin controller is a piece of hardware, usually a set of registers, that
  20  can control PINs. It may be able to multiplex, bias, set load capacitance,
  21  set drive strength etc for individual pins or groups of pins.
  22
  23Definition of PIN:
  24
  25- PINS are equal to pads, fingers, balls or whatever packaging input or
  26  output line you want to control and these are denoted by unsigned integers
  27  in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
  28  there may be several such number spaces in a system. This pin space may
  29  be sparse - i.e. there may be gaps in the space with numbers where no
  30  pin exists.
  31
  32When a PIN CONTROLLER is instantiated, it will register a descriptor to the
  33pin control framework, and this descriptor contains an array of pin descriptors
  34describing the pins handled by this specific pin controller.
  35
  36Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
  37
  38        A   B   C   D   E   F   G   H
  39
  40   8    o   o   o   o   o   o   o   o
  41
  42   7    o   o   o   o   o   o   o   o
  43
  44   6    o   o   o   o   o   o   o   o
  45
  46   5    o   o   o   o   o   o   o   o
  47
  48   4    o   o   o   o   o   o   o   o
  49
  50   3    o   o   o   o   o   o   o   o
  51
  52   2    o   o   o   o   o   o   o   o
  53
  54   1    o   o   o   o   o   o   o   o
  55
  56To register a pin controller and name all the pins on this package we can do
  57this in our driver:
  58
  59#include <linux/pinctrl/pinctrl.h>
  60
  61const struct pinctrl_pin_desc foo_pins[] = {
  62      PINCTRL_PIN(0, "A8"),
  63      PINCTRL_PIN(1, "B8"),
  64      PINCTRL_PIN(2, "C8"),
  65      ...
  66      PINCTRL_PIN(61, "F1"),
  67      PINCTRL_PIN(62, "G1"),
  68      PINCTRL_PIN(63, "H1"),
  69};
  70
  71static struct pinctrl_desc foo_desc = {
  72        .name = "foo",
  73        .pins = foo_pins,
  74        .npins = ARRAY_SIZE(foo_pins),
  75        .maxpin = 63,
  76        .owner = THIS_MODULE,
  77};
  78
  79int __init foo_probe(void)
  80{
  81        struct pinctrl_dev *pctl;
  82
  83        pctl = pinctrl_register(&foo_desc, <PARENT>, NULL);
  84        if (IS_ERR(pctl))
  85                pr_err("could not register foo pin driver\n");
  86}
  87
  88To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and
  89selected drivers, you need to select them from your machine's Kconfig entry,
  90since these are so tightly integrated with the machines they are used on.
  91See for example arch/arm/mach-u300/Kconfig for an example.
  92
  93Pins usually have fancier names than this. You can find these in the dataheet
  94for your chip. Notice that the core pinctrl.h file provides a fancy macro
  95called PINCTRL_PIN() to create the struct entries. As you can see I enumerated
  96the pins from 0 in the upper left corner to 63 in the lower right corner.
  97This enumeration was arbitrarily chosen, in practice you need to think
  98through your numbering system so that it matches the layout of registers
  99and such things in your driver, or the code may become complicated. You must
 100also consider matching of offsets to the GPIO ranges that may be handled by
 101the pin controller.
 102
 103For a padring with 467 pads, as opposed to actual pins, I used an enumeration
 104like this, walking around the edge of the chip, which seems to be industry
 105standard too (all these pads had names, too):
 106
 107
 108     0 ..... 104
 109   466        105
 110     .        .
 111     .        .
 112   358        224
 113    357 .... 225
 114
 115
 116Pin groups
 117==========
 118
 119Many controllers need to deal with groups of pins, so the pin controller
 120subsystem has a mechanism for enumerating groups of pins and retrieving the
 121actual enumerated pins that are part of a certain group.
 122
 123For example, say that we have a group of pins dealing with an SPI interface
 124on { 0, 8, 16, 24 }, and a group of pins dealing with an I2C interface on pins
 125on { 24, 25 }.
 126
 127These two groups are presented to the pin control subsystem by implementing
 128some generic pinctrl_ops like this:
 129
 130#include <linux/pinctrl/pinctrl.h>
 131
 132struct foo_group {
 133        const char *name;
 134        const unsigned int *pins;
 135        const unsigned num_pins;
 136};
 137
 138static const unsigned int spi0_pins[] = { 0, 8, 16, 24 };
 139static const unsigned int i2c0_pins[] = { 24, 25 };
 140
 141static const struct foo_group foo_groups[] = {
 142        {
 143                .name = "spi0_grp",
 144                .pins = spi0_pins,
 145                .num_pins = ARRAY_SIZE(spi0_pins),
 146        },
 147        {
 148                .name = "i2c0_grp",
 149                .pins = i2c0_pins,
 150                .num_pins = ARRAY_SIZE(i2c0_pins),
 151        },
 152};
 153
 154
 155static int foo_get_groups_count(struct pinctrl_dev *pctldev)
 156{
 157        return ARRAY_SIZE(foo_groups);
 158}
 159
 160static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
 161                                       unsigned selector)
 162{
 163        return foo_groups[selector].name;
 164}
 165
 166static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
 167                               unsigned ** const pins,
 168                               unsigned * const num_pins)
 169{
 170        *pins = (unsigned *) foo_groups[selector].pins;
 171        *num_pins = foo_groups[selector].num_pins;
 172        return 0;
 173}
 174
 175static struct pinctrl_ops foo_pctrl_ops = {
 176        .get_groups_count = foo_get_groups_count,
 177        .get_group_name = foo_get_group_name,
 178        .get_group_pins = foo_get_group_pins,
 179};
 180
 181
 182static struct pinctrl_desc foo_desc = {
 183       ...
 184       .pctlops = &foo_pctrl_ops,
 185};
 186
 187The pin control subsystem will call the .get_groups_count() function to
 188determine total number of legal selectors, then it will call the other functions
 189to retrieve the name and pins of the group. Maintaining the data structure of
 190the groups is up to the driver, this is just a simple example - in practice you
 191may need more entries in your group structure, for example specific register
 192ranges associated with each group and so on.
 193
 194
 195Pin configuration
 196=================
 197
 198Pins can sometimes be software-configured in an various ways, mostly related
 199to their electronic properties when used as inputs or outputs. For example you
 200may be able to make an output pin high impedance, or "tristate" meaning it is
 201effectively disconnected. You may be able to connect an input pin to VDD or GND
 202using a certain resistor value - pull up and pull down - so that the pin has a
 203stable value when nothing is driving the rail it is connected to, or when it's
 204unconnected.
 205
 206Pin configuration can be programmed either using the explicit APIs described
 207immediately below, or by adding configuration entries into the mapping table;
 208see section "Board/machine configuration" below.
 209
 210For example, a platform may do the following to pull up a pin to VDD:
 211
 212#include <linux/pinctrl/consumer.h>
 213
 214ret = pin_config_set("foo-dev", "FOO_GPIO_PIN", PLATFORM_X_PULL_UP);
 215
 216The format and meaning of the configuration parameter, PLATFORM_X_PULL_UP
 217above, is entirely defined by the pin controller driver.
 218
 219The pin configuration driver implements callbacks for changing pin
 220configuration in the pin controller ops like this:
 221
 222#include <linux/pinctrl/pinctrl.h>
 223#include <linux/pinctrl/pinconf.h>
 224#include "platform_x_pindefs.h"
 225
 226static int foo_pin_config_get(struct pinctrl_dev *pctldev,
 227                    unsigned offset,
 228                    unsigned long *config)
 229{
 230        struct my_conftype conf;
 231
 232        ... Find setting for pin @ offset ...
 233
 234        *config = (unsigned long) conf;
 235}
 236
 237static int foo_pin_config_set(struct pinctrl_dev *pctldev,
 238                    unsigned offset,
 239                    unsigned long config)
 240{
 241        struct my_conftype *conf = (struct my_conftype *) config;
 242
 243        switch (conf) {
 244                case PLATFORM_X_PULL_UP:
 245                ...
 246                }
 247        }
 248}
 249
 250static int foo_pin_config_group_get (struct pinctrl_dev *pctldev,
 251                    unsigned selector,
 252                    unsigned long *config)
 253{
 254        ...
 255}
 256
 257static int foo_pin_config_group_set (struct pinctrl_dev *pctldev,
 258                    unsigned selector,
 259                    unsigned long config)
 260{
 261        ...
 262}
 263
 264static struct pinconf_ops foo_pconf_ops = {
 265        .pin_config_get = foo_pin_config_get,
 266        .pin_config_set = foo_pin_config_set,
 267        .pin_config_group_get = foo_pin_config_group_get,
 268        .pin_config_group_set = foo_pin_config_group_set,
 269};
 270
 271/* Pin config operations are handled by some pin controller */
 272static struct pinctrl_desc foo_desc = {
 273        ...
 274        .confops = &foo_pconf_ops,
 275};
 276
 277Since some controllers have special logic for handling entire groups of pins
 278they can exploit the special whole-group pin control function. The
 279pin_config_group_set() callback is allowed to return the error code -EAGAIN,
 280for groups it does not want to handle, or if it just wants to do some
 281group-level handling and then fall through to iterate over all pins, in which
 282case each individual pin will be treated by separate pin_config_set() calls as
 283well.
 284
 285
 286Interaction with the GPIO subsystem
 287===================================
 288
 289The GPIO drivers may want to perform operations of various types on the same
 290physical pins that are also registered as pin controller pins.
 291
 292First and foremost, the two subsystems can be used as completely orthogonal,
 293see the section named "pin control requests from drivers" and
 294"drivers needing both pin control and GPIOs" below for details. But in some
 295situations a cross-subsystem mapping between pins and GPIOs is needed.
 296
 297Since the pin controller subsystem have its pinspace local to the pin
 298controller we need a mapping so that the pin control subsystem can figure out
 299which pin controller handles control of a certain GPIO pin. Since a single
 300pin controller may be muxing several GPIO ranges (typically SoCs that have
 301one set of pins but internally several GPIO silicon blocks, each modeled as
 302a struct gpio_chip) any number of GPIO ranges can be added to a pin controller
 303instance like this:
 304
 305struct gpio_chip chip_a;
 306struct gpio_chip chip_b;
 307
 308static struct pinctrl_gpio_range gpio_range_a = {
 309        .name = "chip a",
 310        .id = 0,
 311        .base = 32,
 312        .pin_base = 32,
 313        .npins = 16,
 314        .gc = &chip_a;
 315};
 316
 317static struct pinctrl_gpio_range gpio_range_b = {
 318        .name = "chip b",
 319        .id = 0,
 320        .base = 48,
 321        .pin_base = 64,
 322        .npins = 8,
 323        .gc = &chip_b;
 324};
 325
 326{
 327        struct pinctrl_dev *pctl;
 328        ...
 329        pinctrl_add_gpio_range(pctl, &gpio_range_a);
 330        pinctrl_add_gpio_range(pctl, &gpio_range_b);
 331}
 332
 333So this complex system has one pin controller handling two different
 334GPIO chips. "chip a" has 16 pins and "chip b" has 8 pins. The "chip a" and
 335"chip b" have different .pin_base, which means a start pin number of the
 336GPIO range.
 337
 338The GPIO range of "chip a" starts from the GPIO base of 32 and actual
 339pin range also starts from 32. However "chip b" has different starting
 340offset for the GPIO range and pin range. The GPIO range of "chip b" starts
 341from GPIO number 48, while the pin range of "chip b" starts from 64.
 342
 343We can convert a gpio number to actual pin number using this "pin_base".
 344They are mapped in the global GPIO pin space at:
 345
 346chip a:
 347 - GPIO range : [32 .. 47]
 348 - pin range  : [32 .. 47]
 349chip b:
 350 - GPIO range : [48 .. 55]
 351 - pin range  : [64 .. 71]
 352
 353When GPIO-specific functions in the pin control subsystem are called, these
 354ranges will be used to look up the appropriate pin controller by inspecting
 355and matching the pin to the pin ranges across all controllers. When a
 356pin controller handling the matching range is found, GPIO-specific functions
 357will be called on that specific pin controller.
 358
 359For all functionalities dealing with pin biasing, pin muxing etc, the pin
 360controller subsystem will subtract the range's .base offset from the passed
 361in gpio number, and add the ranges's .pin_base offset to retrive a pin number.
 362After that, the subsystem passes it on to the pin control driver, so the driver
 363will get an pin number into its handled number range. Further it is also passed
 364the range ID value, so that the pin controller knows which range it should
 365deal with.
 366
 367
 368PINMUX interfaces
 369=================
 370
 371These calls use the pinmux_* naming prefix.  No other calls should use that
 372prefix.
 373
 374
 375What is pinmuxing?
 376==================
 377
 378PINMUX, also known as padmux, ballmux, alternate functions or mission modes
 379is a way for chip vendors producing some kind of electrical packages to use
 380a certain physical pin (ball, pad, finger, etc) for multiple mutually exclusive
 381functions, depending on the application. By "application" in this context
 382we usually mean a way of soldering or wiring the package into an electronic
 383system, even though the framework makes it possible to also change the function
 384at runtime.
 385
 386Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
 387
 388        A   B   C   D   E   F   G   H
 389      +---+
 390   8  | o | o   o   o   o   o   o   o
 391      |   |
 392   7  | o | o   o   o   o   o   o   o
 393      |   |
 394   6  | o | o   o   o   o   o   o   o
 395      +---+---+
 396   5  | o | o | o   o   o   o   o   o
 397      +---+---+               +---+
 398   4    o   o   o   o   o   o | o | o
 399                              |   |
 400   3    o   o   o   o   o   o | o | o
 401                              |   |
 402   2    o   o   o   o   o   o | o | o
 403      +-------+-------+-------+---+---+
 404   1  | o   o | o   o | o   o | o | o |
 405      +-------+-------+-------+---+---+
 406
 407This is not tetris. The game to think of is chess. Not all PGA/BGA packages
 408are chessboard-like, big ones have "holes" in some arrangement according to
 409different design patterns, but we're using this as a simple example. Of the
 410pins you see some will be taken by things like a few VCC and GND to feed power
 411to the chip, and quite a few will be taken by large ports like an external
 412memory interface. The remaining pins will often be subject to pin multiplexing.
 413
 414The example 8x8 PGA package above will have pin numbers 0 thru 63 assigned to
 415its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using
 416pinctrl_register_pins() and a suitable data set as shown earlier.
 417
 418In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port
 419(these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as
 420some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can
 421be used as an I2C port (these are just two pins: SCL, SDA). Needless to say,
 422we cannot use the SPI port and I2C port at the same time. However in the inside
 423of the package the silicon performing the SPI logic can alternatively be routed
 424out on pins { G4, G3, G2, G1 }.
 425
 426On the botton row at { A1, B1, C1, D1, E1, F1, G1, H1 } we have something
 427special - it's an external MMC bus that can be 2, 4 or 8 bits wide, and it will
 428consume 2, 4 or 8 pins respectively, so either { A1, B1 } are taken or
 429{ A1, B1, C1, D1 } or all of them. If we use all 8 bits, we cannot use the SPI
 430port on pins { G4, G3, G2, G1 } of course.
 431
 432This way the silicon blocks present inside the chip can be multiplexed "muxed"
 433out on different pin ranges. Often contemporary SoC (systems on chip) will
 434contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to
 435different pins by pinmux settings.
 436
 437Since general-purpose I/O pins (GPIO) are typically always in shortage, it is
 438common to be able to use almost any pin as a GPIO pin if it is not currently
 439in use by some other I/O port.
 440
 441
 442Pinmux conventions
 443==================
 444
 445The purpose of the pinmux functionality in the pin controller subsystem is to
 446abstract and provide pinmux settings to the devices you choose to instantiate
 447in your machine configuration. It is inspired by the clk, GPIO and regulator
 448subsystems, so devices will request their mux setting, but it's also possible
 449to request a single pin for e.g. GPIO.
 450
 451Definitions:
 452
 453- FUNCTIONS can be switched in and out by a driver residing with the pin
 454  control subsystem in the drivers/pinctrl/* directory of the kernel. The
 455  pin control driver knows the possible functions. In the example above you can
 456  identify three pinmux functions, one for spi, one for i2c and one for mmc.
 457
 458- FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array.
 459  In this case the array could be something like: { spi0, i2c0, mmc0 }
 460  for the three available functions.
 461
 462- FUNCTIONS have PIN GROUPS as defined on the generic level - so a certain
 463  function is *always* associated with a certain set of pin groups, could
 464  be just a single one, but could also be many. In the example above the
 465  function i2c is associated with the pins { A5, B5 }, enumerated as
 466  { 24, 25 } in the controller pin space.
 467
 468  The Function spi is associated with pin groups { A8, A7, A6, A5 }
 469  and { G4, G3, G2, G1 }, which are enumerated as { 0, 8, 16, 24 } and
 470  { 38, 46, 54, 62 } respectively.
 471
 472  Group names must be unique per pin controller, no two groups on the same
 473  controller may have the same name.
 474
 475- The combination of a FUNCTION and a PIN GROUP determine a certain function
 476  for a certain set of pins. The knowledge of the functions and pin groups
 477  and their machine-specific particulars are kept inside the pinmux driver,
 478  from the outside only the enumerators are known, and the driver core can:
 479
 480  - Request the name of a function with a certain selector (>= 0)
 481  - A list of groups associated with a certain function
 482  - Request that a certain group in that list to be activated for a certain
 483    function
 484
 485  As already described above, pin groups are in turn self-descriptive, so
 486  the core will retrieve the actual pin range in a certain group from the
 487  driver.
 488
 489- FUNCTIONS and GROUPS on a certain PIN CONTROLLER are MAPPED to a certain
 490  device by the board file, device tree or similar machine setup configuration
 491  mechanism, similar to how regulators are connected to devices, usually by
 492  name. Defining a pin controller, function and group thus uniquely identify
 493  the set of pins to be used by a certain device. (If only one possible group
 494  of pins is available for the function, no group name need to be supplied -
 495  the core will simply select the first and only group available.)
 496
 497  In the example case we can define that this particular machine shall
 498  use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function
 499  fi2c0 group gi2c0, on the primary pin controller, we get mappings
 500  like these:
 501
 502  {
 503    {"map-spi0", spi0, pinctrl0, fspi0, gspi0},
 504    {"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0}
 505  }
 506
 507  Every map must be assigned a state name, pin controller, device and
 508  function. The group is not compulsory - if it is omitted the first group
 509  presented by the driver as applicable for the function will be selected,
 510  which is useful for simple cases.
 511
 512  It is possible to map several groups to the same combination of device,
 513  pin controller and function. This is for cases where a certain function on
 514  a certain pin controller may use different sets of pins in different
 515  configurations.
 516
 517- PINS for a certain FUNCTION using a certain PIN GROUP on a certain
 518  PIN CONTROLLER are provided on a first-come first-serve basis, so if some
 519  other device mux setting or GPIO pin request has already taken your physical
 520  pin, you will be denied the use of it. To get (activate) a new setting, the
 521  old one has to be put (deactivated) first.
 522
 523Sometimes the documentation and hardware registers will be oriented around
 524pads (or "fingers") rather than pins - these are the soldering surfaces on the
 525silicon inside the package, and may or may not match the actual number of
 526pins/balls underneath the capsule. Pick some enumeration that makes sense to
 527you. Define enumerators only for the pins you can control if that makes sense.
 528
 529Assumptions:
 530
 531We assume that the number of possible function maps to pin groups is limited by
 532the hardware. I.e. we assume that there is no system where any function can be
 533mapped to any pin, like in a phone exchange. So the available pins groups for
 534a certain function will be limited to a few choices (say up to eight or so),
 535not hundreds or any amount of choices. This is the characteristic we have found
 536by inspecting available pinmux hardware, and a necessary assumption since we
 537expect pinmux drivers to present *all* possible function vs pin group mappings
 538to the subsystem.
 539
 540
 541Pinmux drivers
 542==============
 543
 544The pinmux core takes care of preventing conflicts on pins and calling
 545the pin controller driver to execute different settings.
 546
 547It is the responsibility of the pinmux driver to impose further restrictions
 548(say for example infer electronic limitations due to load etc) to determine
 549whether or not the requested function can actually be allowed, and in case it
 550is possible to perform the requested mux setting, poke the hardware so that
 551this happens.
 552
 553Pinmux drivers are required to supply a few callback functions, some are
 554optional. Usually the enable() and disable() functions are implemented,
 555writing values into some certain registers to activate a certain mux setting
 556for a certain pin.
 557
 558A simple driver for the above example will work by setting bits 0, 1, 2, 3 or 4
 559into some register named MUX to select a certain function with a certain
 560group of pins would work something like this:
 561
 562#include <linux/pinctrl/pinctrl.h>
 563#include <linux/pinctrl/pinmux.h>
 564
 565struct foo_group {
 566        const char *name;
 567        const unsigned int *pins;
 568        const unsigned num_pins;
 569};
 570
 571static const unsigned spi0_0_pins[] = { 0, 8, 16, 24 };
 572static const unsigned spi0_1_pins[] = { 38, 46, 54, 62 };
 573static const unsigned i2c0_pins[] = { 24, 25 };
 574static const unsigned mmc0_1_pins[] = { 56, 57 };
 575static const unsigned mmc0_2_pins[] = { 58, 59 };
 576static const unsigned mmc0_3_pins[] = { 60, 61, 62, 63 };
 577
 578static const struct foo_group foo_groups[] = {
 579        {
 580                .name = "spi0_0_grp",
 581                .pins = spi0_0_pins,
 582                .num_pins = ARRAY_SIZE(spi0_0_pins),
 583        },
 584        {
 585                .name = "spi0_1_grp",
 586                .pins = spi0_1_pins,
 587                .num_pins = ARRAY_SIZE(spi0_1_pins),
 588        },
 589        {
 590                .name = "i2c0_grp",
 591                .pins = i2c0_pins,
 592                .num_pins = ARRAY_SIZE(i2c0_pins),
 593        },
 594        {
 595                .name = "mmc0_1_grp",
 596                .pins = mmc0_1_pins,
 597                .num_pins = ARRAY_SIZE(mmc0_1_pins),
 598        },
 599        {
 600                .name = "mmc0_2_grp",
 601                .pins = mmc0_2_pins,
 602                .num_pins = ARRAY_SIZE(mmc0_2_pins),
 603        },
 604        {
 605                .name = "mmc0_3_grp",
 606                .pins = mmc0_3_pins,
 607                .num_pins = ARRAY_SIZE(mmc0_3_pins),
 608        },
 609};
 610
 611
 612static int foo_get_groups_count(struct pinctrl_dev *pctldev)
 613{
 614        return ARRAY_SIZE(foo_groups);
 615}
 616
 617static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
 618                                       unsigned selector)
 619{
 620        return foo_groups[selector].name;
 621}
 622
 623static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
 624                               unsigned ** const pins,
 625                               unsigned * const num_pins)
 626{
 627        *pins = (unsigned *) foo_groups[selector].pins;
 628        *num_pins = foo_groups[selector].num_pins;
 629        return 0;
 630}
 631
 632static struct pinctrl_ops foo_pctrl_ops = {
 633        .get_groups_count = foo_get_groups_count,
 634        .get_group_name = foo_get_group_name,
 635        .get_group_pins = foo_get_group_pins,
 636};
 637
 638struct foo_pmx_func {
 639        const char *name;
 640        const char * const *groups;
 641        const unsigned num_groups;
 642};
 643
 644static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
 645static const char * const i2c0_groups[] = { "i2c0_grp" };
 646static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp",
 647                                        "mmc0_3_grp" };
 648
 649static const struct foo_pmx_func foo_functions[] = {
 650        {
 651                .name = "spi0",
 652                .groups = spi0_groups,
 653                .num_groups = ARRAY_SIZE(spi0_groups),
 654        },
 655        {
 656                .name = "i2c0",
 657                .groups = i2c0_groups,
 658                .num_groups = ARRAY_SIZE(i2c0_groups),
 659        },
 660        {
 661                .name = "mmc0",
 662                .groups = mmc0_groups,
 663                .num_groups = ARRAY_SIZE(mmc0_groups),
 664        },
 665};
 666
 667int foo_get_functions_count(struct pinctrl_dev *pctldev)
 668{
 669        return ARRAY_SIZE(foo_functions);
 670}
 671
 672const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
 673{
 674        return foo_functions[selector].name;
 675}
 676
 677static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
 678                          const char * const **groups,
 679                          unsigned * const num_groups)
 680{
 681        *groups = foo_functions[selector].groups;
 682        *num_groups = foo_functions[selector].num_groups;
 683        return 0;
 684}
 685
 686int foo_enable(struct pinctrl_dev *pctldev, unsigned selector,
 687                unsigned group)
 688{
 689        u8 regbit = (1 << selector + group);
 690
 691        writeb((readb(MUX)|regbit), MUX)
 692        return 0;
 693}
 694
 695void foo_disable(struct pinctrl_dev *pctldev, unsigned selector,
 696                unsigned group)
 697{
 698        u8 regbit = (1 << selector + group);
 699
 700        writeb((readb(MUX) & ~(regbit)), MUX)
 701        return 0;
 702}
 703
 704struct pinmux_ops foo_pmxops = {
 705        .get_functions_count = foo_get_functions_count,
 706        .get_function_name = foo_get_fname,
 707        .get_function_groups = foo_get_groups,
 708        .enable = foo_enable,
 709        .disable = foo_disable,
 710};
 711
 712/* Pinmux operations are handled by some pin controller */
 713static struct pinctrl_desc foo_desc = {
 714        ...
 715        .pctlops = &foo_pctrl_ops,
 716        .pmxops = &foo_pmxops,
 717};
 718
 719In the example activating muxing 0 and 1 at the same time setting bits
 7200 and 1, uses one pin in common so they would collide.
 721
 722The beauty of the pinmux subsystem is that since it keeps track of all
 723pins and who is using them, it will already have denied an impossible
 724request like that, so the driver does not need to worry about such
 725things - when it gets a selector passed in, the pinmux subsystem makes
 726sure no other device or GPIO assignment is already using the selected
 727pins. Thus bits 0 and 1 in the control register will never be set at the
 728same time.
 729
 730All the above functions are mandatory to implement for a pinmux driver.
 731
 732
 733Pin control interaction with the GPIO subsystem
 734===============================================
 735
 736The public pinmux API contains two functions named pinctrl_request_gpio()
 737and pinctrl_free_gpio(). These two functions shall *ONLY* be called from
 738gpiolib-based drivers as part of their gpio_request() and
 739gpio_free() semantics. Likewise the pinctrl_gpio_direction_[input|output]
 740shall only be called from within respective gpio_direction_[input|output]
 741gpiolib implementation.
 742
 743NOTE that platforms and individual drivers shall *NOT* request GPIO pins to be
 744controlled e.g. muxed in. Instead, implement a proper gpiolib driver and have
 745that driver request proper muxing and other control for its pins.
 746
 747The function list could become long, especially if you can convert every
 748individual pin into a GPIO pin independent of any other pins, and then try
 749the approach to define every pin as a function.
 750
 751In this case, the function array would become 64 entries for each GPIO
 752setting and then the device functions.
 753
 754For this reason there are two functions a pin control driver can implement
 755to enable only GPIO on an individual pin: .gpio_request_enable() and
 756.gpio_disable_free().
 757
 758This function will pass in the affected GPIO range identified by the pin
 759controller core, so you know which GPIO pins are being affected by the request
 760operation.
 761
 762If your driver needs to have an indication from the framework of whether the
 763GPIO pin shall be used for input or output you can implement the
 764.gpio_set_direction() function. As described this shall be called from the
 765gpiolib driver and the affected GPIO range, pin offset and desired direction
 766will be passed along to this function.
 767
 768Alternatively to using these special functions, it is fully allowed to use
 769named functions for each GPIO pin, the pinctrl_request_gpio() will attempt to
 770obtain the function "gpioN" where "N" is the global GPIO pin number if no
 771special GPIO-handler is registered.
 772
 773
 774Board/machine configuration
 775==================================
 776
 777Boards and machines define how a certain complete running system is put
 778together, including how GPIOs and devices are muxed, how regulators are
 779constrained and how the clock tree looks. Of course pinmux settings are also
 780part of this.
 781
 782A pin controller configuration for a machine looks pretty much like a simple
 783regulator configuration, so for the example array above we want to enable i2c
 784and spi on the second function mapping:
 785
 786#include <linux/pinctrl/machine.h>
 787
 788static const struct pinctrl_map mapping[] __initconst = {
 789        {
 790                .dev_name = "foo-spi.0",
 791                .name = PINCTRL_STATE_DEFAULT,
 792                .type = PIN_MAP_TYPE_MUX_GROUP,
 793                .ctrl_dev_name = "pinctrl-foo",
 794                .data.mux.function = "spi0",
 795        },
 796        {
 797                .dev_name = "foo-i2c.0",
 798                .name = PINCTRL_STATE_DEFAULT,
 799                .type = PIN_MAP_TYPE_MUX_GROUP,
 800                .ctrl_dev_name = "pinctrl-foo",
 801                .data.mux.function = "i2c0",
 802        },
 803        {
 804                .dev_name = "foo-mmc.0",
 805                .name = PINCTRL_STATE_DEFAULT,
 806                .type = PIN_MAP_TYPE_MUX_GROUP,
 807                .ctrl_dev_name = "pinctrl-foo",
 808                .data.mux.function = "mmc0",
 809        },
 810};
 811
 812The dev_name here matches to the unique device name that can be used to look
 813up the device struct (just like with clockdev or regulators). The function name
 814must match a function provided by the pinmux driver handling this pin range.
 815
 816As you can see we may have several pin controllers on the system and thus
 817we need to specify which one of them that contain the functions we wish
 818to map.
 819
 820You register this pinmux mapping to the pinmux subsystem by simply:
 821
 822       ret = pinctrl_register_mappings(mapping, ARRAY_SIZE(mapping));
 823
 824Since the above construct is pretty common there is a helper macro to make
 825it even more compact which assumes you want to use pinctrl-foo and position
 8260 for mapping, for example:
 827
 828static struct pinctrl_map __initdata mapping[] = {
 829        PIN_MAP_MUX_GROUP("foo-i2c.o", PINCTRL_STATE_DEFAULT, "pinctrl-foo", NULL, "i2c0"),
 830};
 831
 832The mapping table may also contain pin configuration entries. It's common for
 833each pin/group to have a number of configuration entries that affect it, so
 834the table entries for configuration reference an array of config parameters
 835and values. An example using the convenience macros is shown below:
 836
 837static unsigned long i2c_grp_configs[] = {
 838        FOO_PIN_DRIVEN,
 839        FOO_PIN_PULLUP,
 840};
 841
 842static unsigned long i2c_pin_configs[] = {
 843        FOO_OPEN_COLLECTOR,
 844        FOO_SLEW_RATE_SLOW,
 845};
 846
 847static struct pinctrl_map __initdata mapping[] = {
 848        PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", "i2c0"),
 849        PIN_MAP_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", i2c_grp_configs),
 850        PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0scl", i2c_pin_configs),
 851        PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0sda", i2c_pin_configs),
 852};
 853
 854Finally, some devices expect the mapping table to contain certain specific
 855named states. When running on hardware that doesn't need any pin controller
 856configuration, the mapping table must still contain those named states, in
 857order to explicitly indicate that the states were provided and intended to
 858be empty. Table entry macro PIN_MAP_DUMMY_STATE serves the purpose of defining
 859a named state without causing any pin controller to be programmed:
 860
 861static struct pinctrl_map __initdata mapping[] = {
 862        PIN_MAP_DUMMY_STATE("foo-i2c.0", PINCTRL_STATE_DEFAULT),
 863};
 864
 865
 866Complex mappings
 867================
 868
 869As it is possible to map a function to different groups of pins an optional
 870.group can be specified like this:
 871
 872...
 873{
 874        .dev_name = "foo-spi.0",
 875        .name = "spi0-pos-A",
 876        .type = PIN_MAP_TYPE_MUX_GROUP,
 877        .ctrl_dev_name = "pinctrl-foo",
 878        .function = "spi0",
 879        .group = "spi0_0_grp",
 880},
 881{
 882        .dev_name = "foo-spi.0",
 883        .name = "spi0-pos-B",
 884        .type = PIN_MAP_TYPE_MUX_GROUP,
 885        .ctrl_dev_name = "pinctrl-foo",
 886        .function = "spi0",
 887        .group = "spi0_1_grp",
 888},
 889...
 890
 891This example mapping is used to switch between two positions for spi0 at
 892runtime, as described further below under the heading "Runtime pinmuxing".
 893
 894Further it is possible for one named state to affect the muxing of several
 895groups of pins, say for example in the mmc0 example above, where you can
 896additively expand the mmc0 bus from 2 to 4 to 8 pins. If we want to use all
 897three groups for a total of 2+2+4 = 8 pins (for an 8-bit MMC bus as is the
 898case), we define a mapping like this:
 899
 900...
 901{
 902        .dev_name = "foo-mmc.0",
 903        .name = "2bit"
 904        .type = PIN_MAP_TYPE_MUX_GROUP,
 905        .ctrl_dev_name = "pinctrl-foo",
 906        .function = "mmc0",
 907        .group = "mmc0_1_grp",
 908},
 909{
 910        .dev_name = "foo-mmc.0",
 911        .name = "4bit"
 912        .type = PIN_MAP_TYPE_MUX_GROUP,
 913        .ctrl_dev_name = "pinctrl-foo",
 914        .function = "mmc0",
 915        .group = "mmc0_1_grp",
 916},
 917{
 918        .dev_name = "foo-mmc.0",
 919        .name = "4bit"
 920        .type = PIN_MAP_TYPE_MUX_GROUP,
 921        .ctrl_dev_name = "pinctrl-foo",
 922        .function = "mmc0",
 923        .group = "mmc0_2_grp",
 924},
 925{
 926        .dev_name = "foo-mmc.0",
 927        .name = "8bit"
 928        .type = PIN_MAP_TYPE_MUX_GROUP,
 929        .ctrl_dev_name = "pinctrl-foo",
 930        .function = "mmc0",
 931        .group = "mmc0_1_grp",
 932},
 933{
 934        .dev_name = "foo-mmc.0",
 935        .name = "8bit"
 936        .type = PIN_MAP_TYPE_MUX_GROUP,
 937        .ctrl_dev_name = "pinctrl-foo",
 938        .function = "mmc0",
 939        .group = "mmc0_2_grp",
 940},
 941{
 942        .dev_name = "foo-mmc.0",
 943        .name = "8bit"
 944        .type = PIN_MAP_TYPE_MUX_GROUP,
 945        .ctrl_dev_name = "pinctrl-foo",
 946        .function = "mmc0",
 947        .group = "mmc0_3_grp",
 948},
 949...
 950
 951The result of grabbing this mapping from the device with something like
 952this (see next paragraph):
 953
 954        p = devm_pinctrl_get(dev);
 955        s = pinctrl_lookup_state(p, "8bit");
 956        ret = pinctrl_select_state(p, s);
 957
 958or more simply:
 959
 960        p = devm_pinctrl_get_select(dev, "8bit");
 961
 962Will be that you activate all the three bottom records in the mapping at
 963once. Since they share the same name, pin controller device, function and
 964device, and since we allow multiple groups to match to a single device, they
 965all get selected, and they all get enabled and disable simultaneously by the
 966pinmux core.
 967
 968
 969Pin control requests from drivers
 970=================================
 971
 972Generally it is discouraged to let individual drivers get and enable pin
 973control. So if possible, handle the pin control in platform code or some other
 974place where you have access to all the affected struct device * pointers. In
 975some cases where a driver needs to e.g. switch between different mux mappings
 976at runtime this is not possible.
 977
 978A typical case is if a driver needs to switch bias of pins from normal
 979operation and going to sleep, moving from the PINCTRL_STATE_DEFAULT to
 980PINCTRL_STATE_SLEEP at runtime, re-biasing or even re-muxing pins to save
 981current in sleep mode.
 982
 983A driver may request a certain control state to be activated, usually just the
 984default state like this:
 985
 986#include <linux/pinctrl/consumer.h>
 987
 988struct foo_state {
 989       struct pinctrl *p;
 990       struct pinctrl_state *s;
 991       ...
 992};
 993
 994foo_probe()
 995{
 996        /* Allocate a state holder named "foo" etc */
 997        struct foo_state *foo = ...;
 998
 999        foo->p = devm_pinctrl_get(&device);
1000        if (IS_ERR(foo->p)) {
1001                /* FIXME: clean up "foo" here */
1002                return PTR_ERR(foo->p);
1003        }
1004
1005        foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
1006        if (IS_ERR(foo->s)) {
1007                /* FIXME: clean up "foo" here */
1008                return PTR_ERR(s);
1009        }
1010
1011        ret = pinctrl_select_state(foo->s);
1012        if (ret < 0) {
1013                /* FIXME: clean up "foo" here */
1014                return ret;
1015        }
1016}
1017
1018This get/lookup/select/put sequence can just as well be handled by bus drivers
1019if you don't want each and every driver to handle it and you know the
1020arrangement on your bus.
1021
1022The semantics of the pinctrl APIs are:
1023
1024- pinctrl_get() is called in process context to obtain a handle to all pinctrl
1025  information for a given client device. It will allocate a struct from the
1026  kernel memory to hold the pinmux state. All mapping table parsing or similar
1027  slow operations take place within this API.
1028
1029- devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put()
1030  to be called automatically on the retrieved pointer when the associated
1031  device is removed. It is recommended to use this function over plain
1032  pinctrl_get().
1033
1034- pinctrl_lookup_state() is called in process context to obtain a handle to a
1035  specific state for a the client device. This operation may be slow too.
1036
1037- pinctrl_select_state() programs pin controller hardware according to the
1038  definition of the state as given by the mapping table. In theory this is a
1039  fast-path operation, since it only involved blasting some register settings
1040  into hardware. However, note that some pin controllers may have their
1041  registers on a slow/IRQ-based bus, so client devices should not assume they
1042  can call pinctrl_select_state() from non-blocking contexts.
1043
1044- pinctrl_put() frees all information associated with a pinctrl handle.
1045
1046- devm_pinctrl_put() is a variant of pinctrl_put() that may be used to
1047  explicitly destroy a pinctrl object returned by devm_pinctrl_get().
1048  However, use of this function will be rare, due to the automatic cleanup
1049  that will occur even without calling it.
1050
1051  pinctrl_get() must be paired with a plain pinctrl_put().
1052  pinctrl_get() may not be paired with devm_pinctrl_put().
1053  devm_pinctrl_get() can optionally be paired with devm_pinctrl_put().
1054  devm_pinctrl_get() may not be paired with plain pinctrl_put().
1055
1056Usually the pin control core handled the get/put pair and call out to the
1057device drivers bookkeeping operations, like checking available functions and
1058the associated pins, whereas the enable/disable pass on to the pin controller
1059driver which takes care of activating and/or deactivating the mux setting by
1060quickly poking some registers.
1061
1062The pins are allocated for your device when you issue the devm_pinctrl_get()
1063call, after this you should be able to see this in the debugfs listing of all
1064pins.
1065
1066NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the
1067requested pinctrl handles, for example if the pinctrl driver has not yet
1068registered. Thus make sure that the error path in your driver gracefully
1069cleans up and is ready to retry the probing later in the startup process.
1070
1071
1072Drivers needing both pin control and GPIOs
1073==========================================
1074
1075Again, it is discouraged to let drivers lookup and select pin control states
1076themselves, but again sometimes this is unavoidable.
1077
1078So say that your driver is fetching its resources like this:
1079
1080#include <linux/pinctrl/consumer.h>
1081#include <linux/gpio.h>
1082
1083struct pinctrl *pinctrl;
1084int gpio;
1085
1086pinctrl = devm_pinctrl_get_select_default(&dev);
1087gpio = devm_gpio_request(&dev, 14, "foo");
1088
1089Here we first request a certain pin state and then request GPIO 14 to be
1090used. If you're using the subsystems orthogonally like this, you should
1091nominally always get your pinctrl handle and select the desired pinctrl
1092state BEFORE requesting the GPIO. This is a semantic convention to avoid
1093situations that can be electrically unpleasant, you will certainly want to
1094mux in and bias pins in a certain way before the GPIO subsystems starts to
1095deal with them.
1096
1097The above can be hidden: using pinctrl hogs, the pin control driver may be
1098setting up the config and muxing for the pins when it is probing,
1099nevertheless orthogonal to the GPIO subsystem.
1100
1101But there are also situations where it makes sense for the GPIO subsystem
1102to communicate directly with with the pinctrl subsystem, using the latter
1103as a back-end. This is when the GPIO driver may call out to the functions
1104described in the section "Pin control interaction with the GPIO subsystem"
1105above. This only involves per-pin multiplexing, and will be completely
1106hidden behind the gpio_*() function namespace. In this case, the driver
1107need not interact with the pin control subsystem at all.
1108
1109If a pin control driver and a GPIO driver is dealing with the same pins
1110and the use cases involve multiplexing, you MUST implement the pin controller
1111as a back-end for the GPIO driver like this, unless your hardware design
1112is such that the GPIO controller can override the pin controller's
1113multiplexing state through hardware without the need to interact with the
1114pin control system.
1115
1116
1117System pin control hogging
1118==========================
1119
1120Pin control map entries can be hogged by the core when the pin controller
1121is registered. This means that the core will attempt to call pinctrl_get(),
1122lookup_state() and select_state() on it immediately after the pin control
1123device has been registered.
1124
1125This occurs for mapping table entries where the client device name is equal
1126to the pin controller device name, and the state name is PINCTRL_STATE_DEFAULT.
1127
1128{
1129        .dev_name = "pinctrl-foo",
1130        .name = PINCTRL_STATE_DEFAULT,
1131        .type = PIN_MAP_TYPE_MUX_GROUP,
1132        .ctrl_dev_name = "pinctrl-foo",
1133        .function = "power_func",
1134},
1135
1136Since it may be common to request the core to hog a few always-applicable
1137mux settings on the primary pin controller, there is a convenience macro for
1138this:
1139
1140PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-foo", NULL /* group */, "power_func")
1141
1142This gives the exact same result as the above construction.
1143
1144
1145Runtime pinmuxing
1146=================
1147
1148It is possible to mux a certain function in and out at runtime, say to move
1149an SPI port from one set of pins to another set of pins. Say for example for
1150spi0 in the example above, we expose two different groups of pins for the same
1151function, but with different named in the mapping as described under
1152"Advanced mapping" above. So that for an SPI device, we have two states named
1153"pos-A" and "pos-B".
1154
1155This snippet first muxes the function in the pins defined by group A, enables
1156it, disables and releases it, and muxes it in on the pins defined by group B:
1157
1158#include <linux/pinctrl/consumer.h>
1159
1160struct pinctrl *p;
1161struct pinctrl_state *s1, *s2;
1162
1163foo_probe()
1164{
1165        /* Setup */
1166        p = devm_pinctrl_get(&device);
1167        if (IS_ERR(p))
1168                ...
1169
1170        s1 = pinctrl_lookup_state(foo->p, "pos-A");
1171        if (IS_ERR(s1))
1172                ...
1173
1174        s2 = pinctrl_lookup_state(foo->p, "pos-B");
1175        if (IS_ERR(s2))
1176                ...
1177}
1178
1179foo_switch()
1180{
1181        /* Enable on position A */
1182        ret = pinctrl_select_state(s1);
1183        if (ret < 0)
1184            ...
1185
1186        ...
1187
1188        /* Enable on position B */
1189        ret = pinctrl_select_state(s2);
1190        if (ret < 0)
1191            ...
1192
1193        ...
1194}
1195
1196The above has to be done from process context.
1197
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