linux/drivers/video/i740_reg.h
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   1/**************************************************************************
   2
   3Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas.
   4All Rights Reserved.
   5
   6Permission is hereby granted, free of charge, to any person obtaining a
   7copy of this software and associated documentation files (the
   8"Software"), to deal in the Software without restriction, including
   9without limitation the rights to use, copy, modify, merge, publish,
  10distribute, sub license, and/or sell copies of the Software, and to
  11permit persons to whom the Software is furnished to do so, subject to
  12the following conditions:
  13
  14The above copyright notice and this permission notice (including the
  15next paragraph) shall be included in all copies or substantial portions
  16of the Software.
  17
  18THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  22ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26**************************************************************************/
  27
  28/*
  29 * Authors:
  30 *   Kevin E. Martin <kevin@precisioninsight.com>
  31 */
  32
  33/* I/O register offsets */
  34#define SRX VGA_SEQ_I
  35#define GRX VGA_GFX_I
  36#define ARX VGA_ATT_IW
  37#define XRX 0x3D6
  38#define MRX 0x3D2
  39
  40/* VGA Color Palette Registers */
  41#define DACMASK         0x3C6
  42#define DACSTATE        0x3C7
  43#define DACRX           0x3C7
  44#define DACWX           0x3C8
  45#define DACDATA         0x3C9
  46
  47/* CRT Controller Registers (CRX) */
  48#define START_ADDR_HI           0x0C
  49#define START_ADDR_LO           0x0D
  50#define VERT_SYNC_END           0x11
  51#define EXT_VERT_TOTAL          0x30
  52#define EXT_VERT_DISPLAY        0x31
  53#define EXT_VERT_SYNC_START     0x32
  54#define EXT_VERT_BLANK_START    0x33
  55#define EXT_HORIZ_TOTAL         0x35
  56#define EXT_HORIZ_BLANK         0x39
  57#define EXT_START_ADDR          0x40
  58#define EXT_START_ADDR_ENABLE   0x80
  59#define EXT_OFFSET              0x41
  60#define EXT_START_ADDR_HI       0x42
  61#define INTERLACE_CNTL          0x70
  62#define INTERLACE_ENABLE        0x80
  63#define INTERLACE_DISABLE       0x00
  64
  65/* Miscellaneous Output Register */
  66#define MSR_R           0x3CC
  67#define MSR_W           0x3C2
  68#define IO_ADDR_SELECT  0x01
  69
  70#define MDA_BASE        0x3B0
  71#define CGA_BASE        0x3D0
  72
  73/* System Configuration Extension Registers (XRX) */
  74#define IO_CTNL         0x09
  75#define EXTENDED_ATTR_CNTL      0x02
  76#define EXTENDED_CRTC_CNTL      0x01
  77
  78#define ADDRESS_MAPPING 0x0A
  79#define PACKED_MODE_ENABLE      0x04
  80#define LINEAR_MODE_ENABLE      0x02
  81#define PAGE_MAPPING_ENABLE     0x01
  82
  83#define BITBLT_CNTL     0x20
  84#define COLEXP_MODE             0x30
  85#define COLEXP_8BPP             0x00
  86#define COLEXP_16BPP            0x10
  87#define COLEXP_24BPP            0x20
  88#define COLEXP_RESERVED         0x30
  89#define CHIP_RESET              0x02
  90#define BITBLT_STATUS           0x01
  91
  92#define DISPLAY_CNTL    0x40
  93#define VGA_WRAP_MODE           0x02
  94#define VGA_WRAP_AT_256KB       0x00
  95#define VGA_NO_WRAP             0x02
  96#define GUI_MODE                0x01
  97#define STANDARD_VGA_MODE       0x00
  98#define HIRES_MODE              0x01
  99
 100#define DRAM_ROW_TYPE   0x50
 101#define DRAM_ROW_0              0x07
 102#define DRAM_ROW_0_SDRAM        0x00
 103#define DRAM_ROW_0_EMPTY        0x07
 104#define DRAM_ROW_1              0x38
 105#define DRAM_ROW_1_SDRAM        0x00
 106#define DRAM_ROW_1_EMPTY        0x38
 107#define DRAM_ROW_CNTL_LO 0x51
 108#define DRAM_CAS_LATENCY        0x10
 109#define DRAM_RAS_TIMING         0x08
 110#define DRAM_RAS_PRECHARGE      0x04
 111#define DRAM_ROW_CNTL_HI 0x52
 112#define DRAM_EXT_CNTL   0x53
 113#define DRAM_REFRESH_RATE       0x03
 114#define DRAM_REFRESH_DISABLE    0x00
 115#define DRAM_REFRESH_60HZ       0x01
 116#define DRAM_REFRESH_FAST_TEST  0x02
 117#define DRAM_REFRESH_RESERVED   0x03
 118#define DRAM_TIMING     0x54
 119#define DRAM_ROW_BNDRY_0 0x55
 120#define DRAM_ROW_BNDRY_1 0x56
 121
 122#define DPMS_SYNC_SELECT 0x61
 123#define VSYNC_CNTL              0x08
 124#define VSYNC_ON                0x00
 125#define VSYNC_OFF               0x08
 126#define HSYNC_CNTL              0x02
 127#define HSYNC_ON                0x00
 128#define HSYNC_OFF               0x02
 129
 130#define PIXPIPE_CONFIG_0 0x80
 131#define DAC_8_BIT               0x80
 132#define DAC_6_BIT               0x00
 133#define HW_CURSOR_ENABLE        0x10
 134#define EXTENDED_PALETTE        0x01
 135
 136#define PIXPIPE_CONFIG_1 0x81
 137#define DISPLAY_COLOR_MODE      0x0F
 138#define DISPLAY_VGA_MODE        0x00
 139#define DISPLAY_8BPP_MODE       0x02
 140#define DISPLAY_15BPP_MODE      0x04
 141#define DISPLAY_16BPP_MODE      0x05
 142#define DISPLAY_24BPP_MODE      0x06
 143#define DISPLAY_32BPP_MODE      0x07
 144
 145#define PIXPIPE_CONFIG_2 0x82
 146#define DISPLAY_GAMMA_ENABLE    0x08
 147#define DISPLAY_GAMMA_DISABLE   0x00
 148#define OVERLAY_GAMMA_ENABLE    0x04
 149#define OVERLAY_GAMMA_DISABLE   0x00
 150
 151#define CURSOR_CONTROL  0xA0
 152#define CURSOR_ORIGIN_SCREEN    0x00
 153#define CURSOR_ORIGIN_DISPLAY   0x10
 154#define CURSOR_MODE             0x07
 155#define CURSOR_MODE_DISABLE     0x00
 156#define CURSOR_MODE_32_4C_AX    0x01
 157#define CURSOR_MODE_128_2C      0x02
 158#define CURSOR_MODE_128_1C      0x03
 159#define CURSOR_MODE_64_3C       0x04
 160#define CURSOR_MODE_64_4C_AX    0x05
 161#define CURSOR_MODE_64_4C       0x06
 162#define CURSOR_MODE_RESERVED    0x07
 163#define CURSOR_BASEADDR_LO 0xA2
 164#define CURSOR_BASEADDR_HI 0xA3
 165#define CURSOR_X_LO     0xA4
 166#define CURSOR_X_HI     0xA5
 167#define CURSOR_X_POS            0x00
 168#define CURSOR_X_NEG            0x80
 169#define CURSOR_Y_LO     0xA6
 170#define CURSOR_Y_HI     0xA7
 171#define CURSOR_Y_POS            0x00
 172#define CURSOR_Y_NEG            0x80
 173
 174#define VCLK2_VCO_M     0xC8
 175#define VCLK2_VCO_N     0xC9
 176#define VCLK2_VCO_MN_MSBS 0xCA
 177#define VCO_N_MSBS              0x30
 178#define VCO_M_MSBS              0x03
 179#define VCLK2_VCO_DIV_SEL 0xCB
 180#define POST_DIV_SELECT         0x70
 181#define POST_DIV_1              0x00
 182#define POST_DIV_2              0x10
 183#define POST_DIV_4              0x20
 184#define POST_DIV_8              0x30
 185#define POST_DIV_16             0x40
 186#define POST_DIV_32             0x50
 187#define VCO_LOOP_DIV_BY_4M      0x00
 188#define VCO_LOOP_DIV_BY_16M     0x04
 189#define REF_CLK_DIV_BY_5        0x02
 190#define REF_DIV_4               0x00
 191#define REF_DIV_1               0x01
 192
 193#define PLL_CNTL        0xCE
 194#define PLL_MEMCLK_SEL          0x03
 195#define PLL_MEMCLK__66667KHZ    0x00
 196#define PLL_MEMCLK__75000KHZ    0x01
 197#define PLL_MEMCLK__88889KHZ    0x02
 198#define PLL_MEMCLK_100000KHZ    0x03
 199
 200/* Multimedia Extension Registers (MRX) */
 201#define ACQ_CNTL_1      0x02
 202#define ACQ_CNTL_2      0x03
 203#define FRAME_CAP_MODE          0x01
 204#define CONT_CAP_MODE           0x00
 205#define SINGLE_CAP_MODE         0x01
 206#define ACQ_CNTL_3      0x04
 207#define COL_KEY_CNTL_1          0x3C
 208#define BLANK_DISP_OVERLAY      0x20
 209
 210/* FIFOs */
 211#define LP_FIFO         0x1000
 212#define HP_FIFO         0x2000
 213#define INSTPNT         0x3040
 214#define LP_FIFO_COUNT   0x3040
 215#define HP_FIFO_COUNT   0x3041
 216
 217/* FIFO Commands */
 218#define CLIENT          0xE0000000
 219#define CLIENT_2D       0x60000000
 220
 221/* Command Parser Mode Register */
 222#define COMPARS         0x3038
 223#define TWO_D_INST_DISABLE              0x08
 224#define THREE_D_INST_DISABLE            0x04
 225#define STATE_VAR_UPDATE_DISABLE        0x02
 226#define PAL_STIP_DISABLE                0x01
 227
 228/* Interrupt Control Registers */
 229#define IER             0x3030
 230#define IIR             0x3032
 231#define IMR             0x3034
 232#define ISR             0x3036
 233#define VMIINTB_EVENT           0x2000
 234#define GPIO4_INT               0x1000
 235#define DISP_FLIP_EVENT         0x0800
 236#define DVD_PORT_DMA            0x0400
 237#define DISP_VBLANK             0x0200
 238#define FIFO_EMPTY_DMA_DONE     0x0100
 239#define INST_PARSER_ERROR       0x0080
 240#define USER_DEFINED            0x0040
 241#define BREAKPOINT              0x0020
 242#define DISP_HORIZ_COUNT        0x0010
 243#define DISP_VSYNC              0x0008
 244#define CAPTURE_HORIZ_COUNT     0x0004
 245#define CAPTURE_VSYNC           0x0002
 246#define THREE_D_PIPE_FLUSHED    0x0001
 247
 248/* FIFO Watermark and Burst Length Control Register */
 249#define FWATER_BLC      0x00006000
 250#define LMI_BURST_LENGTH        0x7F000000
 251#define LMI_FIFO_WATERMARK      0x003F0000
 252#define AGP_BURST_LENGTH        0x00007F00
 253#define AGP_FIFO_WATERMARK      0x0000003F
 254
 255/* BitBLT Registers */
 256#define SRC_DST_PITCH   0x00040000
 257#define DST_PITCH               0x1FFF0000
 258#define SRC_PITCH               0x00001FFF
 259#define COLEXP_BG_COLOR 0x00040004
 260#define COLEXP_FG_COLOR 0x00040008
 261#define MONO_SRC_CNTL   0x0004000C
 262#define MONO_USE_COLEXP         0x00000000
 263#define MONO_USE_SRCEXP         0x08000000
 264#define MONO_DATA_ALIGN         0x07000000
 265#define MONO_BIT_ALIGN          0x01000000
 266#define MONO_BYTE_ALIGN         0x02000000
 267#define MONO_WORD_ALIGN         0x03000000
 268#define MONO_DWORD_ALIGN        0x04000000
 269#define MONO_QWORD_ALIGN        0x05000000
 270#define MONO_SRC_INIT_DSCRD     0x003F0000
 271#define MONO_SRC_RIGHT_CLIP     0x00003F00
 272#define MONO_SRC_LEFT_CLIP      0x0000003F
 273#define BITBLT_CONTROL  0x00040010
 274#define BLTR_STATUS             0x80000000
 275#define DYN_DEPTH               0x03000000
 276#define DYN_DEPTH_8BPP          0x00000000
 277#define DYN_DEPTH_16BPP         0x01000000
 278#define DYN_DEPTH_24BPP         0x02000000
 279#define DYN_DEPTH_32BPP         0x03000000      /* Unimplemented on the i740 */
 280#define DYN_DEPTH_ENABLE        0x00800000
 281#define PAT_VERT_ALIGN          0x00700000
 282#define SOLID_PAT_SELECT        0x00080000
 283#define PAT_IS_IN_COLOR         0x00000000
 284#define PAT_IS_MONO             0x00040000
 285#define MONO_PAT_TRANSP         0x00020000
 286#define COLOR_TRANSP_ROP        0x00000000
 287#define COLOR_TRANSP_DST        0x00008000
 288#define COLOR_TRANSP_EQ         0x00000000
 289#define COLOR_TRANSP_NOT_EQ     0x00010000
 290#define COLOR_TRANSP_ENABLE     0x00004000
 291#define MONO_SRC_TRANSP         0x00002000
 292#define SRC_IS_IN_COLOR         0x00000000
 293#define SRC_IS_MONO             0x00001000
 294#define SRC_USE_SRC_ADDR        0x00000000
 295#define SRC_USE_BLTDATA         0x00000400
 296#define BLT_TOP_TO_BOT          0x00000000
 297#define BLT_BOT_TO_TOP          0x00000200
 298#define BLT_LEFT_TO_RIGHT       0x00000000
 299#define BLT_RIGHT_TO_LEFT       0x00000100
 300#define BLT_ROP                 0x000000FF
 301#define BLT_PAT_ADDR    0x00040014
 302#define BLT_SRC_ADDR    0x00040018
 303#define BLT_DST_ADDR    0x0004001C
 304#define BLT_DST_H_W     0x00040020
 305#define BLT_DST_HEIGHT          0x1FFF0000
 306#define BLT_DST_WIDTH           0x00001FFF
 307#define SRCEXP_BG_COLOR 0x00040024
 308#define SRCEXP_FG_COLOR 0x00040028
 309#define BLTDATA         0x00050000
 310
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