linux/drivers/scsi/tmscsim.h
<<
>>
Prefs
   1/***********************************************************************
   2;*      File Name : TMSCSIM.H                                          *
   3;*                  TEKRAM DC-390(T) PCI SCSI Bus Master Host Adapter  *
   4;*                  Device Driver                                      *
   5;***********************************************************************/
   6/* $Id: tmscsim.h,v 2.15.2.3 2000/11/17 20:52:27 garloff Exp $ */
   7
   8#ifndef _TMSCSIM_H
   9#define _TMSCSIM_H
  10
  11#include <linux/types.h>
  12
  13#define SCSI_IRQ_NONE 255
  14
  15#define MAX_ADAPTER_NUM         4
  16#define MAX_SG_LIST_BUF         16      /* Not used */
  17#define MAX_SCSI_ID             8
  18#define MAX_SRB_CNT             50      /* Max number of started commands */
  19
  20#define SEL_TIMEOUT             153     /* 250 ms selection timeout (@ 40 MHz) */
  21
  22/*
  23;-----------------------------------------------------------------------
  24; SCSI Request Block
  25;-----------------------------------------------------------------------
  26*/
  27struct dc390_srb
  28{
  29//u8            CmdBlock[12];
  30
  31struct dc390_srb        *pNextSRB;
  32struct dc390_dcb        *pSRBDCB;
  33struct scsi_cmnd        *pcmd;
  34struct scatterlist      *pSegmentList;
  35
  36struct scatterlist Segmentx;    /* make a one entry of S/G list table */
  37
  38unsigned long   SGBusAddr;      /*;a segment starting address as seen by AM53C974A
  39                                  in CPU endianness. We're only getting 32-bit bus
  40                                  addresses by default */
  41unsigned long   SGToBeXferLen;  /*; to be xfer length */
  42unsigned long   TotalXferredLen;
  43unsigned long   SavedTotXLen;
  44unsigned long   Saved_Ptr;
  45u32             SRBState;
  46
  47u8              SRBStatus;
  48u8              SRBFlag;        /*; b0-AutoReqSense,b6-Read,b7-write */
  49                                /*; b4-settimeout,b5-Residual valid */
  50u8              AdaptStatus;
  51u8              TargetStatus;
  52
  53u8              ScsiPhase;
  54s8              TagNumber;
  55u8              SGIndex;
  56u8              SGcount;
  57
  58u8              MsgCnt;
  59u8              EndMessage;
  60
  61u8              MsgInBuf[6];
  62u8              MsgOutBuf[6];
  63
  64//u8            IORBFlag;       /*;81h-Reset, 2-retry */
  65};
  66
  67
  68/*
  69;-----------------------------------------------------------------------
  70; Device Control Block
  71;-----------------------------------------------------------------------
  72*/
  73struct dc390_dcb
  74{
  75struct dc390_dcb        *pNextDCB;
  76struct dc390_acb        *pDCBACB;
  77
  78/* Queued SRBs */
  79struct dc390_srb        *pGoingSRB;
  80struct dc390_srb        *pGoingLast;
  81struct dc390_srb        *pActiveSRB;
  82u8              GoingSRBCnt;
  83
  84u32             TagMask;
  85
  86u8              TargetID;       /*; SCSI Target ID  (SCSI Only) */
  87u8              TargetLUN;      /*; SCSI Log.  Unit (SCSI Only) */
  88u8              DevMode;
  89u8              DCBFlag;
  90
  91u8              CtrlR1;
  92u8              CtrlR3;
  93u8              CtrlR4;
  94
  95u8              SyncMode;       /*; 0:async mode */
  96u8              NegoPeriod;     /*;for nego. */
  97u8              SyncPeriod;     /*;for reg. */
  98u8              SyncOffset;     /*;for reg. and nego.(low nibble) */
  99};
 100
 101
 102/*
 103;-----------------------------------------------------------------------
 104; Adapter Control Block
 105;-----------------------------------------------------------------------
 106*/
 107struct dc390_acb
 108{
 109struct Scsi_Host *pScsiHost;
 110u16             IOPortBase;
 111u8              IRQLevel;
 112u8              status;
 113
 114u8              SRBCount;
 115u8              AdapterIndex;   /*; nth Adapter this driver */
 116u8              DCBCnt;
 117
 118u8              TagMaxNum;
 119u8              ACBFlag;
 120u8              Gmode2;
 121u8              scan_devices;
 122
 123struct dc390_dcb        *pLinkDCB;
 124struct dc390_dcb        *pLastDCB;
 125struct dc390_dcb        *pDCBRunRobin;
 126
 127struct dc390_dcb        *pActiveDCB;
 128struct dc390_srb        *pFreeSRB;
 129struct dc390_srb        *pTmpSRB;
 130
 131u8              msgin123[4];
 132u8              Connected;
 133u8              pad;
 134
 135#if defined(USE_SPINLOCKS) && USE_SPINLOCKS > 1 && (defined(CONFIG_SMP) || DEBUG_SPINLOCKS > 0)
 136spinlock_t      lock;
 137#endif
 138u8              sel_timeout;
 139u8              glitch_cfg;
 140
 141u8              MsgLen;
 142u8              Ignore_IRQ;     /* Not used */
 143
 144struct pci_dev  *pdev;
 145
 146unsigned long   Cmds;
 147u32             SelLost;
 148u32             SelConn;
 149u32             CmdInQ;
 150u32             CmdOutOfSRB;
 151
 152struct dc390_srb        TmpSRB;
 153struct dc390_srb        SRB_array[MAX_SRB_CNT];         /* 50 SRBs */
 154};
 155
 156
 157/*;-----------------------------------------------------------------------*/
 158
 159
 160#define BIT31   0x80000000
 161#define BIT30   0x40000000
 162#define BIT29   0x20000000
 163#define BIT28   0x10000000
 164#define BIT27   0x08000000
 165#define BIT26   0x04000000
 166#define BIT25   0x02000000
 167#define BIT24   0x01000000
 168#define BIT23   0x00800000
 169#define BIT22   0x00400000
 170#define BIT21   0x00200000
 171#define BIT20   0x00100000
 172#define BIT19   0x00080000
 173#define BIT18   0x00040000
 174#define BIT17   0x00020000
 175#define BIT16   0x00010000
 176#define BIT15   0x00008000
 177#define BIT14   0x00004000
 178#define BIT13   0x00002000
 179#define BIT12   0x00001000
 180#define BIT11   0x00000800
 181#define BIT10   0x00000400
 182#define BIT9    0x00000200
 183#define BIT8    0x00000100
 184#define BIT7    0x00000080
 185#define BIT6    0x00000040
 186#define BIT5    0x00000020
 187#define BIT4    0x00000010
 188#define BIT3    0x00000008
 189#define BIT2    0x00000004
 190#define BIT1    0x00000002
 191#define BIT0    0x00000001
 192
 193/*;---UnitCtrlFlag */
 194#define UNIT_ALLOCATED  BIT0
 195#define UNIT_INFO_CHANGED BIT1
 196#define FORMATING_MEDIA BIT2
 197#define UNIT_RETRY      BIT3
 198
 199/*;---UnitFlags */
 200#define DASD_SUPPORT    BIT0
 201#define SCSI_SUPPORT    BIT1
 202#define ASPI_SUPPORT    BIT2
 203
 204/*;----SRBState machine definition */
 205#define SRB_FREE        0
 206#define SRB_WAIT        BIT0
 207#define SRB_READY       BIT1
 208#define SRB_MSGOUT      BIT2    /*;arbitration+msg_out 1st byte*/
 209#define SRB_MSGIN       BIT3
 210#define SRB_MSGIN_MULTI BIT4
 211#define SRB_COMMAND     BIT5
 212#define SRB_START_      BIT6    /*;arbitration+msg_out+command_out*/
 213#define SRB_DISCONNECT  BIT7
 214#define SRB_DATA_XFER   BIT8
 215#define SRB_XFERPAD     BIT9
 216#define SRB_STATUS      BIT10
 217#define SRB_COMPLETED   BIT11
 218#define SRB_ABORT_SENT  BIT12
 219#define DO_SYNC_NEGO    BIT13
 220#define SRB_UNEXPECT_RESEL BIT14
 221
 222/*;---SRBstatus */
 223#define SRB_OK          BIT0
 224#define ABORTION        BIT1
 225#define OVER_RUN        BIT2
 226#define UNDER_RUN       BIT3
 227#define PARITY_ERROR    BIT4
 228#define SRB_ERROR       BIT5
 229
 230/*;---ACBFlag */
 231#define RESET_DEV       BIT0
 232#define RESET_DETECT    BIT1
 233#define RESET_DONE      BIT2
 234
 235/*;---DCBFlag */
 236#define ABORT_DEV_      BIT0
 237
 238/*;---SRBFlag */
 239#define DATAOUT         BIT7
 240#define DATAIN          BIT6
 241#define RESIDUAL_VALID  BIT5
 242#define ENABLE_TIMER    BIT4
 243#define RESET_DEV0      BIT2
 244#define ABORT_DEV       BIT1
 245#define AUTO_REQSENSE   BIT0
 246
 247/*;---Adapter status */
 248#define H_STATUS_GOOD    0
 249#define H_SEL_TIMEOUT    0x11
 250#define H_OVER_UNDER_RUN 0x12
 251#define H_UNEXP_BUS_FREE 0x13
 252#define H_TARGET_PHASE_F 0x14
 253#define H_INVALID_CCB_OP 0x16
 254#define H_LINK_CCB_BAD   0x17
 255#define H_BAD_TARGET_DIR 0x18
 256#define H_DUPLICATE_CCB  0x19
 257#define H_BAD_CCB_OR_SG  0x1A
 258#define H_ABORT          0x0FF
 259
 260/* cmd->result */
 261#define RES_TARGET              0x000000FF      /* Target State */
 262#define RES_TARGET_LNX          STATUS_MASK     /* Only official ... */
 263#define RES_ENDMSG              0x0000FF00      /* End Message */
 264#define RES_DID                 0x00FF0000      /* DID_ codes */
 265#define RES_DRV                 0xFF000000      /* DRIVER_ codes */
 266
 267#define MK_RES(drv,did,msg,tgt) ((int)(drv)<<24 | (int)(did)<<16 | (int)(msg)<<8 | (int)(tgt))
 268#define MK_RES_LNX(drv,did,msg,tgt) ((int)(drv)<<24 | (int)(did)<<16 | (int)(msg)<<8 | (int)(tgt))
 269
 270#define SET_RES_TARGET(who, tgt) do { who &= ~RES_TARGET; who |= (int)(tgt); } while (0)
 271#define SET_RES_TARGET_LNX(who, tgt) do { who &= ~RES_TARGET_LNX; who |= (int)(tgt) << 1; } while (0)
 272#define SET_RES_MSG(who, msg) do { who &= ~RES_ENDMSG; who |= (int)(msg) << 8; } while (0)
 273#define SET_RES_DID(who, did) do { who &= ~RES_DID; who |= (int)(did) << 16; } while (0)
 274#define SET_RES_DRV(who, drv) do { who &= ~RES_DRV; who |= (int)(drv) << 24; } while (0)
 275
 276/*;---Sync_Mode */
 277#define SYNC_DISABLE    0
 278#define SYNC_ENABLE     BIT0
 279#define SYNC_NEGO_DONE  BIT1
 280#define WIDE_ENABLE     BIT2    /* Not used ;-) */
 281#define WIDE_NEGO_DONE  BIT3    /* Not used ;-) */
 282#define EN_TAG_QUEUEING BIT4
 283#define EN_ATN_STOP     BIT5
 284
 285#define SYNC_NEGO_OFFSET 15
 286
 287/*;---SCSI bus phase*/
 288#define SCSI_DATA_OUT   0
 289#define SCSI_DATA_IN    1
 290#define SCSI_COMMAND    2
 291#define SCSI_STATUS_    3
 292#define SCSI_NOP0       4
 293#define SCSI_NOP1       5
 294#define SCSI_MSG_OUT    6
 295#define SCSI_MSG_IN     7
 296
 297/*;----SCSI MSG BYTE*/ /* see scsi/scsi.h */ /* One is missing ! */
 298#define ABORT_TAG       0x0d
 299
 300/*
 301 *      SISC query queue
 302 */
 303typedef struct {
 304        dma_addr_t              saved_dma_handle;
 305} dc390_cmd_scp_t;
 306
 307/*
 308;==========================================================
 309; EEPROM byte offset
 310;==========================================================
 311*/
 312typedef  struct  _EEprom
 313{
 314u8      EE_MODE1;
 315u8      EE_SPEED;
 316u8      xx1;
 317u8      xx2;
 318} EEprom, *PEEprom;
 319
 320#define REAL_EE_ADAPT_SCSI_ID 64
 321#define REAL_EE_MODE2   65
 322#define REAL_EE_DELAY   66
 323#define REAL_EE_TAG_CMD_NUM     67
 324
 325#define EE_ADAPT_SCSI_ID 32
 326#define EE_MODE2        33
 327#define EE_DELAY        34
 328#define EE_TAG_CMD_NUM  35
 329
 330#define EE_LEN          40
 331
 332/*; EE_MODE1 bits definition*/
 333#define PARITY_CHK_     BIT0
 334#define SYNC_NEGO_      BIT1
 335#define EN_DISCONNECT_  BIT2
 336#define SEND_START_     BIT3
 337#define TAG_QUEUEING_   BIT4
 338
 339/*; EE_MODE2 bits definition*/
 340#define MORE2_DRV       BIT0
 341#define GREATER_1G      BIT1
 342#define RST_SCSI_BUS    BIT2
 343#define ACTIVE_NEGATION BIT3
 344#define NO_SEEK         BIT4
 345#define LUN_CHECK       BIT5
 346
 347#define ENABLE_CE       1
 348#define DISABLE_CE      0
 349#define EEPROM_READ     0x80
 350
 351/*
 352;==========================================================
 353;       AMD 53C974 Registers bit Definition
 354;==========================================================
 355*/
 356/*
 357;====================
 358; SCSI Register
 359;====================
 360*/
 361
 362/*; Command Reg.(+0CH) (rw) */
 363#define DMA_COMMAND             BIT7
 364#define NOP_CMD                 0
 365#define CLEAR_FIFO_CMD          1
 366#define RST_DEVICE_CMD          2
 367#define RST_SCSI_BUS_CMD        3
 368
 369#define INFO_XFER_CMD           0x10
 370#define INITIATOR_CMD_CMPLTE    0x11
 371#define MSG_ACCEPTED_CMD        0x12
 372#define XFER_PAD_BYTE           0x18
 373#define SET_ATN_CMD             0x1A
 374#define RESET_ATN_CMD           0x1B
 375
 376#define SEL_WO_ATN              0x41    /* currently not used */
 377#define SEL_W_ATN               0x42
 378#define SEL_W_ATN_STOP          0x43
 379#define SEL_W_ATN3              0x46
 380#define EN_SEL_RESEL            0x44
 381#define DIS_SEL_RESEL           0x45    /* currently not used */
 382#define RESEL                   0x40    /* " */
 383#define RESEL_ATN3              0x47    /* " */
 384
 385#define DATA_XFER_CMD           INFO_XFER_CMD
 386
 387
 388/*; SCSI Status Reg.(+10H) (r) */
 389#define INTERRUPT               BIT7
 390#define ILLEGAL_OP_ERR          BIT6
 391#define PARITY_ERR              BIT5
 392#define COUNT_2_ZERO            BIT4
 393#define GROUP_CODE_VALID        BIT3
 394#define SCSI_PHASE_MASK         (BIT2+BIT1+BIT0) 
 395/* BIT2: MSG phase; BIT1: C/D physe; BIT0: I/O phase */
 396
 397/*; Interrupt Status Reg.(+14H) (r) */
 398#define SCSI_RESET              BIT7
 399#define INVALID_CMD             BIT6
 400#define DISCONNECTED            BIT5
 401#define SERVICE_REQUEST         BIT4
 402#define SUCCESSFUL_OP           BIT3
 403#define RESELECTED              BIT2
 404#define SEL_ATTENTION           BIT1
 405#define SELECTED                BIT0
 406
 407/*; Internal State Reg.(+18H) (r) */
 408#define SYNC_OFFSET_FLAG        BIT3
 409#define INTRN_STATE_MASK        (BIT2+BIT1+BIT0)
 410/* 0x04: Sel. successful (w/o stop), 0x01: Sel. successful (w/ stop) */
 411
 412/*; Clock Factor Reg.(+24H) (w) */
 413#define CLK_FREQ_40MHZ          0
 414#define CLK_FREQ_35MHZ          (BIT2+BIT1+BIT0)
 415#define CLK_FREQ_30MHZ          (BIT2+BIT1)
 416#define CLK_FREQ_25MHZ          (BIT2+BIT0)
 417#define CLK_FREQ_20MHZ          BIT2
 418#define CLK_FREQ_15MHZ          (BIT1+BIT0)
 419#define CLK_FREQ_10MHZ          BIT1
 420
 421/*; Control Reg. 1(+20H) (rw) */
 422#define EXTENDED_TIMING         BIT7
 423#define DIS_INT_ON_SCSI_RST     BIT6
 424#define PARITY_ERR_REPO         BIT4
 425#define SCSI_ID_ON_BUS          (BIT2+BIT1+BIT0) /* host adapter ID */
 426
 427/*; Control Reg. 2(+2CH) (rw) */
 428#define EN_FEATURE              BIT6
 429#define EN_SCSI2_CMD            BIT3
 430
 431/*; Control Reg. 3(+30H) (rw) */
 432#define ID_MSG_CHECK            BIT7
 433#define EN_QTAG_MSG             BIT6
 434#define EN_GRP2_CMD             BIT5
 435#define FAST_SCSI               BIT4    /* ;10MB/SEC */
 436#define FAST_CLK                BIT3    /* ;25 - 40 MHZ */
 437
 438/*; Control Reg. 4(+34H) (rw) */
 439#define EATER_12NS              0
 440#define EATER_25NS              BIT7
 441#define EATER_35NS              BIT6
 442#define EATER_0NS               (BIT7+BIT6)
 443#define REDUCED_POWER           BIT5
 444#define CTRL4_RESERVED          BIT4    /* must be 1 acc. to AM53C974.c */
 445#define NEGATE_REQACKDATA       BIT2
 446#define NEGATE_REQACK           BIT3
 447
 448#define GLITCH_TO_NS(x) (((~x>>6 & 2) >> 1) | ((x>>6 & 1) << 1 ^ (x>>6 & 2)))
 449#define NS_TO_GLITCH(y) (((~y<<7) | ~((y<<6) ^ ((y<<5 & 1<<6) | ~0x40))) & 0xc0)
 450
 451/*
 452;====================
 453; DMA Register
 454;====================
 455*/
 456/*; DMA Command Reg.(+40H) (rw) */
 457#define READ_DIRECTION          BIT7
 458#define WRITE_DIRECTION         0
 459#define EN_DMA_INT              BIT6
 460#define EN_PAGE_INT             BIT5    /* page transfer interrupt enable */
 461#define MAP_TO_MDL              BIT4
 462#define DIAGNOSTIC              BIT2
 463#define DMA_IDLE_CMD            0
 464#define DMA_BLAST_CMD           BIT0
 465#define DMA_ABORT_CMD           BIT1
 466#define DMA_START_CMD           (BIT1+BIT0)
 467
 468/*; DMA Status Reg.(+54H) (r) */
 469#define PCI_MS_ABORT            BIT6
 470#define BLAST_COMPLETE          BIT5
 471#define SCSI_INTERRUPT          BIT4
 472#define DMA_XFER_DONE           BIT3
 473#define DMA_XFER_ABORT          BIT2
 474#define DMA_XFER_ERROR          BIT1
 475#define POWER_DOWN              BIT0
 476
 477/*; DMA SCSI Bus and Ctrl.(+70H) */
 478#define EN_INT_ON_PCI_ABORT     BIT25
 479#define WRT_ERASE_DMA_STAT      BIT24
 480#define PW_DOWN_CTRL            BIT21
 481#define SCSI_BUSY               BIT20
 482#define SCLK                    BIT19
 483#define SCAM                    BIT18
 484#define SCSI_LINES              0x0003ffff
 485
 486/*
 487;==========================================================
 488; SCSI Chip register address offset
 489;==========================================================
 490;Registers are rw unless declared otherwise 
 491*/
 492#define CtcReg_Low      0x00    /* r    curr. transfer count */
 493#define CtcReg_Mid      0x04    /* r */
 494#define CtcReg_High     0x38    /* r */
 495#define ScsiFifo        0x08
 496#define ScsiCmd         0x0C
 497#define Scsi_Status     0x10    /* r */
 498#define INT_Status      0x14    /* r */
 499#define Sync_Period     0x18    /* w */
 500#define Sync_Offset     0x1C    /* w */
 501#define Clk_Factor      0x24    /* w */
 502#define CtrlReg1        0x20    
 503#define CtrlReg2        0x2C
 504#define CtrlReg3        0x30
 505#define CtrlReg4        0x34
 506#define DMA_Cmd         0x40
 507#define DMA_XferCnt     0x44    /* rw   starting transfer count (32 bit) */
 508#define DMA_XferAddr    0x48    /* rw   starting physical address (32 bit) */
 509#define DMA_Wk_ByteCntr 0x4C    /* r    working byte counter */
 510#define DMA_Wk_AddrCntr 0x50    /* r    working address counter */
 511#define DMA_Status      0x54    /* r */
 512#define DMA_MDL_Addr    0x58    /* rw   starting MDL address */
 513#define DMA_Wk_MDL_Cntr 0x5C    /* r    working MDL counter */
 514#define DMA_ScsiBusCtrl 0x70    /* rw   SCSI Bus, PCI/DMA Ctrl */
 515
 516#define StcReg_Low      CtcReg_Low      /* w    start transfer count */
 517#define StcReg_Mid      CtcReg_Mid      /* w */
 518#define StcReg_High     CtcReg_High     /* w */
 519#define Scsi_Dest_ID    Scsi_Status     /* w */
 520#define Scsi_TimeOut    INT_Status      /* w */
 521#define Intern_State    Sync_Period     /* r */
 522#define Current_Fifo    Sync_Offset     /* r    Curr. FIFO / int. state */
 523
 524
 525#define DC390_read8(address)                    \
 526        (inb (pACB->IOPortBase + (address)))
 527
 528#define DC390_read8_(address, base)             \
 529        (inb ((u16)(base) + (address)))
 530
 531#define DC390_read16(address)                   \
 532        (inw (pACB->IOPortBase + (address)))
 533
 534#define DC390_read32(address)                   \
 535        (inl (pACB->IOPortBase + (address)))
 536
 537#define DC390_write8(address,value)             \
 538        outb ((value), pACB->IOPortBase + (address))
 539
 540#define DC390_write8_(address,value,base)       \
 541        outb ((value), (u16)(base) + (address))
 542
 543#define DC390_write16(address,value)            \
 544        outw ((value), pACB->IOPortBase + (address))
 545
 546#define DC390_write32(address,value)            \
 547        outl ((value), pACB->IOPortBase + (address))
 548
 549
 550#endif /* _TMSCSIM_H */
 551
lxr.linux.no kindly hosted by Redpill Linpro AS, provider of Linux consulting and operations services since 1995.