linux/drivers/pinctrl/pinctrl-nomadik.c
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   1/*
   2 * Generic GPIO driver for logic cells found in the Nomadik SoC
   3 *
   4 * Copyright (C) 2008,2009 STMicroelectronics
   5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
   6 *   Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
   7 * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org>
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License version 2 as
  11 * published by the Free Software Foundation.
  12 */
  13#include <linux/kernel.h>
  14#include <linux/module.h>
  15#include <linux/init.h>
  16#include <linux/device.h>
  17#include <linux/platform_device.h>
  18#include <linux/io.h>
  19#include <linux/clk.h>
  20#include <linux/err.h>
  21#include <linux/gpio.h>
  22#include <linux/spinlock.h>
  23#include <linux/interrupt.h>
  24#include <linux/irq.h>
  25#include <linux/irqdomain.h>
  26#include <linux/slab.h>
  27#include <linux/of_device.h>
  28#include <linux/pinctrl/pinctrl.h>
  29#include <linux/pinctrl/pinmux.h>
  30#include <linux/pinctrl/pinconf.h>
  31/* Since we request GPIOs from ourself */
  32#include <linux/pinctrl/consumer.h>
  33/*
  34 * For the U8500 archs, use the PRCMU register interface, for the older
  35 * Nomadik, provide some stubs. The functions using these will only be
  36 * called on the U8500 series.
  37 */
  38#ifdef CONFIG_ARCH_U8500
  39#include <linux/mfd/dbx500-prcmu.h>
  40#else
  41static inline u32 prcmu_read(unsigned int reg) {
  42        return 0;
  43}
  44static inline void prcmu_write(unsigned int reg, u32 value) {}
  45static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {}
  46#endif
  47
  48#include <asm/mach/irq.h>
  49
  50#include <plat/pincfg.h>
  51#include <plat/gpio-nomadik.h>
  52
  53#include "pinctrl-nomadik.h"
  54
  55/*
  56 * The GPIO module in the Nomadik family of Systems-on-Chip is an
  57 * AMBA device, managing 32 pins and alternate functions.  The logic block
  58 * is currently used in the Nomadik and ux500.
  59 *
  60 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
  61 */
  62
  63#define NMK_GPIO_PER_CHIP       32
  64
  65struct nmk_gpio_chip {
  66        struct gpio_chip chip;
  67        struct irq_domain *domain;
  68        void __iomem *addr;
  69        struct clk *clk;
  70        unsigned int bank;
  71        unsigned int parent_irq;
  72        int secondary_parent_irq;
  73        u32 (*get_secondary_status)(unsigned int bank);
  74        void (*set_ioforce)(bool enable);
  75        spinlock_t lock;
  76        bool sleepmode;
  77        /* Keep track of configured edges */
  78        u32 edge_rising;
  79        u32 edge_falling;
  80        u32 real_wake;
  81        u32 rwimsc;
  82        u32 fwimsc;
  83        u32 rimsc;
  84        u32 fimsc;
  85        u32 pull_up;
  86        u32 lowemi;
  87};
  88
  89struct nmk_pinctrl {
  90        struct device *dev;
  91        struct pinctrl_dev *pctl;
  92        const struct nmk_pinctrl_soc_data *soc;
  93};
  94
  95static struct nmk_gpio_chip *
  96nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
  97
  98static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
  99
 100#define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
 101
 102static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
 103                                unsigned offset, int gpio_mode)
 104{
 105        u32 bit = 1 << offset;
 106        u32 afunc, bfunc;
 107
 108        afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
 109        bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
 110        if (gpio_mode & NMK_GPIO_ALT_A)
 111                afunc |= bit;
 112        if (gpio_mode & NMK_GPIO_ALT_B)
 113                bfunc |= bit;
 114        writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
 115        writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
 116}
 117
 118static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
 119                                unsigned offset, enum nmk_gpio_slpm mode)
 120{
 121        u32 bit = 1 << offset;
 122        u32 slpm;
 123
 124        slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
 125        if (mode == NMK_GPIO_SLPM_NOCHANGE)
 126                slpm |= bit;
 127        else
 128                slpm &= ~bit;
 129        writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
 130}
 131
 132static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
 133                                unsigned offset, enum nmk_gpio_pull pull)
 134{
 135        u32 bit = 1 << offset;
 136        u32 pdis;
 137
 138        pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
 139        if (pull == NMK_GPIO_PULL_NONE) {
 140                pdis |= bit;
 141                nmk_chip->pull_up &= ~bit;
 142        } else {
 143                pdis &= ~bit;
 144        }
 145
 146        writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
 147
 148        if (pull == NMK_GPIO_PULL_UP) {
 149                nmk_chip->pull_up |= bit;
 150                writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
 151        } else if (pull == NMK_GPIO_PULL_DOWN) {
 152                nmk_chip->pull_up &= ~bit;
 153                writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
 154        }
 155}
 156
 157static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
 158                                  unsigned offset, bool lowemi)
 159{
 160        u32 bit = BIT(offset);
 161        bool enabled = nmk_chip->lowemi & bit;
 162
 163        if (lowemi == enabled)
 164                return;
 165
 166        if (lowemi)
 167                nmk_chip->lowemi |= bit;
 168        else
 169                nmk_chip->lowemi &= ~bit;
 170
 171        writel_relaxed(nmk_chip->lowemi,
 172                       nmk_chip->addr + NMK_GPIO_LOWEMI);
 173}
 174
 175static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
 176                                  unsigned offset)
 177{
 178        writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
 179}
 180
 181static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
 182                                  unsigned offset, int val)
 183{
 184        if (val)
 185                writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
 186        else
 187                writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
 188}
 189
 190static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
 191                                  unsigned offset, int val)
 192{
 193        writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
 194        __nmk_gpio_set_output(nmk_chip, offset, val);
 195}
 196
 197static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
 198                                     unsigned offset, int gpio_mode,
 199                                     bool glitch)
 200{
 201        u32 rwimsc = nmk_chip->rwimsc;
 202        u32 fwimsc = nmk_chip->fwimsc;
 203
 204        if (glitch && nmk_chip->set_ioforce) {
 205                u32 bit = BIT(offset);
 206
 207                /* Prevent spurious wakeups */
 208                writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
 209                writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
 210
 211                nmk_chip->set_ioforce(true);
 212        }
 213
 214        __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
 215
 216        if (glitch && nmk_chip->set_ioforce) {
 217                nmk_chip->set_ioforce(false);
 218
 219                writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
 220                writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
 221        }
 222}
 223
 224static void
 225nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
 226{
 227        u32 falling = nmk_chip->fimsc & BIT(offset);
 228        u32 rising = nmk_chip->rimsc & BIT(offset);
 229        int gpio = nmk_chip->chip.base + offset;
 230        int irq = NOMADIK_GPIO_TO_IRQ(gpio);
 231        struct irq_data *d = irq_get_irq_data(irq);
 232
 233        if (!rising && !falling)
 234                return;
 235
 236        if (!d || !irqd_irq_disabled(d))
 237                return;
 238
 239        if (rising) {
 240                nmk_chip->rimsc &= ~BIT(offset);
 241                writel_relaxed(nmk_chip->rimsc,
 242                               nmk_chip->addr + NMK_GPIO_RIMSC);
 243        }
 244
 245        if (falling) {
 246                nmk_chip->fimsc &= ~BIT(offset);
 247                writel_relaxed(nmk_chip->fimsc,
 248                               nmk_chip->addr + NMK_GPIO_FIMSC);
 249        }
 250
 251        dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio);
 252}
 253
 254static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
 255        unsigned offset, unsigned alt_num)
 256{
 257        int i;
 258        u16 reg;
 259        u8 bit;
 260        u8 alt_index;
 261        const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
 262        const u16 *gpiocr_regs;
 263
 264        if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) {
 265                dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n",
 266                        alt_num);
 267                return;
 268        }
 269
 270        for (i = 0 ; i < npct->soc->npins_altcx ; i++) {
 271                if (npct->soc->altcx_pins[i].pin == offset)
 272                        break;
 273        }
 274        if (i == npct->soc->npins_altcx) {
 275                dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n",
 276                        offset);
 277                return;
 278        }
 279
 280        pin_desc = npct->soc->altcx_pins + i;
 281        gpiocr_regs = npct->soc->prcm_gpiocr_registers;
 282
 283        /*
 284         * If alt_num is NULL, just clear current ALTCx selection
 285         * to make sure we come back to a pure ALTC selection
 286         */
 287        if (!alt_num) {
 288                for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
 289                        if (pin_desc->altcx[i].used == true) {
 290                                reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
 291                                bit = pin_desc->altcx[i].control_bit;
 292                                if (prcmu_read(reg) & BIT(bit)) {
 293                                        prcmu_write_masked(reg, BIT(bit), 0);
 294                                        dev_dbg(npct->dev,
 295                                                "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
 296                                                offset, i+1);
 297                                }
 298                        }
 299                }
 300                return;
 301        }
 302
 303        alt_index = alt_num - 1;
 304        if (pin_desc->altcx[alt_index].used == false) {
 305                dev_warn(npct->dev,
 306                        "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",
 307                        offset, alt_num);
 308                return;
 309        }
 310
 311        /*
 312         * Check if any other ALTCx functions are activated on this pin
 313         * and disable it first.
 314         */
 315        for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
 316                if (i == alt_index)
 317                        continue;
 318                if (pin_desc->altcx[i].used == true) {
 319                        reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
 320                        bit = pin_desc->altcx[i].control_bit;
 321                        if (prcmu_read(reg) & BIT(bit)) {
 322                                prcmu_write_masked(reg, BIT(bit), 0);
 323                                dev_dbg(npct->dev,
 324                                        "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
 325                                        offset, i+1);
 326                        }
 327                }
 328        }
 329
 330        reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index];
 331        bit = pin_desc->altcx[alt_index].control_bit;
 332        dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
 333                offset, alt_index+1);
 334        prcmu_write_masked(reg, BIT(bit), BIT(bit));
 335}
 336
 337static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
 338                             pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
 339{
 340        static const char *afnames[] = {
 341                [NMK_GPIO_ALT_GPIO]     = "GPIO",
 342                [NMK_GPIO_ALT_A]        = "A",
 343                [NMK_GPIO_ALT_B]        = "B",
 344                [NMK_GPIO_ALT_C]        = "C"
 345        };
 346        static const char *pullnames[] = {
 347                [NMK_GPIO_PULL_NONE]    = "none",
 348                [NMK_GPIO_PULL_UP]      = "up",
 349                [NMK_GPIO_PULL_DOWN]    = "down",
 350                [3] /* illegal */       = "??"
 351        };
 352        static const char *slpmnames[] = {
 353                [NMK_GPIO_SLPM_INPUT]           = "input/wakeup",
 354                [NMK_GPIO_SLPM_NOCHANGE]        = "no-change/no-wakeup",
 355        };
 356
 357        int pin = PIN_NUM(cfg);
 358        int pull = PIN_PULL(cfg);
 359        int af = PIN_ALT(cfg);
 360        int slpm = PIN_SLPM(cfg);
 361        int output = PIN_DIR(cfg);
 362        int val = PIN_VAL(cfg);
 363        bool glitch = af == NMK_GPIO_ALT_C;
 364
 365        dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
 366                pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
 367                output ? "output " : "input",
 368                output ? (val ? "high" : "low") : "");
 369
 370        if (sleep) {
 371                int slpm_pull = PIN_SLPM_PULL(cfg);
 372                int slpm_output = PIN_SLPM_DIR(cfg);
 373                int slpm_val = PIN_SLPM_VAL(cfg);
 374
 375                af = NMK_GPIO_ALT_GPIO;
 376
 377                /*
 378                 * The SLPM_* values are normal values + 1 to allow zero to
 379                 * mean "same as normal".
 380                 */
 381                if (slpm_pull)
 382                        pull = slpm_pull - 1;
 383                if (slpm_output)
 384                        output = slpm_output - 1;
 385                if (slpm_val)
 386                        val = slpm_val - 1;
 387
 388                dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
 389                        pin,
 390                        slpm_pull ? pullnames[pull] : "same",
 391                        slpm_output ? (output ? "output" : "input") : "same",
 392                        slpm_val ? (val ? "high" : "low") : "same");
 393        }
 394
 395        if (output)
 396                __nmk_gpio_make_output(nmk_chip, offset, val);
 397        else {
 398                __nmk_gpio_make_input(nmk_chip, offset);
 399                __nmk_gpio_set_pull(nmk_chip, offset, pull);
 400        }
 401
 402        __nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg));
 403
 404        /*
 405         * If the pin is switching to altfunc, and there was an interrupt
 406         * installed on it which has been lazy disabled, actually mask the
 407         * interrupt to prevent spurious interrupts that would occur while the
 408         * pin is under control of the peripheral.  Only SKE does this.
 409         */
 410        if (af != NMK_GPIO_ALT_GPIO)
 411                nmk_gpio_disable_lazy_irq(nmk_chip, offset);
 412
 413        /*
 414         * If we've backed up the SLPM registers (glitch workaround), modify
 415         * the backups since they will be restored.
 416         */
 417        if (slpmregs) {
 418                if (slpm == NMK_GPIO_SLPM_NOCHANGE)
 419                        slpmregs[nmk_chip->bank] |= BIT(offset);
 420                else
 421                        slpmregs[nmk_chip->bank] &= ~BIT(offset);
 422        } else
 423                __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
 424
 425        __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch);
 426}
 427
 428/*
 429 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
 430 *  - Save SLPM registers
 431 *  - Set SLPM=0 for the IOs you want to switch and others to 1
 432 *  - Configure the GPIO registers for the IOs that are being switched
 433 *  - Set IOFORCE=1
 434 *  - Modify the AFLSA/B registers for the IOs that are being switched
 435 *  - Set IOFORCE=0
 436 *  - Restore SLPM registers
 437 *  - Any spurious wake up event during switch sequence to be ignored and
 438 *    cleared
 439 */
 440static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
 441{
 442        int i;
 443
 444        for (i = 0; i < NUM_BANKS; i++) {
 445                struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
 446                unsigned int temp = slpm[i];
 447
 448                if (!chip)
 449                        break;
 450
 451                clk_enable(chip->clk);
 452
 453                slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
 454                writel(temp, chip->addr + NMK_GPIO_SLPC);
 455        }
 456}
 457
 458static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
 459{
 460        int i;
 461
 462        for (i = 0; i < NUM_BANKS; i++) {
 463                struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
 464
 465                if (!chip)
 466                        break;
 467
 468                writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
 469
 470                clk_disable(chip->clk);
 471        }
 472}
 473
 474static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
 475{
 476        static unsigned int slpm[NUM_BANKS];
 477        unsigned long flags;
 478        bool glitch = false;
 479        int ret = 0;
 480        int i;
 481
 482        for (i = 0; i < num; i++) {
 483                if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) {
 484                        glitch = true;
 485                        break;
 486                }
 487        }
 488
 489        spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
 490
 491        if (glitch) {
 492                memset(slpm, 0xff, sizeof(slpm));
 493
 494                for (i = 0; i < num; i++) {
 495                        int pin = PIN_NUM(cfgs[i]);
 496                        int offset = pin % NMK_GPIO_PER_CHIP;
 497
 498                        if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C)
 499                                slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset);
 500                }
 501
 502                nmk_gpio_glitch_slpm_init(slpm);
 503        }
 504
 505        for (i = 0; i < num; i++) {
 506                struct nmk_gpio_chip *nmk_chip;
 507                int pin = PIN_NUM(cfgs[i]);
 508
 509                nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP];
 510                if (!nmk_chip) {
 511                        ret = -EINVAL;
 512                        break;
 513                }
 514
 515                clk_enable(nmk_chip->clk);
 516                spin_lock(&nmk_chip->lock);
 517                __nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP,
 518                                 cfgs[i], sleep, glitch ? slpm : NULL);
 519                spin_unlock(&nmk_chip->lock);
 520                clk_disable(nmk_chip->clk);
 521        }
 522
 523        if (glitch)
 524                nmk_gpio_glitch_slpm_restore(slpm);
 525
 526        spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
 527
 528        return ret;
 529}
 530
 531/**
 532 * nmk_config_pin - configure a pin's mux attributes
 533 * @cfg: pin confguration
 534 * @sleep: Non-zero to apply the sleep mode configuration
 535 * Configures a pin's mode (alternate function or GPIO), its pull up status,
 536 * and its sleep mode based on the specified configuration.  The @cfg is
 537 * usually one of the SoC specific macros defined in mach/<soc>-pins.h.  These
 538 * are constructed using, and can be further enhanced with, the macros in
 539 * plat/pincfg.h.
 540 *
 541 * If a pin's mode is set to GPIO, it is configured as an input to avoid
 542 * side-effects.  The gpio can be manipulated later using standard GPIO API
 543 * calls.
 544 */
 545int nmk_config_pin(pin_cfg_t cfg, bool sleep)
 546{
 547        return __nmk_config_pins(&cfg, 1, sleep);
 548}
 549EXPORT_SYMBOL(nmk_config_pin);
 550
 551/**
 552 * nmk_config_pins - configure several pins at once
 553 * @cfgs: array of pin configurations
 554 * @num: number of elments in the array
 555 *
 556 * Configures several pins using nmk_config_pin().  Refer to that function for
 557 * further information.
 558 */
 559int nmk_config_pins(pin_cfg_t *cfgs, int num)
 560{
 561        return __nmk_config_pins(cfgs, num, false);
 562}
 563EXPORT_SYMBOL(nmk_config_pins);
 564
 565int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
 566{
 567        return __nmk_config_pins(cfgs, num, true);
 568}
 569EXPORT_SYMBOL(nmk_config_pins_sleep);
 570
 571/**
 572 * nmk_gpio_set_slpm() - configure the sleep mode of a pin
 573 * @gpio: pin number
 574 * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
 575 *
 576 * This register is actually in the pinmux layer, not the GPIO block itself.
 577 * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP
 578 * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code).
 579 * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is
 580 * HIGH, overriding the normal setting defined by GPIO_AFSELx registers.
 581 * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit),
 582 * the GPIOs return to the normal setting defined by GPIO_AFSELx registers.
 583 *
 584 * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO
 585 * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is
 586 * entered) regardless of the altfunction selected. Also wake-up detection is
 587 * ENABLED.
 588 *
 589 * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains
 590 * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS
 591 * (for altfunction GPIO) or respective on-chip peripherals (for other
 592 * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED.
 593 *
 594 * Note that enable_irq_wake() will automatically enable wakeup detection.
 595 */
 596int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
 597{
 598        struct nmk_gpio_chip *nmk_chip;
 599        unsigned long flags;
 600
 601        nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
 602        if (!nmk_chip)
 603                return -EINVAL;
 604
 605        clk_enable(nmk_chip->clk);
 606        spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
 607        spin_lock(&nmk_chip->lock);
 608
 609        __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode);
 610
 611        spin_unlock(&nmk_chip->lock);
 612        spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
 613        clk_disable(nmk_chip->clk);
 614
 615        return 0;
 616}
 617
 618/**
 619 * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
 620 * @gpio: pin number
 621 * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
 622 *
 623 * Enables/disables pull up/down on a specified pin.  This only takes effect if
 624 * the pin is configured as an input (either explicitly or by the alternate
 625 * function).
 626 *
 627 * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
 628 * configured as an input.  Otherwise, due to the way the controller registers
 629 * work, this function will change the value output on the pin.
 630 */
 631int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
 632{
 633        struct nmk_gpio_chip *nmk_chip;
 634        unsigned long flags;
 635
 636        nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
 637        if (!nmk_chip)
 638                return -EINVAL;
 639
 640        clk_enable(nmk_chip->clk);
 641        spin_lock_irqsave(&nmk_chip->lock, flags);
 642        __nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull);
 643        spin_unlock_irqrestore(&nmk_chip->lock, flags);
 644        clk_disable(nmk_chip->clk);
 645
 646        return 0;
 647}
 648
 649/* Mode functions */
 650/**
 651 * nmk_gpio_set_mode() - set the mux mode of a gpio pin
 652 * @gpio: pin number
 653 * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
 654 *             NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
 655 *
 656 * Sets the mode of the specified pin to one of the alternate functions or
 657 * plain GPIO.
 658 */
 659int nmk_gpio_set_mode(int gpio, int gpio_mode)
 660{
 661        struct nmk_gpio_chip *nmk_chip;
 662        unsigned long flags;
 663
 664        nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
 665        if (!nmk_chip)
 666                return -EINVAL;
 667
 668        clk_enable(nmk_chip->clk);
 669        spin_lock_irqsave(&nmk_chip->lock, flags);
 670        __nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode);
 671        spin_unlock_irqrestore(&nmk_chip->lock, flags);
 672        clk_disable(nmk_chip->clk);
 673
 674        return 0;
 675}
 676EXPORT_SYMBOL(nmk_gpio_set_mode);
 677
 678int nmk_gpio_get_mode(int gpio)
 679{
 680        struct nmk_gpio_chip *nmk_chip;
 681        u32 afunc, bfunc, bit;
 682
 683        nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
 684        if (!nmk_chip)
 685                return -EINVAL;
 686
 687        bit = 1 << (gpio % NMK_GPIO_PER_CHIP);
 688
 689        clk_enable(nmk_chip->clk);
 690
 691        afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
 692        bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
 693
 694        clk_disable(nmk_chip->clk);
 695
 696        return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
 697}
 698EXPORT_SYMBOL(nmk_gpio_get_mode);
 699
 700
 701/* IRQ functions */
 702static inline int nmk_gpio_get_bitmask(int gpio)
 703{
 704        return 1 << (gpio % NMK_GPIO_PER_CHIP);
 705}
 706
 707static void nmk_gpio_irq_ack(struct irq_data *d)
 708{
 709        struct nmk_gpio_chip *nmk_chip;
 710
 711        nmk_chip = irq_data_get_irq_chip_data(d);
 712        if (!nmk_chip)
 713                return;
 714
 715        clk_enable(nmk_chip->clk);
 716        writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
 717        clk_disable(nmk_chip->clk);
 718}
 719
 720enum nmk_gpio_irq_type {
 721        NORMAL,
 722        WAKE,
 723};
 724
 725static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
 726                                  int gpio, enum nmk_gpio_irq_type which,
 727                                  bool enable)
 728{
 729        u32 bitmask = nmk_gpio_get_bitmask(gpio);
 730        u32 *rimscval;
 731        u32 *fimscval;
 732        u32 rimscreg;
 733        u32 fimscreg;
 734
 735        if (which == NORMAL) {
 736                rimscreg = NMK_GPIO_RIMSC;
 737                fimscreg = NMK_GPIO_FIMSC;
 738                rimscval = &nmk_chip->rimsc;
 739                fimscval = &nmk_chip->fimsc;
 740        } else  {
 741                rimscreg = NMK_GPIO_RWIMSC;
 742                fimscreg = NMK_GPIO_FWIMSC;
 743                rimscval = &nmk_chip->rwimsc;
 744                fimscval = &nmk_chip->fwimsc;
 745        }
 746
 747        /* we must individually set/clear the two edges */
 748        if (nmk_chip->edge_rising & bitmask) {
 749                if (enable)
 750                        *rimscval |= bitmask;
 751                else
 752                        *rimscval &= ~bitmask;
 753                writel(*rimscval, nmk_chip->addr + rimscreg);
 754        }
 755        if (nmk_chip->edge_falling & bitmask) {
 756                if (enable)
 757                        *fimscval |= bitmask;
 758                else
 759                        *fimscval &= ~bitmask;
 760                writel(*fimscval, nmk_chip->addr + fimscreg);
 761        }
 762}
 763
 764static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
 765                                int gpio, bool on)
 766{
 767        /*
 768         * Ensure WAKEUP_ENABLE is on.  No need to disable it if wakeup is
 769         * disabled, since setting SLPM to 1 increases power consumption, and
 770         * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
 771         */
 772        if (nmk_chip->sleepmode && on) {
 773                __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP,
 774                                    NMK_GPIO_SLPM_WAKEUP_ENABLE);
 775        }
 776
 777        __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
 778}
 779
 780static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
 781{
 782        struct nmk_gpio_chip *nmk_chip;
 783        unsigned long flags;
 784        u32 bitmask;
 785
 786        nmk_chip = irq_data_get_irq_chip_data(d);
 787        bitmask = nmk_gpio_get_bitmask(d->hwirq);
 788        if (!nmk_chip)
 789                return -EINVAL;
 790
 791        clk_enable(nmk_chip->clk);
 792        spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
 793        spin_lock(&nmk_chip->lock);
 794
 795        __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
 796
 797        if (!(nmk_chip->real_wake & bitmask))
 798                __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
 799
 800        spin_unlock(&nmk_chip->lock);
 801        spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
 802        clk_disable(nmk_chip->clk);
 803
 804        return 0;
 805}
 806
 807static void nmk_gpio_irq_mask(struct irq_data *d)
 808{
 809        nmk_gpio_irq_maskunmask(d, false);
 810}
 811
 812static void nmk_gpio_irq_unmask(struct irq_data *d)
 813{
 814        nmk_gpio_irq_maskunmask(d, true);
 815}
 816
 817static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
 818{
 819        struct nmk_gpio_chip *nmk_chip;
 820        unsigned long flags;
 821        u32 bitmask;
 822
 823        nmk_chip = irq_data_get_irq_chip_data(d);
 824        if (!nmk_chip)
 825                return -EINVAL;
 826        bitmask = nmk_gpio_get_bitmask(d->hwirq);
 827
 828        clk_enable(nmk_chip->clk);
 829        spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
 830        spin_lock(&nmk_chip->lock);
 831
 832        if (irqd_irq_disabled(d))
 833                __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
 834
 835        if (on)
 836                nmk_chip->real_wake |= bitmask;
 837        else
 838                nmk_chip->real_wake &= ~bitmask;
 839
 840        spin_unlock(&nmk_chip->lock);
 841        spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
 842        clk_disable(nmk_chip->clk);
 843
 844        return 0;
 845}
 846
 847static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 848{
 849        bool enabled = !irqd_irq_disabled(d);
 850        bool wake = irqd_is_wakeup_set(d);
 851        struct nmk_gpio_chip *nmk_chip;
 852        unsigned long flags;
 853        u32 bitmask;
 854
 855        nmk_chip = irq_data_get_irq_chip_data(d);
 856        bitmask = nmk_gpio_get_bitmask(d->hwirq);
 857        if (!nmk_chip)
 858                return -EINVAL;
 859        if (type & IRQ_TYPE_LEVEL_HIGH)
 860                return -EINVAL;
 861        if (type & IRQ_TYPE_LEVEL_LOW)
 862                return -EINVAL;
 863
 864        clk_enable(nmk_chip->clk);
 865        spin_lock_irqsave(&nmk_chip->lock, flags);
 866
 867        if (enabled)
 868                __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
 869
 870        if (enabled || wake)
 871                __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
 872
 873        nmk_chip->edge_rising &= ~bitmask;
 874        if (type & IRQ_TYPE_EDGE_RISING)
 875                nmk_chip->edge_rising |= bitmask;
 876
 877        nmk_chip->edge_falling &= ~bitmask;
 878        if (type & IRQ_TYPE_EDGE_FALLING)
 879                nmk_chip->edge_falling |= bitmask;
 880
 881        if (enabled)
 882                __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
 883
 884        if (enabled || wake)
 885                __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
 886
 887        spin_unlock_irqrestore(&nmk_chip->lock, flags);
 888        clk_disable(nmk_chip->clk);
 889
 890        return 0;
 891}
 892
 893static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
 894{
 895        struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
 896
 897        clk_enable(nmk_chip->clk);
 898        nmk_gpio_irq_unmask(d);
 899        return 0;
 900}
 901
 902static void nmk_gpio_irq_shutdown(struct irq_data *d)
 903{
 904        struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
 905
 906        nmk_gpio_irq_mask(d);
 907        clk_disable(nmk_chip->clk);
 908}
 909
 910static struct irq_chip nmk_gpio_irq_chip = {
 911        .name           = "Nomadik-GPIO",
 912        .irq_ack        = nmk_gpio_irq_ack,
 913        .irq_mask       = nmk_gpio_irq_mask,
 914        .irq_unmask     = nmk_gpio_irq_unmask,
 915        .irq_set_type   = nmk_gpio_irq_set_type,
 916        .irq_set_wake   = nmk_gpio_irq_set_wake,
 917        .irq_startup    = nmk_gpio_irq_startup,
 918        .irq_shutdown   = nmk_gpio_irq_shutdown,
 919        .flags          = IRQCHIP_MASK_ON_SUSPEND,
 920};
 921
 922static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
 923                                   u32 status)
 924{
 925        struct nmk_gpio_chip *nmk_chip;
 926        struct irq_chip *host_chip = irq_get_chip(irq);
 927
 928        chained_irq_enter(host_chip, desc);
 929
 930        nmk_chip = irq_get_handler_data(irq);
 931        while (status) {
 932                int bit = __ffs(status);
 933
 934                generic_handle_irq(irq_find_mapping(nmk_chip->domain, bit));
 935                status &= ~BIT(bit);
 936        }
 937
 938        chained_irq_exit(host_chip, desc);
 939}
 940
 941static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 942{
 943        struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
 944        u32 status;
 945
 946        clk_enable(nmk_chip->clk);
 947        status = readl(nmk_chip->addr + NMK_GPIO_IS);
 948        clk_disable(nmk_chip->clk);
 949
 950        __nmk_gpio_irq_handler(irq, desc, status);
 951}
 952
 953static void nmk_gpio_secondary_irq_handler(unsigned int irq,
 954                                           struct irq_desc *desc)
 955{
 956        struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
 957        u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
 958
 959        __nmk_gpio_irq_handler(irq, desc, status);
 960}
 961
 962static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
 963{
 964        irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
 965        irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
 966
 967        if (nmk_chip->secondary_parent_irq >= 0) {
 968                irq_set_chained_handler(nmk_chip->secondary_parent_irq,
 969                                        nmk_gpio_secondary_irq_handler);
 970                irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip);
 971        }
 972
 973        return 0;
 974}
 975
 976/* I/O Functions */
 977
 978static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset)
 979{
 980        /*
 981         * Map back to global GPIO space and request muxing, the direction
 982         * parameter does not matter for this controller.
 983         */
 984        int gpio = chip->base + offset;
 985
 986        return pinctrl_request_gpio(gpio);
 987}
 988
 989static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset)
 990{
 991        int gpio = chip->base + offset;
 992
 993        pinctrl_free_gpio(gpio);
 994}
 995
 996static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
 997{
 998        struct nmk_gpio_chip *nmk_chip =
 999                container_of(chip, struct nmk_gpio_chip, chip);
1000
1001        clk_enable(nmk_chip->clk);
1002
1003        writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
1004
1005        clk_disable(nmk_chip->clk);
1006
1007        return 0;
1008}
1009
1010static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
1011{
1012        struct nmk_gpio_chip *nmk_chip =
1013                container_of(chip, struct nmk_gpio_chip, chip);
1014        u32 bit = 1 << offset;
1015        int value;
1016
1017        clk_enable(nmk_chip->clk);
1018
1019        value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
1020
1021        clk_disable(nmk_chip->clk);
1022
1023        return value;
1024}
1025
1026static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
1027                                int val)
1028{
1029        struct nmk_gpio_chip *nmk_chip =
1030                container_of(chip, struct nmk_gpio_chip, chip);
1031
1032        clk_enable(nmk_chip->clk);
1033
1034        __nmk_gpio_set_output(nmk_chip, offset, val);
1035
1036        clk_disable(nmk_chip->clk);
1037}
1038
1039static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
1040                                int val)
1041{
1042        struct nmk_gpio_chip *nmk_chip =
1043                container_of(chip, struct nmk_gpio_chip, chip);
1044
1045        clk_enable(nmk_chip->clk);
1046
1047        __nmk_gpio_make_output(nmk_chip, offset, val);
1048
1049        clk_disable(nmk_chip->clk);
1050
1051        return 0;
1052}
1053
1054static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1055{
1056        struct nmk_gpio_chip *nmk_chip =
1057                container_of(chip, struct nmk_gpio_chip, chip);
1058
1059        return irq_create_mapping(nmk_chip->domain, offset);
1060}
1061
1062#ifdef CONFIG_DEBUG_FS
1063
1064#include <linux/seq_file.h>
1065
1066static void nmk_gpio_dbg_show_one(struct seq_file *s, struct gpio_chip *chip,
1067                                  unsigned offset, unsigned gpio)
1068{
1069        const char *label = gpiochip_is_requested(chip, offset);
1070        struct nmk_gpio_chip *nmk_chip =
1071                container_of(chip, struct nmk_gpio_chip, chip);
1072        int mode;
1073        bool is_out;
1074        bool pull;
1075        u32 bit = 1 << offset;
1076        const char *modes[] = {
1077                [NMK_GPIO_ALT_GPIO]     = "gpio",
1078                [NMK_GPIO_ALT_A]        = "altA",
1079                [NMK_GPIO_ALT_B]        = "altB",
1080                [NMK_GPIO_ALT_C]        = "altC",
1081        };
1082
1083        clk_enable(nmk_chip->clk);
1084        is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);
1085        pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
1086        mode = nmk_gpio_get_mode(gpio);
1087
1088        seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
1089                   gpio, label ?: "(none)",
1090                   is_out ? "out" : "in ",
1091                   chip->get
1092                   ? (chip->get(chip, offset) ? "hi" : "lo")
1093                   : "?  ",
1094                   (mode < 0) ? "unknown" : modes[mode],
1095                   pull ? "pull" : "none");
1096
1097        if (label && !is_out) {
1098                int             irq = gpio_to_irq(gpio);
1099                struct irq_desc *desc = irq_to_desc(irq);
1100
1101                /* This races with request_irq(), set_irq_type(),
1102                 * and set_irq_wake() ... but those are "rare".
1103                 */
1104                if (irq >= 0 && desc->action) {
1105                        char *trigger;
1106                        u32 bitmask = nmk_gpio_get_bitmask(gpio);
1107
1108                        if (nmk_chip->edge_rising & bitmask)
1109                                trigger = "edge-rising";
1110                        else if (nmk_chip->edge_falling & bitmask)
1111                                trigger = "edge-falling";
1112                        else
1113                                trigger = "edge-undefined";
1114
1115                        seq_printf(s, " irq-%d %s%s",
1116                                   irq, trigger,
1117                                   irqd_is_wakeup_set(&desc->irq_data)
1118                                   ? " wakeup" : "");
1119                }
1120        }
1121        clk_disable(nmk_chip->clk);
1122}
1123
1124static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1125{
1126        unsigned                i;
1127        unsigned                gpio = chip->base;
1128
1129        for (i = 0; i < chip->ngpio; i++, gpio++) {
1130                nmk_gpio_dbg_show_one(s, chip, i, gpio);
1131                seq_printf(s, "\n");
1132        }
1133}
1134
1135#else
1136static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
1137                                         struct gpio_chip *chip,
1138                                         unsigned offset, unsigned gpio)
1139{
1140}
1141#define nmk_gpio_dbg_show       NULL
1142#endif
1143
1144/* This structure is replicated for each GPIO block allocated at probe time */
1145static struct gpio_chip nmk_gpio_template = {
1146        .request                = nmk_gpio_request,
1147        .free                   = nmk_gpio_free,
1148        .direction_input        = nmk_gpio_make_input,
1149        .get                    = nmk_gpio_get_input,
1150        .direction_output       = nmk_gpio_make_output,
1151        .set                    = nmk_gpio_set_output,
1152        .to_irq                 = nmk_gpio_to_irq,
1153        .dbg_show               = nmk_gpio_dbg_show,
1154        .can_sleep              = 0,
1155};
1156
1157void nmk_gpio_clocks_enable(void)
1158{
1159        int i;
1160
1161        for (i = 0; i < NUM_BANKS; i++) {
1162                struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1163
1164                if (!chip)
1165                        continue;
1166
1167                clk_enable(chip->clk);
1168        }
1169}
1170
1171void nmk_gpio_clocks_disable(void)
1172{
1173        int i;
1174
1175        for (i = 0; i < NUM_BANKS; i++) {
1176                struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1177
1178                if (!chip)
1179                        continue;
1180
1181                clk_disable(chip->clk);
1182        }
1183}
1184
1185/*
1186 * Called from the suspend/resume path to only keep the real wakeup interrupts
1187 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
1188 * and not the rest of the interrupts which we needed to have as wakeups for
1189 * cpuidle.
1190 *
1191 * PM ops are not used since this needs to be done at the end, after all the
1192 * other drivers are done with their suspend callbacks.
1193 */
1194void nmk_gpio_wakeups_suspend(void)
1195{
1196        int i;
1197
1198        for (i = 0; i < NUM_BANKS; i++) {
1199                struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1200
1201                if (!chip)
1202                        break;
1203
1204                clk_enable(chip->clk);
1205
1206                writel(chip->rwimsc & chip->real_wake,
1207                       chip->addr + NMK_GPIO_RWIMSC);
1208                writel(chip->fwimsc & chip->real_wake,
1209                       chip->addr + NMK_GPIO_FWIMSC);
1210
1211                clk_disable(chip->clk);
1212        }
1213}
1214
1215void nmk_gpio_wakeups_resume(void)
1216{
1217        int i;
1218
1219        for (i = 0; i < NUM_BANKS; i++) {
1220                struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1221
1222                if (!chip)
1223                        break;
1224
1225                clk_enable(chip->clk);
1226
1227                writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
1228                writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
1229
1230                clk_disable(chip->clk);
1231        }
1232}
1233
1234/*
1235 * Read the pull up/pull down status.
1236 * A bit set in 'pull_up' means that pull up
1237 * is selected if pull is enabled in PDIS register.
1238 * Note: only pull up/down set via this driver can
1239 * be detected due to HW limitations.
1240 */
1241void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
1242{
1243        if (gpio_bank < NUM_BANKS) {
1244                struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];
1245
1246                if (!chip)
1247                        return;
1248
1249                *pull_up = chip->pull_up;
1250        }
1251}
1252
1253int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1254                          irq_hw_number_t hwirq)
1255{
1256        struct nmk_gpio_chip *nmk_chip = d->host_data;
1257
1258        if (!nmk_chip)
1259                return -EINVAL;
1260
1261        irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq);
1262        set_irq_flags(irq, IRQF_VALID);
1263        irq_set_chip_data(irq, nmk_chip);
1264        irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING);
1265
1266        return 0;
1267}
1268
1269const struct irq_domain_ops nmk_gpio_irq_simple_ops = {
1270        .map = nmk_gpio_irq_map,
1271        .xlate = irq_domain_xlate_twocell,
1272};
1273
1274static int __devinit nmk_gpio_probe(struct platform_device *dev)
1275{
1276        struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
1277        struct device_node *np = dev->dev.of_node;
1278        struct nmk_gpio_chip *nmk_chip;
1279        struct gpio_chip *chip;
1280        struct resource *res;
1281        struct clk *clk;
1282        int secondary_irq;
1283        void __iomem *base;
1284        int irq_start = 0;
1285        int irq;
1286        int ret;
1287
1288        if (!pdata && !np) {
1289                dev_err(&dev->dev, "No platform data or device tree found\n");
1290                return -ENODEV;
1291        }
1292
1293        if (np) {
1294                pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
1295                if (!pdata)
1296                        return -ENOMEM;
1297
1298                if (of_get_property(np, "st,supports-sleepmode", NULL))
1299                        pdata->supports_sleepmode = true;
1300
1301                if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
1302                        dev_err(&dev->dev, "gpio-bank property not found\n");
1303                        ret = -EINVAL;
1304                        goto out;
1305                }
1306
1307                pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
1308                pdata->num_gpio   = NMK_GPIO_PER_CHIP;
1309        }
1310
1311        res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1312        if (!res) {
1313                ret = -ENOENT;
1314                goto out;
1315        }
1316
1317        irq = platform_get_irq(dev, 0);
1318        if (irq < 0) {
1319                ret = irq;
1320                goto out;
1321        }
1322
1323        secondary_irq = platform_get_irq(dev, 1);
1324        if (secondary_irq >= 0 && !pdata->get_secondary_status) {
1325                ret = -EINVAL;
1326                goto out;
1327        }
1328
1329        base = devm_request_and_ioremap(&dev->dev, res);
1330        if (!base) {
1331                ret = -ENOMEM;
1332                goto out;
1333        }
1334
1335        clk = devm_clk_get(&dev->dev, NULL);
1336        if (IS_ERR(clk)) {
1337                ret = PTR_ERR(clk);
1338                goto out;
1339        }
1340        clk_prepare(clk);
1341
1342        nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1343        if (!nmk_chip) {
1344                ret = -ENOMEM;
1345                goto out;
1346        }
1347
1348        /*
1349         * The virt address in nmk_chip->addr is in the nomadik register space,
1350         * so we can simply convert the resource address, without remapping
1351         */
1352        nmk_chip->bank = dev->id;
1353        nmk_chip->clk = clk;
1354        nmk_chip->addr = base;
1355        nmk_chip->chip = nmk_gpio_template;
1356        nmk_chip->parent_irq = irq;
1357        nmk_chip->secondary_parent_irq = secondary_irq;
1358        nmk_chip->get_secondary_status = pdata->get_secondary_status;
1359        nmk_chip->set_ioforce = pdata->set_ioforce;
1360        nmk_chip->sleepmode = pdata->supports_sleepmode;
1361        spin_lock_init(&nmk_chip->lock);
1362
1363        chip = &nmk_chip->chip;
1364        chip->base = pdata->first_gpio;
1365        chip->ngpio = pdata->num_gpio;
1366        chip->label = pdata->name ?: dev_name(&dev->dev);
1367        chip->dev = &dev->dev;
1368        chip->owner = THIS_MODULE;
1369
1370        clk_enable(nmk_chip->clk);
1371        nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1372        clk_disable(nmk_chip->clk);
1373
1374#ifdef CONFIG_OF_GPIO
1375        chip->of_node = np;
1376#endif
1377
1378        ret = gpiochip_add(&nmk_chip->chip);
1379        if (ret)
1380                goto out;
1381
1382        BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1383
1384        nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
1385
1386        platform_set_drvdata(dev, nmk_chip);
1387
1388        if (!np)
1389                irq_start = NOMADIK_GPIO_TO_IRQ(pdata->first_gpio);
1390        nmk_chip->domain = irq_domain_add_simple(np,
1391                                NMK_GPIO_PER_CHIP, irq_start,
1392                                &nmk_gpio_irq_simple_ops, nmk_chip);
1393        if (!nmk_chip->domain) {
1394                dev_err(&dev->dev, "failed to create irqdomain\n");
1395                ret = -ENOSYS;
1396                goto out;
1397        }
1398
1399        nmk_gpio_init_irq(nmk_chip);
1400
1401        dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
1402
1403        return 0;
1404
1405out:
1406        dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
1407                  pdata->first_gpio, pdata->first_gpio+31);
1408
1409        return ret;
1410}
1411
1412static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1413{
1414        struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1415
1416        return npct->soc->ngroups;
1417}
1418
1419static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1420                                       unsigned selector)
1421{
1422        struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1423
1424        return npct->soc->groups[selector].name;
1425}
1426
1427static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1428                              const unsigned **pins,
1429                              unsigned *num_pins)
1430{
1431        struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1432
1433        *pins = npct->soc->groups[selector].pins;
1434        *num_pins = npct->soc->groups[selector].npins;
1435        return 0;
1436}
1437
1438static struct pinctrl_gpio_range *
1439nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset)
1440{
1441        struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1442        int i;
1443
1444        for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1445                struct pinctrl_gpio_range *range;
1446
1447                range = &npct->soc->gpio_ranges[i];
1448                if (offset >= range->pin_base &&
1449                    offset <= (range->pin_base + range->npins - 1))
1450                        return range;
1451        }
1452        return NULL;
1453}
1454
1455static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1456                   unsigned offset)
1457{
1458        struct pinctrl_gpio_range *range;
1459        struct gpio_chip *chip;
1460
1461        range = nmk_match_gpio_range(pctldev, offset);
1462        if (!range || !range->gc) {
1463                seq_printf(s, "invalid pin offset");
1464                return;
1465        }
1466        chip = range->gc;
1467        nmk_gpio_dbg_show_one(s, chip, offset - chip->base, offset);
1468}
1469
1470static struct pinctrl_ops nmk_pinctrl_ops = {
1471        .get_groups_count = nmk_get_groups_cnt,
1472        .get_group_name = nmk_get_group_name,
1473        .get_group_pins = nmk_get_group_pins,
1474        .pin_dbg_show = nmk_pin_dbg_show,
1475};
1476
1477static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1478{
1479        struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1480
1481        return npct->soc->nfunctions;
1482}
1483
1484static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1485                                         unsigned function)
1486{
1487        struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1488
1489        return npct->soc->functions[function].name;
1490}
1491
1492static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1493                                   unsigned function,
1494                                   const char * const **groups,
1495                                   unsigned * const num_groups)
1496{
1497        struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1498
1499        *groups = npct->soc->functions[function].groups;
1500        *num_groups = npct->soc->functions[function].ngroups;
1501
1502        return 0;
1503}
1504
1505static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
1506                          unsigned group)
1507{
1508        struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1509        const struct nmk_pingroup *g;
1510        static unsigned int slpm[NUM_BANKS];
1511        unsigned long flags;
1512        bool glitch;
1513        int ret = -EINVAL;
1514        int i;
1515
1516        g = &npct->soc->groups[group];
1517
1518        if (g->altsetting < 0)
1519                return -EINVAL;
1520
1521        dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
1522
1523        /*
1524         * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
1525         * we may pass through an undesired state. In this case we take
1526         * some extra care.
1527         *
1528         * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
1529         *  - Save SLPM registers (since we have a shadow register in the
1530         *    nmk_chip we're using that as backup)
1531         *  - Set SLPM=0 for the IOs you want to switch and others to 1
1532         *  - Configure the GPIO registers for the IOs that are being switched
1533         *  - Set IOFORCE=1
1534         *  - Modify the AFLSA/B registers for the IOs that are being switched
1535         *  - Set IOFORCE=0
1536         *  - Restore SLPM registers
1537         *  - Any spurious wake up event during switch sequence to be ignored
1538         *    and cleared
1539         *
1540         * We REALLY need to save ALL slpm registers, because the external
1541         * IOFORCE will switch *all* ports to their sleepmode setting to as
1542         * to avoid glitches. (Not just one port!)
1543         */
1544        glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C);
1545
1546        if (glitch) {
1547                spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1548
1549                /* Initially don't put any pins to sleep when switching */
1550                memset(slpm, 0xff, sizeof(slpm));
1551
1552                /*
1553                 * Then mask the pins that need to be sleeping now when we're
1554                 * switching to the ALT C function.
1555                 */
1556                for (i = 0; i < g->npins; i++)
1557                        slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
1558                nmk_gpio_glitch_slpm_init(slpm);
1559        }
1560
1561        for (i = 0; i < g->npins; i++) {
1562                struct pinctrl_gpio_range *range;
1563                struct nmk_gpio_chip *nmk_chip;
1564                struct gpio_chip *chip;
1565                unsigned bit;
1566
1567                range = nmk_match_gpio_range(pctldev, g->pins[i]);
1568                if (!range) {
1569                        dev_err(npct->dev,
1570                                "invalid pin offset %d in group %s at index %d\n",
1571                                g->pins[i], g->name, i);
1572                        goto out_glitch;
1573                }
1574                if (!range->gc) {
1575                        dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n",
1576                                g->pins[i], g->name, i);
1577                        goto out_glitch;
1578                }
1579                chip = range->gc;
1580                nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1581                dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
1582
1583                clk_enable(nmk_chip->clk);
1584                bit = g->pins[i] % NMK_GPIO_PER_CHIP;
1585                /*
1586                 * If the pin is switching to altfunc, and there was an
1587                 * interrupt installed on it which has been lazy disabled,
1588                 * actually mask the interrupt to prevent spurious interrupts
1589                 * that would occur while the pin is under control of the
1590                 * peripheral. Only SKE does this.
1591                 */
1592                nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1593
1594                __nmk_gpio_set_mode_safe(nmk_chip, bit,
1595                        (g->altsetting & NMK_GPIO_ALT_C), glitch);
1596                clk_disable(nmk_chip->clk);
1597
1598                /*
1599                 * Call PRCM GPIOCR config function in case ALTC
1600                 * has been selected:
1601                 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers
1602                 *   must be set.
1603                 * - If selection is pure ALTC and previous selection was ALTCx,
1604                 *   then some bits in PRCM GPIOCR registers must be cleared.
1605                 */
1606                if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)
1607                        nmk_prcm_altcx_set_mode(npct, g->pins[i],
1608                                g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);
1609        }
1610
1611        /* When all pins are successfully reconfigured we get here */
1612        ret = 0;
1613
1614out_glitch:
1615        if (glitch) {
1616                nmk_gpio_glitch_slpm_restore(slpm);
1617                spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1618        }
1619
1620        return ret;
1621}
1622
1623static void nmk_pmx_disable(struct pinctrl_dev *pctldev,
1624                            unsigned function, unsigned group)
1625{
1626        struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1627        const struct nmk_pingroup *g;
1628
1629        g = &npct->soc->groups[group];
1630
1631        if (g->altsetting < 0)
1632                return;
1633
1634        /* Poke out the mux, set the pin to some default state? */
1635        dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins);
1636}
1637
1638int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1639                            struct pinctrl_gpio_range *range,
1640                            unsigned offset)
1641{
1642        struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1643        struct nmk_gpio_chip *nmk_chip;
1644        struct gpio_chip *chip;
1645        unsigned bit;
1646
1647        if (!range) {
1648                dev_err(npct->dev, "invalid range\n");
1649                return -EINVAL;
1650        }
1651        if (!range->gc) {
1652                dev_err(npct->dev, "missing GPIO chip in range\n");
1653                return -EINVAL;
1654        }
1655        chip = range->gc;
1656        nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1657
1658        dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1659
1660        clk_enable(nmk_chip->clk);
1661        bit = offset % NMK_GPIO_PER_CHIP;
1662        /* There is no glitch when converting any pin to GPIO */
1663        __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1664        clk_disable(nmk_chip->clk);
1665
1666        return 0;
1667}
1668
1669void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1670                           struct pinctrl_gpio_range *range,
1671                           unsigned offset)
1672{
1673        struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1674
1675        dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1676        /* Set the pin to some default state, GPIO is usually default */
1677}
1678
1679static struct pinmux_ops nmk_pinmux_ops = {
1680        .get_functions_count = nmk_pmx_get_funcs_cnt,
1681        .get_function_name = nmk_pmx_get_func_name,
1682        .get_function_groups = nmk_pmx_get_func_groups,
1683        .enable = nmk_pmx_enable,
1684        .disable = nmk_pmx_disable,
1685        .gpio_request_enable = nmk_gpio_request_enable,
1686        .gpio_disable_free = nmk_gpio_disable_free,
1687};
1688
1689int nmk_pin_config_get(struct pinctrl_dev *pctldev,
1690                       unsigned pin,
1691                       unsigned long *config)
1692{
1693        /* Not implemented */
1694        return -EINVAL;
1695}
1696
1697int nmk_pin_config_set(struct pinctrl_dev *pctldev,
1698                       unsigned pin,
1699                       unsigned long config)
1700{
1701        static const char *pullnames[] = {
1702                [NMK_GPIO_PULL_NONE]    = "none",
1703                [NMK_GPIO_PULL_UP]      = "up",
1704                [NMK_GPIO_PULL_DOWN]    = "down",
1705                [3] /* illegal */       = "??"
1706        };
1707        static const char *slpmnames[] = {
1708                [NMK_GPIO_SLPM_INPUT]           = "input/wakeup",
1709                [NMK_GPIO_SLPM_NOCHANGE]        = "no-change/no-wakeup",
1710        };
1711        struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1712        struct nmk_gpio_chip *nmk_chip;
1713        struct pinctrl_gpio_range *range;
1714        struct gpio_chip *chip;
1715        unsigned bit;
1716
1717        /*
1718         * The pin config contains pin number and altfunction fields, here
1719         * we just ignore that part. It's being handled by the framework and
1720         * pinmux callback respectively.
1721         */
1722        pin_cfg_t cfg = (pin_cfg_t) config;
1723        int pull = PIN_PULL(cfg);
1724        int slpm = PIN_SLPM(cfg);
1725        int output = PIN_DIR(cfg);
1726        int val = PIN_VAL(cfg);
1727        bool lowemi = PIN_LOWEMI(cfg);
1728        bool gpiomode = PIN_GPIOMODE(cfg);
1729        bool sleep = PIN_SLEEPMODE(cfg);
1730
1731        range = nmk_match_gpio_range(pctldev, pin);
1732        if (!range) {
1733                dev_err(npct->dev, "invalid pin offset %d\n", pin);
1734                return -EINVAL;
1735        }
1736        if (!range->gc) {
1737                dev_err(npct->dev, "GPIO chip missing in range for pin %d\n",
1738                        pin);
1739                return -EINVAL;
1740        }
1741        chip = range->gc;
1742        nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1743
1744        if (sleep) {
1745                int slpm_pull = PIN_SLPM_PULL(cfg);
1746                int slpm_output = PIN_SLPM_DIR(cfg);
1747                int slpm_val = PIN_SLPM_VAL(cfg);
1748
1749                /* All pins go into GPIO mode at sleep */
1750                gpiomode = true;
1751
1752                /*
1753                 * The SLPM_* values are normal values + 1 to allow zero to
1754                 * mean "same as normal".
1755                 */
1756                if (slpm_pull)
1757                        pull = slpm_pull - 1;
1758                if (slpm_output)
1759                        output = slpm_output - 1;
1760                if (slpm_val)
1761                        val = slpm_val - 1;
1762
1763                dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
1764                        pin,
1765                        slpm_pull ? pullnames[pull] : "same",
1766                        slpm_output ? (output ? "output" : "input") : "same",
1767                        slpm_val ? (val ? "high" : "low") : "same");
1768        }
1769
1770        dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1771                pin, cfg, pullnames[pull], slpmnames[slpm],
1772                output ? "output " : "input",
1773                output ? (val ? "high" : "low") : "",
1774                lowemi ? "on" : "off" );
1775
1776        clk_enable(nmk_chip->clk);
1777        bit = pin % NMK_GPIO_PER_CHIP;
1778        if (gpiomode)
1779                /* No glitch when going to GPIO mode */
1780                __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1781        if (output)
1782                __nmk_gpio_make_output(nmk_chip, bit, val);
1783        else {
1784                __nmk_gpio_make_input(nmk_chip, bit);
1785                __nmk_gpio_set_pull(nmk_chip, bit, pull);
1786        }
1787        /* TODO: isn't this only applicable on output pins? */
1788        __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1789
1790        __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1791        clk_disable(nmk_chip->clk);
1792        return 0;
1793}
1794
1795static struct pinconf_ops nmk_pinconf_ops = {
1796        .pin_config_get = nmk_pin_config_get,
1797        .pin_config_set = nmk_pin_config_set,
1798};
1799
1800static struct pinctrl_desc nmk_pinctrl_desc = {
1801        .name = "pinctrl-nomadik",
1802        .pctlops = &nmk_pinctrl_ops,
1803        .pmxops = &nmk_pinmux_ops,
1804        .confops = &nmk_pinconf_ops,
1805        .owner = THIS_MODULE,
1806};
1807
1808static const struct of_device_id nmk_pinctrl_match[] = {
1809        {
1810                .compatible = "stericsson,nmk_pinctrl",
1811                .data = (void *)PINCTRL_NMK_DB8500,
1812        },
1813        {},
1814};
1815
1816static int __devinit nmk_pinctrl_probe(struct platform_device *pdev)
1817{
1818        const struct platform_device_id *platid = platform_get_device_id(pdev);
1819        struct device_node *np = pdev->dev.of_node;
1820        struct nmk_pinctrl *npct;
1821        unsigned int version = 0;
1822        int i;
1823
1824        npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
1825        if (!npct)
1826                return -ENOMEM;
1827
1828        if (platid)
1829                version = platid->driver_data;
1830        else if (np)
1831                version = (unsigned int)
1832                        of_match_device(nmk_pinctrl_match, &pdev->dev)->data;
1833
1834        /* Poke in other ASIC variants here */
1835        if (version == PINCTRL_NMK_STN8815)
1836                nmk_pinctrl_stn8815_init(&npct->soc);
1837        if (version == PINCTRL_NMK_DB8500)
1838                nmk_pinctrl_db8500_init(&npct->soc);
1839        if (version == PINCTRL_NMK_DB8540)
1840                nmk_pinctrl_db8540_init(&npct->soc);
1841
1842        /*
1843         * We need all the GPIO drivers to probe FIRST, or we will not be able
1844         * to obtain references to the struct gpio_chip * for them, and we
1845         * need this to proceed.
1846         */
1847        for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1848                if (!nmk_gpio_chips[i]) {
1849                        dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
1850                        return -EPROBE_DEFER;
1851                }
1852                npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[i]->chip;
1853        }
1854
1855        nmk_pinctrl_desc.pins = npct->soc->pins;
1856        nmk_pinctrl_desc.npins = npct->soc->npins;
1857        npct->dev = &pdev->dev;
1858        npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct);
1859        if (!npct->pctl) {
1860                dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
1861                return -EINVAL;
1862        }
1863
1864        /* We will handle a range of GPIO pins */
1865        for (i = 0; i < npct->soc->gpio_num_ranges; i++)
1866                pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]);
1867
1868        platform_set_drvdata(pdev, npct);
1869        dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
1870
1871        return 0;
1872}
1873
1874static const struct of_device_id nmk_gpio_match[] = {
1875        { .compatible = "st,nomadik-gpio", },
1876        {}
1877};
1878
1879static struct platform_driver nmk_gpio_driver = {
1880        .driver = {
1881                .owner = THIS_MODULE,
1882                .name = "gpio",
1883                .of_match_table = nmk_gpio_match,
1884        },
1885        .probe = nmk_gpio_probe,
1886};
1887
1888static const struct platform_device_id nmk_pinctrl_id[] = {
1889        { "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
1890        { "pinctrl-db8500", PINCTRL_NMK_DB8500 },
1891        { "pinctrl-db8540", PINCTRL_NMK_DB8540 },
1892};
1893
1894static struct platform_driver nmk_pinctrl_driver = {
1895        .driver = {
1896                .owner = THIS_MODULE,
1897                .name = "pinctrl-nomadik",
1898                .of_match_table = nmk_pinctrl_match,
1899        },
1900        .probe = nmk_pinctrl_probe,
1901        .id_table = nmk_pinctrl_id,
1902};
1903
1904static int __init nmk_gpio_init(void)
1905{
1906        int ret;
1907
1908        ret = platform_driver_register(&nmk_gpio_driver);
1909        if (ret)
1910                return ret;
1911        return platform_driver_register(&nmk_pinctrl_driver);
1912}
1913
1914core_initcall(nmk_gpio_init);
1915
1916MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
1917MODULE_DESCRIPTION("Nomadik GPIO Driver");
1918MODULE_LICENSE("GPL");
1919
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