linux/drivers/gpio/gpio-mxs.c
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   1/*
   2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
   3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4 *
   5 * Based on code from Freescale,
   6 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License
  10 * as published by the Free Software Foundation; either version 2
  11 * of the License, or (at your option) any later version.
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  20 * MA  02110-1301, USA.
  21 */
  22
  23#include <linux/init.h>
  24#include <linux/interrupt.h>
  25#include <linux/io.h>
  26#include <linux/irq.h>
  27#include <linux/irqdomain.h>
  28#include <linux/gpio.h>
  29#include <linux/of.h>
  30#include <linux/of_address.h>
  31#include <linux/of_device.h>
  32#include <linux/platform_device.h>
  33#include <linux/slab.h>
  34#include <linux/basic_mmio_gpio.h>
  35#include <linux/module.h>
  36
  37#define MXS_SET         0x4
  38#define MXS_CLR         0x8
  39
  40#define PINCTRL_DOUT(p)         ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
  41#define PINCTRL_DIN(p)          ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
  42#define PINCTRL_DOE(p)          ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
  43#define PINCTRL_PIN2IRQ(p)      ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
  44#define PINCTRL_IRQEN(p)        ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
  45#define PINCTRL_IRQLEV(p)       ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
  46#define PINCTRL_IRQPOL(p)       ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
  47#define PINCTRL_IRQSTAT(p)      ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
  48
  49#define GPIO_INT_FALL_EDGE      0x0
  50#define GPIO_INT_LOW_LEV        0x1
  51#define GPIO_INT_RISE_EDGE      0x2
  52#define GPIO_INT_HIGH_LEV       0x3
  53#define GPIO_INT_LEV_MASK       (1 << 0)
  54#define GPIO_INT_POL_MASK       (1 << 1)
  55
  56enum mxs_gpio_id {
  57        IMX23_GPIO,
  58        IMX28_GPIO,
  59};
  60
  61struct mxs_gpio_port {
  62        void __iomem *base;
  63        int id;
  64        int irq;
  65        struct irq_domain *domain;
  66        struct bgpio_chip bgc;
  67        enum mxs_gpio_id devid;
  68};
  69
  70static inline int is_imx23_gpio(struct mxs_gpio_port *port)
  71{
  72        return port->devid == IMX23_GPIO;
  73}
  74
  75static inline int is_imx28_gpio(struct mxs_gpio_port *port)
  76{
  77        return port->devid == IMX28_GPIO;
  78}
  79
  80/* Note: This driver assumes 32 GPIOs are handled in one register */
  81
  82static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
  83{
  84        u32 pin_mask = 1 << d->hwirq;
  85        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  86        struct mxs_gpio_port *port = gc->private;
  87        void __iomem *pin_addr;
  88        int edge;
  89
  90        switch (type) {
  91        case IRQ_TYPE_EDGE_RISING:
  92                edge = GPIO_INT_RISE_EDGE;
  93                break;
  94        case IRQ_TYPE_EDGE_FALLING:
  95                edge = GPIO_INT_FALL_EDGE;
  96                break;
  97        case IRQ_TYPE_LEVEL_LOW:
  98                edge = GPIO_INT_LOW_LEV;
  99                break;
 100        case IRQ_TYPE_LEVEL_HIGH:
 101                edge = GPIO_INT_HIGH_LEV;
 102                break;
 103        default:
 104                return -EINVAL;
 105        }
 106
 107        /* set level or edge */
 108        pin_addr = port->base + PINCTRL_IRQLEV(port);
 109        if (edge & GPIO_INT_LEV_MASK)
 110                writel(pin_mask, pin_addr + MXS_SET);
 111        else
 112                writel(pin_mask, pin_addr + MXS_CLR);
 113
 114        /* set polarity */
 115        pin_addr = port->base + PINCTRL_IRQPOL(port);
 116        if (edge & GPIO_INT_POL_MASK)
 117                writel(pin_mask, pin_addr + MXS_SET);
 118        else
 119                writel(pin_mask, pin_addr + MXS_CLR);
 120
 121        writel(pin_mask,
 122               port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
 123
 124        return 0;
 125}
 126
 127/* MXS has one interrupt *per* gpio port */
 128static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 129{
 130        u32 irq_stat;
 131        struct mxs_gpio_port *port = irq_get_handler_data(irq);
 132
 133        desc->irq_data.chip->irq_ack(&desc->irq_data);
 134
 135        irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
 136                        readl(port->base + PINCTRL_IRQEN(port));
 137
 138        while (irq_stat != 0) {
 139                int irqoffset = fls(irq_stat) - 1;
 140                generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
 141                irq_stat &= ~(1 << irqoffset);
 142        }
 143}
 144
 145/*
 146 * Set interrupt number "irq" in the GPIO as a wake-up source.
 147 * While system is running, all registered GPIO interrupts need to have
 148 * wake-up enabled. When system is suspended, only selected GPIO interrupts
 149 * need to have wake-up enabled.
 150 * @param  irq          interrupt source number
 151 * @param  enable       enable as wake-up if equal to non-zero
 152 * @return       This function returns 0 on success.
 153 */
 154static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
 155{
 156        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 157        struct mxs_gpio_port *port = gc->private;
 158
 159        if (enable)
 160                enable_irq_wake(port->irq);
 161        else
 162                disable_irq_wake(port->irq);
 163
 164        return 0;
 165}
 166
 167static void __init mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
 168{
 169        struct irq_chip_generic *gc;
 170        struct irq_chip_type *ct;
 171
 172        gc = irq_alloc_generic_chip("gpio-mxs", 1, irq_base,
 173                                    port->base, handle_level_irq);
 174        gc->private = port;
 175
 176        ct = gc->chip_types;
 177        ct->chip.irq_ack = irq_gc_ack_set_bit;
 178        ct->chip.irq_mask = irq_gc_mask_clr_bit;
 179        ct->chip.irq_unmask = irq_gc_mask_set_bit;
 180        ct->chip.irq_set_type = mxs_gpio_set_irq_type;
 181        ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
 182        ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
 183        ct->regs.mask = PINCTRL_IRQEN(port);
 184
 185        irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
 186}
 187
 188static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 189{
 190        struct bgpio_chip *bgc = to_bgpio_chip(gc);
 191        struct mxs_gpio_port *port =
 192                container_of(bgc, struct mxs_gpio_port, bgc);
 193
 194        return irq_find_mapping(port->domain, offset);
 195}
 196
 197static struct platform_device_id mxs_gpio_ids[] = {
 198        {
 199                .name = "imx23-gpio",
 200                .driver_data = IMX23_GPIO,
 201        }, {
 202                .name = "imx28-gpio",
 203                .driver_data = IMX28_GPIO,
 204        }, {
 205                /* sentinel */
 206        }
 207};
 208MODULE_DEVICE_TABLE(platform, mxs_gpio_ids);
 209
 210static const struct of_device_id mxs_gpio_dt_ids[] = {
 211        { .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
 212        { .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
 213        { /* sentinel */ }
 214};
 215MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);
 216
 217static int __devinit mxs_gpio_probe(struct platform_device *pdev)
 218{
 219        const struct of_device_id *of_id =
 220                        of_match_device(mxs_gpio_dt_ids, &pdev->dev);
 221        struct device_node *np = pdev->dev.of_node;
 222        struct device_node *parent;
 223        static void __iomem *base;
 224        struct mxs_gpio_port *port;
 225        struct resource *iores = NULL;
 226        int irq_base;
 227        int err;
 228
 229        port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
 230        if (!port)
 231                return -ENOMEM;
 232
 233        if (np) {
 234                port->id = of_alias_get_id(np, "gpio");
 235                if (port->id < 0)
 236                        return port->id;
 237                port->devid = (enum mxs_gpio_id) of_id->data;
 238        } else {
 239                port->id = pdev->id;
 240                port->devid = pdev->id_entry->driver_data;
 241        }
 242
 243        port->irq = platform_get_irq(pdev, 0);
 244        if (port->irq < 0)
 245                return port->irq;
 246
 247        /*
 248         * map memory region only once, as all the gpio ports
 249         * share the same one
 250         */
 251        if (!base) {
 252                if (np) {
 253                        parent = of_get_parent(np);
 254                        base = of_iomap(parent, 0);
 255                        of_node_put(parent);
 256                } else {
 257                        iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 258                        base = devm_request_and_ioremap(&pdev->dev, iores);
 259                }
 260                if (!base)
 261                        return -EADDRNOTAVAIL;
 262        }
 263        port->base = base;
 264
 265        /*
 266         * select the pin interrupt functionality but initially
 267         * disable the interrupts
 268         */
 269        writel(~0U, port->base + PINCTRL_PIN2IRQ(port));
 270        writel(0, port->base + PINCTRL_IRQEN(port));
 271
 272        /* clear address has to be used to clear IRQSTAT bits */
 273        writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
 274
 275        irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
 276        if (irq_base < 0)
 277                return irq_base;
 278
 279        port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
 280                                             &irq_domain_simple_ops, NULL);
 281        if (!port->domain) {
 282                err = -ENODEV;
 283                goto out_irqdesc_free;
 284        }
 285
 286        /* gpio-mxs can be a generic irq chip */
 287        mxs_gpio_init_gc(port, irq_base);
 288
 289        /* setup one handler for each entry */
 290        irq_set_chained_handler(port->irq, mxs_gpio_irq_handler);
 291        irq_set_handler_data(port->irq, port);
 292
 293        err = bgpio_init(&port->bgc, &pdev->dev, 4,
 294                         port->base + PINCTRL_DIN(port),
 295                         port->base + PINCTRL_DOUT(port), NULL,
 296                         port->base + PINCTRL_DOE(port), NULL, 0);
 297        if (err)
 298                goto out_irqdesc_free;
 299
 300        port->bgc.gc.to_irq = mxs_gpio_to_irq;
 301        port->bgc.gc.base = port->id * 32;
 302
 303        err = gpiochip_add(&port->bgc.gc);
 304        if (err)
 305                goto out_bgpio_remove;
 306
 307        return 0;
 308
 309out_bgpio_remove:
 310        bgpio_remove(&port->bgc);
 311out_irqdesc_free:
 312        irq_free_descs(irq_base, 32);
 313        return err;
 314}
 315
 316static struct platform_driver mxs_gpio_driver = {
 317        .driver         = {
 318                .name   = "gpio-mxs",
 319                .owner  = THIS_MODULE,
 320                .of_match_table = mxs_gpio_dt_ids,
 321        },
 322        .probe          = mxs_gpio_probe,
 323        .id_table       = mxs_gpio_ids,
 324};
 325
 326static int __init mxs_gpio_init(void)
 327{
 328        return platform_driver_register(&mxs_gpio_driver);
 329}
 330postcore_initcall(mxs_gpio_init);
 331
 332MODULE_AUTHOR("Freescale Semiconductor, "
 333              "Daniel Mack <danielncaiaq.de>, "
 334              "Juergen Beisert <kernel@pengutronix.de>");
 335MODULE_DESCRIPTION("Freescale MXS GPIO");
 336MODULE_LICENSE("GPL");
 337
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